TWI577009B - Enhanced High Electron Mobility Crystal - Google Patents
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本發明是有關於一種電晶體，特別是指一種加強型高電子遷移率電晶體。 This invention relates to a transistor, and more particularly to a reinforced high electron mobility transistor.
氮化鎵因為具有寬能隙，所以除了可做為發光材之外，目前已成功的被應用在高頻之功率元件。氮化鎵/氮化鋁鎵材料所製作之電晶體，由於在氮化鎵/氮化鋁鎵間之能隙差異造成能帶彎曲與能帶不連續，因此，在界面能帶彎曲部分會局限大量的電子，而形成2DEG(二維電子氣)。2DEG的電子遷移率極高(約1500cm2/Vs)，因此具有高的切換速度，但也因為電子存在此一區域，使得電晶體需在空乏模式(Depletion mode)操作，在此空乏模式操作的電晶體一般稱為常開式(normal on)電晶體。此種常開式電晶體的臨界電壓(threshold voltage)為負值，因此，在閘極零偏壓時電晶體仍會導通電流，而會形成額外的功率耗損。 Since gallium nitride has a wide energy gap, it can be successfully applied to high-frequency power components in addition to being used as a light-emitting material. In a transistor made of gallium nitride/aluminum gallium nitride material, the bending of the band and the discontinuity of the band due to the difference in energy gap between gallium nitride/aluminum gallium nitride are limited. A large number of electrons form 2DEG (two-dimensional electron gas). 2DEG has a very high electron mobility (about 1500 cm 2 /Vs) and therefore has a high switching speed, but also because electrons exist in this region, so that the transistor needs to operate in a depletion mode, operating in this depletion mode. A transistor is generally referred to as a normally on transistor. The threshold voltage of such a normally-on transistor is a negative value, so that the transistor still conducts current when the gate is zero-biased, and additional power consumption is formed.
為了將氮化鎵/氮化鋁鎵電晶體應用在如高功率高效率放大器，高能量切換裝置與省電模式等元件上，需要形成常閉式(normal off)電晶體，亦即元件在零偏壓時不導通，在施加偏壓操作時始導通的電晶體。而此類常閉式(normal off)電晶體的製作，目前有利用凹陷式閘極結構 (recessed gate)，也有利用在氮化鋁鎵(AlGaN)的通道下方加入阻障層，利用阻障層的極化電荷空乏通道的電荷，或是利用CF4電漿處理方式，令氟離子進入氮化鋁鎵的通道中，空乏通道的電荷，使得電晶體在零偏壓時不導通，而得到該常閉式(normal off)電晶體。 In order to apply GaN/AlGaN crystals to components such as high-power high-efficiency amplifiers, high-energy switching devices, and power-saving modes, it is necessary to form a normally off transistor, that is, components are biased at zero. A transistor that is not turned on during pressing and is turned on when a biasing operation is applied. Such a normally off transistor is currently fabricated using a recessed gate, or a barrier layer under the channel of aluminum gallium nitride (AlGaN), using a barrier layer. Polarized charge depletion channel charge, or CF 4 plasma treatment, so that fluoride ions enter the channel of aluminum gallium nitride, the charge of the depletion channel, so that the transistor does not conduct at zero bias, and get the usual Normal off the transistor.
但是，前述要利用將氮化鎵/氮化鋁鎵電晶體形成常閉式(normal off)電晶體，利用凹陷式閘極結構，因為須蝕刻，所以容易造成片電阻增加及漏電流增加等問題，而影響電晶體的特性；而利用電漿處理方式，也容易因為氟離子為進入半導體的深層區域，而容易對半導體材料產生影響。 However, the above-mentioned gallium nitride/aluminum gallium nitride crystal is formed into a normally off transistor, and a recessed gate structure is used. Since etching is required, problems such as an increase in sheet resistance and an increase in leakage current are likely to occur. It affects the characteristics of the transistor; and the plasma treatment method is also easy to affect the semiconductor material because the fluoride ion enters the deep region of the semiconductor.
因此，本發明之目的，即在提供一種加強型高電子遷移率電晶體。 Accordingly, it is an object of the present invention to provide a reinforced high electron mobility transistor.
於是，本發明加強型高電子遷移率電晶體，包含：一個基板、一個半導體單元、一層帶負電層、一層介電層，及一個電極單元。 Thus, the reinforced high electron mobility transistor of the present invention comprises: a substrate, a semiconductor unit, a negatively charged layer, a dielectric layer, and an electrode unit.
該半導體單元含有氮化鎵系半導體材料，形成於該基板表面，並具有一遠離該基板的頂面。 The semiconductor unit includes a gallium nitride-based semiconductor material formed on a surface of the substrate and having a top surface away from the substrate.
該帶負電層形成於該半導體單元的頂面往下的區域。 The negatively charged layer is formed in a region of the top surface of the semiconductor unit.
該介電層設置於部分的該半導體單元的頂面，並覆蓋帶負電層。 The dielectric layer is disposed on a portion of the top surface of the semiconductor unit and covers the negatively charged layer.
該電極單元包括設置於該半導體單元的頂面， 且經由該介電層彼此間隔的一源極、汲極，及一設置於該介電層上的閘極。 The electrode unit includes a top surface disposed on the semiconductor unit, And a source, a drain, and a gate disposed on the dielectric layer via the dielectric layer.
本發明之功效在於，於該半導體單元的頂面淺層區域形成一層帶負電層，利用該帶負電層空乏通道區的電子，而得到常閉式(normal off)電晶體，因為，該帶負電層僅形成在淺層區域，因此，不會損壞該半導體單元的材料特性。 The invention has the effect of forming a negatively charged layer in the shallow region of the top surface of the semiconductor unit, and using the electrons in the negatively charged channel region of the negatively charged layer to obtain a normally off transistor, because the negatively charged layer It is formed only in the shallow region and, therefore, does not damage the material properties of the semiconductor unit.
21‧‧‧基板 21‧‧‧Substrate
22‧‧‧緩衝層 22‧‧‧ Buffer layer
23‧‧‧半導體單元 23‧‧‧Semiconductor unit
231‧‧‧第一半導體層 231‧‧‧First semiconductor layer
232‧‧‧第二半導體層 232‧‧‧Second semiconductor layer
233‧‧‧第三半導體層 233‧‧‧ Third semiconductor layer
24‧‧‧帶負電層 24‧‧‧With negative layer
25‧‧‧介電層 25‧‧‧Dielectric layer
26‧‧‧電極單元 26‧‧‧Electrode unit
261‧‧‧源極 261‧‧‧ source
262‧‧‧汲極 262‧‧‧汲polar
263‧‧‧閘極 263‧‧‧ gate
本發明之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1是一元件結構圖，說明本發明加強型高電子遷移率電晶體的一實施例；圖2是物性分析圖，以SIMS(二次離子質譜儀分析)圖證實氟離子位於一第三半導體層的上表面；圖3是一電性圖，說明一具體例在VGS分別是0V、1V、2V、3V、4V、5V之下的VDS-IDS；及圖4是一電性圖，說明一具體例在VDS分別是5V、10V、15V、20V之下的VGS-IDS。 Other features and effects of the present invention will be apparent from the embodiments of the present invention, wherein: FIG. 1 is a block diagram showing an embodiment of the reinforced high electron mobility transistor of the present invention; It is a physical property analysis diagram, and the SIMS (Secondary Ion Mass Spectrometer Analysis) diagram confirms that the fluoride ion is located on the upper surface of a third semiconductor layer; FIG. 3 is an electrical diagram illustrating a specific example in which V GS is 0 V, 1 V, respectively. V DS -I DS under 2V, 3V, 4V, 5V; and FIG. 4 is an electrical diagram illustrating V GS -I DS under V DS of 5V, 10V, 15V, 20V, respectively.
參閱圖1，本發明加強型高電子遷移率電晶體的一實施例，包含：一個基板21、一層緩衝層22、一個半導體單元23、一個帶負電層24、一層介電層25，及一個電極單元26。 Referring to FIG. 1, an embodiment of a reinforced high electron mobility transistor of the present invention comprises: a substrate 21, a buffer layer 22, a semiconductor unit 23, a negatively charged layer 24, a dielectric layer 25, and an electrode. Unit 26.
該基板21可選自藍寶石(Sapphire)、碳化矽(SiC)或矽(Si)。 The substrate 21 may be selected from sapphire, tantalum carbide (SiC) or bismuth (Si).
該緩衝層22形成於該基板表面，選自氮化鎵或氮化鋁材料。 The buffer layer 22 is formed on the surface of the substrate and is selected from a gallium nitride or aluminum nitride material.
該半導體單元23包括依序自該緩衝層22表面向上形成的一第一半導體層231、一第二半導體層232，及一第三半導體層233，其中，該第三半導體層233的表面即為該半導體單元23的頂面。 The semiconductor unit 23 includes a first semiconductor layer 231, a second semiconductor layer 232, and a third semiconductor layer 233 formed in this order from the surface of the buffer layer 22, wherein the surface of the third semiconductor layer 233 is The top surface of the semiconductor unit 23.
該半導體單元23可以化學氣相沉積(CVD)、分子束磊晶成長(MBE)或有機金屬氣相磊晶(MOVPE)沉積而得，由於該些製程方法為本技術領域所周知，因此不再多加贅述。 The semiconductor unit 23 can be deposited by chemical vapor deposition (CVD), molecular beam epitaxial growth (MBE) or organometallic vapor phase epitaxy (MOVPE), and since these process methods are well known in the art, they are no longer More details.
其中，該第一、二、三半導體層231、232、233是選自氮化鎵系化合物，於本發明該實施例中，該第一、三半導體層231、233的構成材料為氮化鎵(GaN)，該第二半導體層232的構成材料為氮化鋁鎵(AlGaN)。要說明的是，該半導體單元23的膜層結構也可視需求而進一步於該第一半導體層231與該基板21之間再形成一層由氮化鋁鎵(AlGaN)構成的AlGaN半導體層，或是再進一步形成多層分別由氮化鎵(GaN)及氮化鋁鎵(AlGaN)構成之半導體膜層，而形成(AlGaN/GaN)n/GaN/AlGaN/GaN，n≧1的多膜層結構，由於該等半導體膜層相關的相關材料及膜層結構為於HFMT技術領域者所周知，且非為本技術之重點，因此，不再多加詳述說明。 The first, second, and third semiconductor layers 231, 232, and 233 are selected from gallium nitride-based compounds. In the embodiment of the present invention, the first and third semiconductor layers 231 and 233 are made of gallium nitride. (GaN), the constituent material of the second semiconductor layer 232 is aluminum gallium nitride (AlGaN). It is to be noted that the film structure of the semiconductor unit 23 may further form an AlGaN semiconductor layer made of aluminum gallium nitride (AlGaN) between the first semiconductor layer 231 and the substrate 21 as needed, or Further forming a plurality of semiconductor film layers each composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) to form a multi-layer structure of (AlGaN/GaN)n/GaN/AlGaN/GaN, n≧1, Since the related materials and film structures related to the semiconductor film layers are well known to those skilled in the art of HFMT, and are not the focus of the present technology, detailed descriptions thereof will not be repeated.
該帶負電層24含有多數負電荷，該等負電荷可為負離子或電子，形成於該半導體單元23部份的頂面往下的淺層區域。 The negatively charged layer 24 contains a plurality of negative charges, which may be negative ions or electrons, formed in a shallow region of the top surface of the portion of the semiconductor unit 23.
詳細的說，該帶負電層24可以是利用ICP-RIE(CF4、SF6)(感應耦合電漿反應離子蝕刻)，於氮氣腔體內，在上、下電極分別為800/150W，且處理時間為100秒的條件下，令複數由電漿強化後的反應離子氣體轟擊該第三半導體層233的部份表面，對該第三半導體層233進行氟離子電漿表面處理，而於該第三半導體層233經由氟離子電漿表面處理後的區域形成該帶負電層24，而令該帶負電層24位於該第三半導體層233的表面往下的淺層區域。 In detail, the negatively charged layer 24 may be ICP-RIE (CF 4 , SF 6 ) (inductively coupled plasma reactive ion etching) in a nitrogen chamber, and the upper and lower electrodes are respectively 800/150 W, and processed. The surface of the third semiconductor layer 233 is bombarded by the plasma-enhanced reactive ion gas under the condition of a time of 100 seconds, and the third semiconductor layer 233 is subjected to a fluoride ion plasma surface treatment. The third semiconductor layer 233 is formed with the negatively charged layer 24 via the surface treated by the fluoride ion plasma, and the negatively charged layer 24 is placed in the shallow region of the surface of the third semiconductor layer 233.
要補充說明的是，當該帶負電層24的氟離子濃度不足時(即氟離子電漿表面處理時間過短)，該帶負電層24無法有效截斷電流。 It should be additionally noted that when the concentration of the fluoride ion of the negatively charged layer 24 is insufficient (that is, the surface treatment time of the fluoride ion plasma is too short), the negatively charged layer 24 cannot effectively interrupt the current.
該介電層25設置於部分的該半導體單元23的頂面，並覆蓋該帶負電層24。 The dielectric layer 25 is disposed on a portion of the top surface of the semiconductor unit 23 and covers the negatively charged layer 24.
該介電層25的材料選自下列群組之一：Al2O3、HfO2、La2O3、ZrO2、AlN、TiO2、Y2O3、Ta2O5、BST、STO。且是以化學氣相沉積(CVD)、電子束蒸鍍(E-gun evaporator)、機金屬氣相磊晶(MOVPE)，或原子層沉積(ALD)方式沉積而得。 The material of the dielectric layer 25 is selected from one of the group consisting of Al 2 O 3 , HfO 2 , La 2 O 3 , ZrO 2 , AlN, TiO 2 , Y 2 O 3 , Ta 2 O 5 , BST, STO. It is deposited by chemical vapor deposition (CVD), electron beam evaporation (E-gun), organic metal vapor phase epitaxy (MOVPE), or atomic layer deposition (ALD).
該電極單元26包括設置於該半導體單元23的頂面，且經由該介電層25彼此間隔的一源極261和一汲極 262；以及一設置於該介電層25上，並與該帶負電層24的位置相對應的閘極263，且其中，該閘極263的表面積不小於該帶負電層24的表面積。 The electrode unit 26 includes a source 261 and a drain disposed on a top surface of the semiconductor unit 23 and spaced apart from each other via the dielectric layer 25 262; and a gate 263 disposed on the dielectric layer 25 and corresponding to the location of the negatively charged layer 24, and wherein the surface area of the gate 263 is not less than the surface area of the negatively charged layer 24.
該閘極263、該源極261，及該汲極262的材料可選自下列常用的金屬群組之一組合：Ti、Al、Au、Cu，且可視需求而為單層或多層結構。由於該電極單元26的製備、膜層結構及材料選擇為本技術領域所習知，因此不再多加贅述。 The material of the gate 263, the source 261, and the drain 262 may be selected from one of the following common metal groups: Ti, Al, Au, Cu, and may be a single layer or a multilayer structure as desired. Since the preparation, film structure and material selection of the electrode unit 26 are well known in the art, no further details are provided.
本發明利用ICP-RIE(CF4、SF6)(感應耦合電漿反應離子蝕刻)對該半導體單元23進行氟離子電漿表面處理，令該半導體單元23於靠近頂面的表(淺)層區域形成帶有多數氟離子的帶負電層24，因此，可藉由該等氟離子消除對應於該閘極263下方，並位於該第一、二半導體層261、262接面(GaN/AlGaN)之間的2DEG電荷，令其在閘極偏壓為零時不導通，而得到常閉式(normal off)電晶體。此方式可避免習知利用凹陷式閘極結構，或直接於AlGaN/GaN界面進行氟離子電漿處理的方式，因為對該半導體材料的晶格結構造成破壞，所導致的例如片電阻增加及漏電流增加等問題。 The present invention performs fluorochemical plasma surface treatment on the semiconductor unit 23 by ICP-RIE (CF 4 , SF 6) (inductively coupled plasma reactive ion etching) so that the semiconductor unit 23 is on the top (shallow) layer near the top surface. The region forms a negatively charged layer 24 with a plurality of fluoride ions, and therefore, the fluoride ions can be removed by the lower portion of the gate 263 and located at the junction of the first and second semiconductor layers 261 and 262 (GaN/AlGaN). The 2DEG charge between them is such that it does not conduct when the gate bias is zero, resulting in a normally off transistor. This method can avoid the conventional method of using the recessed gate structure, or the fluoride ion plasma treatment directly at the AlGaN/GaN interface, because the lattice structure of the semiconductor material is damaged, resulting in, for example, increased sheet resistance and leakage. Problems such as increased current.
接著，利用一具體例詳細說明本發明該加強型高電子遷移率電晶體，當可更清楚明白。 Next, the reinforced high electron mobility transistor of the present invention will be described in detail using a specific example, which can be more clearly understood.
本發明加強型高電子遷移率電晶體的一具體例，其結構與該實施例大致相同，惟更加精確說明結構的實際厚度，及材料的選擇。 A specific example of the reinforced high electron mobility transistor of the present invention has substantially the same structure as the embodiment, but more precisely explains the actual thickness of the structure and the choice of materials.
於該具體例中，該基板的材料是矽(Si)，該緩衝層為選自氮化鎵或氮化鋁，該半導體單元是自該緩衝層向上，具有4層半導體層(依序為第一AlGaN層、第一GaN層、第二AlGaN層，及第二GaN層)的堆疊結構。 In this embodiment, the material of the substrate is bismuth (Si), the buffer layer is selected from gallium nitride or aluminum nitride, and the semiconductor unit is upward from the buffer layer and has four semiconductor layers (in order A stacked structure of an AlGaN layer, a first GaN layer, a second AlGaN layer, and a second GaN layer).
其中，該緩衝層的厚度約為5μm，該半導體單元中各膜層(第一AlGaN層/第一GaN層/第二AlGaN層/第二GaN層)的厚度分別為10nm/1μm/25nm/1.5nm。 Wherein, the thickness of the buffer layer is about 5 μm, and the thickness of each of the film layers (the first AlGaN layer/the first GaN layer/the second AlGaN layer/the second GaN layer) in the semiconductor unit is 10 nm/1 μm/25 nm/1.5, respectively. Nm.
該帶負電層位於該第二GaN層的表面往下的淺層表面。 The negatively charged layer is located on a shallow surface of the surface of the second GaN layer.
該介電層覆蓋該帶負電層，該閘級位於該介電層上，且該閘級的正投影為完全遮覆該帶負電層；該源極及汲極位於該介電層的兩側，而位於該第二GaN層的表面。於本具體例中，該介電層為Al2O3，厚度為25nm，該閘極寬度為7μm，且該源極及該汲極是使用鈦/鋁/鈦/金(Ti/Al/Ti/Au)的膜層組成，厚度依序為25nm/1250nm/45nm/60nm。該閘極的使用鎳/金(Ni/Au)的膜層組成，後續依序為150nm/50nm。 The dielectric layer covers the negatively charged layer, the gate level is located on the dielectric layer, and the orthographic projection of the gate level completely covers the negatively charged layer; the source and the drain are located on both sides of the dielectric layer And located on the surface of the second GaN layer. In this embodiment, the dielectric layer is Al 2 O 3 , the thickness is 25 nm, the gate width is 7 μm, and the source and the drain are made of titanium/aluminum/titanium/gold (Ti/Al/Ti). /Au) The film composition has a thickness of 25 nm / 1250 nm / 45 nm / 60 nm. The gate was composed of a nickel/gold (Ni/Au) film layer, followed by a sequence of 150 nm/50 nm.
茲將前述該加強型高電子遷移率電晶體的具體例的製作方法說明如下。 A method for producing a specific example of the above-described reinforced high electron mobility transistor will be described below.
首先自一基板表面，利用化學氣相沉積(MOCVD)方式形成該緩衝層，接著，再利用MOCVD方式，自該緩衝層表面依序沉積形成該第一AlGaN層、第一GaN層、第二AlGaN層、第二GaN層。然後利用濕式蝕刻，自該第二GaN層頂面向下蝕刻至該第一GaN層的部份表面露出，形 成一平台(mesa)，而得到該半導體單元。 First, the buffer layer is formed by chemical vapor deposition (MOCVD) from a substrate surface, and then the first AlGaN layer, the first GaN layer, and the second AlGaN are sequentially deposited from the surface of the buffer layer by MOCVD. Layer, second GaN layer. Then, by wet etching, a portion of the surface of the first GaN layer is exposed from the top surface of the second GaN layer to be exposed, and the surface is exposed. Forming a platform (mesa) to obtain the semiconductor unit.
接著，利用微影製程，於該第二GaN層表面形成具有二個彼此間隔之開口的遮罩，自該二個開口於該第二GaN層表面沉積形成兩個金屬層，接著，移除該遮罩，並對該兩個金屬層進行快速熱退火(870℃，N2條件、30sec)而得到該源極及汲極。 Then, a mask having two openings spaced apart from each other is formed on the surface of the second GaN layer by using a lithography process, and two metal layers are deposited on the surface of the second GaN layer from the two openings, and then the The source and the drain were obtained by masking and rapidly annealing the two metal layers (870 ° C, N 2 condition, 30 sec).
接著再利用第二次微影製程，於該第二GaN層表面形成一具有位於該源極及汲極之間的一開口的遮罩，然後自該開口對該第二GaN層進行氟離子電漿表面處理100秒，接著移除該遮罩，即可得到位於該第二GaN層，並鄰近該第二GaN層頂面的淺層區域的該帶負電層，且形成該帶負電層層後不須經過退火步驟即可進行後續製程。 Then, using a second lithography process, a mask having an opening between the source and the drain is formed on the surface of the second GaN layer, and then the second GaN layer is subjected to fluoride ionization from the opening. The surface of the slurry is treated for 100 seconds, and then the mask is removed to obtain the negatively charged layer located in the second GaN layer adjacent to the shallow region of the top surface of the second GaN layer, and after forming the negatively charged layer Subsequent processes can be performed without an annealing step.
再接著，使用ALD(Atomic Layer Deposition)在該第二GaN層的表面，對應該帶負電層的位置形成該介電層，最後，於該介電質層表面以濺鍍方式形成足以覆蓋該帶負電層範圍的閘極，即可製得本發明該加強型高電子遷移率電晶體。 Then, an ALD (Atomic Layer Deposition) is used to form the dielectric layer on the surface of the second GaN layer corresponding to the negative electrode layer, and finally, the surface of the dielectric layer is formed by sputtering to cover the tape. The reinforced high electron mobility transistor of the present invention can be obtained by the gate of the negative electrode layer.
接著將前述該具體例製得的加強型高電子遷移率電晶體進行物性與電性量測。 Next, the reinforced high electron mobility transistor prepared in the above specific example was subjected to physical properties and electrical measurements.
參閱圖2，圖2是該加強型高電子遷移率電晶體的SIMS(二次離子質譜分析圖)量測結果。本發明該具體例整體的結構自該介電層往下依序為Al2O3/帶負電層/GaN/AlGaN/GaN(25nm/1.5nm/25nm/1μm/10nm)。從SIMS結果可以看出，元素氟(F)的峰值約位於26nm處，因此證 實元素氟(F)位於第二GaN層的淺層表面區域。 Referring to FIG. 2, FIG. 2 is a SIMS (Secondary Ion Mass Spectrometry) measurement result of the reinforced high electron mobility transistor. The overall structure of this embodiment of the present invention is sequentially from the dielectric layer to Al 2 O 3 / negatively charged layer / GaN / AlGaN / GaN (25 nm / 1.5 nm / 25 nm / 1 μm / 10 nm). It can be seen from the SIMS results that the peak of the elemental fluorine (F) is located at about 26 nm, thus confirming that the elemental fluorine (F) is located in the shallow surface region of the second GaN layer.
此外，常閉式電晶體是在閘極偏壓(VGS)小於零時，由於該閘極正投影下方被空乏(沒有載子通過)，造成汲極電流(IDS)不導通。參閱圖3，圖3是說明該具體例在不同閘極偏壓(VGS)(0V、1V、2V、3V、4V、5V)之下，汲極電壓VDS對汲極電流(IDS)的變化。在圖3中，當閘極偏壓(VGS)為0V時，由於該等氟離子的作用，使得閘極正投影處的部分2DEG電荷被排除，使得汲極電流(IDS)為無法順利導通(IDS值為零)，且當閘極偏壓(VGS)漸漸增加時，汲極電流(IDS)始導通。證實了本發明可藉由表面氟離子電漿處理的方式而得到一常閉式電晶體。 In addition, the normally-closed transistor is such that when the gate bias voltage (V GS ) is less than zero, the gate current (I DS ) is not turned on due to the lack of space under the positive projection of the gate (no carrier passes). Referring to FIG. 3, FIG. 3 is a diagram illustrating the drain voltage V DS versus the drain current ( I DS ) of the specific example under different gate bias voltages (V GS ) (0V, 1V, 2V, 3V, 4V, 5V). The change. In Fig. 3, when the gate bias voltage (V GS ) is 0 V, due to the action of the fluorine ions, part of the 2DEG charge at the positive projection of the gate is excluded, so that the drain current (I DS ) is not smooth. Turned on (I DS value is zero), and when the gate bias (V GS ) gradually increases, the drain current (I DS ) begins to conduct. It was confirmed that the present invention can obtain a normally closed transistor by means of surface fluoride ion plasma treatment.
參閱圖4，圖4，為本發明該具體例(CF4電漿處理時間為100秒)在不同VDS(5V、10V、15V、20V)之下的VGS-IDS，由圖4可知當汲極偏壓(VDS)=5V時，臨界電壓(VTH)=0.7V，且無論汲極偏壓(VDS)=10V、15V，或20V時，汲極電流(IDS)的大小是與閘極偏壓(VGS)所施加的偏壓呈現相關性，證實了本發明的閘極偏壓(VGS)具有良好的電流控制性。 Referring to FIG. 4, FIG. 4 is a V GS -I DS of the specific example (CF 4 plasma processing time is 100 seconds) under different V DS (5V, 10V, 15V, 20V), which is known from FIG. 4 . When the drain bias voltage (V DS )=5V, the threshold voltage (V TH )=0.7V, and the drain current (I DS ) regardless of the drain bias voltage (V DS )=10V, 15V, or 20V The magnitude is related to the bias applied by the gate bias (V GS ), confirming that the gate bias (V GS ) of the present invention has good current control.
此外，要補充說明的是，VTH(臨界電壓)的大小可進一步透過該帶負電層的濃度來調控，當該帶負電層的濃度增加時，需要加上閘極偏壓(VGS)中和帶負電層，令2DEG能夠順利導通，因此，此時所需的VTH(臨界電壓)也隨之增大。 In addition, it should be added that the magnitude of V TH (threshold voltage) can be further regulated by the concentration of the negatively charged layer, and when the concentration of the negatively charged layer is increased, the gate bias (V GS ) needs to be added. With a negative layer, the 2DEG can be turned on smoothly, so the required V TH (threshold voltage) is also increased.
綜上所述，本發明藉由對該第二GaN層進行氟 離子電漿表面處理，於該閘極下方形成由多個負離子或電子構成的帶負電層，因此，可藉由該等負電荷消除對應於該閘極下方，並位於該第一、二半導體層(GaN/AlGaN)接面之間的2DEG的電荷，不僅製程簡單，且可避免習知的凹陷式閘極結構，或直接於AlGaN/GaN界面進行氟離子電漿處理的方式，對該半導體材料的晶格結構造成破壞，而影響電晶體特性，故確實能達成本發明之目的。 In summary, the present invention performs fluorine on the second GaN layer. The surface treatment of the ionic plasma forms a negatively charged layer composed of a plurality of negative ions or electrons under the gate, and therefore can be eliminated by the negative charge corresponding to the underside of the gate and located at the first and second semiconductor layers The charge of 2DEG between the (GaN/AlGaN) junctions is not only simple in process, but also avoids the conventional recessed gate structure, or the method of performing fluoride ion plasma treatment directly on the AlGaN/GaN interface. The lattice structure causes damage and affects the characteristics of the crystal, so that the object of the present invention can be achieved.
惟以上所述者，僅為本發明之實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。 However, the above is only the embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and the patent specification of the present invention are still It is within the scope of the patent of the present invention.
21‧‧‧基板 21‧‧‧Substrate
22‧‧‧緩衝層 22‧‧‧ Buffer layer
23‧‧‧半導體單元 23‧‧‧Semiconductor unit
231‧‧‧第一半導體層 231‧‧‧First semiconductor layer
232‧‧‧第二半導體層 232‧‧‧Second semiconductor layer
233‧‧‧第三半導體層 233‧‧‧ Third semiconductor layer
24‧‧‧帶負電層 24‧‧‧With negative layer
25‧‧‧介電層 25‧‧‧Dielectric layer
26‧‧‧電極單元 26‧‧‧Electrode unit
261‧‧‧源極 261‧‧‧ source
262‧‧‧汲極 262‧‧‧汲polar
263‧‧‧閘極 263‧‧‧ gate
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| TWI676293B (en) * | 2018-10-09 | 2019-11-01 | 世界先進積體電路股份有限公司 | Semiconductor devices and methods for forming same |
| CN111092118A (en) * | 2018-10-23 | 2020-05-01 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| US10804385B2 (en) | 2018-12-28 | 2020-10-13 | Vanguard International Semiconductor Corporation | Semiconductor devices with fluorinated region and methods for forming the same |
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| TW201251010A (en) * | 2011-02-16 | 2012-12-16 | Fujitsu Ltd | Semiconductor device, power-supply unit, amplifier and method of manufacturing semiconductor device |
| TW201407776A (en) * | 2012-08-09 | 2014-02-16 | Taiwan Semiconductor Mfg | High electron mobility transistor and method of forming the same |
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| TW201407776A (en) * | 2012-08-09 | 2014-02-16 | Taiwan Semiconductor Mfg | High electron mobility transistor and method of forming the same |
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| TWI676293B (en) * | 2018-10-09 | 2019-11-01 | 世界先進積體電路股份有限公司 | Semiconductor devices and methods for forming same |
| CN111092118A (en) * | 2018-10-23 | 2020-05-01 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN111092118B (en) * | 2018-10-23 | 2023-03-24 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| US10804385B2 (en) | 2018-12-28 | 2020-10-13 | Vanguard International Semiconductor Corporation | Semiconductor devices with fluorinated region and methods for forming the same |
| US11545567B2 (en) | 2018-12-28 | 2023-01-03 | Vanguard International Semiconductor Corporation | Methods for forming fluorine doped high electron mobility transistor (HEMT) devices |
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