TWI574365B - Integrated circuit structures and methods for forming the same - Google Patents
Integrated circuit structures and methods for forming the same Download PDFInfo
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Description
本揭示係有關於積體電路(integrated circuit，IC)結構及其製造方法，且特別是有關於多晶片模組(multi-chip-module)的積體電路結構。 The present disclosure relates to an integrated circuit (IC) structure and a method of fabricating the same, and more particularly to an integrated circuit structure for a multi-chip module.
積體電路通常形成於基底上，例如半導體晶圓。接合凸塊(bonding bump)/走線上方凸塊(bump-on-trace)為積體電路中互連結構的一部分。凸塊提供與積體電路裝置的介面，藉此建立與此裝置的電性連接。可利用傳統技術來將封裝引線(package terminal)連接至積體電路，例如使用熱壓(thermocompression)或熱聲波(thermosonic)打線接合及其他習知技術。 Integrated circuits are typically formed on a substrate, such as a semiconductor wafer. The bonding bump/bump-on-trace is part of the interconnect structure in the integrated circuit. The bumps provide an interface to the integrated circuit device thereby establishing an electrical connection to the device. Conventional techniques can be utilized to connect package terminals to integrated circuits, such as using thermocompression or thermosonic wire bonding and other conventional techniques.
晶片互連技術，例如覆晶(flip chip)，也稱為控制塌陷晶片連接(Controlled Collapse Chip Connection，C4)，將半導體裝置互連至具有焊接尖端放置於晶片輸出接點上的外部電路。焊料凸塊在進行最後的晶圓製程步驟期間，放置於晶圓頂端的晶片接墊上。為了將晶片安裝至外部電路(例如，電路板或另一晶片或晶圓)上，將晶片反置，使其頂端面向下，且其接觸墊覆蓋外部電路上相稱的接墊，接著焊料溢流於覆晶 與用於支撐外部電路的基底之間，以完成互連。相較於打線接合，在此晶片為直立安裝且利用接線將晶片接墊互連至外部電路。所完成的覆晶封裝遠小於傳統以載板為基礎的(carrier-based)系統，原因在於晶片是直接坐落於電路板上。當互連接線更短，可大幅降低電感及熱阻。因此，覆晶可容許更高速的裝置。 Wafer interconnect technology, such as flip chip, also known as Controlled Collapse Chip Connection (C4), interconnects semiconductor devices to external circuitry with solder tips placed on the wafer output contacts. The solder bumps are placed on the wafer pads on the top of the wafer during the final wafer processing step. In order to mount the wafer on an external circuit (for example, a circuit board or another wafer or wafer), the wafer is inverted with its top end facing down, and its contact pads cover the corresponding pads on the external circuit, followed by solder overflow. Flip chip Between the substrate used to support the external circuit to complete the interconnection. In contrast to wire bonding, the wafer is mounted upright and the wafer pads are interconnected to external circuitry using wires. The completed flip chip package is much smaller than the traditional carrier-based system because the wafer is directly on the board. When the interconnect wiring is shorter, the inductance and thermal resistance can be greatly reduced. Therefore, flip chip can allow for a higher speed device.
高密度覆晶互連的近來趨勢是在CPU及GPU封裝中採用圓形或近圓形的銅柱焊料凸塊(copper pillar solder bump)。對於傳統焊料凸塊來說，銅柱焊料凸塊為一種引人注目的替代物，原因在於其可提供不受接合打線間距影響的固定的支座(stand-off)。這是十分關鍵的，因為大部分的高密度電路具黏性的類高分子的黏著劑混合物進行底部填充，較小的支座會造成底部填充的黏著劑難以流動至晶片下方。 A recent trend in high-density flip-chip interconnects is the use of round or nearly circular copper pillar solder bumps in CPU and GPU packages. Copper stud bumps are a compelling alternative to conventional solder bumps because they provide a fixed stand-off that is unaffected by the bond wire spacing. This is critical because most high-density circuits have a viscous polymer-like adhesive mixture that is underfilled, and smaller mounts can cause underfilled adhesives to flow underneath the wafer.
然而，傳統上圓形的銅柱焊料凸塊存在數個缺點。其一為圓形的銅柱焊料凸塊的尺寸增加了互連結構，而限制用在互連接的金屬走線的間距大小。因此，現今的圓形銅柱焊料凸塊最終將成為IC工業中裝置持續微縮的瓶頸。 However, conventionally round copper pillar solder bumps have several disadvantages. One of the dimensions of the circular copper pillar solder bumps increases the interconnect structure and limits the spacing of the metal traces used for interconnection. As a result, today's round copper pillar solder bumps will eventually become the bottleneck for continued shrinkage of devices in the IC industry.
另一缺點在於封裝電路及下方各層的機械應力。此應力來自於晶片與封裝結構的熱膨脹不匹配。此應力對於具有介電常數低於3的超低介電常數(extra low K,ELK)介電層的電路來說特別關鍵。封裝變得更加的脆弱，導致各層間的分離。 Another disadvantage is the mechanical stress of the packaged circuit and the underlying layers. This stress is due to the wafer's thermal expansion mismatch with the package structure. This stress is particularly critical for circuits having an ultra low K (ELK) dielectric layer with a dielectric constant below 3. Encapsulation becomes more fragile, leading to separation between layers.
另外，在焊料凸塊對接墊界面處的大電流密度引起電遷移及電應力。由電遷移所造成的損害類型包含焊料接點內的微裂紋(microcracking)以及接合層的脫層(delamination)。 In addition, the large current density at the solder bump pad interface causes electromigration and electrical stress. Types of damage caused by electromigration include microcracking within solder joints and delamination of the bonding layer.
如此說來，我們所需的是可允許高密度間距的低應力互連電路。 In this sense, what we need is a low-stress interconnect circuit that allows high-density spacing.
在一些實施例中，本揭示提供積體電路(IC)結構，其包含第一基底，具有複數個導電特徵形成於一個表面上；複數個晶片與第一基底機械地接合並電性耦接，這些晶片中的第一晶片具有第一凸塊附著至這些導電特徵中的第一導電特徵，第一凸塊在平行於第一基底的此表面的平面中具有細長形剖面，且第一基底與第一晶片接合成一配置，使得第一凸塊的長軸係定位為指向第一基底的中心位置並背向第一晶片的中心位置。 In some embodiments, the present disclosure provides an integrated circuit (IC) structure including a first substrate having a plurality of conductive features formed on a surface; a plurality of wafers mechanically bonded to and electrically coupled to the first substrate, The first of the wafers has a first bump attached to the first conductive feature of the conductive features, the first bump having an elongated profile in a plane parallel to the surface of the first substrate, and the first substrate The first wafer is bonded in a configuration such that the major axis of the first bump is positioned to point toward a central location of the first substrate and facing away from a central location of the first wafer.
在一些其他實施例中，本揭示提供積體電路(IC)結構，其包含第一基底，具有複數個導電特徵形成於表面上；複數個晶片與第一基底機械地接合並電性耦接，這些晶片中的第一晶片具有第一子集的導電凸塊個別地附著至這些導電特徵中的第一子集，第一子集的導電凸塊在平行於此表面的平面中具有細長形剖面，且第一基底與第一晶片係接合成一配置，使得在上視圖中第一晶片的中心位置遠離第一基底的中心位置，且第一子集的導電凸塊具有各自的長軸定位指向第一基底的中心位置。 In some other embodiments, the present disclosure provides an integrated circuit (IC) structure including a first substrate having a plurality of conductive features formed on a surface; a plurality of wafers being mechanically bonded and electrically coupled to the first substrate, A first of the plurality of wafers has a first subset of conductive bumps individually attached to a first subset of the conductive features, the first subset of conductive bumps having an elongated profile in a plane parallel to the surface And the first substrate is bonded to the first wafer system in a configuration such that the central position of the first wafer is away from the center position of the first substrate in the upper view, and the conductive bumps of the first subset have respective long axis positioning directions The center position of the first substrate.
在另外一些實施例中，本揭示提供積體電路(IC)結構的製造方法，此方法包含接收定義複數個導電凸塊的IC設計布局；以及依據晶片與封裝基底之間的配置，當晶片接合至封裝基底時，重新塑形此積體電路設計布局上的此些導電凸塊 中的第一導電凸塊，藉此產生修改後的積體電路設計布局，其中第一導電凸塊具有細長形剖面，其具有沿著第一長軸的第一長度，且第一長軸具有平行於第一方向的第一定向，第一方向定義為在配置中從晶片的第一導電凸塊到封裝基底的中心位置。 In still other embodiments, the present disclosure provides a method of fabricating an integrated circuit (IC) structure, the method comprising receiving an IC design layout defining a plurality of conductive bumps; and when the wafer is bonded according to a configuration between the wafer and the package substrate Reshaping the conductive bumps on the integrated circuit design layout to the package substrate a first conductive bump, thereby creating a modified integrated circuit design layout, wherein the first conductive bump has an elongated profile having a first length along a first major axis and the first major axis has A first orientation parallel to the first direction, the first direction being defined as a central location from the first conductive bump of the wafer to the package substrate in the configuration.
100、190‧‧‧積體電路(IC)結構 100, 190‧‧‧ integrated circuit (IC) structure
102‧‧‧第一基底 102‧‧‧First substrate
104、104A、104B、104C、180‧‧‧晶片 104, 104A, 104B, 104C, 180‧‧‧ wafer
106‧‧‧走線上方凸塊接合結構 106‧‧‧Bump joint structure above the trace
108、108A、108B、182‧‧‧導電凸塊 108, 108A, 108B, 182‧‧‧ conductive bumps
110‧‧‧導電特徵/走線 110‧‧‧ Conductive features/wiring
112、166‧‧‧中心 112, 166‧‧" Center
113‧‧‧虛線 113‧‧‧ dotted line
114‧‧‧晶片基底 114‧‧‧ wafer base
116‧‧‧內連線結構 116‧‧‧Inline structure
118‧‧‧導電特徵 118‧‧‧Electrical characteristics
120‧‧‧保護層 120‧‧‧Protective layer
121‧‧‧導電柱 121‧‧‧conductive column
122‧‧‧介面層 122‧‧‧Interface
124‧‧‧焊料尖端 124‧‧‧ solder tip
125‧‧‧阻焊層 125‧‧‧solder layer
126‧‧‧導電材料層/凸塊下金屬化層(UBM) 126‧‧‧ Conductive material layer/under bump metallization (UBM)
128A‧‧‧第一方向 128A‧‧‧First direction
128B‧‧‧第二方向 128B‧‧‧second direction
130、132、134、136、138、140、142、144、146、150、152、154、160、162、164‧‧‧結構 130, 132, 134, 136, 138, 140, 142, 144, 146, 150, 152, 154, 160, 162, 164 ‧ ‧ structures
168‧‧‧長軸 168‧‧‧ long axis
170‧‧‧方向 170‧‧‧ Direction
192‧‧‧接墊 192‧‧‧ pads
194‧‧‧阻焊開口 194‧‧‧ solder mask opening
200、250‧‧‧方法 200, 250‧‧‧ method
202、204、206、208、210、212、214、216、218、220、222、252、254、256、258‧‧‧操作 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 252, 254, 256, 258‧‧‧ operations
D1‧‧‧第一尺寸 D1‧‧‧ first size
D2‧‧‧第二尺寸 D2‧‧‧ second size
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 The full disclosure is based on the following detailed description and in conjunction with the drawings. It should be noted that the illustrations are not necessarily drawn to scale in accordance with the general operation of the industry. In fact, it is possible to arbitrarily enlarge or reduce the size of the component for a clear explanation.
第1圖顯示依據本揭示的一些實施例建構之積體電路結構的上視圖。 1 shows a top view of an integrated circuit structure constructed in accordance with some embodiments of the present disclosure.
第2圖顯示依據一些實施例建構之第1圖的積體電路結構的剖面示意圖。 Fig. 2 is a cross-sectional view showing the structure of the integrated circuit of Fig. 1 constructed in accordance with some embodiments.
第3A圖顯示依據一些實施例建構之第1圖的積體電路結構的部分剖面示意圖。 Figure 3A is a partial cross-sectional view showing the integrated circuit structure of Figure 1 constructed in accordance with some embodiments.
第3B圖顯示依據一些其他實施例建構之第1圖的積體電路結構的部分剖面示意圖。 Fig. 3B is a partial cross-sectional view showing the integrated circuit structure of Fig. 1 constructed in accordance with some other embodiments.
第4-8圖顯示依據各種實施例建構之第1圖的積體電路結構的走線上方凸塊結構的上視圖。 4-8 are top views showing the structure of the bump above the trace of the integrated circuit structure of Fig. 1 constructed in accordance with various embodiments.
第9圖顯示依據一些實施例建構之第1圖的積體電路結構的部分上視圖。 Figure 9 is a partial top plan view showing the integrated circuit structure of Figure 1 constructed in accordance with some embodiments.
第10圖顯示依據本揭示的一些實施例建構之積體電路結構的上視圖。 Figure 10 shows a top view of an integrated circuit structure constructed in accordance with some embodiments of the present disclosure.
第11圖顯示依據本揭示的一些實施例建構之積體電路結構的上視圖。 Figure 11 shows a top view of an integrated circuit structure constructed in accordance with some embodiments of the present disclosure.
第12圖顯示依據本揭示的一些其他實施例建構之積體電路結構的上視圖。 Figure 12 shows a top view of an integrated circuit structure constructed in accordance with some other embodiments of the present disclosure.
第13圖顯示依據一些實施例建構之第12圖的積體電路結構的部分剖面示意圖。 Figure 13 is a partial cross-sectional view showing the integrated circuit structure of Fig. 12 constructed in accordance with some embodiments.
第14圖顯示依據本揭示的一些實施例之積體電路的製造方法的流程圖。 Figure 14 shows a flow chart of a method of fabricating an integrated circuit in accordance with some embodiments of the present disclosure.
第15圖顯示依據本揭示的一些實施例之方法的流程圖。 Figure 15 shows a flow chart of a method in accordance with some embodiments of the present disclosure.
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。 It is to be understood that the following disclosure of the specification provides many different embodiments or examples to implement various features of the invention. The disclosure of the present specification is a specific example of the various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the invention. For example, if the disclosure of the present specification describes forming a first feature on or above a second feature, that is, it includes an embodiment in which the formed first feature is in direct contact with the second feature. Also included is an embodiment in which additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact. In addition, different examples in the description of the invention may use repeated reference symbols and/or words. These repeated symbols or words are not intended to limit the relationship between the various embodiments and/or the appearance structures for the purpose of simplicity and clarity.
再者，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形 成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，在空間上的相關用語，例如”上/下”、”頂部/底部”、”垂直/水平”，係使本說明書容易表達而非限定一絕對方向。舉例來說，一上層及一下層可表示關於基底或是形成於一基底上的積體電路各自的關係，而非絕對方向。 Furthermore, if the disclosure of the present specification describes forming a first feature on or above a first feature, it means that it contains a shape. The embodiment in which the first feature is directly in contact with the second feature, and the additional feature is formed between the first feature and the second feature, and the first feature and the first feature are Embodiments in which the features may not be in direct contact. In addition, spatially related terms such as "up/down", "top/bottom", "vertical/horizontal" are used to make the description easy to express rather than define an absolute direction. For example, an upper layer and a lower layer may represent respective relationships with respect to a substrate or an integrated circuit formed on a substrate, rather than an absolute direction.
第1圖顯示依據本揭示的一些實施例建構之積體電路(IC)結構100的上視圖。第2圖顯示依據本揭示的一些實施例之IC結構100的剖面示意圖。IC結構100包含第一基底102。在一些實施例中，第一基底102為選自於由封裝基底、印刷電路板、中介層與半導體基底所組成的群組之基底。在一些其他實施例中，第一基底102為選自於由封裝基底、印刷電路板、中介層、半導體基底、介電基底、陶瓷基底與玻璃基底所組成的群組之基底。 1 shows a top view of an integrated circuit (IC) structure 100 constructed in accordance with some embodiments of the present disclosure. 2 shows a cross-sectional view of an IC structure 100 in accordance with some embodiments of the present disclosure. The IC structure 100 includes a first substrate 102. In some embodiments, the first substrate 102 is a substrate selected from the group consisting of a package substrate, a printed circuit board, an interposer, and a semiconductor substrate. In some other embodiments, the first substrate 102 is a substrate selected from the group consisting of a package substrate, a printed circuit board, an interposer, a semiconductor substrate, a dielectric substrate, a ceramic substrate, and a glass substrate.
IC結構100包含兩個或多個IC晶片104，例如第1圖顯示之例示性的晶片104A、104B與104C。這些晶片104接合至第一基底102並電性耦接至第一基底102。每一IC晶片104為形成於單一半導體基底的一積體電路，每一晶片104為半導體晶圓的一部分並具有形成於其上的積體電路。舉例來說，在製造完半導體晶圓後，此晶圓藉由切割穿透晶圓上的切割道而分離成複數個晶片。在一些實施例中，每一晶片104具有各自形成於其上的電路。 The IC structure 100 includes two or more IC wafers 104, such as the exemplary wafers 104A, 104B, and 104C shown in FIG. The wafers 104 are bonded to the first substrate 102 and electrically coupled to the first substrate 102. Each IC wafer 104 is an integrated circuit formed on a single semiconductor substrate, each wafer 104 being part of a semiconductor wafer and having an integrated circuit formed thereon. For example, after the semiconductor wafer is fabricated, the wafer is separated into a plurality of wafers by cutting through the dicing streets on the wafer. In some embodiments, each wafer 104 has circuitry that is each formed thereon.
作為說明的例子，晶片104包含半導體基底、各種 形成於其上的元件及形成於這些元件上並連接這些元件的互連結構，以形成積體電路。在一些實施例中，這些元件包含電晶體(例如場效電晶體)、感測器(例如影像感測器)、記憶體單元(例如隨機存取記憶體單元)、二極體、被動元件(例如電阻、電容及/或電感)及/或其他元件。每一晶片104(例如晶片104A、104B與104C)可包含不同的電路。此多個晶片104接合至第一基底102並電性連接至第一基底102以形成功能電路，以達成所需功能。在一些實施例中，這些晶片104具有形成於各自的前表面的電路，並將這些晶片104反置以與第一基底102接合，如此一來，這些電路被夾設於第一基底102與晶片半導體基底之間。 As an illustrative example, wafer 104 includes a semiconductor substrate, various The elements formed thereon and the interconnect structures formed on these elements and connected to form an integrated circuit. In some embodiments, these elements include a transistor (eg, a field effect transistor), a sensor (eg, an image sensor), a memory unit (eg, a random access memory unit), a diode, a passive component ( For example, resistors, capacitors and/or inductors) and/or other components. Each wafer 104 (e.g., wafers 104A, 104B, and 104C) can include different circuits. The plurality of wafers 104 are bonded to the first substrate 102 and electrically connected to the first substrate 102 to form a functional circuit to achieve the desired function. In some embodiments, the wafers 104 have circuits formed on respective front surfaces and the wafers 104 are inverted to engage the first substrate 102 such that the circuits are sandwiched between the first substrate 102 and the wafer. Between semiconductor substrates.
IC結構100更包含走線上方凸塊接合結構106，其同時作為接合特徵和在第一基底102與晶片104之間的電性連接。詳細來說，每一晶片104包含形成於晶片接合面上的複數個導電凸塊108。導電凸塊108透過內連線結構連接晶片的元件。第一基底102包含形成於第一基底102之接合表面上的複數個導電特徵(走線或內連線特徵)110，第一基底102可更包含形成於其上的內連線結構。舉例來說，印刷電路板可被使用作第一基底並包含其內連線結構。走線110連接至第一基底102的內連線結構並延伸至與一個凸塊接合的位置。導電凸塊108和走線110機械地接合在一起並電性連接以形成走線上方凸塊接合結構106。 The IC structure 100 further includes a trace upper bump bond structure 106 that serves as both an bond feature and an electrical connection between the first substrate 102 and the wafer 104. In detail, each wafer 104 includes a plurality of conductive bumps 108 formed on the wafer bonding surface. The conductive bumps 108 connect the components of the wafer through an interconnect structure. The first substrate 102 includes a plurality of conductive features (straightening or interconnecting features) 110 formed on the bonding surface of the first substrate 102, and the first substrate 102 may further include an interconnect structure formed thereon. For example, a printed circuit board can be used as the first substrate and includes its interconnect structure. The trace 110 is connected to the interconnect structure of the first substrate 102 and extends to a position where it is bonded to one bump. Conductive bumps 108 and traces 110 are mechanically bonded together and electrically connected to form a bump upper bond structure 106.
在一些實施例中，走線包含的材料係選自於由銅、銅/鎳合金、銅-浸鍍錫(immersion Sn，IT)、銅-無電電鍍鎳無電電鍍鈀浸鍍金(electroless nickel electroless palladium immersion gold，ENEPIG)、銅-有機可焊性防腐劑(organic solderability preservatives，OSP)、鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物、銅合金、鉭、氮化鉭及前述之組合所組成的群組。 In some embodiments, the traces comprise materials selected from the group consisting of copper, copper/nickel alloys, immersion tin (IT), copper-electroless nickel electroless nickel plating (electroless nickel electroless) Palladium Immersion gold, ENEPIG), organic solderability preservatives (OSP), aluminum, aluminum/bismuth/copper alloys, titanium, titanium nitride, tungsten, polycrystalline germanium, metal telluride, copper alloys, tantalum, A group consisting of tantalum nitride and combinations of the foregoing.
如第1圖所示，從上視圖來看，第一基底102具有幾何中心112。相較之下，在上視圖中，每一晶片104具有自己的幾何中心(未顯示於第1圖)。舉例來說，矩形形狀的晶片具有位於距離相對的邊緣(各自沿著長軸與垂直軸)等距離的幾何中心。在本揭示的實施例中，從上視圖來看，晶片104的幾何中心與第一基底102的幾何中心112不重疊或彼此分隔開。在一特別的例子中，一個晶片104可具有與第一基底102的幾何中心112重疊的中心。因為各種晶片直接設置於第一基底102的不同位置並直接接合至第一基底102，從上視圖來看，剩餘的晶片無法與第一基底102同中心。一般來說，晶片104的中心不會與中心112重疊。 As shown in FIG. 1, the first substrate 102 has a geometric center 112 as seen from a top view. In contrast, in the top view, each wafer 104 has its own geometric center (not shown in Figure 1). For example, a rectangular shaped wafer has geometric centers that are equidistant from opposite edges (each along the major axis and the vertical axis). In the disclosed embodiment, the geometric center of the wafer 104 does not overlap or be spaced apart from the geometric center 112 of the first substrate 102 from a top view. In a particular example, a wafer 104 can have a center that overlaps the geometric center 112 of the first substrate 102. Since the various wafers are disposed directly at different locations of the first substrate 102 and directly bonded to the first substrate 102, the remaining wafers cannot be concentric with the first substrate 102 from a top view. In general, the center of the wafer 104 does not overlap the center 112.
雖然從上視圖來看是看不到導電凸塊108的，因為其被各自的晶片半導體基底覆蓋，但是晶片104的導電凸塊108也顯示於第1圖以便說明。導電凸塊108從剖面圖來看(或從上視圖來看)具有細長形的形狀。因此，每一導電凸塊108具有長軸與短軸。此外，將每一導電凸塊108定位，使得其長軸朝向第一基底102的中心112。第1圖的虛線顯示一個導電凸塊108的長軸定位在指向中心112的方向。因為晶片104的中心不與中心112重疊，晶片的導電凸塊108大抵上沒有朝向晶片的中心定位。當凸塊指向中心112時，一個晶片的少數凸塊可能發生指 向晶片的中心，但是大部分的導電凸塊108係定位為使其指向遠離晶片的中心。然而，晶片104的所有導電凸塊108大致上指向中心112，這更顯示於第9圖，其為依據本揭示的一些實施例之IC結構100的部分上視圖。詳細來說，當晶片104A接合至第一基底102，從上視圖來看，晶片104A的中心166被配置為遠離第一基底102的中心112。以導電凸塊108A為例，將細長形的導電凸塊108A定位，使得其長軸168被定位為指向中心112。然而，從導電凸塊108A到晶片中心166的方向170與長軸168不平行，而是兩者之間具有角度。 Although the conductive bumps 108 are not visible from the top view because they are covered by the respective wafer semiconductor substrate, the conductive bumps 108 of the wafer 104 are also shown in FIG. 1 for illustration. The conductive bumps 108 have an elongated shape as viewed in cross section (or from a top view). Therefore, each of the conductive bumps 108 has a long axis and a short axis. In addition, each of the conductive bumps 108 is positioned such that its long axis is toward the center 112 of the first substrate 102. The dashed line of Figure 1 shows that the long axis of one of the conductive bumps 108 is oriented in a direction toward the center 112. Because the center of the wafer 104 does not overlap the center 112, the conductive bumps 108 of the wafer are substantially not oriented toward the center of the wafer. When the bump points to the center 112, a few bumps of a wafer may occur To the center of the wafer, but most of the conductive bumps 108 are positioned such that they are directed away from the center of the wafer. However, all of the conductive bumps 108 of the wafer 104 are generally directed toward the center 112, which is further illustrated in FIG. 9, which is a partial top view of the IC structure 100 in accordance with some embodiments of the present disclosure. In detail, when the wafer 104A is bonded to the first substrate 102, the center 166 of the wafer 104A is configured to be away from the center 112 of the first substrate 102 from a top view. Taking the conductive bumps 108A as an example, the elongated conductive bumps 108A are positioned such that their long axes 168 are positioned to point toward the center 112. However, the direction 170 from the conductive bump 108A to the wafer center 166 is not parallel to the major axis 168, but rather has an angle therebetween.
此外，每一凸塊具有自己各自的定位。由於各種凸塊設置於不同的位置且都向著中心112定位，因此這些凸塊具有各自的定向以達到這些需求。 In addition, each bump has its own positioning. Since the various bumps are placed at different locations and are both oriented toward the center 112, the bumps have their respective orientations to meet these needs.
在本揭示的實施例中，形成於第一基底102上的走線110與整合至第一基底102之晶片104的導電凸塊108配對。這些配對的導電凸塊108與走線110各自地接合在一起，並形成走線上方凸塊接合結構106，從而整合晶片104至第一基底102以形成多晶片模組。為了當晶片104接合至第一基底102能適當的接合，配對的導電凸塊108與走線110被設計為凸塊108與配對的走線110重疊(例如與配對走線110的末端重疊)。在一些實施例中，導電凸塊108與導電特徵110被設計為當將晶片104反置並放置於第一基底102上時，配對的導電凸塊108與走線110的接合部分大致上各自地重疊。在後續的接合製程中，使用熱處理製程並可能在凸塊與導電特徵之間產生接合應力，這是因為第一基底102與晶片104之間不同的熱膨脹係數所造成。在一些 其他考慮到熱膨脹的實施例中，晶片104及/或第一基底102被設計為具有偏移(offsets)，如此一來，配對的導電凸塊108和走線110的接合部分接合在一起來彌補第一基底102與晶片104之間的不匹配。 In an embodiment of the present disclosure, traces 110 formed on first substrate 102 are paired with conductive bumps 108 that are integrated into wafers 104 of first substrate 102. The pair of conductive bumps 108 and the traces 110 are individually bonded together and form a trace upper bump bond structure 106 to integrate the wafer 104 to the first substrate 102 to form a multi-wafer module. To enable proper bonding of the wafer 104 to the first substrate 102, the paired conductive bumps 108 and traces 110 are designed such that the bumps 108 overlap with the mating traces 110 (e.g., overlap the ends of the mating traces 110). In some embodiments, the conductive bumps 108 and the conductive features 110 are designed to substantially separate the mating portions of the mating conductive bumps 108 and the traces 110 when the wafer 104 is inverted and placed on the first substrate 102. overlapping. In a subsequent bonding process, a heat treatment process is used and joint stress may be created between the bumps and the conductive features due to the different coefficients of thermal expansion between the first substrate 102 and the wafer 104. In some In other embodiments in which thermal expansion is contemplated, the wafer 104 and/or the first substrate 102 are designed to have offsets such that the mating conductive bumps 108 and the bonding portions of the traces 110 are bonded together to compensate A mismatch between the first substrate 102 and the wafer 104.
走線110也設計為具有細長形狀且走線110的接合部分與各自配對的凸塊108同軸定向。詳細來說，走線110的接合部分的長軸沿著配對凸塊108的長軸定位，從而形成具有最大化的接合面積與接合強度的走線上方凸塊接合結構106。 The traces 110 are also designed to have an elongated shape and the joint portions of the traces 110 are oriented coaxially with the respective mating bumps 108. In detail, the major axis of the joint portion of the trace 110 is positioned along the long axis of the mating bump 108 to form the upper bump bond structure 106 with maximized joint area and joint strength.
第3A圖為依據本揭示的一些實施例建構之IC結構100的部分剖面示意圖。詳細來說，第3圖包含例示性的晶片104和例示性的走線上方凸塊接合結構106(例如在第2圖的虛線113中的一個)以顯示更多細節特徵。參考第1-3圖進一步描述IC結構100。 3A is a partial cross-sectional view of an IC structure 100 constructed in accordance with some embodiments of the present disclosure. In detail, FIG. 3 includes an exemplary wafer 104 and an exemplary over-bump bond structure 106 (eg, one of the dashed lines 113 in FIG. 2) to show more detailed features. The IC structure 100 is further described with reference to Figures 1-3.
晶片104包含晶片基底114。在一些實施例中，晶片基底14為半導體基底，例如半導體晶圓的一部分。在本揭示的例子中，晶片基底114為矽基底。在一些其他例子中，晶片基底114可包含其他半導體基底(例如藍寶石基底，包含其他半導體材料(例如鍺、矽鍺、碳化矽、砷化鎵))或包含絕緣層覆矽(silicon-on-insulator，SOI)基底。晶片104也包含形成於晶片基底114上的各種元件(例如電晶體、二極體、感測器及/或被動元件)。 Wafer 104 includes a wafer substrate 114. In some embodiments, wafer substrate 14 is a semiconductor substrate, such as a portion of a semiconductor wafer. In the example of the present disclosure, wafer substrate 114 is a germanium substrate. In some other examples, wafer substrate 114 may comprise other semiconductor substrates (eg, sapphire substrates, including other semiconductor materials (eg, tantalum, niobium, tantalum carbide, gallium arsenide)) or silicon-on-insulators. , SOI) substrate. Wafer 104 also includes various components (e.g., transistors, diodes, sensors, and/or passive components) formed on wafer substrate 114.
晶片104更包含形成於晶片基底114上的內連線結構116，其被設計為連接元件至功能電路。內連線結構116包含各種導電特徵(例如金屬線、金屬接點和金屬導通孔特徵)用於 電性連接，以及一個或多個隔離用的介電材料。在一些實施例中，內連線結構116包含多個金屬層。詳細來說，內連線結構116包含耦接導電凸塊108的導電特徵118。在一些例子中，導電特徵118為內連線結構116的一個金屬層(例如頂部金屬層)內的金屬特徵。在一些其他例子中，導電特徵118為電性連接至內連線結構116的接合墊。導電特徵118可包含銅、鋁、其他合適的導電材料或前述之組合。晶片104也可包含形成於內連線結構116上的保護層，其被設計為提供對電路(元件及內連線結構116)的保護，使得電路可不被環境損害(例如濕氣劣化)。 The wafer 104 further includes an interconnect structure 116 formed on the wafer substrate 114 that is designed to connect the components to the functional circuitry. The interconnect structure 116 includes various conductive features (eg, metal lines, metal contacts, and metal via features) for Electrically connected, and one or more dielectric materials for isolation. In some embodiments, interconnect structure 116 includes a plurality of metal layers. In detail, the interconnect structure 116 includes conductive features 118 that couple the conductive bumps 108. In some examples, the conductive features 118 are metal features within one metal layer (eg, the top metal layer) of the interconnect structure 116. In some other examples, the conductive features 118 are bond pads that are electrically connected to the interconnect structure 116. Conductive features 118 can comprise copper, aluminum, other suitable electrically conductive materials, or a combination of the foregoing. The wafer 104 may also include a protective layer formed on the interconnect structure 116 that is designed to provide protection to the circuitry (element and interconnect structure 116) such that the circuitry may not be damaged by the environment (eg, moisture degradation).
走線上方凸塊接合結構106形成於接合製程後，並包含導電凸塊108和走線110(導電特徵)接合在一起。在一些實施例中，導電凸塊108包含導電柱121，例如銅柱或其他金屬或金屬合金的導電柱。導電柱121在其一末端電性連接至導電特徵118(例如穿過保護層120或更詳細來說，穿過保護層120的開口)。導電柱121透過貫穿末端的介面層122附著至焊料尖端124，接著將晶片104反置以面向第一基底102的走線110。在一些實施例中，第一基底102可更包含阻焊層(或防焊層)125提供保護，例如保護第一基底102的非接合區遠離焊料。在一些其他實施例中，將阻焊層125圖案化以形成開口，使得走線110暴露以與導電凸塊108接合。 The upper bump bonding structure 106 is formed after the bonding process and includes conductive bumps 108 and traces 110 (conductive features) bonded together. In some embodiments, the conductive bumps 108 comprise conductive pillars 121, such as copper pillars or other metal or metal alloy conductive pillars. The conductive post 121 is electrically connected at one end thereof to the conductive feature 118 (eg, through the protective layer 120 or, more specifically, through the opening of the protective layer 120). The conductive pillars 121 are attached to the solder tip 124 through the interfacial interface layer 122, and then the wafer 104 is inverted to face the traces 110 of the first substrate 102. In some embodiments, the first substrate 102 can further include a solder mask (or solder mask) 125 to provide protection, such as protecting the non-bonded regions of the first substrate 102 away from the solder. In some other embodiments, the solder mask layer 125 is patterned to form openings such that the traces 110 are exposed to bond with the conductive bumps 108.
走線上方凸塊接合結構106可具有不同的設計，例如不同的材料層以達到更好的接合效果與其他例如電性連接及保護的整合的考慮。第3B圖為依據本揭示的一些其他實施例建構之IC結構100的部分剖面示意圖。導電柱121透過一個或多 個另外的導電材料層126，例如凸塊下金屬化層(under bump metallization，UBM)，連接至內連線結構116(詳細來說，連接至導電特徵118)。UBM126可提供低電阻的電性連接至導電特徵118，提供良好黏著至導電特徵118和保護層120，以產生氣密密封，避免其他凸塊金屬擴散進入IC，並可以被凸塊金屬濕潤。UBM需要多層不同金屬，例如黏著層、擴散阻障層、可焊接層和氧化阻障層。在一些例子中，UBM126包含鈦、鉻、鋁、銅、鎳、金、一種或多種上述金屬的合金或每一層為上述金屬和合金之組合的多層薄膜堆疊。在其他例子中，UBM126包含黏著層(例如Ti/Cr/Al層)、擴散阻障層(例如Cr：Cu層)和焊料濕潤層(例如Cu/Ni：V層)。 The upper bump bonding structure 106 can have different designs, such as different material layers to achieve better bonding effects and other integration considerations such as electrical connections and protection. 3B is a partial cross-sectional view of an IC structure 100 constructed in accordance with some other embodiments of the present disclosure. Conductive column 121 through one or more An additional layer of conductive material 126, such as an under bump metallization (UBM), is attached to the interconnect structure 116 (in detail, to the conductive features 118). The UBM 126 can provide a low resistance electrical connection to the conductive features 118, providing good adhesion to the conductive features 118 and the protective layer 120 to create a hermetic seal that prevents other bump metal from diffusing into the IC and can be wetted by the bump metal. UBM requires multiple layers of different metals, such as an adhesion layer, a diffusion barrier layer, a solderable layer, and an oxidation barrier layer. In some examples, UBM 126 comprises an alloy of titanium, chromium, aluminum, copper, nickel, gold, one or more of the foregoing metals, or a multilayer film stack in which each layer is a combination of the foregoing metals and alloys. In other examples, UBM 126 includes an adhesion layer (eg, a Ti/Cr/Al layer), a diffusion barrier layer (eg, a Cr:Cu layer), and a solder wetting layer (eg, a Cu/Ni:V layer).
導電凸塊108與走線110的幾何形狀、相對位置和尺寸可參考本揭示的其他實施例的其他圖式進一步描述。 The geometry, relative position and dimensions of the conductive bumps 108 and traces 110 can be further described with reference to other figures of other embodiments of the present disclosure.
請參照第4圖，其為依據本揭示的一些實施例之IC結構100的部分上視圖。導電凸塊108設置於配對走線110的接合部分上，導電凸塊108具有細長形狀，其在第一方向128A跨出第一尺寸D1，並在第二方向128B跨出第二尺寸D2，D1大於D2。因此，將導電凸塊108沿著第一方向128A的軸稱為長軸，並將導電凸塊108沿著第二方向128B的軸稱為短軸。在一些實施例中，沿著此短軸，走線110的接合部分跨出的尺寸小於導電凸塊108對應的尺寸D2。凸塊108可具有不同的形狀。 Please refer to FIG. 4, which is a partial top view of an IC structure 100 in accordance with some embodiments of the present disclosure. The conductive bumps 108 are disposed on the joint portion of the mating traces 110. The conductive bumps 108 have an elongated shape that spans the first dimension D1 in the first direction 128A and the second dimension D2 in the second direction 128B, D1 Greater than D2. Therefore, the axis of the conductive bump 108 along the first direction 128A is referred to as the major axis, and the axis of the conductive bump 108 along the second direction 128B is referred to as the minor axis. In some embodiments, along this short axis, the joint portion of the trace 110 spans a dimension that is smaller than the corresponding dimension D2 of the conductive bump 108. The bumps 108 can have different shapes.
請參照第5圖，其顯示依據本揭示的一些實施例之細長形走線上方凸塊接合結構之三個例示性結構的上視圖。結構130包含形成於走線110上的導電凸塊108，凸塊的形狀為具 有兩側凸起彎曲的矩形。此矩形的細長軸與走線110同軸延伸，即平行或接***行於走線110的軸。結構132包含形成於走線110上的橢圓形狀導電凸塊108，此橢圓形的長軸也與走線110同軸。相似地，結構134包含形成於走線110上的膠囊形狀凸塊108，此導電凸塊108的長軸也與走線110同軸。這些細長的凸塊的長軸對齊走線方向使凸塊的側邊至最靠近的相鄰走線的空間最大化。本實施例的上述特徵使圖案化凸塊和接合間距能夠更密集，因此達到更緊密的金屬間隔設計規則。 Referring to FIG. 5, there is shown a top view of three exemplary configurations of the bump-bonding structure above the elongated traces in accordance with some embodiments of the present disclosure. The structure 130 includes a conductive bump 108 formed on the trace 110. The shape of the bump is There are rectangles that are convexly curved on both sides. The elongated axis of the rectangle extends coaxially with the trace 110, i.e., parallel or nearly parallel to the axis of the trace 110. Structure 132 includes elliptical shaped conductive bumps 108 formed on traces 110, the long axes of which are also coaxial with traces 110. Similarly, structure 134 includes a capsule shaped bump 108 formed on trace 110, the long axis of which is also coaxial with trace 110. The long axes of these elongated bumps are aligned to the routing direction to maximize the space from the sides of the bumps to the nearest adjacent traces. The above features of this embodiment enable the patterning bumps and joint pitch to be denser, thus achieving a tighter metal spacing design rule.
在一些實施例中，IC結構100具有混合式的配置結構，其包含具有配置與定向如上述的細長形導電凸塊108之一子集的晶片104，和具有不同設計的凸塊之另一個子集的晶片104，例如具有從上視圖來看為圓形或方形的凸塊。第10圖顯示具有混合式的配置結構之IC結構100的上視圖。在第10圖中，IC結構100包含例示性的晶片104A和104B，將其設計為具有定位朝向第一基底102的中心112的細長形凸塊。此IC結構100更包含例示性的晶片180，其具有傳統的導電凸塊182，例如圓形、方形或其他形狀的凸塊，其在互相垂直的軸上具有大致相似的尺寸，這些凸塊被統稱為對稱的凸塊。在混合式的IC結構100中，將具有細長形的凸塊的晶片104設計成與第1圖的晶片相似。舉例來說，將細長形的導電凸塊108定位朝向中心112並與對應的走線110同軸。 In some embodiments, the IC structure 100 has a hybrid configuration comprising a wafer 104 having a subset of the elongated conductive bumps 108 configured and oriented as described above, and another sub-block having a different design. The wafer 104 of the set has, for example, a bump that is circular or square in a top view. Figure 10 shows a top view of an IC structure 100 having a hybrid configuration. In FIG. 10, IC structure 100 includes exemplary wafers 104A and 104B that are designed to have elongated bumps that are oriented toward a center 112 of first substrate 102. The IC structure 100 further includes an exemplary wafer 180 having conventional conductive bumps 182, such as circular, square or other shaped bumps having substantially similar dimensions on mutually perpendicular axes, the bumps being They are collectively referred to as symmetrical bumps. In the hybrid IC structure 100, the wafer 104 having elongated bumps is designed to be similar to the wafer of FIG. For example, the elongated conductive bumps 108 are positioned toward the center 112 and are coaxial with the corresponding traces 110.
第6圖顯示本揭示的各種實施例之走線上方凸塊接合結構的上視圖。詳細來說，凸塊可在一個子集的晶片中為細長形或在另一個子集的晶片中為對稱的。結構136包含走線 110和在短軸上與走線110有相同尺寸的導電凸塊108(凸塊108與走線110完全重疊，因此無法看到凸塊108)。結構138包含走線110和圓形導電凸塊108。結構140包含走線110和方形導電凸塊108。在其他結構中，例如結構142、144和146，導電凸塊108具有如第6圖所示之不同形狀。 Figure 6 shows a top view of the upper bump bonding structure of the various embodiments of the present disclosure. In detail, the bumps may be elongated in one subset of wafers or symmetric in another subset of wafers. Structure 136 includes traces 110 and conductive bumps 108 having the same dimensions as the traces 110 on the short axis (the bumps 108 are completely overlapped with the traces 110, so the bumps 108 are not visible). Structure 138 includes traces 110 and circular conductive bumps 108. Structure 140 includes traces 110 and square conductive bumps 108. In other constructions, such as structures 142, 144, and 146, conductive bumps 108 have different shapes as shown in FIG.
在走線上方凸塊接合結構中，導電凸塊108與走線110可具有不同的相對尺寸。第7圖顯示本揭示的各種實施例之走線上方凸塊接合結構的上視圖。在結構150中，細長形的導電凸塊108在短軸上具有相較於走線更大的尺寸。在結構152中，細長形的導電凸塊108在短軸上具有與走線相同的尺寸。在結構154中，細長形的導電凸塊108在短軸上具有相較於走線更小的尺寸。 In the bump bonding structure above the trace, the conductive bumps 108 and the traces 110 may have different relative sizes. Figure 7 shows a top view of the upper bump bonding structure of the various embodiments of the present disclosure. In structure 150, the elongated conductive bumps 108 have a larger dimension on the short axis than the traces. In structure 152, the elongated conductive bumps 108 have the same dimensions on the stub axis as the traces. In structure 154, the elongated conductive bumps 108 have a smaller dimension on the short axis than the traces.
在走線上方凸塊接合結構中，可將導電凸塊108與走線110以不同的配置結構設置和重疊。第8圖顯示膠囊形凸塊與走線的相對位置。細長形的凸塊可突出於走線中心(結構160)，只重疊於走線的一側的一部分(結構162)或在走線的中間(結構164)。 In the bump bonding structure above the trace, the conductive bumps 108 and the traces 110 may be disposed and overlapped in different configurations. Figure 8 shows the relative position of the capsule-shaped bumps to the traces. The elongated bumps may protrude from the center of the trace (structure 160), overlapping only a portion of one side of the trace (structure 162) or intermediate the trace (structure 164).
第11圖更顯示依據一些實施例，具有走線上方凸塊接合結構的IC結構100與其配置結構的一部分之示意圖。在第11圖中，不標記各種晶片，且將導電凸塊108和對應的走線110顯示，以更好理解並與其他後面介紹的IC結構比較。在其他的實施例中，導電凸塊108限制走線110的可布線性(routability)。 Figure 11 further shows a schematic diagram of a portion of the IC structure 100 with the bump bonding structure above the trace and its configuration in accordance with some embodiments. In Fig. 11, various wafers are not marked, and conductive bumps 108 and corresponding traces 110 are shown for better understanding and comparison with other IC structures described later. In other embodiments, the conductive bumps 108 limit the routability of the traces 110.
雖然上述各種實施例的IC結構包含走線上方凸塊 接合結構，但是本揭示的範圍並不限於此。可合併其他接合結構，例如接墊上方凸塊(bump-on-pad)接合結構。依據一些實施例，第12圖顯示IC結構190的上視圖，第13圖顯示其剖面圖。IC結構190包含接墊上方凸塊接合結構以接合多個晶片104至封裝基底102。相似地，在第12圖中不標記各種晶片，且將導電凸塊108和對應的接墊192顯示以更好理解。第12、13圖所示的IC結構190係透過與上述各種圖式大致相同的步驟與製程製造並包含大致相似的結構(第1-2、3A、3B、4-10圖)。因此，第12-13圖所示之結構的製造步驟和特徵如上所述不重複於此以避免冗長的描述，但可完全地被應用於此實施例。與第1-2、3A、3B、4-10圖顯示之相同或大致相似的元件可以用相同或相似的標號，且與上述描述的第1-2、3A、3B、4-10圖具有相同或相似的結構、功能和製造方法。詳細來說，導電凸塊108具有細長形狀，其長軸定位朝向封裝基底102的中心112。在一些實施例中，IC結構190具有混合式結構，其更包含具有細長形狀的凸塊之第一子集的晶片104與具有傳統的凸塊之第二子集的晶片定位朝向中心112。在一些實施例中，將導電特徵118(和導電凸塊108)預先移位以作熱補償之用。 Although the IC structure of the various embodiments described above includes bumps above the traces The joint structure, but the scope of the present disclosure is not limited thereto. Other joint structures may be incorporated, such as a bump-on-pad joint structure. In accordance with some embodiments, Fig. 12 shows a top view of IC structure 190, and Fig. 13 shows a cross-sectional view thereof. The IC structure 190 includes a pad bump bonding structure over the pads to bond the plurality of wafers 104 to the package substrate 102. Similarly, various wafers are not labeled in Figure 12, and conductive bumps 108 and corresponding pads 192 are shown for better understanding. The IC structure 190 shown in Figs. 12 and 13 is manufactured through substantially the same steps and processes as those of the above various drawings, and includes substantially similar structures (Figs. 1-2, 3A, 3B, and 4-10). Therefore, the manufacturing steps and features of the structure shown in Figs. 12-13 are not repeated as described above to avoid lengthy description, but can be completely applied to this embodiment. Elements that are the same or substantially similar to those shown in Figures 1-2, 3A, 3B, and 4-10 may have the same or similar reference numerals and have the same dimensions as Figures 1-2, 3A, 3B, and 4-10 described above. Or similar structures, functions, and manufacturing methods. In detail, the conductive bumps 108 have an elongated shape with a long axis oriented toward the center 112 of the package substrate 102. In some embodiments, the IC structure 190 has a hybrid structure that further includes a wafer 104 having a first subset of bumps having an elongated shape and a wafer having a second subset of conventional bumps positioned toward the center 112. In some embodiments, conductive features 118 (and conductive bumps 108) are pre-shifted for thermal compensation.
封裝基底102包含複數個接合墊192(取代走線)被設計為與晶片104的導電凸塊108配對的配置。每一晶片104具有複數個接合至封裝基底102的對應接墊192的導電凸塊108。在第13圖中，將阻焊層125圖案化以形成阻焊開口194，如此一來暴露出下方的接墊192並將其透過焊接接合至導電凸塊108。因此，多個晶片104透過接墊上方凸塊接合結構接合至封 裝基底102。由於可避免走線110的限制，導電凸塊108具有更大的設計自由度，且因此達到更多的設計可行性。 The package substrate 102 includes a plurality of bond pads 192 (instead of traces) that are designed to mate with the conductive bumps 108 of the wafer 104. Each wafer 104 has a plurality of conductive bumps 108 bonded to corresponding pads 192 of package substrate 102. In FIG. 13, the solder mask layer 125 is patterned to form a solder resist opening 194 such that the underlying pads 192 are exposed and bonded to the conductive bumps 108 by soldering. Therefore, the plurality of wafers 104 are bonded to the seal through the bump bonding structure above the pads. The substrate 102 is loaded. Since the limitation of the traces 110 can be avoided, the conductive bumps 108 have greater design freedom and thus achieve more design feasibility.
第14圖顯示依據本揭示的一些實施例之IC結構100的製造方法200的流程圖。可以理解的是，在此方法的其他實施例中，可在方法200之前、期間和之後提供額外的步驟，且下面描述的一些步驟可被取代或消除。雖然下面描述為有關於走線上方凸塊結構，但是其大抵上也可應用於接墊上方凸塊結構。 Figure 14 shows a flow diagram of a method 200 of fabricating an IC structure 100 in accordance with some embodiments of the present disclosure. It will be appreciated that in other embodiments of the method, additional steps may be provided before, during, and after the method 200, and some of the steps described below may be replaced or eliminated. Although described below with respect to the bump structure above the trace, it can also be applied to the bump structure above the pad.
方法200從操作202開始，形成積體電路或部分地形成積體電路的一部分於晶片104上。操作202包含形成具有各自電路的多個晶片104(例如晶片104A、104B等等)。雖然在下面的描述僅提及一個晶片，但是可以理解的是，可在相似的技術中製造多個晶片。在一些例子中，在接合至基底102前，可同時或獨立地處理各種晶片。每一晶片104包含半導體基底，例如矽基底。或者，基底可包含其他的元素半導體材料，例如絕緣層覆矽(SOI)、鍺，化合物半導體例如碳化矽、砷化鎵、砷化銦和磷化銦，及合金半導體材料例如矽鍺、碳化矽鍺、磷化鎵砷和磷化鎵銦及/或其他習知的基底組成。 The method 200 begins at operation 202 by forming an integrated circuit or partially forming a portion of the integrated circuit on the wafer 104. Operation 202 includes forming a plurality of wafers 104 (e.g., wafers 104A, 104B, etc.) having respective circuits. Although only one wafer is mentioned in the following description, it will be understood that a plurality of wafers can be fabricated in a similar technique. In some examples, various wafers may be processed simultaneously or independently prior to bonding to substrate 102. Each wafer 104 includes a semiconductor substrate, such as a germanium substrate. Alternatively, the substrate may comprise other elemental semiconductor materials such as insulating layer overlay (SOI), germanium, compound semiconductors such as tantalum carbide, gallium arsenide, indium arsenide, and indium phosphide, and alloy semiconductor materials such as tantalum and tantalum carbide. Bismuth, gallium arsenide and gallium indium phosphide and/or other conventional substrate compositions.
使用例如導電層、半導體層和絕緣層設置於基底上以形成積體電路。在操作204形成在積體電路表面做為製造接合結構的開口，在操作206放置金屬層於積體電路表面，在操作208圖案化成互連用的所需膠囊形狀金屬柱，並在操作210蝕刻以形成出自於金屬層的膠囊形柱體。形成的互連柱狀結構提供積體電路的元件至封裝端子的店性接觸。互連結構的導電 柱的材料可包含例如鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭及/或其他合適的材料。形成互連柱狀結構的製程包含物理氣相沉積(或濺鍍)、化學氣相沉積(chemical vapor deposition，CVD)、電鍍及/或其他合適的製程。其他用以形成互連柱狀結構的製造技術可包含用於垂直柱之微影製程和將導電層圖案化的蝕刻，且可接著進行回蝕刻製程或化學機械研磨(chemical mechanical polish，CMP)製程。 The substrate is provided on the substrate using, for example, a conductive layer, a semiconductor layer, and an insulating layer to form an integrated circuit. An opening is formed in the integrated circuit surface as a fabrication joint structure at operation 204, a metal layer is placed on the integrated circuit surface at operation 206, patterned into a desired capsule-shaped metal pillar for interconnection at operation 208, and etched at operation 210. To form a capsule-shaped cylinder from the metal layer. The interconnected pillar structure formed provides a storey contact of the components of the integrated circuit to the package terminals. Conductive structure of interconnect structure The material of the column may include, for example, aluminum, aluminum/bismuth/copper alloy, titanium, titanium nitride, tungsten, polycrystalline germanium, metal telluride (for example, nickel telluride, cobalt telluride, tantalum telluride, antimony telluride, titanium telluride, antimony telluride, antimony telluride) , palladium or a combination thereof, copper, copper alloy, tantalum, tantalum nitride and/or other suitable materials. The process of forming the interconnected pillar structure includes physical vapor deposition (or sputtering), chemical vapor deposition (CVD), electroplating, and/or other suitable processes. Other fabrication techniques for forming interconnected pillar structures may include lithography for vertical pillars and etching of the conductive layer, and may be followed by an etch back process or a chemical mechanical polish (CMP) process. .
在後續的操作210中，放置焊料尖端於柱體的尖端上。在操作212中，反置含有積體電路的晶片使焊料尖端面向將被連接的走線110(或接合墊192)。 In a subsequent operation 210, the solder tip is placed on the tip of the cylinder. In operation 212, the wafer containing the integrated circuit is reversed such that the solder tip faces the trace 110 (or bond pad 192) to be connected.
方法200接著進行至操作214，形成導電層於隔開的基底102上，接著進行操作216，將導電層圖案化以形成走線(或接墊)。可透過例如包含形成光阻層、烘烤製程、曝光製程、顯影製程的微影製程、濕或乾蝕刻製程及/或其他合適的製程之技術實施於導電層上。在一些實施例中，形成走線上方凸塊結構，走線被佈線並連接至在不同的位置之基底102的其他內連線特徵。在一些其他實施例中，形成接墊上方凸塊結構，接墊連接至在相同的位置之基底102的下方內連線特徵。在其他實施例中，由於可避免走線的佈線，導電凸塊108獲得額外的設計自由度。 The method 200 then proceeds to operation 214 to form a conductive layer on the spaced apart substrate 102, followed by operation 216 to pattern the conductive layer to form traces (or pads). The conductive layer can be implemented by, for example, a lithography process including a photoresist layer, a baking process, an exposure process, a development process, a wet or dry etch process, and/or other suitable processes. In some embodiments, a bump structure above the traces is formed, the traces being routed and connected to other interconnect features of the substrate 102 at different locations. In some other embodiments, a bump structure above the pads is formed, the pads being connected to the lower interconnect features of the substrate 102 at the same location. In other embodiments, the conductive bumps 108 achieve additional design freedom since wiring of the traces can be avoided.
方法200接著進行至操作218，放置阻焊層並圖案化以形成內連接的開口。阻焊層可避免發生在定義的開口外的 任何內連接短路，在此開口走線暴露以配對焊料柱。在一些其他實施例中，形成接墊上方凸塊結構，形成阻焊開口194，如此一來暴露接墊192並透過焊料在阻焊開口194中與導電凸塊108接合。 The method 200 then proceeds to operation 218 where the solder mask is placed and patterned to form an interconnected opening. The solder mask can be avoided from occurring outside the defined opening Any internal connections are shorted, where the open traces are exposed to pair the solder columns. In some other embodiments, a bump structure over the pads is formed to form a solder mask opening 194 such that the pads 192 are exposed and bonded to the conductive bumps 108 in the solder mask openings 194 by solder.
方法200接著進行操作220，反置的晶片對齊第二基底且有著焊料尖端的柱體與導電走線重疊以形成互連。可施加許多的製程，例如熱空氣回焊或熱聲波接合將焊料尖端液化以形成互連。操作222透過使用黏著劑底部填充圍繞柱體的間隙完成接合，黏著劑例如為高分子材料以提供絕緣、支撐和穩定性。 The method 200 then proceeds to operation 220 where the inverted wafer is aligned with the second substrate and the pillar with the solder tip overlaps the conductive traces to form an interconnect. A number of processes can be applied, such as hot air reflow or thermoacoustic bonding to liquefy the solder tip to form an interconnect. Operation 222 accomplishes the bonding by filling the gap around the cylinder with an adhesive underfill, such as a polymeric material to provide insulation, support, and stability.
第15圖顯示依據本揭示的一些實施例之IC結構(例如第1圖、第10圖的IC結構100或第13圖的IC結構190)的製造方法250的流程圖。IC結構包含各種接合特徵，例如導電凸塊108和走線110(或導電凸塊108與接墊192)。第15圖的流程圖之方法250可包含製作IC結構100(或IC結構190)的一個操作子集。方法250開始於操作252，接收IC結構的IC設計。在一些實施例中，IC設計包含形成於各種晶片104上的電路和形成於第一基底102上的導電結構。詳細來說，形成於晶片104上的電路包含晶片的各種導電特徵118；且形成於第一基底102上的導電結構包含走線110(或接墊192)。在一些實施例中，第一基底102可更包含元件或電路形成於其上。在此情形下，IC設計也包含形成於第一基底102上的電路。 Figure 15 shows a flow diagram of a method 250 of fabricating an IC structure (e.g., IC structure 100 of Figure 1, Figure 10, or IC structure 190 of Figure 13) in accordance with some embodiments of the present disclosure. The IC structure includes various bonding features, such as conductive bumps 108 and traces 110 (or conductive bumps 108 and pads 192). The method 250 of the flowchart of FIG. 15 may include making an operational subset of the IC structure 100 (or IC structure 190). The method 250 begins at operation 252 by receiving an IC design of an IC structure. In some embodiments, the IC design includes circuitry formed on various wafers 104 and conductive structures formed on the first substrate 102. In detail, the circuitry formed on wafer 104 includes various conductive features 118 of the wafer; and the conductive structures formed on first substrate 102 include traces 110 (or pads 192). In some embodiments, the first substrate 102 can further include elements or circuitry formed thereon. In this case, the IC design also includes circuitry formed on the first substrate 102.
方法250也包含操作254，以作熱補償的預先移位，重新設計導電特徵118，導電凸塊108也一起移位。在一些 例子中，如果是在特定範圍內的不匹配的情況下，不將導電特徵118移位但是透過操作254將導電凸塊108移位。在一些例子中，不將導電特徵118移位但是透過操作254將走線110(或接墊192)移位，以提供在走線110(或接墊192)與配對的導電凸塊108之間相對的預先移位。 The method 250 also includes an operation 254 for pre-shifting the thermal compensation, redesigning the conductive features 118, and the conductive bumps 108 are also displaced together. In some In the example, if it is a mismatch in a particular range, the conductive features 118 are not displaced but the conductive bumps 108 are displaced by operation 254. In some examples, the conductive features 118 are not displaced but the traces 110 (or pads 192) are displaced by operation 254 to provide between the traces 110 (or pads 192) and the paired conductive bumps 108. Relative pre-shift.
依據走線上方凸塊接合結構106(或接墊上方凸塊接合結構)相對於中心112的位置和第一基底102與晶片104之間的熱膨脹差異，可個別地決定預先移位。如前所述，將導電特徵118預先移位，以補償晶片104與第一基底102之間在接合製程中由於晶片104與第一基底102不同的熱膨脹造成的不匹配。在接合製程期間，將晶片104和第一基底102加熱至較高的溫度然後冷卻。原始IC包含導電特徵118和走線110設計的設置為每一對(導電特徵118和走線110)彼此對齊，然而，當加熱後，第一基底102和晶片104由於不同的熱膨脹係數而不同地膨脹，這將在接合後造成不匹配或應力，其依據加熱和接合的順序而定。此不匹配(或應力)係有關於接合結構中的晶片104和第一基底102的相對配置，第一基底102和晶片104的熱膨脹係數及接合製程的最高加熱溫度。這些因素會決定不匹配。因為每一對的走線(或接墊)與凸塊相對於中心112具有不同的位置，其對應的不匹配可能彼此不同。操作254依據各自的不匹配來個別地重新設計每一對。在一些實施例中，接合製程可包含一個順序，其為先加熱第一基底102和晶片104，之後接觸並將其接合在一起。因此，在加熱的溫度中，因為已補償不匹配，每一對導電凸塊108和走線110(或接墊192)已匹配。可將此重新設計 以不同的方式實施來得到更好的接合結構，其考慮到位置的匹配、應力及/或接合強度。 The pre-shift can be individually determined depending on the position of the bump bonding structure 106 above the bump (or the bump bonding structure above the pad) relative to the center 112 and the difference in thermal expansion between the first substrate 102 and the wafer 104. As previously described, the conductive features 118 are pre-shifted to compensate for the mismatch between the wafer 104 and the first substrate 102 during the bonding process due to the different thermal expansion of the wafer 104 from the first substrate 102. During the bonding process, wafer 104 and first substrate 102 are heated to a higher temperature and then cooled. The original IC includes conductive features 118 and traces 110 designed to align each pair (conductive features 118 and traces 110) with each other, however, when heated, first substrate 102 and wafer 104 differ differently due to different coefficients of thermal expansion Expansion, which will cause mismatch or stress after joining, depending on the order of heating and joining. This mismatch (or stress) is related to the relative configuration of the wafer 104 and the first substrate 102 in the bonded structure, the coefficient of thermal expansion of the first substrate 102 and the wafer 104, and the maximum heating temperature of the bonding process. These factors will determine the mismatch. Because each pair of traces (or pads) and bumps have different positions relative to the center 112, their corresponding mismatches may differ from one another. Operation 254 individually redesigns each pair based on the respective mismatch. In some embodiments, the bonding process can include a sequence that first heats the first substrate 102 and the wafer 104, then contacts and bonds them together. Thus, in the heated temperature, each pair of conductive bumps 108 and traces 110 (or pads 192) have been matched because the compensation mismatch has been made. Can redesign this It is implemented in different ways to obtain a better joint structure that takes into account the matching of the position, the stress and/or the joint strength.
在一些實施例中，操作254也包含將上述的導電凸塊108重新塑形。舉例來說，重新塑形包含改變導電凸塊108使其具有細長形定向，如此一來，凸塊的長軸指向接合結構中的中心112。 In some embodiments, operation 254 also includes reshaping the conductive bumps 108 described above. For example, reshaping includes changing the conductive bumps 108 to have an elongated orientation such that the major axis of the bumps points toward the center 112 in the bonded structure.
方法250也可包含操作256，製作定義這些導電凸塊108的圖案的光罩和依據重新設計的IC設計圖案製作其他光罩。或者，當IC圖案直接形成於半導體基底，例如透過電子束直接寫入，這些圖案會以適當的形式(例如GDS形式)存在資料檔案中，並被使用於電子束微影。 The method 250 can also include an operation 256 of fabricating a mask defining the pattern of the conductive bumps 108 and fabricating other masks in accordance with the redesigned IC design pattern. Alternatively, when the IC pattern is formed directly on the semiconductor substrate, such as by direct writing through an electron beam, the patterns are stored in a data file in an appropriate form (e.g., in the form of GDS) and used in electron beam lithography.
方法250進行至操作258，製造IC結構(100或190)。IC結構的製造包含接合晶片104至第一基底102。在一些實施例中，IC結構的製造也包含形成第一基底102和晶片104。在本實施例中，IC結構的製造為方法200或相等於方法200的替代方法。 The method 250 proceeds to operation 258 to fabricate an IC structure (100 or 190). Fabrication of the IC structure includes bonding the wafer 104 to the first substrate 102. In some embodiments, fabrication of the IC structure also includes forming the first substrate 102 and the wafer 104. In the present embodiment, the fabrication of the IC structure is a method 200 or an alternative to method 200.
本揭示的實施例提供IC結構及其製造方法。在一些實施例中，IC結構(100或190)包含接合至基底102的多個晶片104。詳細來說，將晶片104中的凸塊或部分的凸塊設計為有著指向第一基底102中心112的長軸之細長形狀，並和配對的走線110同軸(如果接合結構為走線上方凸塊結構)。在一些實施例中，將凸塊預先移位來補償因不同的熱膨脹係數造成的不匹配。IC結構及其製造方法的各種實施例可呈現各種優勢。舉例來說，形成的IC結構因此具有強的接合強度和較少的不匹配情 形。 Embodiments of the present disclosure provide an IC structure and a method of fabricating the same. In some embodiments, the IC structure (100 or 190) includes a plurality of wafers 104 bonded to a substrate 102. In detail, the bumps or portions of the bumps in the wafer 104 are designed to have an elongated shape that is directed toward the long axis of the center 112 of the first substrate 102 and are coaxial with the mating traces 110 (if the joint structure is convex above the traces) Block structure). In some embodiments, the bumps are pre-shifted to compensate for mismatches due to different coefficients of thermal expansion. Various embodiments of the IC structure and method of fabricating the same can present various advantages. For example, the resulting IC structure thus has strong bond strength and less mismatch shape.
因此，本揭示提供依據一些實施例之積體電路(IC)結構。IC結構包含第一基底，其具有複數個導電特徵形成於一個表面上，且複數個晶片與第一基底機械地接合並電性耦接。這些晶片中的第一晶片具有第一凸塊附著至這些導電特徵中的第一導電特徵，第一凸塊在平行於第一基底的此表面的平面中具有細長形剖面。第一基底與第一晶片係接合成一配置，使得第一凸塊的長軸定位指向第一基底的中心位置並背向第一晶片的中心位置。 Accordingly, the present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a first substrate having a plurality of conductive features formed on a surface, and the plurality of wafers are mechanically bonded and electrically coupled to the first substrate. The first of the wafers has a first bump attached to the first conductive feature of the conductive features, the first bump having an elongated profile in a plane parallel to the surface of the first substrate. The first substrate is bonded to the first wafer system in a configuration such that the long axis of the first bump is positioned toward the center of the first substrate and away from the center of the first wafer.
本揭示也提供依據一些實施例之積體電路(IC)結構。積體電路結構包含第一基底，其具有複數個導電特徵形成於一個表面上，且複數個晶片與第一基底機械地接合並電性耦接，這些晶片中的第一晶片具有第一子集的導電凸塊個別地附著至這些導電特徵中的第一子集，第一子集的導電凸塊在平行於此表面的平面中具有細長形剖面。第一基底與第一晶片係接合成一配置，使得在上視圖中第一晶片的中心位置遠離第一基底的中心位置，且第一子集的導電凸塊具有各自的長軸定位指向第一基底的中心位置。 The present disclosure also provides an integrated circuit (IC) structure in accordance with some embodiments. The integrated circuit structure includes a first substrate having a plurality of conductive features formed on a surface, and a plurality of wafers are mechanically bonded and electrically coupled to the first substrate, the first of the wafers having the first subset The conductive bumps are individually attached to a first subset of the conductive features, the conductive bumps of the first subset having an elongated profile in a plane parallel to the surface. The first substrate is bonded to the first wafer system in a configuration such that the central position of the first wafer is away from the center position of the first substrate in the upper view, and the conductive bumps of the first subset have respective long axis orientations directed to the first The center position of the base.
本揭示也提供依據一些實施例之積體電路(IC)結構的製造方法，包含接收定義複數個導電凸塊的積體電路設計布局，且依據晶片與封裝基底之間的配置，當晶片接合至封裝基底時，重新塑形此積體電路設計上的這些導電凸塊中的第一導電凸塊，藉此產生修改後的積體電路設計布局。第一導電凸塊具有細長形剖面，其具有沿著第一長軸的第一長度，且第一 長軸具有平行於第一方向的第一定向，第一方向定義為在配置中從晶片的第一導電凸塊到封裝基底的中心位置。 The present disclosure also provides a method of fabricating an integrated circuit (IC) structure in accordance with some embodiments, comprising receiving an integrated circuit design layout defining a plurality of conductive bumps, and depending on the configuration between the wafer and the package substrate, when the wafer is bonded to When the substrate is packaged, the first conductive bumps of the conductive bumps on the integrated circuit design are reshaped, thereby producing a modified integrated circuit design layout. The first conductive bump has an elongated profile having a first length along the first major axis, and first The long axis has a first orientation parallel to the first direction, the first direction being defined as a central location from the first conductive bump of the wafer to the package substrate in the configuration.
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。 The foregoing summary of the invention is inferred by the claims It will be understood by those of ordinary skill in the art, and other processes and structures may be readily designed or modified on the basis of the present disclosure, and thus achieve the same objectives and/or achieve the same embodiments as those described herein. The advantages. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or alterations may be made in the present disclosure without departing from the spirit and scope of the invention.
100‧‧‧積體電路(IC)結構 100‧‧‧Integrated circuit (IC) structure
102‧‧‧第一基底 102‧‧‧First substrate
104A、104B、104C‧‧‧晶片 104A, 104B, 104C‧‧‧ wafer
108‧‧‧導電凸塊 108‧‧‧Electrical bumps
112‧‧‧中心 112‧‧‧ Center
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