TWI572018B - Memory device and fabricating method thereof - Google Patents

Description

記憶體元件及其製作方法 Memory element and manufacturing method thereof

本發明是有關於一種記憶體元件。特別是有關於一種立體記憶體陣列，其位元線和共同源極線被排列來提供簡單的佈線結構。 The invention relates to a memory component. In particular, there is a stereo memory array in which bit lines and common source lines are arranged to provide a simple wiring structure.

隨著積體電路的關鍵尺寸被微縮至一般記憶胞技術的極限。設計者尋求以多層記憶胞堆疊(stack multiple levels of memory cells)技術來取得較大的儲存容量(storage capacity)以及較低的位元成本(costs per bit)。例如，Lai et al.,“A Multi-Layer Stackable Thin-Film Transistor(TFT)NAND-Type Flash Memory,”IEEE Int'l Electron Devices Meeting,11-13 Dec.2006以及Jung et al.,“Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,”IEEE Int'l Electron Devices Meeting,11-13 Dec.2006提出將薄膜電晶體技術應用於電荷捕捉記憶體技術中。 As the critical dimensions of the integrated circuit are scaled down to the limits of general memory cell technology. Designers seek to achieve larger storage capacity and lower cost per bit with stack multiple levels of memory cells. For example, Lai et al. , "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006 and Jung et al. , "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node, "IEEE Int'l Electron Devices Meeting, 11-13 Dec.2006 proposes the application of thin film transistor technology in charge trapping memory technology .

Katsumata et al.,“Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers,2009.則提出另一種結構，提供一種應用電荷捕捉記憶體技術的NAND記憶胞。Katsumata et al所描述的結構包括一個垂直NAND閘極，並使用矽-矽氧化物-氮化矽-矽氧化物-矽(silicon-oxide-nitride-oxide-silicon，SONOS)的電荷捕捉技術，在每一個閘極/垂直通道介面(gate/vertical channel interface)上形成記憶儲位(memory sites)。此一記憶體結構是以一個柱狀的半導體材料作為基礎，用來作為NAND閘極的垂直通道、鄰接基材的下方選擇閘極(lower select gate)以及位於頂部的上方選擇閘極(upper select gate)。 Katsumata et al. , "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices," 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. A NAND memory cell using charge trapping memory technology. The structure described by Katsumata et al includes a vertical NAND gate and uses a charge-trapping technique of silicon-oxide-nitride-oxide-silicon (SONOS). Memory sites are formed on each gate/vertical channel interface. The memory structure is based on a columnar semiconductor material used as a vertical channel for the NAND gate, a lower select gate adjacent to the substrate, and a top select gate at the top (upper select) Gate).

複數條使用平面字元線層所構成的水平字元(horizontal word lines)與該柱狀半導體材料交叉，藉以在每一層中形成所謂的閘極圍繞式(gate-all-around)記憶胞。Katsumata et al指出此一結構可採用多位元寫入(multiple-bit-per-cell programming)技術來實施。多位元寫入技術需要對數以千計的控制電壓作精細的控制，這使得讀取和寫入干擾特性變得更加重要。因此，立體快閃技術即便具有高儲存密度，但是其儲存密度仍然有所限制。 A plurality of horizontal word lines formed by a layer of planar word lines intersect the columnar semiconductor material to form a so-called gate-all-around memory cell in each layer. Katsumata et al pointed out that this structure can be implemented using multiple-bit-per-cell programming techniques. Multi-bit write technology requires fine control over thousands of control voltages, making read and write interference characteristics even more important. Therefore, even if the stereo flash technology has a high storage density, its storage density is still limited.

由於複雜的後端佈線backend of line routings(BEOL routings)，使得低良率和高成本成為製造立體記憶體時的主要課題。 Due to the complicated backend of line routings (BEOL routings), low yield and high cost are the main issues when manufacturing stereo memory.

因此，有需要提供立體積體電路記憶體一種製作成本較低以及簡化後端佈線的結構，使其具有可靠、微小記憶單元以及高資料密度。 Therefore, there is a need to provide a bulk volume circuit memory with a low cost of fabrication and a simplified back-end wiring structure that provides reliable, small memory cells and high data density.

本說明書描述一種立體記憶體陣列，其係由包含有多個串連形式之奇數和偶數記憶胞的U型NAND串列所組成。偶數記憶胞位於偶數導電條帶堆疊結構(stacks of conductive strips)中，通過主動柱狀體(pillar)和導電條帶可存取的介面區(interface regions)上。奇數記憶胞位於奇數導電條帶堆疊結構中，通過主動柱狀體和導電條帶可存取的介面區上。主動柱狀體的頂部截頭體(top frustum)包括位於偶數端，且受偶數堆疊結構中頂部條帶之信號控制的第一開關，以及位於奇數端，且受奇數堆疊結構中頂部條帶之信號控制的第二開關，第一開關(例如，閘極選擇電晶體)可以用來將NAND串列連接至參考線，用以作為共同源極線。第二開關(例如，串列選擇電晶體)可以用來將NAND串列通過層間連接器(inter-level connector)連接至具有延伸部的位元線。參考線和層間連接器位於第一圖案化導電平面層(first level of patterned conductors)中。位元線和延伸部位於第二圖案化導電平面層(second level of patterned conductors)中。第一圖案化導電平面層即是立體記憶體陣列中的第一金屬層。控制電路係建構來對奇數和偶數條帶施加不同偏壓，並且是建構來對奇數和偶數條帶其中之一者或多者進行寫入操作。資料位元可以被同時儲存在位於被 選取串列之給定截頭體的奇數和偶數記憶胞中。 This specification describes a stereo memory array consisting of a U-shaped NAND string containing a plurality of odd and even memory cells in series. The even memory cells are located in even stacks of conductive strips through interface regions accessible by active pillars and conductive strips. The odd-numbered memory cells are located in an odd-numbered conductive strip stack structure that is accessible through active pillars and conductive strips. The top frustum of the active column includes a first switch at the even end and controlled by the signal of the top strip in the even stack structure, and at the odd end, and the top strip in the odd stack structure A second switch of signal control, a first switch (eg, a gate select transistor) can be used to connect the NAND string to the reference line for use as a common source line. A second switch (eg, a serial selection transistor) can be used to connect the NAND string to the bit line with the extension through an inter-level connector. The reference lines and the interlayer connectors are located in a first level of patterned conductors. The bit lines and extensions are located in a second level of patterned conductors. The first patterned conductive planar layer is the first metal layer in the stereo memory array. The control circuitry is constructed to apply different bias voltages to the odd and even strips and is constructed to perform write operations on one or more of the odd and even strips. Data bits can be stored simultaneously at the location The odd and even memory cells of a given truncated body are selected.

本說明書同時提供製作如前所述之記憶體元件的方法。一方面，此一製作方法包括在偶數和奇數導電條帶堆疊結構上形成第一圖案化導電平面層，其中第一圖案化導電平面層包括位於偶數堆疊結構上用來作為共同源極線的參考線，以及位於奇數堆疊結構上的跨平面層連接器。使用雙鑲嵌製程來形成具有延伸部位之位元線的第二圖案化導電平面層，其中延伸部係用以連接至對應的跨平面層連接器。 This specification also provides a method of making a memory component as described above. In one aspect, the fabrication method includes forming a first patterned conductive planar layer on the even and odd conductive strip stack structures, wherein the first patterned conductive planar layer includes a reference on the even stacked structure for use as a common source line Lines, as well as cross-plane layer connectors on odd stack structures. A dual damascene process is used to form a second patterned conductive planar layer having a bit line of extensions, wherein the extensions are used to connect to corresponding cross-plane layer connectors.

為了讓本發明之上述實施例及其他目的、特徵和優點能更明顯易懂，特舉數個較佳實施例，並配合所附圖式，作詳細說明如下： The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

50、6050‧‧‧垂直通道結構 50, 6050‧‧‧ vertical channel structure

53、1161‧‧‧縫隙 53. 1161‧‧‧ gap

52、1101、1121、1122、1123、1124、1125‧‧‧絕緣層 52, 1101, 1121, 1122, 1123, 1124, 1125‧‧‧ insulation

58、58-1、58-2、59、59-1、59-2、WL、WL0-WL(i)、WL(i+1)-WL(n)‧‧‧字元線 58, 58-1, 58-2, 59, 59-1, 59-2, WL, WL0-WL(i), WL(i+1)-WL(n)‧‧‧ character lines

54、GSL‧‧‧接地選擇線 54. GSL‧‧‧ Grounding selection line

55、SSL‧‧‧串列選擇線 55, SSL‧‧‧ tandem selection line

56、57、62、63‧‧‧導電薄膜 56, 57, 62, 63‧‧‧ conductive film

60、61‧‧‧輔助閘極線 60, 61‧‧‧Auxiliary gate line

69‧‧‧資料儲存結構 69‧‧‧Data storage structure

70、71‧‧‧記憶胞 70, 71‧‧‧ memory cells

80a、80b、81a、81b‧‧‧垂直通道膜 80a, 80b, 81a, 81b‧‧‧ vertical channel membrane

80-1、80-2、80-3、80-4‧‧‧薄膜半導體條帶 80-1, 80-2, 80-3, 80-4‧‧‧ Thin film semiconductor strips

1105‧‧‧氮化矽頂部層 1105‧‧‧The top layer of tantalum nitride

128‧‧‧位元線接觸 128‧‧‧ bit line contact

129‧‧‧共同源極線 129‧‧‧Common source line

131、132‧‧‧開關 131, 132‧‧‧ switch

134‧‧‧堆疊結構的底部 134‧‧‧Bottom of stacked structure

135‧‧‧輔助閘極結構 135‧‧‧Auxiliary gate structure

1110、1111、1112、1113、2011-E、2011-O‧‧‧導電條帶堆疊結構 1110, 1111, 1112, 1113, 2011-E, 2011-O‧‧‧ Conductive strip stacking structure

1130、6057‧‧‧阻擋層 1130, 6057‧‧‧ barrier

1131、6056、6059‧‧‧電荷儲存層 1131, 6056, 6059‧‧‧ charge storage layer

1132、6053、6054、6055‧‧‧穿隧層 1132, 6053, 6054, 6055‧‧‧ tunneling layer

1140、6052‧‧‧薄膜半導體層 1140, 6052‧‧‧ Thin film semiconductor layer

1140-E、1140-O‧‧‧薄膜半導體層的一部分 Part of the 1140-E, 1140-O‧‧ ‧ thin film semiconductor layer

1141‧‧‧區域 1141‧‧‧Area

1162‧‧‧填充部 1162‧‧‧Filling Department

2000、2001、2002、2003、2004、2005‧‧‧絕緣結構 2000, 2001, 2002, 2003, 2004, 2005‧‧‧ ‧ insulation structure

2012‧‧‧絕緣材料 2012‧‧‧Insulation materials

2020、2021、2022、2023、2024、2025、2026、2027、2124-2129‧‧‧層間連接器 2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027, 2124-2129‧ ‧ inter-layer connectors

2030、2034‧‧‧參考線 2030, 2034‧‧‧ reference line

2031、2032、2033、2035、2036、2037、2137-2139‧‧‧跨平面層連接器 2031, 2032, 2033, 2035, 2036, 2037, 2137-2139‧‧‧ cross-plane layer connectors

2035、2036、2037‧‧‧跨平面層間連接器 2035, 2036, 2037‧‧‧cross-plane interlayer connectors

2041、2042、2043、2045、2046、2047‧‧‧延伸部 2041, 2042, 2043, 2045, 2046, 2047‧‧‧ extensions

2060-2062、5060、5061‧‧‧位元線 2060-2062, 5060, 5061‧‧‧ bit line

2069‧‧‧電流路徑 2069‧‧‧ Current path

2060-2067‧‧‧位元線 2060-2067‧‧‧ bit line

2070、2071、2073、2074、2075、2077、2078、2079‧‧‧薄膜 半導體層的部分 2070, 2071, 2073, 2074, 2075, 2077, 2078, 2079‧‧ ‧ films Part of the semiconductor layer

2111、2112、2113‧‧‧絕緣膜 2111, 2112, 2113‧‧ ‧ insulating film

2113-1-2113-9‧‧‧絕緣條帶 2113-1-2113-9‧‧‧Insulated strip

2160‧‧‧導電材料 2160‧‧‧Electrical materials

2300‧‧‧長方形區域 2300‧‧‧Rectangular area

2310‧‧‧圓形區域 2310‧‧‧Circular area

2400‧‧‧光阻罩幕 2400‧‧‧Light-resistance mask

2410‧‧‧開口 2410‧‧‧ openings

2411-2418‧‧‧開孔 2411-2418‧‧‧Opening

2500‧‧‧開口區域 2500‧‧‧Open area

2561-2564‧‧‧曲邊 2561-2564‧‧‧ 曲边

2571、2572、2573、2574‧‧‧側邊 2571, 2572, 2573, 2574‧‧‧ side

3601‧‧‧在基材上形成一絕緣層 3601‧‧‧ Forming an insulating layer on the substrate

3602‧‧‧在絕緣層上形成複數個導電條帶堆疊結構 3602‧‧‧ Forming a plurality of conductive strip stack structures on the insulating layer

3603‧‧‧在導電條帶的側邊表面形成資料儲存結構 3603‧‧‧ Forming a data storage structure on the side surface of the conductive strip

3604‧‧‧於這些導電條帶堆疊結構上形成半導體薄膜層，並且於底端相互電性連接 3604‧‧‧ A semiconductor thin film layer is formed on these conductive strip stack structures, and electrically connected to each other at the bottom end

3605‧‧‧在位於相鄰導電條帶堆疊結構之側壁上相互對立的半導體薄膜層之間提供絕緣結構 3605‧‧‧ Providing an insulating structure between mutually opposing semiconductor film layers on the sidewalls of adjacent conductive strip stack structures

3605‧‧‧圖案化薄層結構以形成包括彼此分離之垂直通道膜的主動柱狀體 3605‧‧‧ patterned thin layer structure to form active columnar bodies comprising vertical channel membranes separated from each other

3607‧‧‧在主動柱狀體之間提供絕緣結構 3607‧‧‧Insulation structure between active columns

3608‧‧‧圖案化半導體薄膜層，藉以定義出複數個位元線銲墊和共同源極線銲墊 3608‧‧‧ patterned semiconductor film layer to define a plurality of bit line pads and common source line pads

3609‧‧‧形成參考線片段和位元線片段，使其分別連接至共同源極線銲墊和位元線銲墊 3609‧‧‧ Forming reference line segments and bit line segments to be connected to common source wire pads and bit line pads

5030‧‧‧連接器 5030‧‧‧Connector

6050a‧‧‧垂直通道結構的表面 6050a‧‧‧ Surface of vertical channel structure

6058‧‧‧閘極材料層 6058‧‧‧ gate material layer

901‧‧‧積體電路 901‧‧‧Integrated circuit

930‧‧‧匯流排 930‧‧ ‧ busbar

910‧‧‧控制邏輯 910‧‧‧Control logic

920‧‧‧偏壓配置電壓源 920‧‧‧ bias voltage source

940‧‧‧串列選擇線/接地選擇線行解碼器 940‧‧‧Serial selection line/ground selection line decoder

945‧‧‧串列選擇線/接地選擇線 945‧‧‧Serial selection line/ground selection line

950‧‧‧單數/偶數平面層解碼器 950‧‧‧single/even plane layer decoder

955‧‧‧單數/偶數字元線 955‧‧‧single/even digital lines

960‧‧‧記憶體陣列 960‧‧‧Memory array

965‧‧‧全域位元線 965‧‧‧Global bit line

970‧‧‧全域位元線列解碼器 970‧‧‧Global Bit Line Decoder

975‧‧‧第一資料線 975‧‧‧First data line

980‧‧‧感測放大器/寫入緩衝電路 980‧‧‧Sense Amplifier/Write Buffer Circuit

985‧‧‧第二資料 985‧‧‧Second information

990‧‧‧多階層資料緩衝器 990‧‧‧Multi-level data buffer

991‧‧‧輸入/輸出電路 991‧‧‧Input/Output Circuit

993‧‧‧線資料路徑 993‧‧‧ Line data path

AA’‧‧‧切線 AA’‧‧‧ Tangent

AG‧‧‧輔助閘極 AG‧‧‧Auxiliary gate

SL、BL‧‧‧接觸點 SL, BL‧‧‧ touch points

X₁、X₂‧‧‧偏移距離 X ₁ , X ₂ ‧‧‧ offset distance

第1圖係繪示具有垂直通道結構的立體記憶體元件的結構透視圖。 Figure 1 is a perspective view showing the structure of a three-dimensional memory element having a vertical channel structure.

第2圖係繪示本發明的實施例之結構中位於單一主動柱狀體(single active pillar)上的U形NAND串列電路示意圖。 2 is a schematic diagram of a U-shaped NAND string circuit located on a single active pillar in the structure of an embodiment of the present invention.

第3圖係繪示一種位於立體記憶體元件中，具有U形垂直通道膜之主動柱狀體的結構剖面圖。 Figure 3 is a cross-sectional view showing the structure of an active columnar body having a U-shaped vertical channel film in a three-dimensional memory element.

第4圖係繪示立體記憶體元件中主動柱狀體之頂部的結構透視圖。 Figure 4 is a perspective view showing the structure of the top of the active column in the three-dimensional memory element.

第5圖係繪示記憶體元件中具有被縫隙(seam)所分隔之薄膜 通道結構的兩個主動柱狀體之平截頭體以及主動柱狀之複數個記憶胞的結構透視圖。 Figure 5 is a diagram showing a memory element having a film separated by a seam. A perspective view of the frustum of two active cylinders of the channel structure and a plurality of memory cells of the active column.

第6圖係繪示立體記憶體元件中主動柱狀體之底部的結構透視圖。 Figure 6 is a perspective view showing the structure of the bottom of the active column in the three-dimensional memory element.

第7A圖係繪示位於垂直薄膜通道結構之間可用來形成立體記憶體陣列之字元線的上視圖。 Figure 7A is a top plan view of a word line between vertical film channel structures that can be used to form a three dimensional memory array.

第7B圖係繪示位於交錯(twisted)排列之垂直薄膜通道結構之間的字元線的上視圖。 Figure 7B is a top view showing the word lines between the twisted aligned vertical film channel structures.

第8圖至第16圖係繪示製作本發明之實施例所述之立體NAND記憶體之各個製程步驟的結構透視圖。 8 to 16 are structural perspective views showing respective process steps for fabricating a stereo NAND memory according to an embodiment of the present invention.

第17A圖係繪示用來形成第15圖之第一圖案化導電平面層的部分光阻罩幕結構上視圖。 Figure 17A is a top plan view showing a portion of the photoresist mask structure used to form the first patterned conductive planar layer of Figure 15.

第17B圖係第15圖所繪示之結構的部分結構簡化示意圖。 Fig. 17B is a simplified schematic view showing a partial structure of the structure shown in Fig. 15.

第18A圖、第18B圖、第19A圖、第19B圖、第20A圖、第20B圖、第21A圖和第21B圖係繪示製作第16圖之第二圖案化導電平面層之各個製程步驟中的結構簡化示意圖。 18A, 18B, 19A, 19B, 20A, 20B, 21A, and 21B illustrate various process steps for fabricating the second patterned conductive planar layer of FIG. A simplified schematic of the structure in the middle.

第22A圖係沿著第21B圖之X-Y平面所繪示的部分結構剖面放大圖。 Figure 22A is an enlarged cross-sectional view of a portion of the structure taken along the X-Y plane of Figure 21B.

第22B圖係繪示位元線的透視結構放大圖。 Figure 22B is an enlarged view showing the perspective structure of the bit line.

第23A圖係沿著第21A圖之切線AA’所繪示之無錯位(misalignment)的結構剖面圖。 Fig. 23A is a cross-sectional view showing the structure of the misalignment shown along the tangent AA' of Fig. 21A.

第23B圖係沿著第21B圖之切線AA’所繪示有錯位的結構剖 面圖。 Figure 23B is a cross-sectional view of the structure taken along the tangent AA' of Figure 21B. Surface map.

第24圖係繪示不採用雙相嵌製程所形成之元件的錯位結構剖面圖。 Figure 24 is a cross-sectional view showing the dislocation structure of an element formed without using a two-phase embedded process.

第25圖係繪示一種可以使用於本發明之實施例所述之立體NAND記憶體中的資料儲存結構。 Figure 25 is a diagram showing a data storage structure that can be used in the stereo NAND memory of the embodiment of the present invention.

第26圖係繪示用來製作本發明之實施例所述之雙閘極垂直通道結構的方法流程圖。 Figure 26 is a flow chart showing a method for fabricating a dual gate vertical channel structure in accordance with an embodiment of the present invention.

第27圖係繪示本發明之實施例所述之包含具有薄膜通道結構之立體記憶體陣列之積體電路的方塊圖。 Figure 27 is a block diagram showing an integrated circuit including a three-dimensional memory array having a thin film channel structure according to an embodiment of the present invention.

本發明的實施例將參照第1圖至第27圖來進行說明。 Embodiments of the present invention will be described with reference to Figs. 1 to 27.

第1圖係繪示立體記憶體元件的結構透視圖。此處所述的立體記憶體元件包括複數個具有交錯堆疊之多層導電條帶(GSL、SSL、WL、AG)和多個絕緣層(1121-1125)的堆疊結構、位於堆疊結構側邊的資料儲存結構69以及與資料儲存結構69接觸的垂直通道膜80a/80b。堆疊結構上方設置有共同源極線，例如參考線2030、2034，以及位元線2060-2062。電流路徑(circuit path)2069顯示電流流過U形NAND串列。垂直通道膜80a/80b和資料儲存結構69的組合以下稱之為主動柱狀體。 Fig. 1 is a perspective view showing the structure of a three-dimensional memory element. The three-dimensional memory component described herein includes a plurality of stacked structures having a plurality of staggered stacked conductive strips (GSL, SSL, WL, AG) and a plurality of insulating layers (1121-1125), and materials located on the side of the stacked structure. The storage structure 69 and the vertical channel film 80a/80b in contact with the data storage structure 69. A common source line is disposed over the stacked structure, such as reference lines 2030, 2034, and bit lines 2060-2062. A circuit path 2069 shows current flowing through the U-shaped NAND string. The combination of vertical channel films 80a/80b and data storage structure 69 is hereinafter referred to as active columnar body.

第2圖係繪示對應於第1圖所示之電流路徑2069，從參考線2034至位元線2060的U形NAND串列電路示意圖。U 形NAND串列係連結於位元線接觸128和共同源極線129之間。主動柱狀體係位於奇數和偶數導電堆疊結構之間。在本實施例中，偶數導電堆疊結構的上方平面層(upper level)包括一條串列選擇案，用來作為NAND串列之第一開關(switch)131的閘極；且奇數導電堆疊結構的上方平面層包括一條接地選擇案，用來作為同一條NAND串列之第二開關132的閘極。這些堆疊結構的中間平面層(intermediate levels)包含奇數和偶數字元線，其中奇數字元線包括WL0至WL(i)的字元線；偶數字元線包括WL(i+1)至WL(n)的字元線。在堆疊結構的底部134，提供薄膜通道結構的多個半導體薄膜層彼此電性連接。例如，這些半導體薄膜層係藉由連接導電條帶堆疊結構之間的空間的單層連續薄膜所形成。在此處所繪示的實施例中，還包含通過閘極介電層耦合至位於堆疊結構底部之半導體薄膜層的輔助閘極結構135。輔助閘極結構135可以被用於誘導產生反轉區(inversion region)，以提高偶數和奇數側之導電條帶間的導電性。輔助閘極結構135可以藉由位於基材中主動柱狀體下方之摻雜區，或使用其他技術來加以實現。U型串列包括位於偶數堆疊結構之一側的多個偶數記憶胞，以及位於奇數堆疊結構之一側的多個奇數記憶胞。 2 is a schematic diagram of a U-shaped NAND string circuit corresponding to the current path 2069 shown in FIG. 1 from the reference line 2034 to the bit line 2060. U The NAND string is coupled between the bit line contact 128 and the common source line 129. The active columnar system is located between the odd and even conductive stack structures. In this embodiment, the upper level of the even-numbered conductive stack structure includes a serial selection case for serving as the gate of the first switch 131 of the NAND string; and above the odd-numbered conductive stack structure The planar layer includes a ground selection for use as the gate of the second switch 132 of the same NAND string. The intermediate levels of these stacked structures include odd and even digital metalines, where the odd digital lines include the word lines of WL0 through WL(i); the even digital lines include WL(i+1) through WL ( n) The word line. At the bottom 134 of the stacked structure, a plurality of semiconductor thin film layers providing a thin film via structure are electrically connected to each other. For example, these semiconductor thin film layers are formed by a single layer of continuous film connecting the spaces between the conductive strip stack structures. In the embodiment illustrated herein, an auxiliary gate structure 135 coupled to the semiconductor film layer at the bottom of the stacked structure via a gate dielectric layer is also included. The auxiliary gate structure 135 can be used to induce an inversion region to improve the conductivity between the conductive strips on the even and odd sides. The auxiliary gate structure 135 can be implemented by doping regions under the active pillars in the substrate, or using other techniques. The U-type string includes a plurality of even-numbered memory cells on one side of the even-numbered stacked structure, and a plurality of odd-numbered memory cells on one side of the odd-numbered stacked structure.

第3圖係繪示一種可以用來實現第2圖所繪示之U形串列的主動柱狀體結構剖面圖。第3圖的主動柱狀體包括垂直通道結構50。此垂直通道結構50包括垂直多晶矽半導體本體(vertical polysilicon semiconductor body)，包括沿著柱狀體之長度 方向被縫隙53所分隔的奇數和偶數薄膜通道，並且在柱狀體的底部彼此電性連接。資料儲存結構69位於柱狀體的每一側邊。垂直通道結構50包括用來在一側提供通道本體一個接地選擇線電晶體的部位80a，以及用來在另一側提供通道本體一個串列選擇線電晶體的部位80b。在部位80a和80b以及垂直通道結構的底部之間配置有一縫隙53，位於奇數和偶數字元線之間的垂直通道結構50中。在一些實施例之中，縫隙53分隔了位於與字元線交叉之縱列平截頭體(例如與字元線58和59等高)上的兩個薄膜通道。縫隙53也將垂直通道結構分割成彼此分離，且延伸穿過串列選擇線閘極和接地選擇線閘極的多個薄膜垂直通道。 Fig. 3 is a cross-sectional view showing the structure of an active columnar body which can be used to realize the U-shaped string shown in Fig. 2. The active column of Figure 3 includes a vertical channel structure 50. The vertical channel structure 50 includes a vertical polysilicon semiconductor body including length along the columnar body The odd-numbered and even-numbered film channels separated by the slit 53 are electrically connected to each other at the bottom of the columnar body. A data storage structure 69 is located on each side of the column. The vertical channel structure 50 includes a portion 80a for providing a ground selection line transistor of the channel body on one side, and a portion 80b for providing a series selection line transistor of the channel body on the other side. A gap 53 is disposed between the portions 80a and 80b and the bottom of the vertical channel structure in the vertical channel structure 50 between the odd and even digital lines. In some embodiments, the slit 53 separates two film channels located on a tandem frustum that intersects the word line (e.g., the same height as word lines 58 and 59). The slit 53 also divides the vertical channel structure into two separate vertical channels that extend through the tandem select line gate and the ground select line gate.

第3圖繪示同時在堆疊結構的上方平面層導電條帶中，建構用來作為多條接地選擇線54以及一條串列選擇線55的多條導電條帶。接地選擇線54以及串列選擇線55可以更包括位於其表面上，且導電度更高的導電薄膜56和57，例如金屬矽化物薄膜。 FIG. 3 illustrates the construction of a plurality of conductive strips for use as a plurality of ground select lines 54 and a series select line 55 in the upper planar layer conductive strips of the stacked structure. The ground selection line 54 and the tandem selection line 55 may further include conductive films 56 and 57 having a higher conductivity on the surface thereof, such as a metal halide film.

第3圖繪示輔助閘極線60和61，其可藉由位於堆疊結構中包含字元線的導電條帶來加以實現。輔助閘極線60和61可以更包括位於其表面上，且導電度更高的導電薄膜62和63，例如金屬矽化物薄膜。 Figure 3 illustrates auxiliary gate lines 60 and 61 which may be implemented by a strip of conductive strips containing word lines in a stacked structure. The auxiliary gate lines 60 and 61 may further include conductive films 62 and 63 on the surface thereof and having higher conductivity, such as a metal halide film.

同樣的，導電條帶被佈置成位於垂直通道結構50兩側的奇數和偶數字元線。因此偶數字元線59和奇數字元線58係相對設置於此結構之中。在本實施例之中，只繪示了8個字元 線層。然而，也可以採用更多數量，例如16個、32個或更多數量，的字元線層。 Likewise, the conductive strips are arranged as odd and even digital lines on either side of the vertical channel structure 50. Therefore, the even digital line 59 and the odd digital line 58 are relatively disposed in this structure. In this embodiment, only 8 characters are shown. Line layer. However, it is also possible to use a greater number of, for example, 16, 32 or more number of word line layers.

如第3圖所繪示，字元線的外表面也可以更包含金屬矽化物薄膜，或其他高導電度的薄膜(例如，導電薄膜62)。 As shown in FIG. 3, the outer surface of the word line may further comprise a metal halide film, or other high conductivity film (eg, conductive film 62).

在其他實施例中，所有的或部分的串列選擇線、字元線和接地選擇線可以採用金屬或其他不是多晶矽的導電材料來加以實現。 In other embodiments, all or a portion of the string select lines, word lines, and ground select lines can be implemented using a metal or other conductive material that is not polysilicon.

第3圖所繪示的結構提供具有位於垂直通道結構50奇數和偶數兩側之獨立電荷儲位的記憶胞70和71。而且，此結構支援沿著垂直通道結構50相對兩側索進行的單一U形NAND串列操作。 The structure depicted in FIG. 3 provides memory cells 70 and 71 having independent charge storage locations on the odd and even sides of vertical channel structure 50. Moreover, this structure supports a single U-shaped NAND string operation along opposite sides of the vertical channel structure 50.

在第3圖中，接地選擇線54和串列選擇線55在垂直方向的延伸長度決定了接地選擇電晶體和串列選擇電晶體的通道長度。同樣的，字元線在垂直方向的延伸長度決定了記憶胞的通道長度。 In Fig. 3, the length of the ground selection line 54 and the string selection line 55 in the vertical direction determines the channel length of the ground selection transistor and the tandem selection transistor. Similarly, the length of the character line in the vertical direction determines the channel length of the memory cell.

第3圖所繪示之結構中的接地選擇線54和串列選擇線55在垂直方向具有實質較字元線(例如字元線58和59)還要大的延伸長度，例如大於4倍的延伸長度。較大的通道長度有利於操作串列選擇電晶體，可在垂直通道結構之一側施加足以關閉此電晶體的偏壓，即便施加於另一側的偏壓已足以開啟此電晶體。 The ground select line 54 and the string select line 55 in the structure illustrated in FIG. 3 have a substantially larger extension length in the vertical direction than the word line (eg, word lines 58 and 59), for example, greater than 4 times. Extension length. A larger channel length facilitates operation of the tandem selection transistor, and a bias voltage sufficient to turn off the transistor can be applied to one side of the vertical channel structure even if the bias applied to the other side is sufficient to turn the transistor on.

第3圖所繪示之結構中的輔助閘極線60和61也具有在垂直方向實質大於字元線的延伸長度，如此可促進NAND串 列在U型區域中的導電度。第3圖所繪示的輔助閘極線60和61延伸至基材(未繪示)的絕緣層52上方。 The auxiliary gate lines 60 and 61 in the structure illustrated in FIG. 3 also have an extension length substantially larger than the word line in the vertical direction, thus facilitating the NAND string. The conductivity listed in the U-shaped region. The auxiliary gate lines 60 and 61 depicted in FIG. 3 extend over the insulating layer 52 of the substrate (not shown).

參考線結構，例如位於圖案化金屬層中的參考線(如第1圖所繪示的參考線2030和2034)片段，可以排列於偶數導電條帶堆疊結構中的接地選擇線(GSL)上方，並且連接至主動柱狀體上的接觸點SL。位元線結構，例如位於圖案化金屬層中具有延伸部(如第1圖所繪示的延伸部2045、2046和2047)的位元線(如第1圖所繪示的位元線2060、2061和2062)片段，可以直交排列於奇數和偶數導電條帶堆疊結構上，並且通過跨平面層間連接器(如第1圖所繪示的跨平面層間連接器2035、2036和2037)連接至主動柱狀體的接觸點BL。 A reference line structure, such as a reference line (as reference lines 2030 and 2034 as depicted in FIG. 1) located in the patterned metal layer, may be arranged above the ground select line (GSL) in the even conductive strip stack structure. And connected to the contact point SL on the active column. A bit line structure, such as a bit line having extensions (such as extensions 2045, 2046, and 2047 as depicted in FIG. 1) in the patterned metal layer (such as bit line 2060 depicted in FIG. 1 , The 2061 and 2062) segments, which can be arranged orthogonally on the odd and even conductive strip stack structures, are connected to the active by a trans-plane inter-layer connector (such as the cross-plane inter-layer connectors 2035, 2036, and 2037 depicted in FIG. 1). The contact point BL of the columnar body.

主動柱狀體包括垂直通道結構。垂直通道結構在中間平面層以及串列選擇電晶體和接第選擇電晶體所在的上方平面層中包含有縫隙。記憶胞70和71中的通道，是藉由縫隙所分隔的半導體材質的薄膜。其中，縫隙是用來作為這些薄膜之間的絕緣結構，或部分用來作為這些薄膜之間的絕緣結構。縫隙中包裹例如，來自於製作過程中反應槽裡氣氛所提供的氣體(gas)。而為了方便描述起見，此處稱之為「空氣(air)」。 The active columnar body includes a vertical channel structure. The vertical channel structure includes a slit in the intermediate plane layer and the upper planar layer in which the tandem selection transistor and the second selection transistor are located. The channels in the memory cells 70 and 71 are thin films of semiconductor material separated by slits. Among them, the slit is used as an insulating structure between the films, or partially used as an insulating structure between the films. The wrap in the gap is, for example, from the gas provided by the atmosphere in the reaction tank during the manufacturing process. For the sake of convenience of description, it is referred to herein as "air".

第4圖係繪示接地選擇線54以及串列選擇線55區域範圍內之主動柱狀體的頂部結構。在此圖中，一個主動柱狀體包括垂直通道膜80a/80b，另一主動柱狀體包括垂直通道膜81a/81b。資料儲存結構69，形成於相互對立的兩側，延伸於左 側(偶數)接地選擇線54和右側(奇數)串列選擇線55之間，用來作為閘極介電層。接地選擇電晶體和串列選擇電晶體係實現於每一個主動柱狀體位於接地選擇線和串列選擇線之間的平截頭體上。 4 is a diagram showing the top structure of the active column in the region of the ground selection line 54 and the series selection line 55. In this figure, one active column includes vertical channel films 80a/80b and the other active column includes vertical channel films 81a/81b. The data storage structure 69 is formed on opposite sides of each other and extends to the left Between the side (even) ground selection line 54 and the right (odd) series selection line 55, it serves as a gate dielectric layer. The ground selection transistor and the tandem selection cell system are implemented on each frustum of the active column between the ground selection line and the string selection line.

在本實施例中，縫隙53實現於包括垂直通道膜80a/80b的主動柱狀體以及包括垂直通道膜81a/81b的主動柱狀體之間。可以降低二主動柱狀體之垂直通道膜間的電容耦合(capacitive coupling)。在一些實施例中，縫隙53可以填充固態絕緣體，例如矽氧化物、低介電係數(low-κ)介電材料或其他合適的絕緣材料。 In the present embodiment, the slit 53 is realized between the active columnar body including the vertical channel films 80a/80b and the active columnar body including the vertical channel films 81a/81b. The capacitive coupling between the vertical channel membranes of the two active cylinders can be reduced. In some embodiments, the gap 53 can be filled with a solid insulator, such as tantalum oxide, a low-k dielectric material, or other suitable insulating material.

第5圖係繪示位於字元線區域中包括垂直通道膜80a/80b之主動柱狀體的中間部分，以及包括垂直通道膜81a/81b的其他主動柱狀體。在本實施例中，垂直柱狀體具有包含被縫隙隔開之奇數和偶數垂直通道的薄膜通道結構，藉以形成由半導體薄膜層所構成的第一主動柱狀部(first active pillar portion)(垂直通道膜80a)以及由半導體薄膜層所構成的第二主動柱狀部(垂直通道膜80b)；且形成由半導體薄膜層所構成的第一主動柱狀部(垂直通道膜81a)以及第二主動柱狀部(垂直通道膜81b)。資料儲存結構69形成於複數條字元線的側邊上。複數條字元線包含左側偶數字元線58-1和58-2以及右側奇數字元線59-1和59-2。 Figure 5 illustrates the middle portion of the active column including the vertical channel film 80a/80b in the word line region, and other active columns including the vertical channel film 81a/81b. In the present embodiment, the vertical columnar body has a film channel structure including odd and even vertical channels separated by slits, thereby forming a first active pillar portion (vertical) composed of a semiconductor thin film layer (vertical a channel film 80a) and a second active pillar portion (vertical channel film 80b) composed of a semiconductor thin film layer; and forming a first active pillar portion (vertical channel film 81a) composed of a semiconductor thin film layer and a second active Columnar portion (vertical channel film 81b). A data storage structure 69 is formed on the sides of the plurality of word lines. The plurality of word line lines include the left even digital line lines 58-1 and 58-2 and the right odd digital line lines 59-1 and 59-2.

第6圖係繪示位於輔助閘極區域中主動柱狀體的底部結構。在本實施例中，主動柱狀體包含多個垂直通道膜801a/80b 和81a/81b，於主動柱狀體的底部相互連接，形成U形的薄膜，並將這些垂直通道膜電性連結。垂直通道膜80a/80b和輔助閘極線60和61之間的交叉點就是輔助閘極AG。資料儲存結構69就是用來作為輔助閘極AG的閘氧化層。輔助閘極結構可以藉由位於基材中主動柱狀體下方之摻雜區，或使用其他技術，來加以實現。 Figure 6 shows the bottom structure of the active column in the auxiliary gate region. In this embodiment, the active columnar body includes a plurality of vertical channel films 801a/80b And 81a/81b are connected to each other at the bottom of the active column to form a U-shaped film, and electrically connect the vertical channel films. The intersection between the vertical channel film 80a/80b and the auxiliary gate lines 60 and 61 is the auxiliary gate AG. The data storage structure 69 is the gate oxide layer used as the auxiliary gate AG. The auxiliary gate structure can be implemented by doping regions under the active pillars in the substrate, or using other techniques.

第7A圖係繪示第5圖之字元線58-1和59-1堆疊層，也就是第一和第二導電條帶堆疊結構中之導電條帶，的上視圖。第7A圖係繪示位於每一主動柱狀體之平截頭體上的記憶胞。字元線58-1是第一導電條帶堆疊結構中的一條導電條帶。第一導電條帶堆疊結構具有第一側邊和第二側邊。多個資料儲存結構69分別位於第一導電條帶堆疊結構的第一側邊和第二側邊上。這些資料儲存結構69分別位於第一導電條帶堆疊結構之多條導電條帶之第一側邊和第二側邊的側壁上。請參照字元線58-1，第一薄膜半導體條帶80-1垂直接觸位於第一側邊上的資料儲存結構69。同樣的，第二薄膜半導體條帶80-2垂直接觸位於字元線58-1第二側邊上的資料儲存結構69。複數個記憶胞之中的多個記憶胞具有位於薄膜半導體條帶(80-1和80-2)之中的通道，以及位於用來形成字元線(58-1)之多條導電條帶之中的閘極。 Figure 7A is a top view showing the stacked layers of the word lines 58-1 and 59-1 of Figure 5, that is, the conductive strips in the first and second conductive strip stack structures. Figure 7A shows the memory cells located on the frustum of each active column. Word line 58-1 is a conductive strip in the first conductive strip stack structure. The first conductive strip stack structure has a first side and a second side. A plurality of data storage structures 69 are respectively located on the first side and the second side of the first conductive strip stack structure. The data storage structures 69 are respectively located on the side walls of the first side and the second side of the plurality of conductive strips of the first conductive strip stack structure. Referring to word line 58-1, first thin film semiconductor strip 80-1 vertically contacts data storage structure 69 on the first side. Similarly, the second thin film semiconductor strip 80-2 is in vertical contact with the data storage structure 69 on the second side of the word line 56-1. A plurality of memory cells among the plurality of memory cells have channels located in the thin film semiconductor stripes (80-1 and 80-2) and a plurality of conductive stripes located in the word line (58-1) The gate in the middle.

第7A圖同時繪示字元線59-1，其係位於第二導電條帶堆疊結構中的一條導電條帶。第二導電條帶堆疊結構具有第一側邊和第二側邊。多個資料儲存結構69分別位於第二導電條 帶堆疊結構的第一側邊和第二側邊上。這些資料儲存結構69分別位於第二導電條帶堆疊結構之多條導電條帶之第一側邊和第二側邊的側壁上。 Figure 7A also shows the word line 59-1, which is a strip of conductive strips in the second conductive strip stack structure. The second conductive strip stack structure has a first side and a second side. A plurality of data storage structures 69 are respectively located on the second conductive strip The first side and the second side of the stack structure. The data storage structures 69 are respectively located on the side walls of the first side and the second side of the plurality of conductive strips of the second conductive strip stack structure.

請參照字元線59-1，第三薄膜半導體條帶80-3垂直接觸位於字元線59-1之第一側邊上的資料儲存結構69。第四薄膜半導體條帶80-4垂直接觸位於字元線59-1之第二側邊上的資料儲存結構69。在本實施例中，包括縫隙53的絕緣結構將第二薄膜半導體條帶80-2和第三薄膜半導體條帶80-3隔離。在本發明的一些實施例中，絕緣結構可以包括固態絕緣體，例如二氧化矽以及固態絕緣體和縫隙的組合。值得注意的是，在大部分的實施例中，第二薄膜半導體條帶80-2和第三薄膜半導體條帶80-3是連續U形半導體(例如多晶矽)的兩個側邊，彼此在底部相互連接。 Referring to word line 59-1, third thin film semiconductor strip 80-3 is in vertical contact with data storage structure 69 on the first side of word line 59-1. The fourth thin film semiconductor strip 80-4 is in vertical contact with the data storage structure 69 on the second side of the word line 59-1. In the present embodiment, the insulating structure including the slit 53 isolates the second thin film semiconductor strip 80-2 from the third thin film semiconductor strip 80-3. In some embodiments of the invention, the insulating structure may comprise a solid insulator such as cerium oxide and a combination of solid insulator and gap. It should be noted that in most embodiments, the second thin film semiconductor strip 80-2 and the third thin film semiconductor strip 80-3 are two sides of a continuous U-shaped semiconductor (eg, polysilicon), at the bottom of each other. Connected to each other.

第7B圖係根據後述第12圖之另一實施例中所繪示的陣列佈局。使用於第7A圖的元件符號也適用於第7B圖中，故不在此贅述。第7A圖和第7B圖之間的差異在於薄膜半導體條帶的排列方式。意即，主動柱狀體的排列方式不同。如第7B圖所繪示，主動柱狀體的佈局方式為「交錯」或「蜂窩狀(honeycomb)」排列；而相對於第7A圖的排列方式為「方形(square)」排列。 Fig. 7B is an array layout according to another embodiment of Fig. 12 which will be described later. The symbol of the element used in Fig. 7A also applies to Fig. 7B, and therefore will not be described here. The difference between the 7A and 7B is the arrangement of the thin film semiconductor stripes. That is, the active columns are arranged in different ways. As shown in FIG. 7B, the arrangement of the active columns is "interlaced" or "honeycomb", and the arrangement with respect to the 7A is a "square" arrangement.

位於字元線58-1和59-1之間的薄膜半導體條帶(例如薄膜半導體條帶80-1和80-2)彼此相互對立，並且彼此在端點連接而形成U形薄膜。位於字元線58-1之第一和第二側邊的薄 膜半導體條帶(例如薄膜半導體條帶80-3和80-4)在X軸方向偏移距離X₁。位於字元線59-1之第一和第二側邊的薄膜半導體條帶(例如薄膜半導體條帶80-2和80-3)在X軸方向相同偏移距離X₂。在本實施例之中，偏移距離X₁和偏移距離X₂相同。但在另一些實施例之中，偏移距離X₁和偏移距離X₂可以不同。 The thin film semiconductor stripes (e.g., thin film semiconductor stripes 80-1 and 80-2) located between the word lines 57-1 and 59-1 are opposed to each other and connected to each other at the terminals to form a U-shaped film. The thin film semiconductor stripes (e.g., thin film semiconductor stripes 80-3 and 80-4) located at the first and second sides of the word line 58-1 are offset by a distance X ₁ in the X-axis direction. The thin film semiconductor stripes (e.g., thin film semiconductor stripes 80-2 and 80-3) located at the first and second sides of the word line 59-1 are equally offset by a distance X ₂ in the X-axis direction. In the present embodiment, the offset distance X ₁ and the offset distance X _{2 are the} same. However, in other embodiments, the offset distance X ₁ and the offset distance X ₂ may be different.

第8圖至第16圖係根據本發明的一實施例繪示製作垂直薄膜通道結構的流程。第8圖係繪示形成絕緣層1101的製程階段。其中，絕緣層1101可以包括位於半導體基材上的矽氧化物或其他介電材質。 8 through 16 illustrate the flow of fabricating a vertical film channel structure in accordance with an embodiment of the present invention. FIG. 8 illustrates a process stage in which the insulating layer 1101 is formed. The insulating layer 1101 may include germanium oxide or other dielectric material on the semiconductor substrate.

為了形成第8圖所繪示的結構，在絕緣層1101上方沉積適合輔助閘極的材料層；隨後沉積絕緣層；隨後沉積相互堆疊的材質層，以作為字元線和絕緣材質；並且沉積適合作為串列選擇線SSLs和接地選擇線GSLs的材質。 In order to form the structure illustrated in FIG. 8, a material layer suitable for the auxiliary gate is deposited over the insulating layer 1101; an insulating layer is subsequently deposited; then a material layer stacked on each other is deposited as a word line and an insulating material; and the deposition is suitable It is used as the material of the tandem selection line SSLs and the ground selection line GSLs.

輔助閘極、字元線、串列選擇線SSL和接地選擇線GSL可以使用相同的導電材料來形成。在本實施例中，導電材料可以是重度摻雜的p型摻雜多晶矽(P+多晶矽)，或選擇用來與資料儲存結構相容的其他材料。可提供拉伸應力的氮化矽頂部層1105，沉積於本實施例的複數個堆疊層上。此氮化矽頂部層1105可以維持堆疊層的平整性，當堆疊層被蝕刻而具有高深寬比(aspect ratios)和狹窄蝕刻線時，可減少堆疊層彎曲的程度。這些絕緣材料層可以包括藉由該領域中各種已知技術所沉積而成的二氧化矽。這些絕緣材料層也可以包括其他絕緣材料或絕緣材料 的組合。在本實施例之中，除了頂部層1105以外的絕緣層皆係由相同材料所組成。在其他實施例之中，不同的材料可以根據特定的設計目的而適用於不同層中。在形成上述複數個堆疊層之後，對堆疊層進行圖案化蝕刻製程，藉以形成複數個導電條帶堆疊結構。 The auxiliary gate, the word line, the string selection line SSL, and the ground selection line GSL may be formed using the same conductive material. In this embodiment, the conductive material may be heavily doped p-type doped polysilicon (P+ polysilicon) or other materials selected for compatibility with the data storage structure. A tantalum nitride top layer 1105 that provides tensile stress is deposited on a plurality of stacked layers of this embodiment. This tantalum nitride top layer 1105 can maintain the flatness of the stacked layers, and when the stacked layers are etched to have high aspect ratios and narrow etching lines, the degree of bending of the stacked layers can be reduced. These layers of insulating material may include cerium oxide deposited by various known techniques in the art. These layers of insulating material may also include other insulating materials or insulating materials. The combination. In the present embodiment, the insulating layers other than the top layer 1105 are composed of the same material. In other embodiments, different materials may be suitable for use in different layers depending on the particular design. After forming the plurality of stacked layers, the stacked layers are patterned and etched to form a plurality of conductive strip stack structures.

在其他實施例中，輔助閘極結構可以藉由位於基材中主動柱狀體下方之摻雜區，或使用其他技術，來加以實現。 In other embodiments, the auxiliary gate structure can be implemented by doping regions under the active pillars in the substrate, or using other techniques.

第8圖繪示在對複數個堆疊層進行圖案化蝕刻製程，且停止在絕緣層1101，並定義出複數個導電條帶堆疊結構之後的製程結構。其中，導電條帶堆疊結構包括導電條帶堆疊結構1110、1111、1112和1113。導電條帶堆疊結構1110、1111、1112和1113包括至少一個導電條帶底部平面層(輔助閘極AG)、複數個導電條帶中間平面層(字元線WL)和一個導電條帶頂部平面層(串列選擇線/接地選擇線SSL/GSL)。複數個導電條帶中間平面層可以包括0到N-1個平面，以形成導電條帶堆疊結構。氮化矽頂部層1105沉積在蝕刻後的導電條帶堆疊結構上。導電條帶堆疊結構1110、1111、1112和1113包括複數個絕緣層，如標示於導電條帶堆疊結構1110中的絕緣層1121、1122、1123、1124和1125，可將複數條導電條帶彼此分隔。 FIG. 8 illustrates a process structure after performing a pattern etching process on a plurality of stacked layers, stopping at the insulating layer 1101, and defining a plurality of conductive strip stack structures. The conductive strip stack structure includes conductive strip stack structures 1110, 1111, 1112, and 1113. The conductive strip stack structures 1110, 1111, 1112, and 1113 include at least one conductive strip bottom planar layer (auxiliary gate AG), a plurality of conductive strip intermediate plane layers (word line WL), and a conductive strip top planar layer (serial select line / ground select line SSL/GSL). The plurality of conductive strip intermediate plane layers may include 0 to N-1 planes to form a conductive strip stack structure. A tantalum nitride top layer 1105 is deposited over the etched conductive strip stack structure. Conductive strip stack structures 1110, 1111, 1112, and 1113 include a plurality of insulating layers, such as insulating layers 1121, 1122, 1123, 1124, and 1125, which are labeled in conductive strip stack structure 1110, which can separate a plurality of conductive strips from each other .

第9圖係繪示在導電條帶堆疊結構之導電條帶的上方和側邊形成資料儲存結構69之後的製程結構。資料儲存結構69與這些導電條帶之側邊表面接觸。資料儲存結構69可以包括 穿隧層1132、電荷儲存層1131和阻擋層1130。 Figure 9 is a diagram showing the process structure after the data storage structure 69 is formed above and to the side of the conductive strip of the conductive strip stack structure. The data storage structure 69 is in contact with the side surfaces of the conductive strips. The data storage structure 69 can include The tunnel layer 1132, the charge storage layer 1131, and the barrier layer 1130.

穿隧層1132包含二氧化矽，具有實質介於20Å至60Å的厚度。穿隧層1132可以是藉由，例如低壓化學氣相沉積(Low-pressure CVD,LPCVD)所形成，厚度約40Å的二氧化矽層。也可以採用其他的穿隧材料及結構，例如複合式的穿隧結構，來形成。 The tunneling layer 1132 comprises cerium oxide having a thickness substantially between 20 Å and 60 Å. The tunneling layer 1132 may be a layer of germanium dioxide having a thickness of about 40 Å formed by, for example, low pressure CVD (LPCVD). Other tunneling materials and structures, such as a composite tunneling structure, may also be used.

複合式的穿隧結構包括一層厚度小於2奈米(nm)的二氧化矽、一層厚度小於3奈米的氮化矽和一層厚度小於4奈米的二氧化矽。在一個實施例中，複合式的穿隧結構係由超薄二氧化矽層O₁(例如厚度15Å)、超薄氮化矽矽層N₁(例如厚度30Å)和超薄二氧化矽層O₂(例如厚度35Å)所組成，可使從複合式的穿隧結構與半導體本體之介面起算約15Å或更少距離之偏移位置的價帶能階(valence band energy level)增加約2.6eV。超薄二氧化矽層O₂在第二偏移位置(例如，從介面起算約30Å至40Å)，藉由一個具有較低價帶能階(具有較高的電洞穿隧能障(hole tunneling barrier))和較高導帶能階(conduction band energy level)的區域將超薄氮化矽矽層N₁和電荷儲存層1131隔離。因為第二偏移位置距離介面較遠，當第二偏移位置達到有效消除電洞穿隧能障的能階之後，足以誘發電洞穿隧的電場會提升價帶能階。因此，超薄二氧化矽層O₂並不會顯著地干擾電場輔助電洞穿隧，同時提高了能隙工程隧穿介電層(engineered tunneling dielectric)在低電場期間阻止漏電的能力。這些材質層可以使用，例如低壓化 學氣相沉積，共形沉積而形成。 The composite tunneling structure comprises a layer of germanium dioxide having a thickness of less than 2 nanometers (nm), a layer of tantalum nitride having a thickness of less than 3 nanometers, and a layer of germanium dioxide having a thickness of less than 4 nanometers. In one embodiment, the composite tunneling structure is comprised of an ultra-thin yttria layer O ₁ (eg, thickness) 15Å), ultra-thin tantalum nitride layer N ₁ (eg thickness 30Å) and ultra-thin ruthenium oxide layer O ₂ (eg thickness The composition of 35Å) can increase the valence band energy level of the offset position of the distance between the composite tunneling structure and the semiconductor body by about 15 Å or less by about 2.6 eV. The ultra-thin yttria layer O _{2 is} at a second offset position (eg, from about 30 Å to 40 Å from the interface), with a lower valence band energy level (having a higher hole tunneling barrier (hole tunneling barrier) )) and a region of higher conduction band energy level isolates the ultra-thin tantalum nitride layer N ₁ from the charge storage layer 1131. Because the second offset position is farther from the interface, after the second offset position reaches the energy level of effectively eliminating the tunnel tunneling energy barrier, the electric field sufficient to induce the tunnel tunneling increases the valence band energy level. Therefore, the ultra-thin ruthenium dioxide layer O ₂ does not significantly interfere with the electric field-assisted hole tunneling, and at the same time improves the ability of the energy-filled engineered tunneling dielectric to prevent leakage during low electric fields. These material layers can be formed using, for example, low pressure chemical vapor deposition, conformal deposition.

電荷儲存層1131包括氮化矽，具有實質介於40Å至90Å的厚度。電荷儲存層1131可以是係藉由例如低壓化學氣相沉積所形成，厚度約70Å的氮化矽層。也可以採用其他的電荷儲存材料及結構，例如包括氮氧化矽(silicon oxynitride，Si_xO_yN_z)、富矽氮化物(silicon-rich nitride)、富矽氧化物(silicon-rich oxide)、嵌入奈米粒子的電荷捕捉層...等。 The charge storage layer 1131 includes tantalum nitride having a thickness substantially between 40 Å and 90 Å. The charge storage layer 1131 may be a tantalum nitride layer having a thickness of about 70 Å formed by, for example, low pressure chemical vapor deposition. Other charge storage materials and structures may also be used, including, for example, silicon oxynitride (Si _x O _y N _z ), silicon-rich nitride, silicon-rich oxide, A charge trapping layer embedded in a nanoparticle...etc.

阻擋層1130包含一層厚度實質介於30Å至130Å的二氧化矽。阻擋層1130可以是藉由，例如低壓化學氣相沉積或介由濕爐氧化製程(wet furnace oxidation process)從氮化物濕轉換所形成，厚度約90Å的二氧化矽層。也可以使用其他合適的阻擋材料包括高介電係數材料，像厚度約150Å的氧化鋁來形成。 The barrier layer 1130 comprises a layer of cerium oxide having a thickness substantially between 30 Å and 130 Å. The barrier layer 1130 may be a ruthenium dioxide layer having a thickness of about 90 Å formed by, for example, low pressure chemical vapor deposition or wet transition from a nitride by a wet furnace oxidation process. Other suitable barrier materials can also be used including high dielectric constant materials, such as alumina having a thickness of about 150 Å.

用來形成多層資料儲存結構69的沉積技術，可以採用傳統的低壓化學氣相沉積來實現。另一方面，也可以採用離子層沉積(atomic layer deposition，ALD)或其他適合的工具來形成上述的各種薄膜。位於串列選擇線SSL和接地選擇線GSL層區域中的閘介電層，可以具有與資料儲存結構不同的組成。 The deposition technique used to form the multilayer data storage structure 69 can be accomplished using conventional low pressure chemical vapor deposition. Alternatively, atomic layer deposition (ALD) or other suitable means may be used to form the various films described above. The gate dielectric layer in the region of the tandem select line SSL and the ground select line GSL layer may have a different composition than the data storage structure.

以上所述的資料儲存結構69可以是矽氧化物-氮化矽-矽氧化物(oxide-nitride-oxide、ONO)結構、矽氧化物-氮化矽-矽氧化物-氮化矽-矽氧化物(oxide-nitride-oxide-nitride-oxide，ONONO)結構、矽-矽氧化物-氮化矽-矽氧化物-矽(silicon-oxide-nitride-oxide-silicon，SONOS)結構、能隙工程矽- 矽氧化物-氮化矽-矽氧化物-矽(bandgap engineered silicon-oxide-nitride-oxide-silicon，BE-SONOS BE-SONOS)結構、氮化鉭-氧化鋁-氮化矽-矽氧化物-矽(tantalum nitride,aluminum oxide,silicon nitride,silicon oxide,silicon，TANOS)結構或金屬高介電係數能隙工程矽-矽氧化物-氮化矽-矽氧化物-矽(metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon，MA BE-SONOS)結構。 The data storage structure 69 described above may be a cerium oxide-nitride-oxide (ONO) structure, cerium oxide-cerium nitride-cerium oxide-cerium nitride-cerium oxide. (oxide-nitride-oxide-nitride-oxide, ONONO) structure, silicon-oxide-nitride-oxide-silicon (SONOS) structure, energy gap engineering - G-oxide-nitride-oxide-silicon (BE-SONOS BE-SONOS) structure, tantalum nitride-alumina-tantalum nitride-antimony-oxide Tantalum nitride (aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure or metal high dielectric constant energy gap engineering 矽-矽 oxide-tantalum nitride-矽 oxide-矽 (metal-high-k bandgap -engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS) structure.

在另一個實施例之中，資料儲存結構69可以採用如下述第25圖所繪示的增強介電電荷捕捉結構來實施。增強介電電荷捕捉結構也可參照H.T.Lue等人於2014年6月19日提出申請，審核中且與本案具有共同發明人的美國專利申請案，編號14/309,622，標題為「BANDGAP-ENGINEERED MEMORY WITH MULTIPLE CHARGE TRAPPING LAYERS STORING CHARGE」。其中，該申請案的內容將通過引用併入(incorporated by reference)的方式，將此專利全文收載於本揭露內容之中。 In another embodiment, the data storage structure 69 can be implemented using an enhanced dielectric charge trapping structure as illustrated in Figure 25 below. The enhanced dielectric charge trapping structure can also be referred to by HTLue et al. on June 19, 2014, in the U.S. Patent Application Serial No. 14/309,622, entitled "BANDGAP-ENGINEERED MEMORY" WITH MULTIPLE CHARGE TRAPPING LAYERS STORING CHARGE". The content of the application will be incorporated by reference in the entirety of the disclosure.

第10圖係繪示在位於複數個導電條帶堆疊結構上方的記憶層上形成薄膜半導體層1140，使其與記憶層具有形表面之後的製程結構。在介電電荷儲存的實施例中，薄膜半導體層1140至少在記憶胞形成的區域中與穿隧層1132接觸。薄膜半導體層1140包括透過半導體材料(例如矽)以及摻雜濃度(例如無摻雜或輕摻雜)的選擇所形成的半導體，其可以至少在導電條帶堆疊結構之間的區域中，作為垂直串列記憶胞的通道區。薄膜半導體 層1140的厚度可以等於或小於約10奈米。如圖所示，導電條帶堆疊結構之間的區域(例如區域1141)，薄膜半導體層1140延伸至導電條帶堆疊結構間之區域1141的底部，並覆蓋在穿隧層1132、電荷儲存層1131、阻擋層1130和絕緣層1101上方。可以藉由薄膜半導體層1140的短暫氧化部驟來形成一層矽氧化物薄層(未繪示)。 Figure 10 is a diagram showing the process structure after the thin film semiconductor layer 1140 is formed on the memory layer above the plurality of conductive strip stack structures to have a shaped surface with the memory layer. In an embodiment of dielectric charge storage, the thin film semiconductor layer 1140 is in contact with the tunneling layer 1132 at least in the region where the memory cells are formed. The thin film semiconductor layer 1140 includes a semiconductor formed by selection of a semiconductor material (eg, germanium) and a doping concentration (eg, undoped or lightly doped), which may be at least in a region between the conductive strip stack structures, as a vertical The channel area of the memory cell. Thin film semiconductor The thickness of layer 1140 can be equal to or less than about 10 nanometers. As shown, a region between the conductive strip stack structures (eg, region 1141), the thin film semiconductor layer 1140 extends to the bottom of the region 1141 between the conductive strip stack structures, and overlies the tunneling layer 1132 and the charge storage layer 1131. Above the barrier layer 1130 and the insulating layer 1101. A thin layer of tantalum oxide (not shown) may be formed by the transient oxidation of the thin film semiconductor layer 1140.

第11圖係繪示以絕緣材料填充位於導電條帶堆疊結構之間，薄膜半導體層1140上方的區域(例如第10圖所繪示的區域1141)之後的製程結構。當填充步驟進行後，可能會在薄膜半導體層1140的內表面上方形成凸出部(overhangs)。當相鄰的兩凸出部相當靠近或相互連接時，可能會形成縫隙或空洞1161，因此導電條帶堆疊結構之間的區域沒辦法被絕緣材料完全填滿。填充步驟之後，可以實施回蝕或平坦化步驟，例如化學機械研磨，藉以將薄膜半導體層1140的頂部表面暴露出來。在本實施例之中，填充結構1160包括鄰接導電條帶堆疊結構中的底部平面層和中間平面層之區域內的縫隙(例如，縫隙1161)，以及包括鄰接導電條帶堆疊結構中的頂部平面層之區域內的填充部(例如，填充部1162)。縫隙1161包裹氣體，例如來自於製作過程中反應槽裡氣氛所提供的氣體。而為了方便描述起見，此處稱之為「空氣」。 FIG. 11 illustrates a process structure after filling a region above the thin film semiconductor layer 1140 (for example, the region 1141 shown in FIG. 10) between the conductive strip stack structures with an insulating material. When the filling step is performed, overhangs may be formed over the inner surface of the thin film semiconductor layer 1140. When adjacent two projections are relatively close or interconnected, gaps or voids 1161 may be formed, so that the area between the conductive strip stack structures is not completely filled by the insulating material. After the filling step, an etch back or planarization step, such as chemical mechanical polishing, may be performed to expose the top surface of the thin film semiconductor layer 1140. In the present embodiment, the filling structure 1160 includes a slit (eg, the slit 1161) in a region adjacent to the bottom planar layer and the intermediate planar layer in the conductive strip stack structure, and includes a top plane in the adjacent conductive strip stack structure A fill portion (eg, fill portion 1162) within the region of the layer. The slit 1161 encases the gas, for example, from the gas provided by the atmosphere in the reaction tank during the manufacturing process. For the sake of convenience of description, it is referred to herein as "air."

在一些實施例中，絕緣材料可以完全填充該區域，因此填充結構1160可以被固態絕緣體，例如矽氧化物、低介電係數介電材料或其他合適的絕緣材料所填滿。 In some embodiments, the insulating material can completely fill the region, and thus the filling structure 1160 can be filled with a solid insulator, such as tantalum oxide, a low-k dielectric material, or other suitable insulating material.

在另一些實施例中，縫隙可以延伸至位於導電條帶堆疊結構之間的頂部區域。 In other embodiments, the slits may extend to a top region between the conductive strip stack structures.

包含縫隙或固態絕緣體的填充結構1160可以降低主動柱狀體中薄膜半導體層1140相對側壁之間的電容耦合。 The filling structure 1160 including the slit or solid insulator can reduce the capacitive coupling between the opposite sidewalls of the thin film semiconductor layer 1140 in the active column.

第12圖係繪示在對柱狀體進行裁切蝕刻之後的結構。其中，裁切蝕刻包括在導電條帶堆疊結構之間形成蝕刻開孔，穿過薄膜半導體層，以形成複數個絕緣結構(2000、2001、2002、2003、2004和2005)。在本實施例中，這些開孔向下延伸而將絕緣層1101暴露於外。在形成蝕刻開孔後，接著形成沉積於偶數導電條帶堆疊結構(例如2011-E)和奇數導電條帶堆疊結構(例如2011-O)之間的垂直通道結構。在本實施例中，絕緣結構2002位於偶數導電條帶堆疊結構2011-E和奇數導電條帶堆疊結構2011-O之間。垂直通道結構包括，作為垂直通道膜的奇數和偶數半導體薄膜層，且具有內側表面和外側表面。外側表面位於資料儲存結構上，並與其接觸。其中，資料儲存結構位於對應之奇數和偶數導電條帶堆疊結構的側壁上，用來形成記憶胞立體陣列。內側表面被絕緣結構(例如，絕緣結構2000)所隔離。在本實施例中，絕緣結構2000包括一層絕緣材料(例如，絕緣材料2012)和一個縫隙(例如，縫隙1161)。位於垂直通道結構中的奇數和偶數半導體薄膜層具有約10奈米或更小的厚度。 Fig. 12 is a view showing the structure after the dicing of the columnar body. Wherein the cutting etching comprises forming an etch opening between the conductive strip stack structures and passing through the thin film semiconductor layer to form a plurality of insulating structures (2000, 2001, 2002, 2003, 2004 and 2005). In the present embodiment, the openings extend downward to expose the insulating layer 1101 to the outside. After the etch opening is formed, a vertical channel structure deposited between the even conductive strip stack structure (e.g., 2011-E) and the odd conductive strip stack structure (e.g., 2011-O) is formed. In the present embodiment, the insulating structure 2002 is located between the even-numbered conductive strip stack structure 2011-E and the odd-numbered conductive strip stack structure 2011-O. The vertical channel structure includes odd and even semiconductor film layers as vertical channel films and has an inner side surface and an outer side surface. The outer surface is located on and in contact with the data storage structure. The data storage structure is located on a sidewall of the corresponding odd and even conductive strip stack structure for forming a stereoscopic array of memory cells. The inside surface is isolated by an insulating structure (eg, insulating structure 2000). In the present embodiment, the insulating structure 2000 includes a layer of insulating material (eg, insulating material 2012) and a slit (eg, slit 1161). The odd and even semiconductor film layers located in the vertical channel structure have a thickness of about 10 nm or less.

如第12圖所繪示，垂直通道結構的佈局排列如蜂窩狀。因此，每一行的垂直通道結構都由相鄰一行的垂直通道結構 朝向行的排列方向偏移。蜂窩狀排列方式有利於位於上方且具有較密間距之位元線的形成。接著在垂直通道結構之間的開孔中進行絕緣填充。 As shown in Fig. 12, the layout of the vertical channel structure is arranged in a honeycomb shape. Therefore, the vertical channel structure of each row consists of a vertical channel structure of an adjacent row. The direction of the arrangement of the rows is offset. The honeycomb arrangement facilitates the formation of bit lines located above and having a relatively fine pitch. Insulation fill is then performed in the openings between the vertical channel structures.

在開孔蝕刻之後，薄膜半導體層1140仍是連續的半導體薄膜層，位於導電條帶堆疊結構的頂部，且連接至主動柱狀體的垂直通道膜。薄膜半導體層1140的一部分1140-O覆蓋於奇數導電條帶堆疊結構2011-O的頂部，並沿著奇數導電條帶堆疊結構2011-O的頂部連續延伸。在本實施例中，薄膜半導體層1140的一部分1140-O連接位於絕緣結構2002左側上的垂直通道膜、位於絕緣結構2000右側上的垂直通道膜以及位於絕緣結構2001右側上的垂直通道膜。薄膜半導體層1140的一部分1140-E覆蓋於偶數導電條帶堆疊結構2011-E的頂部，並沿著偶數導電條帶堆疊結構2011-E的頂部連續延伸。薄膜半導體層1140的一部分1140-E連接位於絕緣結構2002右側上的垂直通道膜、位於絕緣結構2003左側上的垂直通道膜以及位於絕緣結構2004左側上的垂直通道膜。 After the via etch, the thin film semiconductor layer 1140 is still a continuous layer of semiconductor film, placed on top of the conductive strip stack structure, and connected to the vertical channel film of the active column. A portion 1140-O of the thin film semiconductor layer 1140 overlies the top of the odd conductive strip stack structure 2011-O and extends continuously along the top of the odd conductive strip stack structure 2011-O. In the present embodiment, a portion 1140-O of the thin film semiconductor layer 1140 is connected to a vertical channel film on the left side of the insulating structure 2002, a vertical channel film on the right side of the insulating structure 2000, and a vertical channel film on the right side of the insulating structure 2001. A portion 1140-E of thin film semiconductor layer 1140 overlies the top of even-numbered conductive strip stack structure 2011-E and extends continuously along the top of even-numbered conductive strip stack structure 2011-E. A portion 1140-E of the thin film semiconductor layer 1140 connects the vertical channel film on the right side of the insulating structure 2002, the vertical channel film on the left side of the insulating structure 2003, and the vertical channel film on the left side of the insulating structure 2004.

第13圖係繪示在進行圖案化蝕刻，將位於導電條帶堆疊結構上剩餘的薄膜半導體層1140加以分隔，以形成陣列連結(array connections)之後的結構。在圖案化蝕刻之後，薄膜半導體層1140可被分隔成覆蓋於偶數導電條帶堆疊結構上的兩個部分2070和2071；以及覆蓋於奇數導電條帶堆疊結構上的6個部分2073、2074、2075、2077、2078和2079。部分2070和2071與 位於NAND串列之共同源極側的主動柱狀體連結在一起；並且提供層間連接器落著區(landing areas)，使其連接至共同源極線。部分2073、2074、2075、2077、2078和2079彼此隔離，且分別提供層間連接器落著區，使其獨立連接至不同位元線。在本實施例中，案絕緣結構2005之側邊的主動柱狀體會在NAND串列的串列選擇線SSL側以及NAND串列之接地選擇線GSL側的垂直通道膜頂端上顯現出銲墊圖來。為方便說明起見，此圖式並未完整繪示所有元件。 Fig. 13 is a view showing the structure after the pattern connection etching is performed to separate the remaining thin film semiconductor layers 1140 on the conductive strip stack structure to form array connections. After the patterned etch, the thin film semiconductor layer 1140 may be divided into two portions 2070 and 2071 overlying the even conductive strip stack structure; and six portions 2073, 2074, 2075 overlying the odd conductive strip stack structure 2077, 2078 and 2079. Part 2070 and 2071 with The active pillars on the common source side of the NAND string are connected together; and the interlayer connector landing areas are provided to connect to the common source line. Portions 2073, 2074, 2075, 2077, 2078, and 2079 are isolated from one another and provide interlayer connector landing regions, respectively, that are independently connected to different bit lines. In this embodiment, the active columnar body on the side of the case insulating structure 2005 exhibits a pad pattern on the side of the vertical channel film on the side of the string selection line SSL side of the NAND string and the ground selection line GSL side of the NAND string. Come. For the sake of explanation, this figure does not fully depict all components.

第14圖係繪示形成層間連接器(2020、2021、2022、2023、2024、2025、2026和2027)陣列，穿過層間介電層(未繪示)，並且落著在薄膜半導體層的相對應部分之後的結構。此一製程可以包括，先於陣列的頂部上形成層間介電層，例如矽氧化物層。層間介電層的厚度，可以例如實質介於100奈米至500奈米之間。接著，形成複數個穿過層間介電層的開口，將位於薄膜半導體層的相對應部分上的落著區暴露於外。沉積可與薄膜半導體層相容的導電材料，用以填充這些開口，進而形成前述的層間連接器。這些層間連接器可以包括多晶矽插塞。層間連接器2020和2024提供電性連接給部分2070和2071，其中部分2070和2071與位於主動柱狀體之接地選擇線GSL側之垂直通道膜連續。層間連接器2021、2022、2023、2025、202和2027分別提供電性連接給部分2073、2074、2075、2077、2078和2079；且部分2073、2074、2075、2077、2078和2079分別位於主動柱狀體之串列選擇線SSL 的一側上。 Figure 14 is a diagram showing the formation of an interlayer connector (2020, 2021, 2022, 2023, 2024, 2025, 2026, and 2027) array, passing through an interlayer dielectric layer (not shown), and falling on the phase of the thin film semiconductor layer. The structure after the corresponding part. Such a process can include forming an interlayer dielectric layer, such as a tantalum oxide layer, on top of the array. The thickness of the interlayer dielectric layer may, for example, be substantially between 100 nm and 500 nm. Next, a plurality of openings through the interlayer dielectric layer are formed to expose the landing regions on the corresponding portions of the thin film semiconductor layer to the outside. A conductive material compatible with the thin film semiconductor layer is deposited to fill the openings to form the aforementioned interlayer connector. These interlayer connectors may include polysilicon plugs. The interlayer connectors 2020 and 2024 provide electrical connections to portions 2070 and 2071, wherein portions 2070 and 2071 are continuous with the vertical channel film on the side of the ground select line GSL of the active column. The interlayer connectors 2021, 2022, 2023, 2025, 202, and 2027 are respectively electrically connected to the portions 2073, 2074, 2075, 2077, 2078, and 2079; and the portions 2073, 2074, 2075, 2077, 2078, and 2079 are respectively located on the active column String selection line SSL On one side.

第15圖係繪示形成包含參考線(例如，參考線2030和2034)和跨平面層連接器(inter-level connectors)(例如，跨平面層連接器2031、2032、2033、2035、2036和2037)的第一圖案化導電平面層之後的結構。詳細的製程步驟將配合圖式第17A圖和第17B圖作詳細說明如下：參考線2034與層間連接器2024電性接觸；位於相同導電條帶堆疊結構上的其他層間連接器(未繪示)連接至位於NAND串列之接地選擇線GSL側的垂直通道膜。藉此，參考線2034可作為區域共同源極線(local common source line)，並提供連接至全域共同源極線(global common source line)。 Figure 15 is a diagram showing the formation of reference lines (e.g., reference lines 2030 and 2034) and inter-level connectors (e.g., cross-plane layer connectors 2031, 2032, 2033, 2035, 2036, and 2037). The structure after the first patterned conductive planar layer. The detailed process steps will be described in detail with reference to Figures 17A and 17B as follows: reference line 2034 is in electrical contact with interlayer connector 2024; other interlayer connectors (not shown) are located on the same conductive strip stack structure. Connected to the vertical channel film on the side of the ground select line GSL of the NAND string. Thereby, the reference line 2034 can serve as a local common source line and provide connection to a global common source line.

此處所述的參考線可以是參考線的一個片段。而此參考線片段和跨平面層連接器係形成於製造過程中首先沉積的金屬層中。 The reference line described herein can be a segment of a reference line. The reference line segment and the cross-planar layer connector are formed in the first deposited metal layer in the manufacturing process.

在本實施例中，跨平面層連接器2035、2036和2037與層間連接器2025、2026和2027對準並且電性接觸。跨平面層連接器連接至位於NAND串列之串列選擇線SSL側上的垂直通道膜，並提供獨立連接至不同位元線。 In the present embodiment, the transplanar layer connectors 2035, 2036, and 2037 are aligned and electrically in contact with the interlayer connectors 2025, 2026, and 2027. The trans-plane layer connector is connected to the vertical channel film on the SSL side of the tandem select line of the NAND string and provides independent connections to different bit lines.

參考線和跨平面層連接器可以包括鎢(W)或其他導電材料，例如銅(Cu)、鈷矽化物(cobalt silicide)、鎢矽化物(tungsten silicide)、其他金屬材料或上述之任意組合，並且形成在同一平面層中。 The reference line and the transplanar layer connector may comprise tungsten (W) or other electrically conductive material such as copper (Cu), cobalt silicide, tungsten silicide, other metallic materials, or any combination thereof. And formed in the same plane layer.

第16圖係繪示在第一圖案化導電平面層上形成第 二圖案化導電平面層之後的結構。第二圖案化導電平面層包括複數條位元線(例如，位元線2060、2061和2062)，其中每條位元線都包括至少一個延伸部。這些延伸部是形成於位元線的製作過程之中，且皆往下延伸。此處所述的位元線可以是位元線的一個片段。例如，位元線2060包括延伸部2041和2045；位元線2061包括延伸部2043和2047以及位元線2062包括延伸部2042和2046。延伸部包括鰭片(fin)。第二圖案化導電平面層係藉由雙鑲嵌製程(dual damascene process)所形成。詳細的製程步驟將配合圖式第18A圖至第21B圖作詳細說明如下：如第16圖係繪示，連接主動柱狀體中位於NAND串列之接地選擇線GSL側之垂直通道膜的薄膜半導體層部分2070，係經由層間連接器(例如，第14圖所繪示的層間連接器2020)連接至第一圖案化導電平面層中的參考線2030。同樣的，連接至主動柱狀體中位於NAND串列之接地選擇線GSL側之垂直通道膜的薄膜半導體層部分2071，係經由層間連接器(例如，第14圖所繪示的層間連接器2024)連接至第一圖案化導電平面層中的參考線2034。參考線2030和2034係沿著相對應的行分別與這些層間連接器連接，並且作為共同源極線。連接至主動柱狀體位於NAND串列之串列選擇線SSL側之垂直通道膜的薄膜半導體層部分2073和2077，係經由跨平面層連接器連接至位元線2060的延伸部2041和2045。連接至主動柱狀體位於NAND串列之串列選擇線SSL側之垂直通道膜的薄膜半導體層部分2075和2079，係經由跨平面層連接器連接至位元線 2061的延伸部2043和2047。連接至主動柱狀體位於NAND串列之串列選擇線SSL側之垂直通道膜的薄膜半導體層部分2074和2078，係經由跨平面層連接器連接至位元線2062的延伸部2042和2046。 Figure 16 is a diagram showing the formation of a first patterned conductive plane layer The structure after the second patterned conductive planar layer. The second patterned conductive planar layer includes a plurality of bit lines (eg, bit lines 2060, 2061, and 2062), wherein each bit line includes at least one extension. These extensions are formed in the fabrication process of the bit lines and extend downward. The bit line described herein can be a segment of a bit line. For example, bit line 2060 includes extensions 2041 and 2045; bit line 2061 includes extensions 2043 and 2047 and bit line 2062 includes extensions 2042 and 2046. The extension includes a fin. The second patterned conductive planar layer is formed by a dual damascene process. The detailed process steps will be described in detail with reference to FIG. 18A to FIG. 21B as follows: as shown in FIG. 16, a film connecting the vertical channel film of the active columnar body on the ground selection line GSL side of the NAND string is shown. The semiconductor layer portion 2070 is connected to a reference line 2030 in the first patterned conductive planar layer via an interlayer connector (eg, the interlayer connector 2020 depicted in FIG. 14). Similarly, the thin film semiconductor layer portion 2071 connected to the vertical channel film on the ground selection line GSL side of the NAND string in the active column is via an interlayer connector (for example, the interlayer connector 2024 shown in FIG. Connected to a reference line 2034 in the first patterned conductive planar layer. Reference lines 2030 and 2034 are connected to the interlayer connectors respectively along corresponding rows and as a common source line. The thin film semiconductor layer portions 2073 and 2077 connected to the vertical channel film of the active columnar body on the side of the tandem selection line SSL of the NAND string are connected to the extensions 2041 and 2045 of the bit line 2060 via the transplanar layer connector. The thin film semiconductor layer portions 2075 and 2079 connected to the vertical channel film of the active columnar body on the side of the string selection line SSL of the NAND string are connected to the bit line via the transplanar layer connector Extensions 2043 and 2047 of 2061. The thin film semiconductor layer portions 2074 and 2078 connected to the vertical channel film of the active columnar body on the side of the tandem select line SSL of the NAND string are connected to the extensions 2042 and 2046 of the bit line 2062 via a transplanar layer connector.

第16圖的電流路徑2069係繪示流經連接參考線2061的延伸部2043和位元線2060間之U形NAND串列的電流。此一結構繪示位於奇數和偶數導電條帶堆疊結構之間的複數個主動柱狀體。這些主動柱狀體包括具有內側表面和外側表面的半導體薄膜層。外側表面位於資料儲存結構上。其中，資料儲存結構位於對應奇數和偶數導電條帶堆疊結構的側壁上，用來形成記憶胞立體陣列。記憶胞彼此連結，而形成從偶數垂直通道膜的上端至下端，再從奇數垂直通道膜的下端至上端的電流路徑。 The current path 2069 of FIG. 16 illustrates the current flowing through the U-shaped NAND string between the extension 2043 of the connection reference line 2061 and the bit line 2060. This structure illustrates a plurality of active cylinders between the odd and even conductive strip stack structures. These active pillars include a semiconductor film layer having an inner side surface and an outer side surface. The outer surface is located on the data storage structure. The data storage structure is located on a sidewall of the stack structure corresponding to the odd and even conductive strips to form a stereoscopic array of memory cells. The memory cells are connected to each other to form a current path from the upper end to the lower end of the even vertical channel film, and from the lower end to the upper end of the odd vertical channel film.

第17A圖係根據本發明的一實施例繪示用來形成第一圖案化導電平面層(如第15圖所繪示，包括參考線2030、2034)和跨平面層連接器2031、2032、2033、2035、2036和2037)之光阻罩幕的部分結構上視圖。此光阻罩幕具有位於層間連接器2024和2124-2126之頂部的長方形區域2300，如第17B圖所繪示，以及位於層間連接器2025-2029和2127-2129(圓形虛線)之頂部的圓形區域2310(圓形實線，全部繪示於第17B圖)。此一製程可以包括，先於層間連接器的頂部上形成一層間介電層，例如二氧化矽或氮化矽層(未繪示)。再形成對應長方形區域2300的溝渠(trenches)和對應圓形區域2310的介層窗(vias)，穿過層間介電層 並將層間連接器暴露於外。在本實施例之中，溝渠係形成於偶數導電條帶堆疊結構中的層間連接器上；介層窗形成於奇數導電條帶堆疊結構中的層間連接器上。其中，他們的對準可採用無邊界氮化矽製程(borderless silicon nitride process)或其他可以提供本實施例位於下方多晶矽插塞良好電性連接的技術來加以實施。 FIG. 17A illustrates a first patterned conductive planar layer (including reference lines 2030, 2034, as shown in FIG. 15) and trans-plane layer connectors 2031, 2032, 2033, in accordance with an embodiment of the present invention. , 2035, 2036, and 2037) Partial structural top view of the photoresist mask. The photoresist mask has a rectangular region 2300 at the top of the interlayer connectors 2024 and 2124-2126, as depicted in Figure 17B, and at the top of the interlayer connectors 2025-2029 and 2127-2129 (circular dotted lines). Circular area 2310 (circular solid line, all shown in Figure 17B). Such a process can include forming an interlevel dielectric layer, such as a hafnium oxide or tantalum nitride layer (not shown), on top of the interlayer connector. Forming trenches corresponding to the rectangular regions 2300 and vias corresponding to the circular regions 2310, passing through the interlayer dielectric layer The interlayer connectors are exposed to the outside. In this embodiment, the trench is formed on the interlayer connector in the even-numbered conductive strip stack structure; the via is formed on the interlayer connector in the odd-numbered conductive strip stack structure. Wherein, their alignment can be carried out using a borderless silicon nitride process or other technique that provides a good electrical connection to the underlying polysilicon plug in this embodiment.

導電材料，例如鎢、銅、鈷矽化物、鎢矽化物、其他金屬材料或上述之任意組合，可以用來填滿溝渠和介層窗。接著，進行化學機械研磨，形成如第17B圖所繪示的參考線(例如，參考線2034)和跨平面層連接器(例如，跨平面層連接器2035-2039,2137-2139)。其中，參考線(例如，參考線2034)和跨平面層連接器(例如，跨平面層連接器2035-2039和2137-2139)都包括相同材質。參考線(例如，參考線2034)係由填充於穿過層間介電層之溝渠中的導電材料所構成，並連接至位於偶數導電條帶堆疊結構上的銲墊。跨平面層連接器(例如，跨平面層連接器2035-2039和2137-2139)係由插塞所構成。此插塞位於穿過層間介電層之介層窗中，係由導電材料所構成，並且連接至位於奇數導電條帶堆疊結構上的銲墊。此處所述的參考線可以是參考線的一個片段。請參照第17A圖和第15圖，參考線2034可以作為區域共同源極線，並且耦接至一參考電壓源，藉此施加一參考電壓給位於NAND串列之接地選擇線GSL側的垂直通道膜。並藉由跨平面層連接器將多條位元線分別連接至位於NAND串列之串列選擇線SSL側的垂直通道膜。 Conductive materials, such as tungsten, copper, cobalt telluride, tungsten germanium, other metallic materials, or any combination of the above, can be used to fill the trenches and vias. Next, chemical mechanical polishing is performed to form a reference line (e.g., reference line 2034) and a cross-planar layer connector (e.g., across planar layer connectors 2035-2039, 2137-2139) as depicted in FIG. 17B. Wherein, the reference lines (eg, reference line 2034) and the cross-planar layer connectors (eg, the cross-planar layer connectors 2035-2039 and 2137-2139) all comprise the same material. The reference line (eg, reference line 2034) is comprised of a conductive material that is filled in a trench that passes through the interlayer dielectric layer and is connected to a pad on the even conductive strip stack structure. The trans-plane layer connectors (eg, across the planar layer connectors 2035-2039 and 2137-2139) are constructed of plugs. The plug is located in a via through the interlayer dielectric layer and is comprised of a conductive material and is connected to pads on the odd conductive strip stack structure. The reference line described herein can be a segment of a reference line. Referring to FIGS. 17A and 15 , the reference line 2034 can serve as a regional common source line and coupled to a reference voltage source, thereby applying a reference voltage to the vertical channel located on the GSL side of the NAND string. membrane. And connecting the plurality of bit lines to the vertical channel film on the SSL side of the tandem selection line of the NAND string by the cross-plane layer connector.

第17B圖係繪示只包含層間連接器2024-2029和2124-2129、參考線2034以及跨平面層連接器2035-2039和2137-2139的簡化結構圖。參考線2034位於複數個層間連接器(例如，2024-2029和2124-2129)的頂部並與層間連接器接觸。 Figure 17B is a simplified block diagram showing only interlayer connectors 2024-2029 and 2124-2129, reference line 2034, and cross-plane layer connectors 2035-2039 and 2137-2139. Reference line 2034 is located on top of a plurality of interlayer connectors (eg, 2024-2029 and 2124-2129) and is in contact with the interlayer connector.

第18A圖至第21B圖係繪示形成如第16圖所示包含位元線2060-2062和延伸部2041-2043和2045-2047之第二圖案化導電平面層的中間製程結構。 18A through 21B illustrate an intermediate process structure for forming a second patterned conductive planar layer including bit lines 2060-2062 and extensions 2041-2043 and 2045-2047 as shown in FIG.

第18B圖係繪示於第二絕緣膜中形成開孔之後的結構。此處所述的製程包括，於第一圖案化導電平面層上沉積第一絕緣膜2111和第二絕緣膜2112。第18A圖係根據本發明的一實施例繪示用來在第二絕緣膜2112中形成複數個開孔之光阻罩幕的部分結構上視圖。在第18A圖中，光阻罩幕2400包括形成於先前的步驟中，位於跨平面層連接器2035-2039和2137-2139頂部(陰影區域)的複數個開口(圓形實線例如，開口2410)。開口2410已被繪示在第18B圖中。在本實施例之中，開口的面積實質等於跨平面層連接器的面積。在另一些實施例之中，和跨平面層連接器相比，開口可以具有不同的面積和不同的形狀。 Fig. 18B is a view showing the structure after the opening is formed in the second insulating film. The process described herein includes depositing a first insulating film 2111 and a second insulating film 2112 on the first patterned conductive planar layer. FIG. 18A is a partial structural top view showing a photoresist mask for forming a plurality of openings in the second insulating film 2112, in accordance with an embodiment of the present invention. In FIG. 18A, the photoresist mask 2400 includes a plurality of openings (circular solid lines, eg, openings 2410) formed in the previous steps, located at the top (shaded area) of the cross-plane layer connectors 2035-2039 and 2137-2139. ). Opening 2410 has been illustrated in Figure 18B. In this embodiment, the area of the opening is substantially equal to the area of the connector across the planar layer. In other embodiments, the openings may have different areas and different shapes than a cross-plane layer connector.

第二絕緣膜2112相對第一絕緣膜2111具有一個蝕刻選擇比。意即，第一絕緣膜2111和第二絕緣膜2112在同一個蝕刻條件下，具有不同的蝕刻速率。使用適當的蝕刻劑，即可蝕穿第二絕緣膜2112而停止於第一絕緣膜2111，進而在第二絕緣膜2112中形成開孔2411-2418。在第二絕緣膜2112中形成開孔 2411-2418的製程中，第一絕緣膜2111的功能係作為蝕刻停止層。例如，第一絕緣膜2111包括矽氧化物，第二絕緣膜2112包括氮化矽。因為氮化矽具有較矽氧化物還要好的蝕刻選擇比，因此可以控制蝕刻移除一部分氮化矽而停止於矽氧化物上。在另一些實施例之中，第一絕緣膜2111可以是矽氧化物或氮氧化矽；第二絕緣膜2112可以是碳化矽。同樣的，因為碳化矽具有較矽氧化物或氮氧化矽還要好的蝕刻選擇比，因此可以控制蝕刻移除一部分碳化矽而停止於矽氧化物或氮氧化矽上。 The second insulating film 2112 has an etching selectivity ratio with respect to the first insulating film 2111. That is, the first insulating film 2111 and the second insulating film 2112 have different etching rates under the same etching condition. With the use of a suitable etchant, the second insulating film 2112 can be etched through the first insulating film 2111, and openings 2411-2418 are formed in the second insulating film 2112. Openings are formed in the second insulating film 2112 In the process of 2411-2418, the function of the first insulating film 2111 serves as an etch stop layer. For example, the first insulating film 2111 includes tantalum oxide, and the second insulating film 2112 includes tantalum nitride. Since tantalum nitride has a better etching selectivity than tantalum oxide, it is possible to control the etching to remove a portion of the tantalum nitride and stop on the tantalum oxide. In other embodiments, the first insulating film 2111 may be tantalum oxide or tantalum oxynitride; and the second insulating film 2112 may be tantalum carbide. Similarly, since tantalum carbide has a better etching selectivity than tantalum oxide or niobium oxynitride, it is possible to control the etching to remove a portion of the tantalum carbide and stop on the tantalum oxide or niobium oxynitride.

第19A圖係根據本發明的一實施例繪示用來圖案化多層絕緣結構之光阻罩幕的部分結構上視圖。如第19A圖所繪示，光阻罩幕包括複數個開口區域(例如，開口區域2500)，每一個開口區域分別對準位於第二絕緣膜2112中的開孔(例如，開孔2411-2418)頂部。 Figure 19A is a partial top plan view of a photoresist mask for patterning a multilayer insulating structure in accordance with an embodiment of the present invention. As shown in FIG. 19A, the photoresist mask includes a plurality of open regions (eg, open regions 2500), each of which is aligned with an opening in the second insulating film 2112 (eg, openings 2411-2418). )top.

第19B圖係繪示形成多層絕緣結構之後的製程結構。此一製程包括，於第二絕緣膜2112上形成第三絕緣膜2113，並且填充位於第二絕緣膜2112中的開孔2411-2418。第三絕緣膜2113包括與第一絕緣膜2111相同的材料。因此，第二絕緣膜2112相對第三絕緣膜2113具有一個蝕刻選擇比。另一方面，在不同蝕刻條件下，第三絕緣膜2113相對於第二絕緣膜2112具有另一個蝕刻選擇比。第一絕緣膜2111、第二絕緣膜2112和第三絕緣膜2113構成了多層絕緣結構。其中，在蝕刻第三絕緣膜2113的製程中，第二絕緣膜2112係用來作為蝕刻停止層；在蝕刻第二絕緣 膜2112的製程中，第一絕緣膜2111係用來作為蝕刻停止層。 Fig. 19B is a view showing a process structure after forming a multilayered insulating structure. This process includes forming a third insulating film 2113 on the second insulating film 2112 and filling the openings 2411-2418 located in the second insulating film 2112. The third insulating film 2113 includes the same material as the first insulating film 2111. Therefore, the second insulating film 2112 has an etching selectivity ratio with respect to the third insulating film 2113. On the other hand, the third insulating film 2113 has another etching selectivity ratio with respect to the second insulating film 2112 under different etching conditions. The first insulating film 2111, the second insulating film 2112, and the third insulating film 2113 constitute a multilayer insulating structure. Wherein, in the process of etching the third insulating film 2113, the second insulating film 2112 is used as an etch stop layer; the second insulation is etched In the process of the film 2112, the first insulating film 2111 is used as an etch stop layer.

可用來蝕刻第一絕緣膜2111和第三絕緣膜2113的蝕刻劑，不會蝕刻第二絕緣膜2112的材料，而僅對應光阻罩幕中之開口區域2500移除一部分的第三絕緣膜2113，進而形成複數條絕緣條帶(例如，絕緣條帶2113-1至2113-9)。藉由先前所述的蝕刻選擇比，此蝕刻製程會停止於圖案化的第二絕緣膜2112，並且進一步移除在沉積第三絕緣膜2113時，用來填滿第二絕緣膜2112之開孔的一部分第三絕緣膜2113。這個蝕刻製程會繼續蝕刻穿過第二絕緣膜2112之開孔，移除一部分的第一絕緣膜2111，將跨平面層連接器(例如，第17B圖所繪示的跨平面層連接器2035-2039和2137-2139)暴露於外。第一絕緣膜2111和第二絕緣膜2112之蝕刻部分的形狀係由開口區域(例如，開口區域2500)和第二絕緣膜2112之開孔(例如，開孔2411-2418)重疊的區域來定義。多層絕緣結構被餘留下來的部分構成了圖案化絕緣結構。 The etchant that can be used to etch the first insulating film 2111 and the third insulating film 2113 does not etch the material of the second insulating film 2112, but only removes a portion of the third insulating film 2113 corresponding to the opening region 2500 in the photoresist mask. Further, a plurality of insulating strips (for example, insulating strips 2113-1 to 2113-9) are formed. By the etching selection ratio previously described, the etching process is stopped at the patterned second insulating film 2112, and the opening for filling the second insulating film 2112 when the third insulating film 2113 is deposited is further removed. A portion of the third insulating film 2113. This etching process continues to etch through the openings of the second insulating film 2112, removing a portion of the first insulating film 2111, which will be across the planar layer connector (eg, the cross-plane layer connector 2035 shown in FIG. 17B- 2039 and 2137-2139) were exposed to the outside. The shape of the etched portion of the first insulating film 2111 and the second insulating film 2112 is defined by an area in which the opening region (for example, the opening region 2500) and the opening of the second insulating film 2112 (for example, the openings 2411-2418) overlap. . The remaining portion of the multilayer insulation structure constitutes a patterned insulating structure.

第20A圖和第20B圖分別繪示在前述圖案化絕緣結構上沉積一層導電材料2160之後的製程結構上視圖。導電材料2160填充於第一絕緣膜2111和第二絕緣膜2112中的蝕刻開孔內，進而形成複數個延伸部，填充位於複數個絕緣條帶(例如，絕緣條帶2113-1至2113-9)之間的空間，進而形成複數條位元線。在單一步驟中，使用導電材料填充至少兩個圖案，藉以形成多層內連線，是習知的雙鑲嵌製程。此導電材料可以包括金屬材料，例如銅、鎢、鈦/氮化鈦(Ti/TiN)、鉬(Molybdenum)、鎢矽化物、鈷矽 化物、鋁以及上述之任意組合。 20A and 20B are respectively top views of the process structure after depositing a layer of conductive material 2160 on the patterned insulating structure. The conductive material 2160 is filled in the etched openings in the first insulating film 2111 and the second insulating film 2112, thereby forming a plurality of extensions, and the filling is in a plurality of insulating strips (for example, the insulating strips 2113-1 to 2113-9) The space between them forms a plurality of bit lines. In a single step, filling at least two patterns with a conductive material to form a multilayer interconnect is a conventional dual damascene process. The conductive material may include a metal material such as copper, tungsten, titanium/titanium nitride (Ti/TiN), molybdenum, tungsten telluride, cobalt ruthenium Compound, aluminum, and any combination of the above.

第20A圖和第20B圖分別繪示在形成位元線之後的製程結構透視圖。此一方法包括對導電材料2160進行化學機械研磨，直到將複數個絕緣條帶(例如，絕緣條帶2113-1至2113-9)的頂部表面暴露於外，藉以形成包括複數條具有延伸部之位元線(例如，位元線2060-2067)的第二圖案化導電平面層，如前所述並參照第16圖。位元線2060-2067繪示於第16圖中。此處所述的位元線可以是位元線的一個片段。延伸部包括具有第一絕緣膜和第二絕緣膜的鰭片。 20A and 20B are perspective views showing a process structure after forming a bit line, respectively. The method includes chemical mechanical polishing of the electrically conductive material 2160 until the top surfaces of the plurality of insulating strips (eg, the insulating strips 2113-1 through 2113-9) are exposed, thereby forming a plurality of strips having extensions. The second patterned conductive planar layer of the bit line (e.g., bit line 2060-2067) is as previously described with reference to FIG. Bit lines 2060-2067 are depicted in Figure 16. The bit line described herein can be a segment of a bit line. The extension includes a fin having a first insulating film and a second insulating film.

第22A圖係沿著之X-Y平面所繪示的部分結構剖面放大圖。其中，X-Y平面穿過第二絕緣膜2112，且與向下延伸且建構來作為一部份位元線的延伸部(例如，延伸部2045和2047，也繪示於第16圖中)交叉。延伸部的形狀係由用來圖案化第二絕緣膜2112之光阻罩幕中的開口區域(例如，開口2410也繪示於第18A圖中)與用來圖案化第三絕緣膜2113之光阻罩幕中的開口區域(例如，開口區域2500也繪示於第19A圖中)二者的重疊區域來決定。在本實施例中，延伸部(例如，延伸部2045和2047)具有兩個對準位元線的直邊，和兩個經由第二絕緣膜2112的開口所定義的曲邊(例如，曲邊2561-2564)，因此延伸部對準第二絕緣膜2112。延伸部(例如，延伸部2045和2047)具有位於側邊(例如，側邊2571/2572和2573/2574)上相互對立的兩側壁，與填滿第二絕緣膜2112開口的第三絕緣膜2113接觸，且具有位於側邊(例如，側邊 2561/2562和2563/2564)並相互對立的其他側壁，與第二絕緣膜2112接觸。 Figure 22A is an enlarged cross-sectional view of a portion of the structure taken along the X-Y plane. Wherein, the X-Y plane passes through the second insulating film 2112 and intersects with an extension extending downwardly and as a part of the bit line (for example, the extensions 2045 and 2047, also shown in FIG. 16). The shape of the extension is formed by an opening region in the photoresist mask for patterning the second insulating film 2112 (for example, the opening 2410 is also shown in FIG. 18A) and the light for patterning the third insulating film 2113. The area of the opening in the mask (e.g., the opening area 2500 is also shown in Figure 19A) is determined by the overlapping area of the two. In the present embodiment, the extensions (eg, extensions 2045 and 2047) have two straight sides aligned with the bit lines, and two curved sides defined by the openings of the second insulating film 2112 (eg, curved edges) 2561-2564), and thus the extension portion is aligned with the second insulating film 2112. The extensions (eg, extensions 2045 and 2047) have two side walls that are opposite each other on the side edges (eg, sides 2571/2572 and 2573/2574), and a third insulating film 2113 that fills the opening of the second insulating film 2112 Contact and have sides (for example, sides) The other side walls which are opposite to each other, 2561/2562 and 2563/2564) are in contact with the second insulating film 2112.

在又一些其他實施例之中，位於光阻罩幕中，用來圖案化第二絕緣膜2112的開口區域(如第18A圖所繪示的開口2410)為方形，具有兩個對準位元線的直邊，和兩個對準第二絕緣膜2112的直邊。 In still other embodiments, in the photoresist mask, the open area for patterning the second insulating film 2112 (such as the opening 2410 shown in FIG. 18A) is square and has two alignment bits. The straight sides of the line, and the two sides are aligned with the straight sides of the second insulating film 2112.

第22B圖係繪示位元線的透視結構放大圖。位元線2060和2061(也繪示於第16圖)具有延伸部2045和2047與位於第一圖案化導電平面層中的跨平面層連接器2035和2037連接。位元線及其延伸部位於第二圖案化導電平面層之中。 Figure 22B is an enlarged view showing the perspective structure of the bit line. Bit lines 2060 and 2061 (also shown in FIG. 16) have extensions 2045 and 2047 coupled to cross-plane layer connectors 2035 and 2037 located in the first patterned conductive planar layer. The bit line and its extension are located in the second patterned conductive planar layer.

第23A圖和第23B圖係分別沿著第21A圖和第21B圖之切線AA’所繪示之的結構剖面圖，其刪除了層間連接器未繪示。第23A圖繪示用來圖案化第二絕緣膜2112之光阻罩幕和用來圖案化第三絕緣膜2113之光阻罩幕之間具有精準對位的結構。位元線2060和其附帶的延伸部2045完全位於跨平面層連接器2035的頂部。鄰接的位元線(例如，位元線2061)停止在第二絕緣膜2112之上。 Figs. 23A and 23B are structural cross-sectional views taken along the line AA' of Figs. 21A and 21B, respectively, which are omitted from the interlayer connector. FIG. 23A illustrates a structure having a precise alignment between the photoresist mask for patterning the second insulating film 2112 and the photoresist mask for patterning the third insulating film 2113. The bit line 2060 and its accompanying extension 2045 are located entirely on top of the cross-planar layer connector 2035. Adjacent bit lines (eg, bit line 2061) stop above the second insulating film 2112.

第23B圖係繪示錯位情況下的結構。第二絕緣膜2112可以阻擋鄰接的位元線(例如，位元線2061)與跨平面層連接器2035接觸，因此位元線(例如，位元線2060)和鄰接的位元線(例如，位元線2061)不會與同一個跨平面層連接器接觸。也因此即使位元線的間距變小，使用雙相嵌製程的結構，仍可以防止兩條 位元線2060和2061之間發生短路。 Figure 23B shows the structure in the case of a misalignment. The second insulating film 2112 may block adjacent bit lines (eg, bit lines 2061) from contacting the trans-plane layer connector 2035, thus bit lines (eg, bit lines 2060) and contiguous bit lines (eg, Bit line 2061) does not come into contact with the same cross-plane layer connector. Therefore, even if the pitch of the bit lines becomes smaller, the structure using the two-phase embedded process can still prevent two A short circuit occurs between bit lines 2060 and 2061.

第24圖係繪示不採用前述雙鑲嵌製程來製作具有延伸部之位元線的結構。在本實施例中，位元線(例如，位元線5060和5061)和連接器(例如，連接器5030)之間的錯位，可能造成兩條位元線連接，進而使整個記憶體陣列發生短路，造成記憶體元件無法操作。為了防止這樣的錯誤發生，也可採用與本發明不同的技術解決方案，例如減少連接器5030的尺寸，藉以使並列的位元線不會因同時與一個連接器接觸而相互連接。這個解決方案可藉由採用自對準雙圖案化製程(Self-Aligned Double Patterning process)來形成尺寸較窄的連接器。但這樣將會增加製程步驟及成本。由此觀之，本發明所揭露的技術在製程中可提供更大的對準公差(tolerance of alignment)，並且具有較高的良率和較低的成本。 Fig. 24 is a view showing a structure in which a bit line having an extension portion is formed without using the above-described dual damascene process. In this embodiment, the misalignment between the bit lines (eg, bit lines 5060 and 5061) and the connector (eg, connector 5030) may cause two bit lines to be connected, thereby causing the entire memory array to occur. Short circuit, causing the memory component to be inoperable. In order to prevent such an error from occurring, a technical solution different from the present invention can also be employed, for example, reducing the size of the connector 5030 so that the parallel bit lines are not connected to each other by being in contact with one connector at the same time. This solution can be used to form a connector of a narrower size by employing a Self-Aligned Double Patterning process. But this will increase the process steps and costs. From this perspective, the disclosed technology can provide greater tolerance of alignment in the process and has higher yield and lower cost.

第16圖係繪示一種記憶體元件，其具有彼此分隔的複數個導電條帶堆疊結構。請參照位於第一和第二導電條帶堆疊結構中的導電條帶，其繪示連接U形NAND串列的內連線結構。第一和第二導電條帶堆疊結構具有相互對立的側壁。資料儲存結構形成於第一和第二導電條帶堆疊結構的側壁上。第一和第二垂直通道膜形成在位於第一和第二導電條帶堆疊結構之側壁上的資料儲存結構上。第一垂直通道膜包括位於第一導電條帶堆疊結構上的第一銲墊，且第一銲墊位於第一垂直通道膜的上端。第二垂直通道膜包括位於第二導電條帶堆疊結構上的第二銲墊，且第 二銲墊位於第二垂直通道膜的上端。第一和第二垂直通道膜在端點上相互連接。 Figure 16 is a diagram showing a memory element having a plurality of conductive strip stack structures separated from one another. Please refer to the conductive strips in the first and second conductive strip stack structures, which illustrate the interconnect structure connecting the U-shaped NAND strings. The first and second conductive strip stack structures have opposing sidewalls. A data storage structure is formed on sidewalls of the first and second conductive strip stack structures. First and second vertical channel films are formed on the data storage structure on the sidewalls of the first and second conductive strip stack structures. The first vertical channel film includes a first pad on the first conductive strip stack structure, and the first pad is located at an upper end of the first vertical channel film. The second vertical channel film includes a second pad on the second conductive strip stack structure, and The second pad is located at the upper end of the second vertical channel film. The first and second vertical channel films are interconnected at the ends.

第一導電條帶堆疊結構的上方導電條帶係建構來作為第一開關(例如，接地選擇線GSL開關)的閘極，並且具有位於第一半導體薄膜層中的通道。第二導電條帶堆疊結構的上方導電條帶係建構來作為第二開關(例如，串列選擇線SSL開關)的閘極，並且具有位於第二半導體薄膜層中的通道。第一和第二導電條帶堆疊結構的中間導電條帶係建構來作為字元線。第一和第二導電條帶堆疊結構的底部導電條帶係建構來作為輔助閘極。 The upper conductive strip of the first conductive strip stack structure is constructed as a gate of a first switch (eg, a ground select line GSL switch) and has a via in the first semiconductor thin film layer. The upper conductive strip of the second conductive strip stack structure is constructed as a gate of a second switch (eg, a tandem select line SSL switch) and has a via in the second semiconductor thin film layer. The intermediate conductive strips of the first and second conductive strip stack structures are constructed as word lines. The bottom conductive strips of the first and second conductive strip stack structures are constructed as auxiliary gates.

第一圖案化導電平面層覆蓋於第一和第二導電條帶堆疊結構上。其包括一條參考線和一個跨平面層連接器。參考線連接至第一銲墊，跨平面層連接器連接至第二銲墊。第二圖案化導電平面層形成於第一圖案化導電平面層上，第二圖案化導電平面層包括一條位元線。此位元線包括與跨平面層連接器接觸的延伸部。 A first patterned conductive planar layer overlies the first and second conductive strip stack structures. It includes a reference line and a cross-plane layer connector. The reference line is connected to the first pad and the cross-plane layer connector is connected to the second pad. The second patterned conductive planar layer is formed on the first patterned conductive planar layer, and the second patterned conductive planar layer comprises a bit line. This bit line includes an extension that contacts the cross-plane layer connector.

另外，垂直通道結構建構於相同的第一和第二導電條帶堆疊結構之間，使位於第一導電條帶堆疊結構上的多個第一半導體薄膜層全部都被電性連結，且可以分享連結至相同的參考線。又，額外的垂直通道結構建構於相同的第一和第二導電條帶堆疊結構之間，使位於第二導電條帶堆疊結構上的多個第二半導體薄膜層彼此電性隔離，並且使用個別的跨平面層連接器，個別地連接至彼此分離的位元線。 In addition, the vertical channel structure is constructed between the same first and second conductive strip stack structures, so that the plurality of first semiconductor thin film layers on the first conductive strip stack structure are all electrically connected and can be shared. Link to the same guide. Moreover, an additional vertical channel structure is constructed between the same first and second conductive strip stack structures to electrically isolate the plurality of second semiconductor thin film layers on the second conductive strip stack structure from each other and to use individual The cross-plane layer connectors are individually connected to bit lines that are separated from one another.

第25圖係繪示一種可以使用於本發明之實施例中的先進能隙工程矽-矽氧化物-氮化矽-矽氧化物-矽(BE-SONOS)資料儲存結構。此資料儲存結構包括與垂直通道結構6050接觸的穿隧層。穿隧層包含複合材料並包括多層結構。例如，包括矽氧化物第一穿隧層6053、氮化矽穿隧層6054和矽氧化物第二穿隧層6055。 Figure 25 is a diagram showing an advanced energy gap engineering 矽-矽 oxide-tantalum nitride-矽 oxide-矽 (BE-SONOS) data storage structure that can be used in embodiments of the present invention. This data storage structure includes a tunneling layer in contact with the vertical channel structure 6050. The tunneling layer comprises a composite material and comprises a multilayer structure. For example, a tantalum oxide first tunneling layer 6053, a tantalum nitride tunneling layer 6054, and a tantalum oxide second tunneling layer 6055 are included.

矽氧化物第一穿隧層6053位於垂直通道結構6050的表面6050a，係使用，例如原位蒸氣生成(in-situ steam generation，ISSG)技術與可選用的氮化製程，藉由沉積後一氧化氮退火處理(post deposition NO annealing)或者在沉積製程中在反應氣體氣氛中添加一氧化氮所製成。矽氧化物第一穿隧層6053的厚度小於約20Å，較佳係介於約7Å至15Å之間。第一穿隧層6053可以使用替代品，例如氮氧化矽，以增進其耐用性；及/或進行氟化處理(fluorine treatments)，以增進介面能態(interface state)的品質。 The tantalum oxide first tunneling layer 6053 is located on the surface 6050a of the vertical channel structure 6050 using, for example, in-situ steam generation (ISSG) techniques and an optional nitridation process, by post-deposition oxidation. It is made by post deposition NO annealing or by adding nitric oxide in a reaction gas atmosphere during the deposition process. The first passivation layer of the tantalum oxide 6053 has a thickness of less than about 20 Å, preferably between about 7 Å and 15 Å. The first tunneling layer 6053 may use alternatives such as bismuth oxynitride to enhance its durability; and/or perform fluoride treatments to enhance the quality of the interface state.

氮化矽穿隧層6054又稱作穿隧氮化層，位於矽氧化物第一穿隧層6053上。可例如使用低壓化學氣相沉積，採用二氯矽烷(dichlorosilane，DCS)和氨作為前驅物(and NH₃ precursors)在680℃的環境下形成。在另一個替代的製程中，穿隧氮化層6054包括在相同製程中使用氧化亞氮(N₂O)當作前驅物所形成的氮氧化矽。氮化矽穿隧層6054的厚度小於約30Å，較佳係介於約10Å至30Å之間，包含例如約20Å。由於厚度較薄，因此氮化矽穿隧層6054的電荷儲存能力較弱。 The tantalum nitride tunneling layer 6054, also referred to as a tunneling nitride layer, is located on the tantalum oxide first tunneling layer 6053. It can be formed, for example, using low pressure chemical vapor deposition using dichlorosilane (DCS) and ammonia as precursors (and NH ₃ precursors) at 680 °C. In another alternative process, tunneling nitride layer 6054 includes niobium oxynitride formed using nitrous oxide (N ₂ O) as a precursor in the same process. The tantalum nitride tunneling layer 6054 has a thickness of less than about 30 Å, preferably between about 10 Å and 30 Å, and includes, for example, about 20 Å. Since the thickness is thin, the charge storage ability of the tantalum nitride tunneling layer 6054 is weak.

穿隧層6054提供較低的電洞能障高度(hole barrier height)有助於電洞注入以進行FN抹除。不過，穿隧層6054具有較低的電荷捕捉效率。根據價帶相對於矽的偏移，穿隧層6054的材質可以是：二氧化矽4.4eV、氮化矽(Si₃N₄)1.8eV、氧化鉭(Ta₂O₅)3.0eV、鈦酸鋇(BaTiO₃)2.3eV、鋯酸鋇(BaZrO₃)3.4eV、氧化鋯(ZrO₂)3.3eV、氧化鉿(HfO₂)3.4eV、氧化鋁(Al₂O₃)4.9eV,氧化釔(Y₂O₃)3.6eV或矽酸鋯(ZrSiO₄)3.4eV。雖然也可能使用其他材料，但是氮化矽具有最低的電洞能障高度1.8eV。 The tunneling layer 6054 provides a lower hole barrier height that facilitates hole injection for FN erasure. However, tunneling layer 6054 has a lower charge trapping efficiency. According to the offset of the valence band with respect to 矽, the material of the tunneling layer 6054 may be: cerium oxide 4.4eV, cerium nitride (Si ₃ N ₄ ) 1.8eV, cerium oxide (Ta ₂ O ₅ ) 3.0eV, titanic acid Barium (BaTiO ₃ ) 2.3eV, barium zirconate (BaZrO ₃ ) 3.4eV, zirconium oxide (ZrO ₂ ) 3.3eV, yttrium oxide (HfO ₂ ) 3.4eV, alumina (Al ₂ O ₃ ) 4.9eV, yttrium oxide ( Y ₂ O ₃ ) 3.6 eV or zirconium silicate (ZrSiO ₄ ) 3.4 eV. Tantalum nitride has the lowest hole barrier height of 1.8 eV, although other materials may be used.

矽氧化物第二穿隧層6055位於氮化矽穿隧層6054上。可例如使用低壓化學氣相沉積高溫氧化物(high temperature oxide，HTO)沉積來形成。矽氧化物第二穿隧層6055的厚度小於約45Å，較佳係介於約15Å至45Å之間，包含例如約30Å。矽氧化物第二穿隧層6055提供足夠的阻障厚度，以阻擋電荷流失，以增進電荷滯留(charge retention)。第二穿隧層6055可阻擋直接穿隧漏電(direct tunneling leakage)。也可以使用其他低漏電氧化物，例如氧化鋁。 The tantalum oxide second tunneling layer 6055 is located on the tantalum nitride tunneling layer 6054. It can be formed, for example, using low pressure chemical vapor deposition high temperature oxide (HTO) deposition. The tantalum oxide second tunneling layer 6055 has a thickness of less than about 45 Å, preferably between about 15 Å and 45 Å, and includes, for example, about 30 Å. The tantalum oxide second tunneling layer 6055 provides sufficient barrier thickness to block charge loss to enhance charge retention. The second tunneling layer 6055 blocks direct tunneling leakage. Other low leakage oxides such as alumina can also be used.

在本實施例中，第一電荷儲存層6056包括氮化矽。其具有實質大於45Å的厚度，較佳係介於45Å至80Å，包含例如55Å。在本實施例中，第一電荷儲存層6056可例如使用低壓化學氣相沉積來形成。也可以使用其他電荷捕捉材料或結構。例如包括氮氧化矽、富矽氮化物、富矽氧化物、嵌入奈米粒子的電荷捕捉層...等。 In the present embodiment, the first charge storage layer 6056 includes tantalum nitride. It has a thickness substantially greater than 45 Å, preferably between 45 Å and 80 Å, including for example 55 Å. In the present embodiment, the first charge storage layer 6056 can be formed, for example, using low pressure chemical vapor deposition. Other charge trapping materials or structures can also be used. Examples include cerium oxynitride, cerium-rich nitride, cerium-rich oxide, charge trapping layer embedded in nanoparticle, and the like.

第一二氧化矽阻障層6057位於第一電荷儲存層6056之上，係例如採用低壓化學氣相沉積高溫氧化物沉積所形成。第一二氧化矽阻障層6057的厚度實質小於70Å，包含介於55Å至70Å的範圍，包含例如50Å。阻障層6057提供足夠的阻障厚度，以阻擋電荷儲存層6056和6059之間的電荷混合和電荷輸送。也可以使用其他低漏電氧化物，例如氧化鋁。 The first ruthenium oxide barrier layer 6057 is over the first charge storage layer 6056 and is formed, for example, by low pressure chemical vapor deposition high temperature oxide deposition. The first cerium oxide barrier layer 6057 has a thickness substantially less than 70 Å, and includes a range of 55 Å to 70 Å, for example, 50 Å. Barrier layer 6057 provides sufficient barrier thickness to block charge mixing and charge transport between charge storage layers 6056 and 6059. Other low leakage oxides such as alumina can also be used.

在本實施例中，第二電荷儲存層6059包括氮化矽。其具有實質大於30Å的厚度，較佳係介於30Å至60Å，包含例如40Å。在本實施例中，第二電荷儲存層6059可例如使用低壓化學氣相沉積來形成。在其他實施例中，第二電荷儲存層6059與第一電荷儲存層6056相似。第二電荷儲存層6059在FN抹除操作中用來捕捉電子以停止閘極電子注入，藉由通道電洞注入允許第一電荷儲存層6056的連續抹除。具有高電荷捕捉效率的替代材質可以包括氮氧化矽、富矽氮化物、嵌入式奈米粒子和氧化鉿。 In the present embodiment, the second charge storage layer 6059 includes tantalum nitride. It has a thickness substantially greater than 30 Å, preferably between 30 Å and 60 Å, including for example 40 Å. In the present embodiment, the second charge storage layer 6059 can be formed, for example, using low pressure chemical vapor deposition. In other embodiments, the second charge storage layer 6059 is similar to the first charge storage layer 6056. The second charge storage layer 6059 is used to capture electrons in the FN erase operation to stop gate electron injection, allowing continuous erase of the first charge storage layer 6056 by channel hole injection. Alternative materials with high charge trapping efficiencies may include bismuth oxynitride, cerium-rich nitride, embedded nanoparticle, and cerium oxide.

第二二氧化矽阻障層6052位於第二電荷儲存層6059之上，係例如採用低壓化學氣相沉積高溫氧化物沉積所形成。第二二氧化矽阻障層6052的厚度實質小於約60Å，包含介於約30Å至60Å之間的範圍，包含例如約35Å。 The second hafnium oxide barrier layer 6052 is over the second charge storage layer 6059 and is formed, for example, by low pressure chemical vapor deposition high temperature oxide deposition. The second cerium oxide barrier layer 6052 has a thickness substantially less than about 60 Å, including a range between about 30 Å and 60 Å, including, for example, about 35 Å.

最後，閘極材料層6058，例如是一種建構來作為垂直通道膜的薄膜半導體層，形成於第二阻擋層6052上方。 Finally, the gate material layer 6058 is, for example, a thin film semiconductor layer constructed as a vertical channel film, formed over the second barrier layer 6052.

第26圖係繪示用來製作記憶體元件的方法流程圖。此處所述的參考線可以是參考線的一個片段。相同的，此處所述 的位元線可以是位元線的一個片段。此方法包括：在基材上定義出要形成具有如第16圖所繪示之結構的立體記憶體區塊的區域。在每一個區域中，此一方法包括，例如藉由在基材上沉積一層二氧化矽，或其他介電材質或上述之任意組合以形成一絕緣層(步驟3601)。在絕緣層(例如第16圖所繪示之絕緣層1101)上所進行的製程包括：形成由第一導電材質所構成，適合作為字元線，且被絕緣層彼此分離的複數層。並且對複數層進行蝕刻，藉以定義出複數個導電條帶堆疊結構(例如第8圖所繪示之導電條帶堆疊結構1111)(步驟3602)。這些導電條帶堆疊結構可以至少包括一個導電條帶底部平面層(輔助閘極AGs)、複數個導電條帶中間平面層(字元線WLs)和一個導電條帶頂部平面層(串列選擇線/接地選擇線SSL/GSL)。 Figure 26 is a flow chart showing the method used to fabricate the memory elements. The reference line described herein can be a segment of a reference line. The same, described here The bit line can be a segment of the bit line. The method includes defining, on a substrate, a region to form a solid memory block having the structure as depicted in FIG. In each of the regions, the method includes forming an insulating layer, for example, by depositing a layer of ruthenium dioxide, or other dielectric material, or any combination thereof, on the substrate (step 3601). The process performed on the insulating layer (for example, the insulating layer 1101 illustrated in FIG. 16) includes forming a plurality of layers composed of the first conductive material, suitable as word lines, and separated from each other by the insulating layers. And etching the plurality of layers to define a plurality of conductive strip stack structures (such as the conductive strip stack structure 1111 illustrated in FIG. 8) (step 3602). The conductive strip stack structure may include at least one conductive strip bottom planar layer (auxiliary gate AGs), a plurality of conductive strip intermediate plane layers (word lines WLs), and a conductive strip top planar layer (serial select lines) / Ground selection line SSL/GSL).

此方法包括：在導電條帶堆疊結構之導電條帶的側邊表面形成資料儲存結構，如第9圖所繪示(步驟3603)。資料儲存結構可以包括如第9圖至第25圖所述的介電電荷捕捉結構。資料儲存結構與這些導電條帶堆疊結構之導電條帶的側邊表面接觸。 The method includes forming a data storage structure on a side surface of a conductive strip of a conductive strip stack structure, as depicted in FIG. 9 (step 3603). The data storage structure may include a dielectric charge trapping structure as described in FIGS. 9 to 25. The data storage structure is in contact with the side surfaces of the conductive strips of the conductive strip stack structure.

此方法包括：於這些導電條帶堆疊結構上形成半導體薄膜層(例如第10圖所繪示之薄膜半導體層1140)，使其具有一個表面與這些導電條帶堆疊結構共形。此薄膜層沿著這些導電條帶堆疊結構的側壁向下延伸，並且於側壁的底端相互連接(步驟3604)。 The method includes forming a semiconductor thin film layer (e.g., the thin film semiconductor layer 1140 illustrated in FIG. 10) on the conductive strip stack structure to have a surface conformal to the conductive strip stack structure. The film layers extend downwardly along the sidewalls of the conductive strip stack structures and are interconnected at the bottom ends of the sidewalls (step 3604).

在位於相鄰導電條帶堆疊結構之側壁上相互對立的半導體薄膜層之間提供絕緣結構(例如第11圖所繪示之填充結構1160)，如第11圖所述(步驟3605)。在一些實施例之中，絕緣結構包括一個縫隙至少位於用來形成記憶胞的區域中。提供絕緣結構的步驟可以包括，單純地使用縫隙將位於相鄰導電條帶堆疊結構之側壁上相互對立的半導體薄膜層隔離。 An insulating structure (e.g., fill structure 1160 as depicted in FIG. 11) is provided between mutually opposing semiconductor film layers on sidewalls of adjacent conductive strip stack structures, as described in FIG. 11 (step 3605). In some embodiments, the insulating structure includes a gap at least in a region for forming a memory cell. The step of providing an insulating structure may include isolating the mutually opposing semiconductor film layers on the sidewalls of the adjacent conductive strip stack structures by simply using the slits.

蝕刻位於複數個導電條帶堆疊結構之間的結構，藉以使用孔洞圖案來定義主動柱狀體。主動柱狀體包括位於記憶胞區域中彼此分離的垂直通道膜，如第12圖所述(步驟3606)。在主動柱狀體之間提供絕緣結構，例如以絕緣材料填充藉由步驟3606所形成的孔洞(步驟3607)。這些絕緣結構可以被絕緣材料完全填滿。這些絕緣結構可以因為具有較大的伸寬比，而僅被絕緣材料部分填滿。進而產生間隙或空隙。 The structure between the plurality of conductive strip stack structures is etched to define the active pillars using the hole pattern. The active column includes vertical channel membranes that are separated from each other in the memory cell region, as described in Figure 12 (step 3606). An insulating structure is provided between the active columns, for example, the holes formed by step 3606 are filled with an insulating material (step 3607). These insulating structures can be completely filled with insulating material. These insulating structures can be partially filled only by the insulating material because of the large aspect ratio. In turn, gaps or voids are created.

圖案化位於複數個導電條帶堆疊結構上的半導體薄膜層，藉以定義出複數個位元線銲墊和共同源極線銲墊(步驟3608)。主動柱狀體包括一個連接至位元線銲墊(如第13圖所繪示的薄膜半導體層部分2073)的垂直通道膜，以及一個連接至共同源極線銲墊(如第13圖所繪示的薄膜半導體層部分2070)的垂直通道膜。兩個以上的主動柱狀體可以分享一個共同源極線銲墊。但是每一個主動柱狀體連接至單一個位元線銲墊。這些共同源極線銲墊/位元線銲墊包括半導體插塞。 A semiconductor film layer on a plurality of conductive strip stack structures is patterned to define a plurality of bit line pads and a common source line pad (step 3608). The active column includes a vertical channel film connected to the bit line pad (such as the thin film semiconductor layer portion 2073 shown in FIG. 13), and a connection to the common source line pad (as depicted in FIG. 13) A vertical channel film of the illustrated thin film semiconductor layer portion 2070). More than two active cylinders can share a common source wire bond pad. However, each active column is connected to a single bit line pad. These common source pad/bit wire pads include semiconductor plugs.

此一方法可以更包括沉積包含參考線(如第15圖所 繪示的參考線2030)片段和跨平面層連接器(如第15圖所繪示的跨平面層連接器2031)的第一圖案化導電平面層。每一個參考線片段耦接至一個參考電壓源，在連接至兩個以上的共同源極線銲墊；每一個層間連接器連接至一個位元線銲墊。這些參考線片段和跨平面層連接器係由相同材料所構成。跨平面層連接器係由插塞所構成，插塞係由導電材料所構成，並位於穿過層間介電層之介層窗中，且連接至位元線銲墊。參考線的片段係由填充於穿過層間介電層之溝渠中的相同導電材料所構成，並且連接至共同源極線銲墊。此一方法可以更包括沉積包含耦接至感測電路之多條位元線片段的第二圖案化導電平面層。其中，每一條位元線片段分別具有複數個延伸部，如第16圖和第18A圖至第21B圖所述(步驟3609)。此外，相同或額外的圖案化導電層可以包含多個連接器。這些連接器可以耦接至串列選擇線SSL條帶、接地選擇線GSL條帶以及位於導電條帶堆疊結構中的字元線銲墊。 This method may further include depositing a reference line (as shown in Figure 15) The illustrated reference line 2030) is a first patterned conductive planar layer of segments and cross-plane layer connectors (such as the cross-planar layer connector 2031 depicted in FIG. 15). Each reference line segment is coupled to a reference voltage source that is connected to more than two common source line pads; each of the interlayer connectors is connected to a bit line pad. These reference line segments and cross-plane layer connectors are constructed of the same material. The trans-plane layer connector is composed of a plug which is made of a conductive material and is located in a via through the interlayer dielectric layer and is connected to the bit line pad. The segments of the reference line are composed of the same conductive material filled in the trenches that pass through the interlayer dielectric layer and are connected to a common source wire bond pad. The method can further include depositing a second patterned conductive planar layer comprising a plurality of bit line segments coupled to the sensing circuit. Wherein each of the bit line segments has a plurality of extensions, as described in FIG. 16 and FIGS. 18A to 21B (step 3609). Additionally, the same or additional patterned conductive layer can include multiple connectors. These connectors can be coupled to a string select line SSL strip, a ground select line GSL strip, and a word line pad located in the conductive strip stack structure.

形成主動柱狀體之後，記憶胞形成在每一個主動柱狀體的平截頭體中，複數個中間平面層(字元線)中的導電條帶之相對立側邊表面與複數條位元線結構之薄膜垂直通道的交叉點的介面區域上。同時，串列選擇開關形成於偶數導電條帶堆疊結構之頂部平面層中的導電條帶(串列選擇線SSLs)與薄膜垂直通道的交叉點的介面區域上。參考選擇開關形成於奇數導電條帶堆疊結構之頂部平面層中的導電條帶(接地選擇線GSLs)與薄膜垂直通道的交叉點的介面區域上。記憶層可以包括用來作為串列選擇 開關和參考選擇開關之閘介電層的介電層。 After the active columnar body is formed, the memory cells are formed in the frustum of each active column, and the opposite side surfaces and the plurality of bits of the conductive strips in the plurality of intermediate plane layers (character lines) On the interface area of the intersection of the vertical channels of the film of the line structure. At the same time, the tandem selection switch is formed on the interface region of the intersection of the conductive strips (serial selection lines SSLs) in the top planar layer of the even-numbered conductive strip stack structure and the vertical channels of the film. The reference selection switch is formed on the interface region of the intersection of the conductive strips (the ground selection line GSLs) in the top planar layer of the odd conductive strip stack structure and the vertical channels of the film. The memory layer can be included as a serial selection The dielectric layer of the gate dielectric of the switch and reference selection switch.

請參照圖26和此處所述的其他內容，將可更容易理解此一製作方法。在本發明的一個實施例中，此處所述的製作方法包括：形成具有側壁的第一和第二導電條帶堆疊結構；在第一和第二導電條帶堆疊結構的側壁上形成資料儲存結構；在資料儲存結構上形成相互對立的第一和第二垂直通道膜；將相互對立的第一和第二垂直通道膜相互連接藉以形成U形電路通道，並形成U形NAND串列。於第一導電條帶堆疊結構上形成第一銲墊，並連接至第一垂直通道膜；於第二導電條帶堆疊結構上形成第二銲墊，並連接至第二垂直通道膜。形成一參考線片段連接至第一銲墊，且第一銲墊可以包括半導體插塞。形成一跨平面連接器連接至第二銲墊，且第二銲墊可以包括半導體插塞。形成一個具有延伸部的位元線片段與跨平面連接器接觸。形成此一結構的結果，可提供一電流路徑，通過此半導體薄膜層，由位於第一導電條帶堆疊結構上的第一銲墊連通至位於第二導電條帶堆疊結構上的第二銲墊，進而操作成一條U形NAND串列。 Please refer to Figure 26 and other content described herein to make this fabrication method easier to understand. In one embodiment of the invention, the fabrication method described herein includes: forming first and second conductive strip stack structures having sidewalls; forming data storage on sidewalls of the first and second conductive strip stack structures a structure; forming mutually opposite first and second vertical channel films on the data storage structure; interconnecting the mutually opposing first and second vertical channel films to form a U-shaped circuit channel, and forming a U-shaped NAND string. Forming a first pad on the first conductive strip stack structure and connecting to the first vertical channel film; forming a second pad on the second conductive strip stack structure and connecting to the second vertical channel film. A reference line segment is formed to be connected to the first pad, and the first pad may include a semiconductor plug. A transplanar connector is formed to connect to the second pad, and the second pad may include a semiconductor plug. A bit line segment having an extension is formed in contact with the cross-plane connector. As a result of forming such a structure, a current path can be provided through which the first pad on the first conductive strip stack structure is connected to the second pad on the second conductive strip stack structure. And in turn operate as a U-shaped NAND string.

第27圖係繪示包含具有垂直薄膜通道膜之立體NAND記憶體陣列之積體電路901的簡化方塊圖。積體電路901記憶體陣列960。記憶體陣列960包括一個或多個具有此處所述之U形NAND串列的記憶體區塊。其中，U形NAND串列具有複數個位於積體電路基材上的垂直通道記憶胞。 Figure 27 is a simplified block diagram of an integrated circuit 901 comprising a stereo NAND memory array having vertical thin film channel films. The integrated circuit 901 is a memory array 960. Memory array 960 includes one or more memory blocks having U-shaped NAND strings as described herein. The U-shaped NAND string has a plurality of vertical channel memory cells on the integrated circuit substrate.

串列選擇線/接地選擇線SSL/GSL行解碼器940與 複數條排列在記憶體陣列960中的串列選擇線/接地選擇線SSL/GSL 945耦接。單數/偶數平面層解碼器950與複數條單數/偶數字元線955耦接。全域位元線列解碼器970與沿著記憶體陣列960的縱列排列之複數條全域位元線965耦接，藉以從記憶體陣列960中讀取資料或將資料寫入記憶體陣列960中。全域位元線被建構如第16圖所繪示的位元線2060-2062及其延伸部2041-2043和2045-2046。位址則係由匯流排930由控制邏輯910提供至全域位元線列解碼器970、串列選擇線/接地選擇線SSL/GSL行解碼器940和單數/偶數平面層解碼器950。感測放大器/寫入緩衝電路980通過第一資料線975耦接至全域位元線列解碼器970。寫入緩衝電路980可以儲存寫入碼以進行多階層寫入(multiple-level programming)，或者除存用來作為寫入碼的數值藉以判斷是否寫入或抑制被選取的位元線。全域位元線列解碼器970可以包括一個電路，用來選擇性地施加寫入或抑制電壓至位於記憶體中的位元線，以回應位於寫入緩衝區中的一個資料數值。 Tandem select line / ground select line SSL / GSL row decoder 940 and A plurality of series of select lines/ground select lines SSL/GSL 945 arranged in the memory array 960 are coupled. The singular/even plane layer decoder 950 is coupled to a plurality of singular/even digital lines 955. The global bit line decoder 970 is coupled to a plurality of global bit lines 965 arranged along the column of the memory array 960 for reading data from or writing data to the memory array 960. . The global bit lines are constructed as bit lines 2060-2062 and their extensions 2041-2043 and 2045-2046 as depicted in FIG. The address is provided by bus 930 from control logic 910 to global bit line column decoder 970, tandem select line/ground select line SSL/GSL row decoder 940, and singular/even plane decoder 950. The sense amplifier/write buffer circuit 980 is coupled to the global bit line column decoder 970 via a first data line 975. The write buffer circuit 980 can store the write code for multiple-level programming, or save the value used as the write code to determine whether to write or suppress the selected bit line. The global bit line column decoder 970 can include a circuit for selectively applying a write or suppression voltage to a bit line located in the memory in response to a data value located in the write buffer.

由感測放大器/寫入緩衝電路980發出的感測資料通過第二資料線985傳輸至多階層資料緩衝器(multi-level data buffer)990，再經由資料路徑993耦合到輸入/輸出電路991。此外在本實施例中，輸入資料被施加到多階層資料緩衝器990，用來支援對陣列中之獨立雙閘極記憶胞的每一個獨立側邊所進行的多階層寫入操作。 Sensing data from the sense amplifier/write buffer circuit 980 is transmitted through a second data line 985 to a multi-level data buffer 990, which is coupled to an input/output circuit 991 via a data path 993. Also in this embodiment, input data is applied to the multi-level data buffer 990 for supporting multi-level write operations to each of the individual sides of the individual dual-gate memory cells in the array.

輸入/輸出電路991將資料驅動至積體電路901外部的目的地。輸入/輸出資料以及控制訊號通過位於輸入/輸出電路991、控制邏輯910、積體電路901上的輸入/輸出連接埠或者積體電路901的內部或外部資料源之間的資料匯流排905來進行傳輸。積體電路901的內部或外部資料源包括，例如通用處理器或特殊用途應用電路，或者是由記憶體陣列960所支援，提供系統整合晶片(system-on-a-chip functionality)功能的模組組合。 The input/output circuit 991 drives the data to a destination outside the integrated circuit 901. The input/output data and control signals are passed through a data bus 905 located between the input/output circuit 991, the control logic 910, the input/output port on the integrated circuit 901, or the internal or external data source of the integrated circuit 901. transmission. The internal or external data source of the integrated circuit 901 includes, for example, a general purpose processor or a special purpose application circuit, or a module supported by the memory array 960 to provide a system-on-a-chip functionality. combination.

在第27圖所繪示的實施例之中，控制邏輯910使用偏壓配置狀態機(bias arrangement state machine)控制藉由電源電壓所產生或通過電壓源(方塊920)所提供的應用程序，例如讀取、抹除、驗證和寫入偏壓。控制邏輯910耦合至多階層資料緩衝器990和記憶體陣列960。控制邏輯910包括控制多階層寫入操作的邏輯。在一些實施例之中，可支援此處所述的U形垂直NAND結構，此邏輯建構來執行下述方法：例如，使用字元線層解碼器，在一陣列中選擇一層記憶胞；例如藉由選擇字元線的奇數或偶數邊的方式，在被選取的記憶胞層中選擇垂直通道結構的一邊；例如，藉由使用位於垂直通道結構之橫向行的串列選擇線開關和接地選擇線開關，在陣列被選取的橫向行中選擇複數個垂直通道結構；使用位元線電路，例如耦接至垂直通道結構之被選取之橫向行的全域位元線上的頁緩衝器(page buffer)，在被選取的層，被選 取之垂直通道的一邊，陣列一或多個被選取之縱列的電荷捕捉儲位中儲存電荷，藉以代表資料。 In the embodiment illustrated in FIG. 27, control logic 910 controls the application provided by the supply voltage or by the voltage source (block 920) using a bias arrangement state machine, such as Read, erase, verify, and write bias. Control logic 910 is coupled to multi-level data buffer 990 and memory array 960. Control logic 910 includes logic to control multi-level write operations. In some embodiments, a U-shaped vertical NAND structure as described herein may be supported, the logic constructing to perform a method of, for example, using a word line layer decoder to select a layer of memory cells in an array; Selecting one side of the vertical channel structure in the selected memory cell layer by selecting an odd or even side of the word line; for example, by using a string select line switch and a ground select line located in a horizontal row of the vertical channel structure a switch that selects a plurality of vertical channel structures in a selected horizontal row of the array; using a bit line circuit, such as a page buffer coupled to a global bit line of the selected horizontal row of the vertical channel structure, Selected at the selected layer Taking one side of the vertical channel, the charge is stored in one or more selected columns of the array of charge traps to represent the data.

在一些實施例之中，這個邏輯係建構來選擇一層，並藉由，例如控制奇數和偶數字元線層解碼器，在陣列被選取之層中選擇奇數和偶數交叉指型字元線結構之一者，來選擇一邊。 In some embodiments, the logic is configured to select a layer and select odd and even interdigitated word line structures in the selected layer of the array by, for example, controlling odd and even digital line layer decoders. One, choose one side.

在一些實施例之中，這個邏輯係建構來儲存多個層級的電荷，藉以使被選取之層的被選取的邊中的一個電荷捕捉儲位代表多個資料位元。以這種方式，位於陣列之垂直通道結構之被選取之平截頭體的一個被選取的記憶胞可儲存大於二個位元的資料，包含此記憶胞的每一邊可儲存大於一位元的資料。 In some embodiments, this logic is constructed to store multiple levels of charge such that one of the selected edges of the selected layer represents a plurality of data bits. In this manner, a selected memory cell of the selected frustum of the vertical channel structure of the array can store more than two bits of data, including that each side of the memory cell can store more than one bit. data.

控制邏輯910可以採用特殊用途邏輯電路來加以實現。在另一實施例中，控制邏輯包括實施於相同積體電路中，用來執行運算程式以控制元件操作的通用處理器。在又一實施例中，可以採用特殊用途邏輯電路和通用處理器的組合來實現此一控制邏輯。 Control logic 910 can be implemented using special purpose logic circuitry. In another embodiment, the control logic includes a general purpose processor implemented in the same integrated circuit for performing an operational program to control component operation. In yet another embodiment, this control logic can be implemented using a combination of special purpose logic circuitry and a general purpose processor.

記憶體陣列960可以包括建構來儲存多位元的電荷捕捉記憶胞。其中儲存多位元的方式，係藉由建立對應電荷儲存數量的多重寫入階層，之後建構記憶胞之臨界電壓V_T來達成。如前所述，單一位元儲存的實施例亦可適用於前述的結構中。 Memory array 960 can include charge trapping memory cells constructed to store multiple bits. The way in which the multi-bits are stored is achieved by establishing multiple write levels corresponding to the number of charge stores, and then constructing the threshold voltage V _{T of the} memory cells. As previously mentioned, embodiments of single bit storage may also be suitable for use in the foregoing structures.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。此處所述的製程步驟和結構並未涵蓋製作整體積體電路的完整製造過程。本發明可以和許多目前已知或未來被發 展出來的不同積體電路製作技術合併實施。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. The process steps and structures described herein do not encompass the complete fabrication process for making a full volume circuit. The invention can be and is currently known or will be issued in the future The different integrated circuit fabrication technologies exhibited were combined and implemented. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

69‧‧‧資料儲存結構 69‧‧‧Data storage structure

80a、80b‧‧‧垂直通道膜 80a, 80b‧‧‧ vertical channel membrane

1105‧‧‧氮化矽頂部層 1105‧‧‧The top layer of tantalum nitride

1130‧‧‧阻擋層 1130‧‧‧Block

1131‧‧‧電荷儲存層 1131‧‧‧Charge storage layer

1132‧‧‧穿隧層 1132‧‧‧ Tunneling

1101、1121、1122、1123、1124、1125‧‧‧絕緣層 1101, 1121, 1122, 1123, 1124, 1125‧‧‧ insulation

2030、2034‧‧‧參考線 2030, 2034‧‧‧ reference line

2035、2036、2037‧‧‧跨平面層間連接器 2035, 2036, 2037‧‧‧cross-plane interlayer connectors

2045、2046、2047‧‧‧延伸部 2045, 2046, 2047‧‧‧ extensions

2060-2062‧‧‧位元線 2060-2062‧‧‧ bit line

2069‧‧‧電流路徑 2069‧‧‧ Current path

2070、2071、2073、2074、2075‧‧‧薄膜半導體層的部分 2070, 2071, 2073, 2074, 2075‧‧‧ part of the thin film semiconductor layer

WL‧‧‧字元線 WL‧‧‧ character line

GSL‧‧‧接地選擇線 GSL‧‧‧ Grounding selection line

SSL‧‧‧串列選擇線 SSL‧‧‧ tandem selection line

AG‧‧‧輔助閘極 AG‧‧‧Auxiliary gate

Claims (10)

一種記憶體元件，包括：一第一導電條帶堆疊結構，具有複數個側壁；一第二導電條帶堆疊結構，具有複數個側壁；複數個資料儲存結構位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上；複數個第一垂直通道膜，位於該些資料儲存結構上，且位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上，其中每一該些第一垂直通道膜包括一第一銲墊位於該第一導電條帶堆疊結構上，且位於該第一垂直通道膜之一頂端；複數個第二垂直通道膜，位於該些資料儲存結構上，且位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上，其中每一該些第二垂直通道膜包括一第二銲墊位於該第二導電條帶堆疊結構上，且位於該第二垂直通道膜之一頂端；其中該些第一垂直通道膜和該些第二垂直通道膜彼此連接於複數個底端；一第一圖案化導電平面層(first level of patterned conductors)，位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構上方，包括一參考線片段以及一跨平面層連接器(inter-level connector)，該參考線片段與該第一銲墊連接，該跨平面層連接器與該第二銲墊連接；以及 一第二圖案化導電平面層，位於該第一圖案化導電平面層上，包括一位元線片段，該位元線片段包括一延伸部與該跨平面層連接器接觸。 A memory device comprising: a first conductive strip stack structure having a plurality of sidewalls; a second conductive strip stack structure having a plurality of sidewalls; a plurality of data storage structures being located in the first conductive strip stack structure and On the sidewalls of the second conductive strip stack structure; a plurality of first vertical channel films are disposed on the data storage structures, and are disposed on the first conductive strip stack structure and the second conductive strip stack structure Each of the first vertical channel films includes a first pad on the first conductive strip stack structure and is located at one end of the first vertical channel film; a plurality of second vertical channels Membrane, on the data storage structures, on the sidewalls of the first conductive strip stack structure and the second conductive strip stack structure, wherein each of the second vertical channel films comprises a second solder a pad is disposed on the second conductive strip stack structure and located at a top end of the second vertical channel film; wherein the first vertical channel film and the second vertical channel films are connected to each other a first level of patterned conductors, located above the first conductive strip stack structure and the second conductive strip stack structure, including a reference line segment and a cross-plane layer An inter-level connector, the reference line segment being coupled to the first pad, the cross-plane layer connector being coupled to the second pad; A second patterned conductive planar layer is disposed on the first patterned conductive planar layer and includes a one-dimensional line segment, the bit line segment including an extension portion in contact with the cross-plane layer connector. 如申請專利範圍第1項所述之記憶體元件，其中該跨平面層連接器係由一插塞所構成，該插塞係由導電材料所構成，位於穿過一層間介電層的一介層窗中，並且連接至該第二銲墊；該參考線片段係由填充於穿過該層間介電層之一溝渠中的一導電材料所構成，並連接至該第一銲墊。 The memory device of claim 1, wherein the cross-plane layer connector is formed by a plug composed of a conductive material and located in a via layer passing through an interlayer dielectric layer. And in the window, and connected to the second pad; the reference line segment is formed by a conductive material filled in a trench passing through one of the interlayer dielectric layers, and is connected to the first pad. 如申請專利範圍第1項所述之記憶體元件，更包括一多層絕緣結構位於該第一圖案化導電平面層，該多層絕緣結構包括一第一絕緣膜、一第二絕緣膜和一第三絕緣膜；該延伸部包括一鰭片位於該第一絕緣膜和該第二絕緣膜之間。 The memory device of claim 1, further comprising a plurality of insulating structures on the first patterned conductive planar layer, the multilayer insulating structure comprising a first insulating film, a second insulating film and a first a third insulating film; the extension portion includes a fin between the first insulating film and the second insulating film. 如申請專利範圍第1項所述之記憶體元件，其中該參考線片段直接與該第一銲墊接觸。 The memory component of claim 1, wherein the reference line segment is in direct contact with the first pad. 一種記憶體元件，包括：一第一導電條帶堆疊結構，具有複數個側壁；一第二導電條帶堆疊結構，具有複數個側壁； 複數個資料儲存結構位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上；複數個U形膜，具有複數個外表面直接與該些資料儲存結構接觸，且位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上；複數個第一銲墊連接位於該第一導電條帶堆疊結構上的一部分該些U形膜的複數個端點；複數個第二銲墊連接位於該第二導電條帶堆疊結構上的其他該些U形膜的複數個端點；一第一圖案化導電平面層，位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構上方，包括一參考線片段以及複數個跨平面層連接器，該參考線片段與該些第一銲墊連接，該跨平面層連接器與該些第二銲墊連接；以及一第二圖案化導電平面層，位於該第一圖案化導電平面層上，包括一位元線片段，該位元線片段包括複數個延伸部與該些跨平面層連接器接觸。 A memory device comprising: a first conductive strip stack structure having a plurality of sidewalls; and a second conductive strip stack structure having a plurality of sidewalls; a plurality of data storage structures are disposed on the sidewalls of the first conductive strip stack structure and the second conductive strip stack structure; a plurality of U-shaped films having a plurality of outer surfaces directly contacting the data storage structures, and Located on the sidewalls of the first conductive strip stack structure and the second conductive strip stack structure; the plurality of first pads are connected to a plurality of the U-shaped films on the first conductive strip stack structure An end point; a plurality of second pads connecting the plurality of end points of the other U-shaped films on the second conductive strip stack structure; a first patterned conductive planar layer located on the first conductive strip Above the stack structure and the second conductive strip stack structure, including a reference line segment and a plurality of cross-plane layer connectors, the reference line segments are connected to the first pads, the cross-plane layer connector and the first a second pad connection; and a second patterned conductive planar layer on the first patterned conductive planar layer, including a one-dimensional line segment, the bit line segment including a plurality of extensions connected to the cross-plane layers Contact. 如申請專利範圍第5項所述之記憶體元件，更包括一多層絕緣結構位於該第一圖案化導電平面層，該多層絕緣結構包括一第一絕緣膜、一第二絕緣膜和一第三絕緣膜；該些延伸部之一者包括一鰭片位於該第一絕緣膜和該第二絕緣膜之間。 The memory device of claim 5, further comprising a plurality of insulating structures on the first patterned conductive planar layer, the multilayer insulating structure comprising a first insulating film, a second insulating film and a first a third insulating film; one of the extensions including a fin between the first insulating film and the second insulating film. 如申請專利範圍第5項所述之記憶體元件，其中該參考線片段直接與該些第一銲墊接觸。 The memory component of claim 5, wherein the reference line segment is in direct contact with the first pads. 一種記憶體元件的製作方法，包括：形成一第一導電條帶堆疊結構，使其具有複數個側壁；形成一第二導電條帶堆疊結構，使其具有複數個側壁；形成複數個資料儲存結構位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構的該些側壁上；形成複數個U形膜，使其具有複數個外表面直接與該些資料儲存結構接觸，且位於該第一導電條帶堆疊結構和該第二導電條帶堆疊結構之間；該些U形膜之一者具有位於該第一導電條帶堆疊結構上一第一銲墊以及位於該第二導電條帶堆疊結構上的一第二銲墊；沉積一第一圖案化導電平面層，以提供一參考線片段與該些第一銲墊連接，以及一跨平面層連接器與該些第二銲墊連接；以及沉積一第二圖案化導電平面層，以提供一位元線片段，使該位元線片段包括一延伸部與該跨平面層連接器接觸。 A method for fabricating a memory device, comprising: forming a first conductive strip stack structure having a plurality of sidewalls; forming a second conductive strip stack structure having a plurality of sidewalls; forming a plurality of data storage structures Positioning on the sidewalls of the first conductive strip stack structure and the second conductive strip stack structure; forming a plurality of U-shaped films having a plurality of outer surfaces directly contacting the data storage structures, and located at the Between the first conductive strip stack structure and the second conductive strip stack structure; one of the U-shaped films has a first pad on the first conductive strip stack structure and the second conductive strip a second pad on the stacked structure; depositing a first patterned conductive planar layer to provide a reference line segment to the first pads, and a cross-plane layer connector and the second pads And depositing a second patterned conductive planar layer to provide a bit line segment such that the bit line segment includes an extension in contact with the cross-plane layer connector. 如申請專利範圍第8項所述之記憶體元件的製作方法，更包括：沉積一第一絕緣膜和一第二絕緣膜於該第一圖案化導電平面層上；圖案化以形成一開孔於該第二絕緣膜中；沉積一第三絕緣膜於圖案化的該第二絕緣膜上；圖案化以於該第三絕緣膜形成一條帶；移除一部分該第一絕緣膜、一部分該第二絕緣膜和一部分該第三絕緣膜，藉以將該跨平面層連接器的一頂面暴露於外；以及以一導電層填充被該第一絕緣膜、該第二絕緣膜和該第三絕緣膜被移除的該些部分。 The method of fabricating the memory device of claim 8, further comprising: depositing a first insulating film and a second insulating film on the first patterned conductive planar layer; patterning to form an opening In the second insulating film; depositing a third insulating film on the patterned second insulating film; patterning to form a strip on the third insulating film; removing a portion of the first insulating film, a portion of the first insulating film a second insulating film and a portion of the third insulating film, thereby exposing a top surface of the trans-plane layer connector to the outside; and filling the first insulating film, the second insulating film and the third insulating layer with a conductive layer The portions of the film that are removed. 如申請專利範圍第9項所述之記憶體元件的製作方法，其中該延伸部包括一鰭片，位於該第一絕緣膜和該第二絕緣膜之間。 The method of fabricating a memory device according to claim 9, wherein the extending portion comprises a fin between the first insulating film and the second insulating film.