TWI571959B - Power trench mosfet with mproved uis performance and preparation method thereof - Google Patents
Power trench mosfet with mproved uis performance and preparation method thereof Download PDFInfo
- Publication number
- TWI571959B TWI571959B TW103130224A TW103130224A TWI571959B TW I571959 B TWI571959 B TW I571959B TW 103130224 A TW103130224 A TW 103130224A TW 103130224 A TW103130224 A TW 103130224A TW I571959 B TWI571959 B TW I571959B
- Authority
- TW
- Taiwan
- Prior art keywords
- contact hole
- trench
- layer
- region
- active
- Prior art date
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本發明涉及一種用於功率轉換之金屬氧化物半導體場效應電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor；MOSFET)的半導體器件，更確切的說，本發明旨在提供具有較好非箝制電感性切換(Unclamped Inductive Switching；UIS)之切換能力的溝槽式功率半導體器件，優化溝槽式功率半導體器件的突崩擊穿能力並提供製備該器件的方法。 The present invention relates to a semiconductor device for a metal-oxide-semiconductor field-effect transistor (MOSFET) for power conversion, and more particularly, the present invention is directed to providing a better non-clamping power A trench power semiconductor device with switching capability of Unclamped Inductive Switching (UIS) optimizes the collapse breakdown capability of the trench power semiconductor device and provides a method of fabricating the device.
在功率半導體器件中，基於電晶體單元密度和其他各種優勢的考慮，閘極可以形成在自半導體矽襯底的表面向下延伸的溝槽之中，典型的範例就是溝槽式金屬氧化物半導體場效應電晶體(MOSFET)，其他的例如還包括溝槽式的絕緣閘極雙極電晶體等，它們有一個共同的特徵，就是都包括各類具有各種功能的溝槽，但出於器件自身結構的特性，某些時候，很多溝槽底部處的電場強度顯示出為器件的最高電場水平，在電壓升高到器件進入突崩擊穿(avalanche breakdown)的點上，在溝槽的角部突崩擊穿過程中將出現碰撞電離，會發生擊穿或崩潰(breakdown)產生崩潰電流。突崩擊穿一般容易導致熱載流子效應，當接近閘極氧化層處發生擊穿時，一個不良後果是熱載流子可以被捕獲注入至閘極氧化層，這可以損傷或斷裂閘極氧化層，誘發功率器件長期的可靠性問題。此外，這樣的溝槽 常常成為器件達到高崩潰電壓的限制因素。 In power semiconductor devices, based on the transistor cell density and various other advantages, the gate can be formed in a trench extending downward from the surface of the semiconductor germanium substrate, a typical example being a trench metal oxide semiconductor. Field effect transistors (MOSFETs), others include, for example, trenched insulated gate bipolar transistors, etc., which have a common feature, which includes various types of trenches with various functions, but for the device itself. The characteristics of the structure, in some cases, the electric field strength at the bottom of many trenches shows the highest electric field level of the device, at the point where the voltage rises to the avalanche breakdown of the device, at the corner of the trench Collision ionization occurs during the breakdown and breakdown, and breakdown or breakdown occurs to generate a breakdown current. Abrupt breakdown generally leads to a hot carrier effect. When breakdown occurs near the gate oxide layer, a negative consequence is that hot carriers can be trapped and injected into the gate oxide layer, which can damage or break the gate. The oxide layer induces long-term reliability problems with power devices. In addition, such a groove It is often the limiting factor for devices to achieve high breakdown voltages.
另一個問題是，如果在低電流水平突崩擊穿期間，終端區發生擊穿不會過大的妨礙器件的性能，此時器件無需擔憂安全工作問題。但是一旦在一些特殊的工作期間，例如非箝制電感性切換(UIS)的切換期間，由於電路系統中電感的電流不會突變，導致器件往往要承受一些比較大的電壓強度，相當於器件處於高電流水平突崩擊穿事件期間，面積有限的終端區很可能將無法安全有效地處理功率損耗，因為一個功率器件不可能消減器件有效電晶體單元的面積而無限地給終端區分配過大的面積，而後果就是，終端區的擊穿會作為一個負面效應來影響了器件的安全工作區域(Safe Operating Area；SOA)，這都是我們所不期望發生的。 Another problem is that if breakdown occurs in the termination region during a low current level burst breakdown, the device does not interfere with device performance, and the device does not need to worry about safe operation. However, during some special work periods, such as non-clamping inductive switching (UIS) switching, the current of the inductor in the circuit system does not change, causing the device to withstand some relatively large voltage strength, which is equivalent to the device being high. During a current level collapse breakdown event, a limited area of the termination area is likely to be unable to handle power loss safely and efficiently, because it is impossible for one power device to reduce the area of the effective transistor unit of the device and to infinitely allocate an excessive area to the termination area. The consequence is that the breakdown of the termination zone can affect the Safe Operating Area (SOA) of the device as a negative effect, which is something we don't expect to happen.
正是鑒於現有技術所面臨的該等各種棘手難題，本發明認為很有必要將器件限定在安全工作區域(SOA)和設定在最優的非箝制電感性切換(UIS)條件下，重新調整分布於器件的電場強度，使功率轉換器件具備較佳的SOA和良好的UIS能力，所以本發明就是在這一前提下提出了後續內容中的各項實施方案。 In view of the various difficult problems faced by the prior art, the present invention recognizes that it is necessary to limit the device to a safe working area (SOA) and to set the optimal non-clamping inductive switching (UIS) condition to readjust the distribution. The electric field strength of the device makes the power conversion device have better SOA and good UIS capability, so the present invention proposes various implementations in the subsequent content under this premise.
在一個實施例中，本發明提出了一種溝槽式功率半導體器件的製備方法，包括以下步驟：提供一個半導體襯底或稱基板/基材，包含底部襯底及位於底部襯底上方的外延層；蝕刻外延層，形成一個環形隔離溝槽和位於隔離溝槽內側的有源溝槽，在隔離溝槽附近的一個有源溝槽與隔離溝槽之間具有一個有源至終端過渡區，介於一有源區和一終端區之間；填充導電材料至隔離溝槽內，並在有源溝槽內製備閘極；沉積一個絕緣鈍 化層覆蓋在半導體襯底上方；蝕刻絕緣鈍化層及過渡區、有源區各自的臺面結構，形成貫穿絕緣鈍化層、向下延伸至有源區臺面結構內的第一接觸孔，和形成貫穿絕緣鈍化層、向下延伸至過渡區臺面結構內的第二接觸孔；第一接觸孔的深度值、寬度值分別對應地大於第二接觸孔的深度值、寬度值。 In one embodiment, the present invention provides a method of fabricating a trench power semiconductor device, comprising the steps of: providing a semiconductor substrate or substrate/substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate Etching the epitaxial layer to form an annular isolation trench and an active trench inside the isolation trench, and an active-to-terminal transition region between the active trench and the isolation trench near the isolation trench Between an active region and a termination region; filling a conductive material into the isolation trench and preparing a gate in the active trench; depositing an insulating blunt The layer is overlying the semiconductor substrate; etching the insulating passivation layer and the mesa structure of the transition region and the active region, forming a first contact hole extending through the insulating passivation layer and extending downward into the active area mesa structure, and forming a through The insulating passivation layer extends downward to the second contact hole in the transition region mesa structure; the depth value and the width value of the first contact hole are respectively corresponding to the depth value and the width value of the second contact hole.
上述方法中，半導體襯底具第一導電類型，在沉積絕緣鈍化層之前，先在外延層的頂部植入摻雜物形成一個第二導電類型的本體層；以及隨後至少在有源區的本體層的頂部植入摻雜物形成一個第一導電類型的頂部摻雜層。 In the above method, the semiconductor substrate has a first conductivity type, and a dopant is implanted on top of the epitaxial layer to form a body layer of a second conductivity type before depositing the insulating passivation layer; and then at least in the body of the active region The top implant of the layer implants a top doped layer of a first conductivity type.
上述方法中，在形成第一及第二接觸孔的步驟中，更包含：將一遮罩覆蓋在絕緣鈍化層上方，並至少形成遮罩中的第一、第二開口；用第一開口來蝕刻製備第一接觸孔的同時，還用第二開口來蝕刻製備第二接觸孔，第一開口比第二開口的尺寸要大。 In the above method, in the step of forming the first and second contact holes, further comprising: covering a mask over the insulating passivation layer and forming at least the first and second openings in the mask; using the first opening While the first contact hole is etched, the second contact hole is also etched by the second opening, and the first opening is larger than the second opening.
上述方法中，在形成第一及第二接觸孔的步驟中，更包含：將一第一遮罩覆蓋在絕緣鈍化層之上並在第一遮罩中至少形成第一開口，以第一開口蝕刻製備第一接觸孔；剝離第一遮罩後，將一第二遮罩覆蓋在絕緣鈍化層之上並在第二遮罩中至少形成第二開口，以第二開口蝕刻製備第二接觸孔；第一開口比第二開口具有更大的開口尺寸。 In the above method, in the step of forming the first and second contact holes, further comprising: covering a first mask over the insulating passivation layer and forming at least a first opening in the first mask to the first opening Etching a first contact hole; after peeling off the first mask, covering a second mask over the insulating passivation layer and forming at least a second opening in the second mask, and etching the second opening to form a second contact hole The first opening has a larger opening size than the second opening.
上述方法中，通過第一、第二接觸孔，向過渡區、有源區各自的本體層中注入與本體層摻雜類型相同，但摻雜濃度更大的摻雜物以形成本體接觸區；由於第二接觸孔相對第一接觸孔而較小的深度值、寬度值，使形成於第二接觸孔底部周圍的本體接觸區比形成於第一接觸孔底部周圍 的本體接觸區深度更淺、擴散範圍更小。 In the above method, dopants having the same doping type as the bulk layer but having a higher doping concentration are implanted into the body layers of the transition region and the active region through the first and second contact holes to form a body contact region; Due to the smaller depth value and width value of the second contact hole relative to the first contact hole, the body contact area formed around the bottom of the second contact hole is formed around the bottom of the first contact hole The body contact area is shallower in depth and has a smaller diffusion range.
在一個實施例中，本發明提出了一種溝槽式功率半導體器件，包括：一個半導體襯底，包含底部襯底及位於底部襯底上方的外延層；設置在外延層中的一個環形隔離溝槽和位於隔離溝槽內側的有源溝槽，在隔離溝槽附近的一個有源溝槽與隔離溝槽之間具有一個有源至終端過渡區，介於一有源區和一終端區之間；內襯於隔離溝槽、有源溝槽底部和側壁的絕緣層，以及設置在隔離溝槽內的導電材料，和設置在有源溝槽內的閘極；覆蓋在半導體襯底上方的一個絕緣鈍化層；貫穿絕緣鈍化層、向下延伸至有源區臺面結構內的第一接觸孔，貫穿絕緣鈍化層、向下延伸至過渡區臺面結構內的第二接觸孔；第一接觸孔的深度值、寬度值分別對應地大於第二接觸孔的深度值、寬度值。 In one embodiment, the present invention provides a trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the underlying substrate; and an annular isolation trench disposed in the epitaxial layer And an active trench located inside the isolation trench, having an active-to-terminal transition region between an active trench and the isolation trench adjacent the isolation trench, between an active region and a termination region An insulating layer lining the isolation trench, the bottom and sidewalls of the active trench, and a conductive material disposed within the isolation trench, and a gate disposed within the active trench; a layer overlying the semiconductor substrate An insulating passivation layer; a first contact hole extending through the insulating passivation layer and extending into the active area mesa structure, a second contact hole extending through the insulating passivation layer and extending downward into the transition region mesa structure; the first contact hole The depth value and the width value are respectively corresponding to the depth value and the width value of the second contact hole.
上述溝槽式功率半導體器件中，設於第一、第二接觸孔內的金屬栓塞，和設於絕緣鈍化層中對準隔離溝槽中導電材料的接觸孔內的金屬栓塞，都與絕緣鈍化層上方交疊在有源區、過渡區及隔離溝槽之上的頂部金屬電極電性接觸。 In the above trench power semiconductor device, the metal plugs disposed in the first and second contact holes, and the metal plugs disposed in the contact holes of the conductive material in the insulating passivation layer aligned with the isolation trench are insulated and passivated The top metal electrode is electrically contacted over the active region, the transition region, and the isolation trench over the layer.
上述溝槽式功率半導體器件中，半導體襯底具第一導電類型，在外延層的頂部形成有一第二導電類型的本體層，和至少在有源區的本體層的頂部形成有一第一導電類型的頂部摻雜層；其中第一、第二接觸孔終止在本體層內。 In the above trench power semiconductor device, the semiconductor substrate has a first conductivity type, a body layer of a second conductivity type is formed on top of the epitaxial layer, and a first conductivity type is formed at least on top of the body layer of the active region a top doped layer; wherein the first and second contact holes terminate within the body layer.
上述溝槽式功率半導體器件中，在第一、第二接觸孔的底部周圍植入有第二導電類型的本體接觸區；其中，第二接觸孔底部周圍的本體接觸區的深度、擴散範圍，分別對應地比第一接觸孔底部周圍的本體接 觸區的深度、擴散範圍要小。器件在非箝制電感性切換(UIS)之轉換期間，當發生突崩擊穿時，有源區本體層和外延層之間PN結發生突崩擊穿時還未觸發隔離溝槽底部拐角處的突崩擊穿。 In the above trench type power semiconductor device, a body contact region of a second conductivity type is implanted around a bottom of the first and second contact holes; wherein a depth of the body contact region around the bottom of the second contact hole, a diffusion range, Correspondingly corresponding to the body around the bottom of the first contact hole The depth and diffusion range of the contact area should be small. During the transition of the device during the non-clamping inductive switching (UIS), when the breakdown breakdown occurs, the PN junction between the active region body layer and the epitaxial layer collapses and does not trigger the bottom corner of the isolation trench. Sudden breakdown.
上述溝槽式功率半導體器件，設置在有源溝槽內的閘極包括位於有源溝槽內下部的屏蔽閘極和位於有源溝槽內上部的控制閘極，並在屏蔽閘極和控制閘極之間設置有絕緣層將它們絕緣隔離；屏蔽閘極與隔離溝槽內的導電材料具有相同的電位。 In the above trench power semiconductor device, the gate disposed in the active trench includes a shield gate located in the lower portion of the active trench and a control gate located in the upper portion of the active trench, and is in the shield gate and the control An insulating layer is disposed between the gates to insulate them; the shield gate has the same potential as the conductive material in the isolation trench.
在另一個可選實施例中，本發明揭示了一種溝槽式功率半導體器件，包括：一個半導體襯底，半導體襯底包含底部襯底及位於底部襯底上方的外延層；具有多個第一溝槽，並設置在相鄰第一溝槽之間的第一臺面以及設置在第一溝槽和第二溝槽之間的第二臺面，其中第一、第二和第三溝槽從外延層的上表面延伸到外延層之中；設置在第一臺面從外延層的上表面延伸到外延層之中第一深度的源極區，該源極區具有與外延層完全相同的導電類型且延伸第一臺面的整個寬度；設置在第一臺面從源極區的底部向下延伸到外延層之中第二深度的第一本體區，第一本體區具有與外延層相反的導電類型且延伸第一臺面的整個寬度；設置在第二臺面從外延層的上表面延伸到外延層之中第三深度的第二本體區，第二本體區具有與外延層相反的導電類型且延伸第二臺面的整個寬度；從外延層的上表面延伸穿過源極區到達第一本體區的第一接觸孔，第一接觸孔被導電材料填充；從外延層的上表面延伸到第二本體區的第二接觸孔，第二接觸孔被導電材料填充；其中第一接觸孔的深度值、寬度值分別對應地大於第二接觸孔的深度值、寬度值。 In another alternative embodiment, the present invention discloses a trench power semiconductor device comprising: a semiconductor substrate comprising a bottom substrate and an epitaxial layer over the bottom substrate; having a plurality of first a trench, and a first mesa disposed between adjacent first trenches and a second mesa disposed between the first trench and the second trench, wherein the first, second, and third trenches are epitaxial An upper surface of the layer extends into the epitaxial layer; a source region extending from the upper surface of the epitaxial layer to a first depth in the epitaxial layer, the source region having exactly the same conductivity type as the epitaxial layer Extending the entire width of the first mesa; providing a first body region extending downward from the bottom of the source region to a second depth in the epitaxial layer, the first body region having a conductivity type opposite to the epitaxial layer and extending a whole width of the first mesa; a second body region extending from the upper surface of the epitaxial layer to a third depth in the epitaxial layer, the second body region having a conductivity type opposite to the epitaxial layer and extending the second mesa of a width; a first contact hole extending from the upper surface of the epitaxial layer through the source region to the first body region, the first contact hole being filled with a conductive material; extending from the upper surface of the epitaxial layer to the second portion of the second body region The contact hole is filled with a conductive material; wherein the depth value and the width value of the first contact hole are respectively larger than the depth value and the width value of the second contact hole.
上述溝槽式功率半導體器件中，所述的第一溝槽為有源溝槽，其內部填充有導電材料，第一溝槽內的所述導電材料與外延層絕緣並形成溝槽閘極。 In the above trench power semiconductor device, the first trench is an active trench filled with a conductive material, and the conductive material in the first trench is insulated from the epitaxial layer and forms a trench gate.
上述溝槽式功率半導體器件中，所述的第二溝槽填充導電材料，第二溝槽內的所述導電材料與外延層絕緣，並且第二溝槽形成隔離溝槽。 In the above trench power semiconductor device, the second trench is filled with a conductive material, the conductive material in the second trench is insulated from the epitaxial layer, and the second trench forms an isolation trench.
上述溝槽式功率半導體器件中，所述的第三深度和第二深度具有相同的深度。 In the above trench power semiconductor device, the third depth and the second depth have the same depth.
上述溝槽式功率半導體器件中，還包括設置在第一接觸孔底部的本體導電型摻雜區或本體接觸區，其摻雜濃度比所述的第一本體區的摻雜濃度還要高。 In the above trench power semiconductor device, the body conductive type doped region or the body contact region disposed at the bottom of the first contact hole is further included, and the doping concentration thereof is higher than the doping concentration of the first body region.
上述溝槽式功率半導體器件中，還包括設置在第二接觸孔底部的本體導電型摻雜區或本體接觸區，其摻雜濃度比所述的第二本體區的摻雜濃度還要高。 The trench power semiconductor device further includes a body conductive type doped region or a body contact region disposed at a bottom of the second contact hole, the doping concentration of which is higher than a doping concentration of the second body region.
上述溝槽式功率半導體器件中，所述的第三溝槽圍繞第一和第二溝槽。 In the above trench power semiconductor device, the third trench surrounds the first and second trenches.
上述溝槽式功率半導體器件中，填充第一接觸孔的導電材料與填充第二接觸孔的導電材料電性連接。 In the above trench type power semiconductor device, the conductive material filling the first contact hole is electrically connected to the conductive material filling the second contact hole.
上述溝槽式功率半導體器件中，為端接溝槽的所述的第三溝槽內填充有導電材料，第三溝槽內所述導電材料與外延層絕緣。 In the above trench type power semiconductor device, the third trench which is a termination trench is filled with a conductive material, and the conductive material in the third trench is insulated from the epitaxial layer.
上述溝槽式功率半導體器件中，還包括設置在第三溝槽外側的外延層頂部的本體區中的第三接觸孔，其中第三接觸孔內填充的導電材 料與填充第三溝槽的導電材料電連接。 The trench power semiconductor device further includes a third contact hole disposed in a body region at the top of the epitaxial layer outside the third trench, wherein the third contact hole is filled with a conductive material The material is electrically connected to the conductive material filling the third trench.
100‧‧‧底部襯底 100‧‧‧Bottom substrate
101‧‧‧端接溝槽 101‧‧‧Terminal trench
101a、102a‧‧‧導電材料 101a, 102a‧‧‧ conductive materials
101b、102b‧‧‧絕緣層 101b, 102b‧‧‧ insulation
102‧‧‧隔離溝槽 102‧‧‧Isolation trench
103‧‧‧有源溝槽 103‧‧‧Active trench
103a‧‧‧屏蔽閘極 103a‧‧‧Shield gate
103b~103d‧‧‧絕緣層 103b~103d‧‧‧Insulation
103e‧‧‧控制閘極 103e‧‧‧Control gate
103-1‧‧‧有源溝槽 103-1‧‧‧Active trench
110‧‧‧外延層 110‧‧‧ Epilayer
120‧‧‧本體層 120‧‧‧ body layer
125‧‧‧邊緣 125‧‧‧ edge
130‧‧‧頂部摻雜層 130‧‧‧Top doped layer
140‧‧‧絕緣鈍化層 140‧‧‧Insulation passivation layer
200‧‧‧終端區 200‧‧‧ terminal area
250‧‧‧過渡區 250‧‧‧Transition zone
250a‧‧‧臺面結構 250a‧‧‧ countertop structure
300‧‧‧有源區 300‧‧‧Active area
300a‧‧‧臺面結構 300a‧‧‧ countertop structure
400‧‧‧遮罩 400‧‧‧ mask
400a~400e‧‧‧開口 400a~400e‧‧‧ openings
401‧‧‧第一遮罩 401‧‧‧ first mask
402‧‧‧第二遮罩 402‧‧‧second mask
501~505‧‧‧接觸孔 501~505‧‧‧Contact hole
504a‧‧‧接觸孔504延伸到半導體襯底內的部份 504a‧‧‧ contact hole 504 extending into the semiconductor substrate
504’‧‧‧接觸孔 504’‧‧‧Contact hole
505a‧‧‧接觸孔505延伸到半導體襯底內的部份 505a‧‧‧ contact hole 505 extending into the semiconductor substrate
555‧‧‧金屬栓塞 555‧‧‧Metal embolism
601、601’、602‧‧‧本體接觸區 601, 601', 602‧‧ ‧ body contact area
611‧‧‧金屬場板 611‧‧‧Metal field plate
612‧‧‧頂部金屬電極 612‧‧‧Top metal electrode
613‧‧‧底部金屬電極 613‧‧‧Bottom metal electrode
700、700’‧‧‧崩潰電流 700,700’‧‧‧Crash current
第1圖是本發明的器件包含了端接溝槽、隔離溝槽和有源溝槽的局部俯視圖。 Figure 1 is a partial top plan view of the device of the present invention including termination trenches, isolation trenches, and active trenches.
第2A~2J圖是製備溝槽式MOSFET器件的方法流程示意圖。 2A~2J are schematic flow diagrams of a method for fabricating a trench MOSFET device.
第3A~3B圖是基於第2A~2J圖的步驟但利用兩個遮罩製備不同深度和寬度的接觸孔。 Figures 3A-3B are based on the steps of Figures 2A-2J but using two masks to make contact holes of different depths and widths.
第4A圖顯示了終端區到有源區介面處的接觸孔與有源區的接觸孔在相同寬度和深度的條件下，該介面處一個隔離溝槽角部附近的大體電場強度。 Fig. 4A shows the general electric field strength near the corner of an isolation trench at the same width and depth of the contact hole between the terminal region and the active region interface and the contact hole of the active region.
第4B圖顯示了第4A圖的結構中終端區到有源區介面處的隔離溝槽角部處發生突崩擊穿時的崩潰電流流向的大致示意圖。 Fig. 4B is a schematic view showing the flow of the collapse current at the corner of the isolation trench at the junction of the terminal region to the active region interface in the structure of Fig. 4A.
第5A圖顯示了終端區到有源區介面處的接觸孔與有源區的接觸孔在不同寬度和深度的條件下，該介面處一個隔離溝槽角部附近的大體電場強度。 Figure 5A shows the approximate electric field strength near the corner of an isolation trench at the interface between the contact hole of the termination region and the active region interface and the contact hole of the active region at different widths and depths.
第5B圖顯示了第5A圖的結構中終端區到有源區介面處的隔離溝槽角部處發生突崩擊穿時的崩潰電流流向的大致示意圖。 Fig. 5B is a schematic view showing the flow of the collapse current at the time of the collapse breakdown at the corner of the isolation trench at the termination region to the active region interface in the structure of Fig. 5A.
在第2A圖中，在溝槽式MOSFET器件中，一個半導體襯底包括一個重摻雜的底部襯底100，和包括一個相對底部襯底100而摻雜濃度要低很多的外延層110，它們的導電摻雜類型相同，後續內容以N+的底部襯 底100和N-的外延層110作為示範進行闡釋。以圖中未示意出的一個帶有開口圖案的遮罩(mask)對外延層110實施蝕刻，分別形成了從外延層110的上表面向下延伸的端接溝槽101、隔離溝槽102和多個有源溝槽103，它們的底部終止在外延層110中。為了更詳盡的瞭解各個溝槽之間的佈局方式，在第1圖的俯視圖中，展示了一個單獨晶片的半導體襯底的局部圖，晶片具有虛線表示的邊緣125，而在半導體襯底的一個環形的隔離溝槽102的內側形成有半導體襯底中的多個有源溝槽103，在隔離溝槽102外側則是半導體襯底的終端區200，終端區200環繞著隔離溝槽102，並且在終端區200中形成有一個環形的端接溝槽101靠近邊緣125。 In FIG. 2A, in a trench MOSFET device, a semiconductor substrate includes a heavily doped underlying substrate 100, and an epitaxial layer 110 including a relatively lower doping concentration relative to the underlying substrate 100. The conductivity doping type is the same, the subsequent content is N+ bottom lining The epitaxial layer 110 of the bottom 100 and N- is illustrated as an example. The epitaxial layer 110 is etched by a mask having an opening pattern, not shown in the figure, to form a termination trench 101, an isolation trench 102, and a recess extending downward from the upper surface of the epitaxial layer 110, respectively. A plurality of active trenches 103 whose bottoms terminate in epitaxial layer 110. For a more detailed understanding of the layout between the various trenches, in the top view of FIG. 1, a partial view of a semiconductor substrate of a single wafer having an edge 125 indicated by a dashed line and a semiconductor substrate The inner side of the annular isolation trench 102 is formed with a plurality of active trenches 103 in the semiconductor substrate, outside the isolation trench 102 is the termination region 200 of the semiconductor substrate, and the termination region 200 surrounds the isolation trench 102, and An annular termination trench 101 is formed in the termination region 200 adjacent the edge 125.
在第2B圖中，先在端接溝槽101側壁及底部形成一個絕緣層101b，和在隔離溝槽102側壁及底部形成一個絕緣層102b，以及在每個有源溝槽103的側壁及底部形成一個絕緣層103b，這些絕緣層101b、102b、103b可以同步形成，例如通過熱氧化工藝生長的二氧化矽層。在第2B~2C圖的步驟中，需要再在各個溝槽內部填充導電材料，例如填充摻雜的多晶矽材料到端接溝槽101、隔離溝槽102和有源溝槽103之中。但需要將每個有源溝槽103上部的導電材料執行回蝕(etch back)以便移除掉，而僅僅保留每個有源溝槽103下部的導電材料構成一個屏蔽閘極(Shield Gate；SG)103a，此後再利用低壓化學氣相沈積法(Low Pressure CVD；LPCVD)或電漿輔助化學氣相沈積(Plasma-Enhanced CVD；PECVD)法製備如SiO2的絕緣材料，填充在有源溝槽103上部由於去除導電材料而形成的間隙空間中，來覆蓋在屏蔽閘極103a之上。並隨即回蝕間隙空間中的絕緣材料和有源溝槽103上部側壁原有的絕緣層103b，將它們移除掉，僅僅保留位於屏蔽閘極103a上方 的一層絕緣層103c。其後再在有源溝槽103上部的側壁上生成緻密的絕緣層103d如SiO2作為閘極氧化層，並在每個有源溝槽103上部的間隙空間中再重新填充導電材料，製備一個控制閘極103e。在有源溝槽103內，作為閘極氧化層的絕緣層103d比有源溝槽103下部的側壁上保留的絕緣層103b要薄，控制閘極103e交疊在屏蔽閘極103a之上，但藉由它們之間的絕緣層103c而彼此相互電絕緣。控制閘極103e作為MOSFET電晶體單元的有效閘極電極，但每個屏蔽閘極103a則都耦合到MOSFET的源極電極而與源極等位，這樣可以適當降低閘極與汲極間的寄生電容Cgd。 In FIG. 2B, an insulating layer 101b is formed on the sidewalls and the bottom of the termination trench 101, and an insulating layer 102b is formed on the sidewalls and the bottom of the isolation trench 102, and at the sidewall and bottom of each active trench 103. An insulating layer 103b is formed, and these insulating layers 101b, 102b, 103b may be formed simultaneously, for example, a cerium oxide layer grown by a thermal oxidation process. In the steps of FIGS. 2B-2C, it is necessary to fill a conductive material inside each trench, for example, filling the doped polysilicon material into the termination trench 101, the isolation trench 102, and the active trench 103. However, it is necessary to perform an etch back of the conductive material on the upper portion of each active trench 103 for removal, and only the conductive material of the lower portion of each active trench 103 is reserved to form a shield gate (Shield Gate; SG 103a, thereafter, an insulating material such as SiO2 is prepared by low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD), and is filled in the active trench 103. The upper portion is covered in the gap space formed by removing the conductive material to cover the shield gate 103a. And then etch back the insulating material in the gap space and the original insulating layer 103b of the upper sidewall of the active trench 103, remove them, and only remain above the shield gate 103a. An insulating layer 103c. Thereafter, a dense insulating layer 103d such as SiO2 is formed as a gate oxide layer on the sidewall of the upper portion of the active trench 103, and a conductive material is refilled in the gap space in the upper portion of each active trench 103 to prepare a control. Gate 103e. In the active trench 103, the insulating layer 103d as the gate oxide layer is thinner than the insulating layer 103b remaining on the sidewall of the lower portion of the active trench 103, and the control gate 103e overlaps the shield gate 103a, but They are electrically insulated from each other by the insulating layer 103c therebetween. The control gate 103e serves as an effective gate electrode of the MOSFET transistor unit, but each of the shield gates 103a is coupled to the source electrode of the MOSFET and is equipotential with the source, so that the parasitic between the gate and the drain can be appropriately reduced. Capacitor Cgd.
在第2C圖中，場效應電晶體單元都形成在有源區300，有源溝槽103作為MOSFET電晶體單元或晶胞的閘極溝槽，在半導體襯底的有源區300製備有多個這樣的有源溝槽103。在隔離溝槽102附近的一個有源溝槽103-1與隔離溝槽102之間具有一個有源至終端過渡區或介面區(Active to termination interface area)250，半導體襯底的該過渡區250介於有源區300和終端區200之間，在很多時候其實也可以認為過渡區250是起到了終端結構的作用。為了進行區分，在所有的有源溝槽103中，定義有源溝槽103-1為所有那些並排設置的有源溝槽103中最靠外的溝槽，同時也最靠近隔離溝槽102的平行於有源溝槽103的那一部分，最外側的這個有源溝槽103-1與隔離溝槽102之間的區域被定義為過渡區250。依第1圖和第2C圖可以獲悉，在隔離溝槽102的內側，除了有源區300之外，還有過渡區250。 In FIG. 2C, field effect transistor units are formed in the active region 300, and the active trench 103 serves as a MOSFET transistor unit or a gate trench of the unit cell, and is prepared in the active region 300 of the semiconductor substrate. One such active trench 103. There is an active-to-terminal transition region 250 between an active trench 103-1 and the isolation trench 102 near the isolation trench 102, the transition region 250 of the semiconductor substrate Between the active area 300 and the terminal area 200, in many cases, the transition area 250 can also be considered to function as a terminal structure. In order to distinguish, in all of the active trenches 103, the active trenches 103-1 are defined as the outermost trenches of all of the active trenches 103 arranged side by side, and also closest to the isolation trenches 102. A portion parallel to the active trench 103, the region between the outermost active trench 103-1 and the isolation trench 102 is defined as a transition region 250. As can be seen from Figures 1 and 2C, on the inside of the isolation trench 102, in addition to the active region 300, there is a transition region 250.
第2A~2C圖僅僅是示範性的給出了製備相應溝槽內的填充材料或控制閘極、屏蔽閘極的方法，但實際上要製備第2C圖的結構，方法並不唯一，還有很多實施方式可以實現，考慮這些步驟並非是本發明最重 要的內容，所以只是很粗略的介紹。 2A~2C are only exemplarily given to the method of preparing the filling material in the corresponding trench or controlling the gate and shielding gate, but in fact, the structure of the 2C figure is prepared, and the method is not unique, and Many implementations can be implemented, and considering these steps is not the heaviest of the present invention. The content is required, so it is only a rough introduction.
隔離溝槽102和鄰近它的有源溝槽103-1限定了它們之間半導體襯底的一個臺面結構(Mesa)250a，而任意相鄰的有源溝槽103則限定了相鄰兩個有源溝槽103之間半導體襯底的一個臺面結構300a。 The isolation trench 102 and the active trench 103-1 adjacent thereto define a mesa structure (Mesa) 250a between the semiconductor substrates, and any adjacent active trenches 103 define adjacent two A mesa structure 300a of the semiconductor substrate between the source trenches 103.
在第2D圖中，製備了本體層120和頂部摻雜層130，其中頂部摻雜層130在有源區300體現為或形成電晶體單元的源極區。例如，以全面植入的方式(blanket implant)，利用P型的摻雜離子植入到整個外延層110的頂部，製備一個位於外延層110頂部的P-型本體層120，圍繞在這些溝槽較上部的側壁周圍。其後，然後再利用N+型的摻雜離子植入到有源區300的本體層120的頂部，在有源區300的本體層120的頂部製備一個N+型的頂部摻雜層130，圍繞在有源溝槽103較上部的側壁周圍，在圖示的實施例中，僅在臺面結構300a內植入有摻雜層130，而未在有源溝槽103-1外側的臺面結構250a內植入摻雜層130。注意本體層120的植入深度，要確保其與外延層110在有源溝槽103附近的交界面略高於控制閘極103e的底面位置，以便在本體層120中能沿著有源溝槽103的側壁形成垂直的反轉層(inversion layer)來建立溝道。雖然沒有特別的解釋，但應瞭解到離子注入還往往伴隨著退火擴散的步驟。雖然在第2D圖的實施例中，僅僅在有源區300的本體層120中形成了頂部摻雜層130，沒有在過渡區250和終端區200的本體層120頂部形成摻雜層130，但在其他的一些可選實施例中，還可以整體性的全面注入方式，同時在過渡區250和終端區200的本體層120頂部一並形成頂部摻雜層130，此時無需在離子注入的步驟中採用額外的遮罩。 In FIG. 2D, a body layer 120 and a top doped layer 130 are prepared, wherein the top doped layer 130 is embodied or formed in the active region 300 as a source region of the transistor unit. For example, in a blanket implant, a P-type dopant ion is implanted on top of the entire epitaxial layer 110 to prepare a P-type body layer 120 on top of the epitaxial layer 110, surrounding the trenches. Around the upper side wall. Thereafter, an N+ type dopant ion is then implanted onto the top of the body layer 120 of the active region 300, and an N+ type top doped layer 130 is prepared on top of the body layer 120 of the active region 300, surrounding Around the upper sidewall of the active trench 103, in the illustrated embodiment, the doped layer 130 is implanted only within the mesa structure 300a, but not within the mesa structure 250a outside the active trench 103-1. The doped layer 130 is implanted. Note that the implantation depth of the body layer 120 is to ensure that its interface with the epitaxial layer 110 near the active trench 103 is slightly higher than the bottom surface of the control gate 103e so as to be along the active trench in the body layer 120. The sidewalls of 103 form a vertical inversion layer to establish the channel. Although not specifically explained, it should be understood that ion implantation is also often accompanied by a step of annealing diffusion. Although in the embodiment of FIG. 2D, only the top doped layer 130 is formed in the body layer 120 of the active region 300, the doped layer 130 is not formed on the top of the bulk region 120 of the transition region 250 and the termination region 200, but In some other optional embodiments, the top doping layer 130 may be formed together at the top of the body layer 120 of the transition region 250 and the termination region 200 in a holistic manner. In this case, no ion implantation step is required. An extra mask is used in the middle.
在第2E圖中，在半導體襯底上方沉積一個絕緣鈍化層140， 覆蓋住外延層110的上表面，同時還覆蓋在端接溝槽101、隔離溝槽102和各有源溝槽103之上。製備絕緣鈍化層140典型的例如沉積低溫氧化物(LTO)和/或含有硼酸的矽玻璃(BPSG)。在第2F圖中，以遮罩400覆蓋在絕緣鈍化層140上，如塗覆光致抗蝕劑層或光阻，經過已知光刻技術的曝光顯影之後，在遮罩400中製備多個開口(400a~400e)。在這些開口中，開口400a對準終端區200的端接溝槽101外側的局部本體層120，開口400b對準端接溝槽101內填充的導電材料101a，而開口400c對準隔離溝槽102內填充的導電材料102a，開口400d對準臺面結構250a，開口400e對準臺面結構300a。此外，遮罩400中一些其他功能的開口並未示意出，例如用於對準閘極拾取溝槽(gate pickup)內填充的閘極材料的開口未示意出。 In FIG. 2E, an insulating passivation layer 140 is deposited over the semiconductor substrate, The upper surface of the epitaxial layer 110 is covered while also overlying the termination trenches 101, the isolation trenches 102, and the active trenches 103. The insulating passivation layer 140 is typically prepared, for example, by depositing a low temperature oxide (LTO) and/or a boronic acid containing barium glass (BPSG). In FIG. 2F, a plurality of masks 400 are overlaid on the insulating passivation layer 140, such as a photoresist layer or photoresist, and after exposure and development by known photolithography techniques, a plurality of layers are prepared in the mask 400. Openings (400a~400e). In these openings, the opening 400a is aligned with the partial body layer 120 outside the termination trench 101 of the termination region 200, the opening 400b is aligned with the conductive material 101a filled in the termination trench 101, and the opening 400c is aligned with the isolation trench 102. The inner conductive material 102a is filled, the opening 400d is aligned with the mesa structure 250a, and the opening 400e is aligned with the mesa structure 300a. Moreover, openings for some other functions in the mask 400 are not shown, such as openings for aligning the gate material filled in the gate pickup.
本發明一個方面就在於，使開口400e的尺寸比開口400d的尺寸更大一些，為了方便區分，有時候可以稱開口400e為第一開口，開口400d稱為第二開口。 One aspect of the present invention resides in that the size of the opening 400e is made larger than the size of the opening 400d. For convenience of distinction, the opening 400e may sometimes be referred to as a first opening and the opening 400d as a second opening.
在第2G圖中，以遮罩400作為蝕刻遮罩，以異向性乾式蝕刻法來製備接觸孔，依次向下蝕刻絕緣鈍化層140、半導體襯底，蝕刻終止在本體層120內。利用開口400d，蝕刻形成了對準過渡區的臺面結構250a的接觸孔504，利用開口400e，蝕刻形成了對準有源區臺面結構300a的接觸孔505。為了區分的方便，可以稱作或定義接觸孔505為第一接觸孔，定義接觸孔504為第二接觸孔，定義接觸孔501為第三接觸孔。 In FIG. 2G, a contact hole is prepared by anisotropic dry etching using the mask 400 as an etch mask, and the insulating passivation layer 140 and the semiconductor substrate are sequentially etched downward, and etching is terminated in the body layer 120. With the opening 400d, the contact hole 504 forming the mesa structure 250a of the alignment region is etched, and the contact hole 505 of the active region mesa structure 300a is etched by the opening 400e. For convenience of distinction, the contact hole 505 may be referred to as a first contact hole, the contact hole 504 is defined as a second contact hole, and the contact hole 501 is defined as a third contact hole.
製備的接觸孔504貫穿絕緣鈍化層140和延伸至臺面結構250a內，並終止在過渡區臺面結構250a的本體層120內。製備的接觸孔505貫穿絕緣鈍化層140和延伸至臺面結構300a內，並貫穿有源區的頂部摻雜層 130和終止在有源區臺面結構300a的本體層120內。由於開口400e比開口400d的開口尺寸要大的緣故，導致開口400e下方暴露出的材質的蝕刻速率，比開口400d下方材質的蝕刻速率要快很多，而且更快的蝕刻速率可以進一步形成更深的接觸孔。所以在接觸孔的蝕刻步驟中，產生了兩方面的影響，其一是有源區接觸孔505的深度值比過渡區接觸孔504的深度值要大，其二是接觸孔505的寬度值或橫向截面尺寸比接觸孔504的寬度值或橫向截面尺寸要大。從第2G圖中可以得知，接觸孔505延伸到半導體襯底內的部分505a比接觸孔504延伸到半導體襯底內的部分504a要深得多。 The prepared contact hole 504 extends through the insulating passivation layer 140 and into the mesa structure 250a and terminates within the body layer 120 of the transition region mesa structure 250a. The prepared contact hole 505 penetrates through the insulating passivation layer 140 and extends into the mesa structure 300a and penetrates the top doped layer of the active region 130 and terminate within the body layer 120 of the active area mesa structure 300a. Since the opening 400e is larger than the opening size of the opening 400d, the etching rate of the material exposed under the opening 400e is much faster than the etching rate of the material under the opening 400d, and the faster etching rate can further form deeper contact. hole. Therefore, in the etching step of the contact hole, two effects are generated, one of which is that the depth value of the active region contact hole 505 is larger than the depth value of the transition region contact hole 504, and the second is the width value of the contact hole 505 or The transverse cross-sectional dimension is larger than the width value or lateral cross-sectional dimension of the contact hole 504. As can be seen from the 2G diagram, the portion 505a of the contact hole 505 extending into the semiconductor substrate is much deeper than the portion 504a of the contact hole 504 extending into the semiconductor substrate.
在第2G圖中的蝕刻步驟中，還同步蝕刻形成了接觸孔501、502、503等。其中利用開口400a蝕刻形成接觸孔501，利用開口400b蝕刻形成接觸孔502和利用開口400c蝕刻形成接觸孔503。由於開口400a位於端接溝槽101外側局部本體層120上方，形成的接觸孔501貫穿絕緣鈍化層140，並延伸進終端區200中位於端接溝槽101外側的本體層120內，如果端接溝槽101外側的本體層120頂部還植入了頂部摻雜層130，則接觸孔501還貫穿該處的頂部摻雜層130。此外，接觸孔502貫穿絕緣鈍化層140並暴露出端接溝槽101內填充的導電材料101a，接觸孔503貫穿絕緣鈍化層140並暴露出隔離溝槽102內填充的導電材料102a。 In the etching step in the FIG. 2G, the contact holes 501, 502, 503 and the like are also formed by synchronous etching. The contact hole 501 is formed by etching using the opening 400a, the contact hole 502 is formed by etching using the opening 400b, and the contact hole 503 is formed by etching using the opening 400c. Since the opening 400a is located above the local body layer 120 outside the termination trench 101, the formed contact hole 501 penetrates the insulating passivation layer 140 and extends into the body layer 120 in the termination region 200 outside the termination trench 101, if terminated The top doped layer 130 is also implanted on top of the body layer 120 outside the trench 101, and the contact hole 501 also penetrates the top doped layer 130 there. In addition, the contact hole 502 penetrates the insulating passivation layer 140 and exposes the conductive material 101a filled in the termination trench 101. The contact hole 503 penetrates the insulating passivation layer 140 and exposes the conductive material 102a filled in the isolation trench 102.
在第2H圖中，為了形成有源區和過渡區的接觸孔底部的本體接觸區，執行一個離子注入的步驟，此步驟中離子注入或P型摻雜物以自對準的方式實現。植入的離子與本體層120的導電類型相同，但比本體層120的摻雜濃度要大，為P+型。通過接觸孔504，植入在過渡區250的本體層120中的離子，形成了臺面結構250a中的本體接觸區601，其位於接觸孔504底 部周圍。通過接觸孔505，植入在有源區300的本體層120中的離子，形成了臺面結構300a中位於接觸孔505底部周圍的本體接觸區602。離子注入還往往伴隨著退火擴散的步驟。由於接觸孔505的寬度尺寸比接觸孔504的寬度尺寸大，所以從接觸孔505注入的離子總量也比從接觸孔504注入的離子總量要多很多，由此則造成本體接觸區602的擴散範圍比本體接觸區601的擴散範圍要大，換言之，最終，本體接觸區602的體積比本體接觸區601體積大。另外，由於接觸孔504延伸到襯底內的部分本身就比較淺，顯然，接觸孔504底部的本體接觸區601自然也就比接觸孔505底部的本體接觸區602在半導體襯底中的深度要淺得多。 In Figure 2H, in order to form the body contact regions of the contact holes at the bottom of the active and transition regions, an ion implantation step is performed in which ion implantation or P-type dopants are implemented in a self-aligned manner. The implanted ions are of the same conductivity type as the body layer 120, but are larger than the doping concentration of the body layer 120, and are of the P+ type. The ions implanted in the body layer 120 of the transition region 250 through the contact holes 504 form a body contact region 601 in the mesa structure 250a, which is located at the bottom of the contact hole 504 Around the ministry. The ions implanted in the body layer 120 of the active region 300 through the contact holes 505 form a body contact region 602 in the mesa structure 300a that is located around the bottom of the contact hole 505. Ion implantation is also often accompanied by a step of annealing diffusion. Since the width dimension of the contact hole 505 is larger than the width dimension of the contact hole 504, the total amount of ions injected from the contact hole 505 is also much larger than the total amount of ions injected from the contact hole 504, thereby causing the body contact region 602. The diffusion range is larger than the diffusion range of the body contact region 601, in other words, finally, the volume of the body contact region 602 is larger than the volume of the body contact region 601. In addition, since the portion of the contact hole 504 extending into the substrate itself is relatively shallow, it is apparent that the body contact region 601 at the bottom of the contact hole 504 is naturally deeper than the body contact region 602 at the bottom of the contact hole 505 in the semiconductor substrate. It is much shallower.
在第2I圖中，在一些實施例中，往往先在各個接觸孔501~505的底部及側壁和在絕緣鈍化層140的上表面上沉積勢壘金屬層，然後再沉積未示意出的金屬材料(如鎢)覆蓋在勢壘金屬層上，金屬材料的一部分還同步填充在各個接觸孔501至505內，之後回蝕金屬材料將絕緣鈍化層140上方的部分金屬材料移除，但保留各個接觸孔501至505內的勢壘金屬層和填充的金屬材料，便可以形成金屬栓塞555或金屬接頭。 In FIG. 2I, in some embodiments, a barrier metal layer is often deposited on the bottom and sidewalls of each of the contact holes 501-505 and on the upper surface of the insulating passivation layer 140, and then a metal material not shown is deposited. (such as tungsten) is overlaid on the barrier metal layer, and a part of the metal material is also simultaneously filled in the respective contact holes 501 to 505, after which the etched metal material removes part of the metal material above the insulating passivation layer 140, but retains each contact The barrier metal layer and the filled metal material in the holes 501 to 505 can form a metal plug 555 or a metal joint.
在第2J圖中，製備一個圖中未示意出的金屬層，沉積在整個絕緣鈍化層140的上方，如果絕緣鈍化層140上表面預先沉積有勢壘金屬層，則金屬層實質是覆蓋在勢壘金屬層之上。之後對它們實施圖案化，分割該金屬層和其下方的勢壘金屬層，形成金屬場板611和頂部金屬電極612，它們之間是斷開和電性隔離的。此外，還在底部襯底100的底面上額外覆蓋有另一個金屬層作為底部金屬電極613，它與重摻雜的底部襯底100之間形成歐姆接觸。絕緣鈍化層140之上的場板611被設置在終端區200，至 少要交疊在端接溝槽101和交疊在接觸孔501上方，以便同時與接觸孔501內的金屬栓塞555和與接觸孔502內的金屬栓塞555電性接觸，使得終端區200中位於端接溝槽101外側的本體層120與端接溝槽101內填充的導電材料101a電性連接，處於相同的電位。如果端接溝槽101外側的本體層120的頂部被植入有頂部摻雜層130，該處的頂部摻雜層130也與接觸孔501內的金屬栓塞555形成短路，從而與端接溝槽101內的導電材料101a等位。端接溝槽101作為通道截止(channel stop)結構。 In FIG. 2J, a metal layer not shown in the figure is prepared and deposited over the entire insulating passivation layer 140. If a barrier metal layer is previously deposited on the upper surface of the insulating passivation layer 140, the metal layer is substantially covered by the potential. Above the metal layer. They are then patterned to divide the metal layer and the barrier metal layer beneath it to form a metal field plate 611 and a top metal electrode 612 that are disconnected and electrically isolated. Further, another metal layer is additionally covered on the bottom surface of the underlying substrate 100 as the bottom metal electrode 613, which forms an ohmic contact with the heavily doped underlying substrate 100. A field plate 611 over the insulating passivation layer 140 is disposed in the termination region 200, to It is less likely to overlap the termination trench 101 and overlap the contact hole 501 so as to be in electrical contact with the metal plug 555 in the contact hole 501 and the metal plug 555 in the contact hole 502, so that the terminal region 200 is located. The body layer 120 outside the termination trench 101 is electrically connected to the conductive material 101a filled in the termination trench 101 at the same potential. If the top of the body layer 120 outside the termination trench 101 is implanted with the top doped layer 130, the top doped layer 130 there is also shorted to the metal plug 555 in the contact hole 501, thereby terminating the trench The conductive material 101a in 101 is in place. The termination trench 101 serves as a channel stop structure.
此外，絕緣鈍化層140之上的頂部金屬電極612則至少被設置在過渡區250和有源區300，並至少交疊在隔離溝槽102和交疊在臺面結構250a、300a之上。在這種情況下，接觸孔503內的金屬栓塞555將隔離溝槽102內填充的導電材料102a電性連接到頂部金屬電極612上，接觸孔504內的金屬栓塞555將過渡區250的本體層120電性連接到頂部金屬電極602上。而接觸孔505內的金屬栓塞555則將有源區300中作為源極區的頂部摻雜層130和本體層120短路，還進一步將源極區和本體層120電性連接到頂部金屬電極612上。值得注意的是，在可選非必須的實施例中，在未示意出的維度上，條狀的有源溝槽103可以與隔離溝槽102的垂直於有源溝槽103的一部分連通，以便每個有源溝槽103內下部的屏蔽閘極103a都與隔離溝槽102內填充的導電材料102a互連，所以同樣也會電性連接到頂部金屬電極612。但控制閘極103e與隔離溝槽102內填充的導電材料102a相互絕緣並不互連。在未示意出的維度上，所有有源溝槽103內上部的控制閘極103e都相互連接，並被連接在閘極拾取溝槽內填充的閘極材料上，並且有一些接觸孔對準閘極拾取溝槽內填充的閘極材料，它們內部可以設置金屬栓塞，將控制閘極103e 導出到絕緣鈍化層140上方的閘極金屬上。 In addition, top metal electrode 612 over insulating passivation layer 140 is disposed at least in transition region 250 and active region 300 and overlaps at least over isolation trench 102 and overlying mesa structures 250a, 300a. In this case, the metal plug 555 in the contact hole 503 electrically connects the conductive material 102a filled in the isolation trench 102 to the top metal electrode 612, and the metal plug 555 in the contact hole 504 connects the body layer of the transition region 250. 120 is electrically connected to the top metal electrode 602. The metal plug 555 in the contact hole 505 shorts the top doping layer 130 and the body layer 120 as the source regions in the active region 300, and further electrically connects the source region and the body layer 120 to the top metal electrode 612. on. It should be noted that in an optional non-essential embodiment, the strip-shaped active trench 103 may be in communication with a portion of the isolation trench 102 perpendicular to the active trench 103 in an unillustrated dimension so that The shield gate 103a in the lower portion of each active trench 103 is interconnected with the conductive material 102a filled in the isolation trench 102, so it is also electrically connected to the top metal electrode 612. However, the control gate 103e is insulated from the conductive material 102a filled in the isolation trench 102 and is not interconnected. In the unillustrated dimension, the upper control gates 103e of all active trenches 103 are connected to each other and connected to the gate material filled in the gate pick-up trenches, and some contact holes are aligned. The pole picks up the gate material filled in the trench, and a metal plug can be disposed inside the gate, and the gate 103e is controlled It is led onto the gate metal above the insulating passivation layer 140.
由於頂部金屬電極612作為MOSFET器件的源極，底部金屬電極613作為MOSFET器件的汲極，所以隔離溝槽102內側的包括了過渡區和有源區的本體層120、有源區300的頂部摻雜層130都與源極等位(如果過渡區250有頂部摻雜層130則其也與源極等位)，屏蔽閘極103a及隔離溝槽102內填充的導電材料102a也與源極等位。 Since the top metal electrode 612 serves as the source of the MOSFET device and the bottom metal electrode 613 serves as the drain of the MOSFET device, the body layer 120 including the transition region and the active region inside the isolation trench 102, and the top portion of the active region 300 are doped. The impurity layer 130 is all equipotential to the source (if the transition region 250 has the top doped layer 130, it is also equiaxed with the source), the shielding gate 103a and the conductive material 102a filled in the isolation trench 102 are also connected to the source, etc. Bit.
在第3A~3B圖的實施例中，用來蝕刻製備接觸孔505的開口400e(第一開口)與用來蝕刻製備接觸孔504的開口400d(第二開口)並非形成在同一個遮罩上。譬如可以在絕緣鈍化層140上塗覆第一遮罩401，先行形成第一遮罩401中的開口400e，並同步還形成了其他開口400a、400b、400c，但並不形成開口400d。先以開口400a、400b、400c、400e依次蝕刻下方的絕緣層101、半導體襯底，分別相對應地形成接觸孔501、502、503、505，然後剝離掉第一遮罩400。其後再在絕緣鈍化層140上塗覆另一個第二遮罩402，並在第二遮罩402中形成開口400d，以開口400d依次蝕刻下方的絕緣層101、半導體襯底，形成接觸孔504。接觸孔501~505的特徵與前述實施例完全相同，僅有的差異只不過是蝕刻製備時機有所改變。 In the embodiment of FIGS. 3A-3B, the opening 400e (first opening) for etching the contact hole 505 and the opening 400d (second opening) for etching the contact hole 504 are not formed on the same mask. . For example, the first mask 401 may be coated on the insulating passivation layer 140, and the opening 400e in the first mask 401 is formed first, and other openings 400a, 400b, 400c are formed in synchronization, but the opening 400d is not formed. First, the insulating layer 101 and the semiconductor substrate are sequentially etched by the openings 400a, 400b, 400c, and 400e, and the contact holes 501, 502, 503, and 505 are respectively formed correspondingly, and then the first mask 400 is peeled off. Thereafter, another second mask 402 is coated on the insulating passivation layer 140, and an opening 400d is formed in the second mask 402, and the underlying insulating layer 101 and the semiconductor substrate are sequentially etched by the opening 400d to form a contact hole 504. The features of the contact holes 501 to 505 are identical to those of the previous embodiment, and the only difference is that the etching preparation timing is changed.
此外，在另一個未示意出的實施例中，可以先在第一遮罩401中形成開口400a、400b、400c、400d，來製備接觸孔501、502、503、504，然後剝離第一遮罩401。其後再在第二遮罩402中形成開口400e，來製備接觸孔505。 In addition, in another embodiment not illustrated, the openings 400a, 400b, 400c, 400d may be formed in the first mask 401 to prepare the contact holes 501, 502, 503, 504, and then the first mask is peeled off. 401. A contact hole 505 is then formed by forming an opening 400e in the second mask 402.
不限於此，還可以選擇不在第一遮罩401中形成開口400a、400b、400c，而在第二遮罩402中形成開口400a、400b、400c。也即先在第 一遮罩401中形成開口400e，製備接觸孔505之後，剝離第一遮罩401。其後再在第二遮罩402中形成開口400a、400b、400c、400d，來製備接觸孔501、502、503、504。或者，先在第一遮罩401中形成開口400d，製備接觸孔504之後，剝離第一遮罩401。其後再在第二遮罩402中形成開口400a、400b、400c、400e，來製備接觸孔501、502、503、505。 Without being limited thereto, it is also possible to select not to form the openings 400a, 400b, 400c in the first mask 401, but to form the openings 400a, 400b, 400c in the second mask 402. First in the first An opening 400e is formed in a mask 401, and after the contact hole 505 is prepared, the first mask 401 is peeled off. Contact openings 501, 502, 503, 504 are then formed by forming openings 400a, 400b, 400c, 400d in second mask 402. Alternatively, the opening 400d is first formed in the first mask 401, and after the contact hole 504 is prepared, the first mask 401 is peeled off. Contact openings 501, 502, 503, 505 are then formed by forming openings 400a, 400b, 400c, 400e in second mask 402.
總之，只要確保開口400e比開口400d具有更大的開口尺寸，藉此製備比接觸孔504更深和更寬的接觸孔505，任何方式都適用於本發明。 In summary, any manner is suitable for the present invention as long as it is ensured that the opening 400e has a larger opening size than the opening 400d, thereby making the contact hole 505 deeper and wider than the contact hole 504.
在第4A圖中，依現有技術，假定延伸至臺面結構250a內的接觸孔504'在半導體襯底中的部分具有深度D'1，並假定延伸至臺面結構300a內的接觸孔505在半導體襯底中的部分具有深度D2，D'1=D2。在器件的UIS負載應用中，底部金屬電極613的電位比頂部金屬電極612高得多，尤其是器件處於非箝制電感性切換(Unclamped Inductive Switching；UIS)之切換事件期間。為了詳細地瞭解器件內的電場分佈，隔離溝槽102和有源溝槽103底部拐角處的等電場強度的大體示意圖被描繪在第4A圖中，不僅隔離溝槽102底部拐角處的電場強度遠遠比有源區300的本體層120與外延層110之間的PN結處的場強大得多，而且隔離溝槽102底部拐角處的電場強度比有源溝槽103底部拐角處的電場強度也要大，使得隔離溝槽102的底部拐角處將是一個主要的突崩擊穿弱點，這是一個不好的現象。過渡區250的崩潰電壓低於有源區300的崩潰電壓，高壓突崩擊穿將會發生在第4A圖的隔離溝槽102底部拐角處的高電場強度位置，崩潰電流將湧入過渡區250，如第4B圖所示的在隔離溝槽102底部拐角處附近誘發的崩潰電流700的流向，從而削弱器件的崩潰耐量性能。在UIS事件中，過渡區250有限的面積很難處理功 率損耗，這嚴重的影響了器件的安全工作區域SOA。 In FIG. 4A, according to the prior art, it is assumed that the portion of the contact hole 504' extending into the mesa structure 250a has a depth D'1 in the semiconductor substrate, and it is assumed that the contact hole 505 extending into the mesa structure 300a is in the semiconductor lining. The portion in the bottom has a depth D2, D'1 = D2. In the UIS load application of the device, the potential of the bottom metal electrode 613 is much higher than the top metal electrode 612, especially during switching events of the device under Unclamped Inductive Switching (UIS). For a detailed understanding of the electric field distribution within the device, a general schematic of the isoelectric field strength at the bottom corners of the isolation trench 102 and the active trench 103 is depicted in FIG. 4A, not only the electric field strength at the bottom corner of the isolation trench 102 is far Far more powerful than the field at the PN junction between the body layer 120 of the active region 300 and the epitaxial layer 110, and the electric field strength at the bottom corner of the isolation trench 102 is also greater than the electric field strength at the bottom corner of the active trench 103. To be large, the bottom corner of the isolation trench 102 will be a major break-through breakdown, which is a bad phenomenon. The breakdown voltage of the transition region 250 is lower than the breakdown voltage of the active region 300, and the high voltage collapse breakdown will occur at the high electric field strength position at the bottom corner of the isolation trench 102 of FIG. 4A, and the breakdown current will flow into the transition region 250. The flow of the collapse current 700 induced near the corner of the bottom of the isolation trench 102 as shown in FIG. 4B, thereby impairing the breakdown resistance performance of the device. In the UIS event, the limited area of the transition zone 250 is difficult to handle. Rate loss, which seriously affects the safe working area of the device SOA.
在第5A圖中，依照本發明，延伸至臺面結構250a內的接觸孔504在半導體襯底中的部分504a具有深度D1，延伸至臺面結構300a內的接觸孔505在半導體襯底中的部分具有深度D2，此時D1<D2。在器件的UIS負載應用中，隔離溝槽102和有源溝槽103各自底部拐角處的等電場強度和有源區300的本體層120與外延層110間的PN結處的場強，大體被描繪在第5A圖中。在本體層120中，接觸孔504底部周圍的本體接觸區601相對接觸孔505底部周圍的本體接觸區602而顯得體積較小、深度較淺。第5A圖相對第4A圖的情形而言，隔離溝槽102和有源溝槽103各自底部拐角處的電場強度，以及有源區300中本體層120與外延層110之間的PN結處的場強發生改變。體現在，隔離溝槽102、有源溝槽103底部拐角處的被弱化的電場強度誘發突崩的機率幾乎可以完全忽略，取而代之的是，有源區300中本體層120與外延層110介面處的PN結在臺面結構300a的中心位置產生最高的垂直電場，這個中心位置大體上也是相鄰兩個有源溝槽103之間的中心位置，而該處的電場強度比隔離溝槽102、有源溝槽103底部拐角處的電場強度要大得多。所以在第5A圖中，器件處於UIS之切換事件期間，有源區的本體層120與外延層110之間的介面(PN結)位於相鄰有源溝槽103之間的中心位置處變成了主要的崩潰弱點，隔離溝槽102的底部拐角處將不再是突崩擊穿弱點，從而致使有源區300中本體-外延層PN結先行觸發突崩擊穿，所以第5B圖與第4A圖相反的是，高壓突崩擊穿不再是發生在隔離溝槽102底部拐角處。第5B圖展示了高壓突崩擊穿後，在有源區本體-外延層間PN結處誘發的崩潰電流700'的流向趨勢。可以獲悉，原本在面積有限的過渡區250的崩潰 電流都被轉移到面積較大的有源區300。這避免了從崩潰區域產生的熱載流子被絕緣層102b捕獲，防止對隔離溝槽102底部的絕緣層102b產生損傷，更重要的是，由於崩潰電流的轉移，提高了溝槽式MOSFET器件的堅固性。 因此，十分有必要設計適宜的過渡區和有源區的接觸孔深度，及改變本體接觸區的深度位置，適當的改變電場分佈，使功率MOSFET的崩潰電壓達到最大，來改善溝槽MOSFET的UIS性能，本發明的發明精神恰好能滿足這些要求。 In FIG. 5A, in accordance with the present invention, the portion 504a of the contact hole 504 extending into the mesa structure 250a has a depth D1 in the semiconductor substrate, and the portion of the contact hole 505 extending into the mesa structure 300a has a portion in the semiconductor substrate. Depth D2, at this time D1 < D2. In the UIS load application of the device, the equal electric field strength at the bottom corner of each of the isolation trench 102 and the active trench 103 and the field strength at the PN junction between the bulk layer 120 of the active region 300 and the epitaxial layer 110 are generally Depicted in Figure 5A. In the body layer 120, the body contact region 601 around the bottom of the contact hole 504 appears to be smaller in volume and shallower in depth than the body contact region 602 around the bottom of the hole 505. 5A shows the electric field strength at the bottom corner of each of the isolation trench 102 and the active trench 103, and the PN junction between the bulk layer 120 and the epitaxial layer 110 in the active region 300, as compared with the case of FIG. 4A. The field strength has changed. It is embodied that the probability of the weakened electric field intensity induced collapse of the isolation trench 102 and the bottom corner of the active trench 103 can be almost completely ignored. Instead, the interface between the body layer 120 and the epitaxial layer 110 in the active region 300 is The PN junction produces the highest vertical electric field at the center of the mesa structure 300a. This central position is also substantially the center position between the adjacent two active trenches 103, and the electric field strength there is greater than the isolation trench 102. The electric field strength at the bottom corner of the source trench 103 is much greater. Therefore, in FIG. 5A, during the switching event of the UIS, the interface between the body layer 120 of the active region and the epitaxial layer 110 (PN junction) is located at the center between the adjacent active trenches 103. The main crash weakness, the bottom corner of the isolation trench 102 will no longer be a breakdown breakdown, causing the bulk-epitaxial PN junction in the active region 300 to trigger a breakdown first, so Figure 5B and 4A In contrast, the high voltage sag breakdown is no longer occurring at the bottom corner of the isolation trench 102. Figure 5B shows the flow tendency of the collapse current 700' induced at the PN junction between the body-epitaxial layer of the active region after high voltage abrupt breakdown. Can be informed that the original 250 in the transition zone with a limited area The current is transferred to the active area 300 having a larger area. This prevents hot carriers generated from the collapsed region from being trapped by the insulating layer 102b, preventing damage to the insulating layer 102b at the bottom of the isolation trench 102, and more importantly, improving the trench MOSFET device due to the transfer of the breakdown current. Rugged. Therefore, it is very necessary to design the contact hole depth of the appropriate transition region and active region, and change the depth position of the body contact region, appropriately change the electric field distribution, and maximize the breakdown voltage of the power MOSFET to improve the UIS of the trench MOSFET. Performance, the inventive spirit of the present invention just meets these requirements.
在第5A~5B圖的實施例中，可以獲悉，過渡區(具有接觸孔504)的本體層120與外延層110之間的交界面依然是水平的，然而有源區(具有接觸孔505)的本體層120與外延層110之間的交界面卻略向下凹陷，這很大程度上是歸結於本體接觸區602的P型摻雜物擴散誘使本體層120向下凸起的緣故，相鄰兩個有源溝槽103之間的中心位置處P型摻雜物擴散得最深，也即在這個中心處本體層120向下延伸凸出得最深。換言之，雖然過渡區本體-外延層PN結依然是平行平面結，但有源區本體-外延層PN結卻不再是理想的平行平面結，取而代之的是，其輪廓實質是曲面的彎曲結，電場更容易在該處積聚，擊穿或崩潰更容易發生。 In the embodiment of FIGS. 5A-5B, it can be learned that the interface between the body layer 120 having the transition region (having the contact hole 504) and the epitaxial layer 110 is still horizontal, whereas the active region (having the contact hole 505) The interface between the body layer 120 and the epitaxial layer 110 is slightly recessed downward, which is largely due to the P-type dopant diffusion of the body contact region 602 causing the body layer 120 to bulge downward. The P-type dopant diffuses the deepest at the center position between the adjacent two active trenches 103, that is, at this center, the body layer 120 extends downward to protrude the deepest. In other words, although the transition region body-epitaxial layer PN junction is still a parallel plane junction, the active region body-epitaxial layer PN junction is no longer an ideal parallel plane junction. Instead, the contour is essentially a curved curved junction. The electric field is more likely to accumulate there, and breakdown or collapse is more likely to occur.
以上，通過說明和附圖，給出了具體實施方式的特定結構的典型實施例，上述發明提出了現有的較佳實施例，但這些內容並不作為局限。對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。 The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.
100‧‧‧底部襯底 100‧‧‧Bottom substrate
110‧‧‧外延層 110‧‧‧ Epilayer
140‧‧‧絕緣鈍化層 140‧‧‧Insulation passivation layer
200‧‧‧終端區 200‧‧‧ terminal area
300‧‧‧有源區 300‧‧‧Active area
601‧‧‧本體接觸區 601‧‧‧ Body contact area
602‧‧‧本體接觸區 602‧‧‧ Body contact area
611‧‧‧金屬場板 611‧‧‧Metal field plate
612‧‧‧頂部金屬電極 612‧‧‧Top metal electrode
613‧‧‧底部金屬電極 613‧‧‧Bottom metal electrode
Claims (20)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103130224A TWI571959B (en) | 2014-09-02 | 2014-09-02 | Power trench mosfet with mproved uis performance and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103130224A TWI571959B (en) | 2014-09-02 | 2014-09-02 | Power trench mosfet with mproved uis performance and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201611183A TW201611183A (en) | 2016-03-16 |
| TWI571959B true TWI571959B (en) | 2017-02-21 |
Family
ID=56085252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103130224A TWI571959B (en) | 2014-09-02 | 2014-09-02 | Power trench mosfet with mproved uis performance and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI571959B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI601295B (en) * | 2016-08-25 | 2017-10-01 | 綠星電子股份有限公司 | Split-gate mosfet |
| TWI737889B (en) * | 2018-02-05 | 2021-09-01 | 力智電子股份有限公司 | Power semiconductor device |
| TWI739252B (en) | 2019-12-25 | 2021-09-11 | 杰力科技股份有限公司 | Trench mosfet and manufacturing method of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201011835A (en) * | 2008-09-04 | 2010-03-16 | Anpec Electronics Corp | Method of forming power device |
| TW201310652A (en) * | 2011-08-18 | 2013-03-01 | Alpha & Omega Semiconductor | Shielded gate trench MOSFET package |
-
2014
- 2014-09-02 TW TW103130224A patent/TWI571959B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201011835A (en) * | 2008-09-04 | 2010-03-16 | Anpec Electronics Corp | Method of forming power device |
| TW201310652A (en) * | 2011-08-18 | 2013-03-01 | Alpha & Omega Semiconductor | Shielded gate trench MOSFET package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201611183A (en) | 2016-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9997593B2 (en) | Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof | |
| US9953969B2 (en) | Semiconductor power device having shielded gate structure and ESD clamp diode manufactured with less mask process | |
| US8709895B2 (en) | Manufacturing method power semiconductor device | |
| CN105448732B (en) | Improve groove power semiconductor device of UIS performances and preparation method thereof | |
| US7494876B1 (en) | Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same | |
| US9401409B2 (en) | High density MOSFET array with self-aligned contacts enhancement plug and method | |
| TWI689977B (en) | Ditch-type power transistor and manufacturing method thereof | |
| US9780196B2 (en) | Method of forming a semiconductor device including forming a shield conductor overlying a gate conductor | |
| CN105489649B (en) | Improve the method for termination environment low breakdown voltage in groove-type power device | |
| TWI571959B (en) | Power trench mosfet with mproved uis performance and preparation method thereof | |
| US20130164915A1 (en) | Method for fabricating power semiconductor device with super junction structure | |
| EP1162665A2 (en) | Trench gate MIS device and method of fabricating the same | |
| US7994001B1 (en) | Trenched power semiconductor structure with schottky diode and fabrication method thereof | |
| EP3933895A1 (en) | Trench field effect transistor structure, and manufacturing method for same | |
| WO2021232802A1 (en) | Igbt device and preparation method therefor | |
| KR20220054247A (en) | Method of manufacturing semiconductor power device | |
| TWI597766B (en) | Trench power semiconductor device and manufacturing method thereof | |
| CN108511346B (en) | Manufacturing method of LDMOS device | |
| TWI517393B (en) | Semiconductor device and method of fabricating the same | |
| KR20050009797A (en) | Structure of high voltage transistor with shallow trench isolation layer | |
| KR102444384B1 (en) | Trench power MOSFET and manufacturing method thereof | |
| US11257720B2 (en) | Manufacturing method for semiconductor device and integrated semiconductor device | |
| JP4425295B2 (en) | Semiconductor device | |
| CN103000521B (en) | Method for manufacturing trench power metal-oxide semiconductor field-effect transistor | |
| JP4381435B2 (en) | Semiconductor device and manufacturing method of semiconductor device |