TWI570260B - Silicon wafer - Google Patents
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- TWI570260B TWI570260B TW104102915A TW104102915A TWI570260B TW I570260 B TWI570260 B TW I570260B TW 104102915 A TW104102915 A TW 104102915A TW 104102915 A TW104102915 A TW 104102915A TW I570260 B TWI570260 B TW I570260B
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Description
本發明係關於一種矽晶圓，尤其係關於一種適於作為氮化物半導體(例如，氮化鎵系半導體)之磊晶成長用之基板者。 The present invention relates to a germanium wafer, and more particularly to a substrate suitable for epitaxial growth of a nitride semiconductor (e.g., a gallium nitride based semiconductor).
氮化鎵(GaN)系半導體材料具有矽(Si)之約3倍之較大之帶隙、Si之約10倍之較高之絕緣擊穿電場、進而為較大之飽和電子速度等優異之特性，因此作為無線通信領域之高頻、高輸出元件用材料而被積極地推進研究開發，且針對行動電話基地台用元件，已經進入實用化之階段。又最近，因可期待同時實現利用先前之Si功率元件難以實現之高耐壓化與低損耗化即低接通電阻化，故亦正著眼於向電力用功率元件之應用。接通電阻之理論值與絕緣擊穿電場之立方成反比，因此使用GaN之功率元件存在Si之約1/1000之超低接通電阻化之可能性。 The gallium nitride (GaN)-based semiconductor material has a band gap of about three times larger than that of bismuth (Si), a dielectric breakdown electric field of about ten times that of Si, and a large saturation electron velocity. As a result, it is actively promoted research and development as a material for high-frequency and high-output components in the field of wireless communication, and has been put into practical use for components for mobile phone base stations. Recently, it is expected that the high voltage resistance and low loss, which is difficult to achieve with the conventional Si power element, can be realized at the same time, and therefore, attention is being paid to the application to the power element for power. The theoretical value of the on-resistance is inversely proportional to the cube of the dielectric breakdown field, so that the power element using GaN has the possibility of an ultra-low on-resistance of about 1/1000 of Si.
用於LED(Lighting Emitting Diode，發光二極體)等光學元件或電晶體等電子元件之GaN系半導體材料一般係藉由磊晶成長(以下，稱為磊晶成長)而形成於藍寶石或碳化矽(SiC)等異質基板上。然而，近年來，由於基板之大口徑化、基板品質本身之提高、及成本方面之原因，先前廣泛使用之Si正被廣泛用作GaN磊晶成長用基板。 A GaN-based semiconductor material used for an optical element such as an LED (Lighting Emitting Diode) or an electronic component such as a transistor is generally formed in sapphire or tantalum carbide by epitaxial growth (hereinafter referred to as epitaxial growth). On a heterogeneous substrate such as (SiC). However, in recent years, Si, which has been widely used in the past, is widely used as a substrate for GaN epitaxial growth due to the large diameter of the substrate, the improvement of the substrate quality itself, and the cost.
然而，關於Si晶圓(以下，適當稱為晶圓)上之氮化物半導體層之結晶成長，因存在氮化物系半導體相對於Si之結晶結構之不同、晶格失配、熱膨脹係數差，故存在產生裂痕、晶圓翹曲、及位錯之問題。 該等會導致晶圓操作錯誤或接面漏電等製造上之問題。例如，作為磊晶成長之基板而使用之Si之晶格常數為5.43埃，與此相對，作為氮化物半導體之一的GaN之晶格常數為3.189埃。又，Si之熱膨脹係數為3.59×10-6/K，與此相對，GaN之熱膨脹係數為5.59×10-6/K。如上所述，兩者之晶格常數及熱膨脹係數差別較大，因此若使GaN於Si上直接磊晶成長，則會出現產生較大之應變或裂痕等之問題。 However, the crystal growth of the nitride semiconductor layer on the Si wafer (hereinafter referred to as a wafer as appropriate) is different in crystal structure of the nitride-based semiconductor with respect to Si, lattice mismatch, and thermal expansion coefficient. There are problems with cracks, wafer warpage, and dislocations. These can cause manufacturing problems such as wafer operation errors or junction leakage. For example, the lattice constant of Si used as a substrate for epitaxial growth is 5.43 angstroms, whereas the lattice constant of GaN which is one of nitride semiconductors is 3.189 angstroms. Further, the thermal expansion coefficient of Si is 3.59 × 10 -6 /K, whereas the thermal expansion coefficient of GaN is 5.59 × 10 -6 /K. As described above, the difference in lattice constant and thermal expansion coefficient between the two is large. Therefore, if GaN is directly epitaxially grown on Si, problems such as occurrence of large strain or cracks occur.
因此，為解決該問題，例如於下述專利文獻1中揭示有如下之技術：於Si上，使氮化鋁(AlN)及氮化鎵鋁(AlGaN)(參照本文獻之段落0025~0026)磊晶成長之後，進而使GaN層(參照本文獻之段落0021)磊晶成長。其目的在於，使AlN或AlGaN作為緩衝層而發揮作用，藉此各層間之晶格失配率減少，應變逐漸緩和，因此可期待晶圓之翹曲或位錯之減少。 Therefore, in order to solve this problem, for example, Patent Document 1 below discloses a technique of forming aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) on Si (refer to paragraphs 0025 to 0026 of the present document). After the epitaxial growth, the GaN layer (see paragraph 0021 of this document) is epitaxially grown. The purpose is to cause AlN or AlGaN to function as a buffer layer, whereby the lattice mismatch ratio between the layers is reduced and the strain is gradually relaxed, so that warpage of wafers or reduction of dislocations can be expected.
[專利文獻1]日本專利特開2012-79952號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2012-79952
於該專利文獻1之構成中，為形成數μm之厚度之磊晶層，需要長時間(通常為數小時以上)進行1000~1200℃左右之高溫之熱處理，且現狀為即便如本構成般形成有緩衝層，亦依然產生如下問題：產生密度高達109/cm2之滑移(位錯)、或晶圓破裂。推測其原因在於，雖藉由形成緩衝層而可使應變於某種程度上得到緩和，但晶圓端面之斜角會與周圍之治具接觸，而新導入成為滑移或破裂之原因之缺陷，或因熱處理中所負擔之應力，而滑移等自晶圓原本存在之缺陷(研磨時之破碎痕或刮痕等)伸展。 In the configuration of Patent Document 1, in order to form an epitaxial layer having a thickness of several μm, it is necessary to heat-treat at a high temperature of about 1000 to 1200 ° C for a long period of time (usually several hours or more), and the present state is formed even if it is configured as described above. The buffer layer also causes problems in that slips (dislocations) having a density of up to 10 9 /cm 2 or wafer breakage are generated. It is presumed that the reason is that although the strain is somewhat relieved by forming the buffer layer, the oblique angle of the wafer end face will come into contact with the surrounding jig, and the new introduction becomes a defect of slip or crack. Or, due to the stress burdened by the heat treatment, the slip or the like stretches from the defect originally existing in the wafer (breaking marks or scratches during polishing, etc.).
因此，本發明之課題在於：抑制當使氮化物半導體層於矽晶圓 上磊晶成長時，晶圓破裂、或位錯伸展而產生較大之翹曲。 Therefore, the object of the present invention is to suppress the use of a nitride semiconductor layer on a germanium wafer. When the epitaxial growth occurs, the wafer is broken or the dislocations are stretched to cause a large warp.
為解決上述課題，於本發明中，構成一種矽晶圓，其特徵在於：其係用以使氮化物半導體層磊晶成長之(111)面方位之圓板狀之矽晶圓，且具有：正面，其供上述氮化物半導體層形成；背面，其與上述正面平行；端面，其具有與上述正面之面法線垂直之面法線，且構成晶圓外周部；第一傾斜面，其與上述正面及上述端面連續，且與上述正面呈傾斜；及第二傾斜面，其與上述背面及上述端面連續，且與上述背面呈傾斜；當將上述端面與上述第一傾斜面之交點和上述正面與上述第一傾斜面之交點之間的沿上述正面之方向之第一投影長設為a1μm，將上述端面與上述第二傾斜面之交點和上述背面與上述第二傾斜面之交點之間的沿上述背面之方向之第二投影長設為a2μm，將上述第一傾斜面距上述正面之第一傾斜角設為θ1，將上述第二傾斜面距上述背面之第二傾斜角設為θ2，將上述正面與上述背面之面間隔設為Tμm時，於磊晶成長之前後，滿足下式：-0.048T≦a1．tanθ1-a2．tanθ2≦0.048T。 In order to solve the above problems, in the present invention, a germanium wafer is characterized in that it is a disk-shaped germanium wafer having a (111) plane orientation in which a nitride semiconductor layer is epitaxially grown, and has: a front surface for forming the nitride semiconductor layer; a back surface parallel to the front surface; an end surface having a surface normal perpendicular to a normal to the front surface of the front surface, and constituting an outer peripheral portion of the wafer; The front surface and the end surface are continuous and inclined to the front surface; and the second inclined surface is continuous with the back surface and the end surface and inclined with respect to the back surface; and the intersection of the end surface and the first inclined surface a first projection length in a direction along the front surface between an intersection of the front surface and the first inclined surface is set to a1 μm, and an intersection between the end surface and the second inclined surface and an intersection between the back surface and the second inclined surface The second projection length in the direction of the back surface is set to a2 μm, the first inclined angle of the first inclined surface from the front surface is θ1, and the second inclined surface is inclined from the second slope of the back surface Set theta] 2, the surface of the front and the back of the set interval Tμm, prior to the epitaxial growth, satisfy the following formula: -0.048T ≦ a1. Tanθ1-a2. Tan θ2 ≦ 0.048T.
或者，構成一種矽晶圓，其特徵在於：其係用以使氮化物半導體層磊晶成長之(111)面方位之圓板之矽晶圓，且具有：正面，其供上述氮化物半導體層形成；背面，其與上述正面平行；曲端面，其具有相對於正面之面法線而連續地變化之面法線，且構成晶圓外周部；第一傾斜面，其與上述正面及上述曲端面連續，且與上述正面呈傾斜；及第二傾斜面，其與上述背面及上述曲端面連續，且與上述背面呈傾斜；當將上述曲端面之最外端和上述正面與上述第一傾斜面之交點之間的沿上述正面之方向之第一投影長設為a1μm，將上述曲端面之最外端和上述背面與上述第二傾斜面之交點之間的沿上述背面之方向之第二投影長設為a2μm，將上述第一傾斜面距上述正面之第一傾 斜角設為θ1，將上述第二傾斜面距上述背面之第二傾斜角設為θ2，將上述正面與上述背面之面間隔設為Tμm時，於磊晶成長之前後，滿足下式：-0.064T≦a1．tanθ1-a2．tanθ2≦0.064T。 Alternatively, a germanium wafer is formed, which is a germanium wafer for a (111) plane orientation of a nitride semiconductor layer epitaxially grown, and has a front surface for the nitride semiconductor layer Forming; a back surface parallel to the front surface; a curved end surface having a surface normal that continuously changes with respect to a surface normal of the front surface, and constituting an outer peripheral portion of the wafer; a first inclined surface, the front surface and the curved surface The end surface is continuous and inclined to the front surface; and the second inclined surface is continuous with the back surface and the curved end surface and inclined with the back surface; and the outermost end of the curved end surface and the front surface are inclined to the first surface The first projection length in the direction of the front surface between the intersections of the faces is set to a1 μm, and the second outermost end of the curved end face and the intersection of the back face and the second inclined face are along the second direction The projection length is set to a2 μm, and the first inclined surface is inclined from the front side The oblique angle is θ1, the second inclined angle of the second inclined surface is θ2 from the back surface, and when the distance between the front surface and the back surface is Tμm, the following formula is satisfied after the epitaxial growth:- 0.064T≦a1. Tanθ1-a2. Tan θ2 ≦ 0.064T.
藉由將根據晶圓之端面形狀使用上式而算出之值(以下，稱為形狀值)收斂於上式之左邊與右邊之範圍內，而使形成氮化物半導體層之前後之斜角之晶圓厚度方向之縱剖面維持為大致對稱形狀。因此，可儘量防止當為進行磊晶成長而將晶圓載置於磊晶成長裝置之基座，且基座與晶圓之端面抵接時，新導入成為於該端面引起晶圓之破裂等之原因的裂痕等缺陷。 By converge the value calculated by using the above formula according to the shape of the end face of the wafer (hereinafter referred to as a shape value) in the range of the left side and the right side of the above formula, the crystal of the oblique angle before and after the formation of the nitride semiconductor layer is formed. The longitudinal section in the thickness direction of the circle is maintained in a substantially symmetrical shape. Therefore, it is possible to prevent the wafer from being placed on the pedestal of the epitaxial growth apparatus for epitaxial growth, and when the susceptor is in contact with the end surface of the wafer, the new introduction causes the wafer to be broken at the end surface. Defects such as cracks.
於該磊晶成長時，晶圓正面與於磊晶成長裝置內流動之原料氣體自由地接觸，另一方面，晶圓背面因面向基座，故與原料氣體幾乎不接觸。其結果，僅於晶圓正面側，會發生伴隨磊晶成長之形狀變化。因此，亦可考慮磊晶前後之晶圓正面側之形狀變化，而使上式之右邊之數值之絕對值較左邊之數值之絕對值小相當於磊晶厚度之量。 During the epitaxial growth, the front side of the wafer is in free contact with the material gas flowing in the epitaxial growth apparatus. On the other hand, since the back surface of the wafer faces the susceptor, it hardly contacts the material gas. As a result, the shape change accompanying the epitaxial growth occurs only on the front side of the wafer. Therefore, it is also possible to consider the shape change of the front side of the wafer before and after the epitaxy, and the absolute value of the value on the right side of the above formula is smaller than the absolute value of the value on the left side by the amount of the epitaxial thickness.
於上述各構成中，較佳為上述第一投影長及上述第二投影長均為50μm以上1000μm以下，且上述第一投影長與第二投影長之差之絕對值為50μm以下。 In each of the above configurations, preferably, the first projection length and the second projection length are both 50 μm or more and 1000 μm or less, and an absolute value of a difference between the first projection length and the second projection length is 50 μm or less.
其原因在於，若將第一投影長及第二投影長設為50μm以下，則導致斜角出現稜角，易於因與基座等治具之接觸而導入裂痕等缺陷。又，其原因在於，若將第一投影長及第二投影長設為1000μm以上，則導致可用於元件之製造之晶圓之表面積實質上變小，從而由1片晶圓可製造之元件之數量減少，製造良率降低。又，其原因在於，若第一投影長與第二投影長之差之絕對值超過50μm，則斜角之形狀之晶圓正面側與背面側之形狀之非對稱性變得顯著，與上述同樣地，易於因與基座等之接觸而導入裂痕等缺陷。 The reason for this is that when the first projection length and the second projection length are 50 μm or less, the bevel angle is formed, and it is easy to introduce defects such as cracks due to contact with the jig such as the susceptor. Moreover, when the first projection length and the second projection length are set to 1000 μm or more, the surface area of the wafer which can be used for the manufacture of the element is substantially reduced, and the component which can be manufactured by one wafer can be manufactured. The number is reduced and the manufacturing yield is reduced. In addition, when the absolute value of the difference between the first projection length and the second projection length exceeds 50 μm, the asymmetry of the shape of the front side and the back side of the wafer having the shape of the oblique angle becomes remarkable. In the ground, it is easy to introduce defects such as cracks due to contact with the susceptor or the like.
上述第一投影長及上述第二投影長更佳為設為50μm以上250μm 以下之範圍內。其原因在於，若如此，則可進一步抑制斜角中之缺陷之產生，並且進一步提高元件之製造良率。 Preferably, the first projection length and the second projection length are set to be 50 μm or more and 250 μm. Within the scope below. The reason for this is that, if so, the occurrence of defects in the oblique angle can be further suppressed, and the manufacturing yield of the element can be further improved.
又，為解決上述課題，構成一種矽晶圓，其特徵在於：其係用以使氮化物半導體層磊晶成長之(111)面方位之圓板之矽晶圓，且於距基板背面之中心為半徑之30%以內之區域內存在的1μm以上之大小之缺陷之個數為5個以下。 Further, in order to solve the above problems, a germanium wafer is formed which is used for a wafer having a (111) plane orientation of a nitride semiconductor layer epitaxially grown and at a center from the back surface of the substrate. The number of defects having a size of 1 μm or more existing in a region within 30% of the radius is 5 or less.
如上所述，與作為磊晶成長用之晶圓而使用之Si之晶格常數相比，氮化物半導體(例如，GaN)之晶格常數大幅小，因此若使氮化物半導體於Si之正面(上表面)磊晶成長，則該晶圓會呈下凸狀翹曲。此時，根據晶圓面內之應力分佈計算可知，於晶圓之中心附近、尤其是相當於距中心為半徑之30%以內之區域內，會產生特別大之應力(晶圓背面側之拉伸應力)。該拉伸應力會以將裂痕等缺陷擴開之方式發揮作用，故而成為起因於該缺陷之位錯之伸展所導致之翹曲、或誘發晶圓之破裂之原因。因此，藉由將該區域內之缺陷之大小及個數控制為特定值以下，可大幅降低晶圓之翹曲等。 As described above, the lattice constant of the nitride semiconductor (for example, GaN) is significantly smaller than the lattice constant of Si used as the wafer for epitaxial growth, so that the nitride semiconductor is formed on the front side of Si ( The upper surface) epitaxial growth, the wafer will be convexly warped. At this time, according to the calculation of the stress distribution in the plane of the wafer, it is known that a particularly large stress is generated in the vicinity of the center of the wafer, particularly in a region within 30% of the radius from the center (the back side of the wafer is pulled). Extensive stress). This tensile stress acts to spread defects such as cracks, and thus causes warpage due to stretching of dislocations of the defects or causes cracking of the wafer. Therefore, by controlling the size and the number of defects in the region to a specific value or less, warpage of the wafer or the like can be greatly reduced.
缺陷之大小與起因於該缺陷之翹曲等之產生容易度之間存在相關關係，若缺陷之大小小於1μm，則即便於該缺陷負擔有應力之情形時，成為翹曲等之起因之虞亦較低。又，雖發現有缺陷之個數越多則翹曲量越大等傾向，但若該個數為5個以下，則可將該翹曲量等保持為充分低之狀態。對於該缺陷之大小之評價，通常使用如掃描式電子顯微鏡或光學顯微鏡等可精度良好地實測缺陷之大小之裝置。 There is a correlation between the size of the defect and the easiness of warpage due to the defect. If the size of the defect is less than 1 μm, even if the defect burden is stressful, the cause of warpage or the like is also caused. Lower. In addition, the number of the defects is increased, and the amount of warpage tends to increase. However, when the number is 5 or less, the amount of warpage or the like can be kept sufficiently low. For the evaluation of the size of the defect, a device capable of accurately measuring the size of the defect such as a scanning electron microscope or an optical microscope is generally used.
又，藉由將結晶方位上易於產生起因於缺陷之破裂或滑移等問題的定向平面或定向凹口之形成位置處之缺陷之大小及個數控制為特定值以下(例如，將1μm以上之大小之缺陷控制為5個以下)，與上述同樣地，可防止起因於該缺陷之位錯之伸展所導致之翹曲、或晶圓之破裂之誘發。對於該缺陷之大小，亦與上述同樣地，通常使用如掃描 式電子顯微鏡或光學顯微鏡等可精度良好地實測缺陷之大小之裝置。 Further, the size and the number of defects at the formation position of the orientation flat or the orientation notch which are liable to cause problems such as cracking or slippage of the defect in the crystal orientation are controlled to a specific value or less (for example, 1 μm or more) The number of defects is controlled to be five or less. In the same manner as described above, it is possible to prevent warpage caused by the stretching of the dislocations of the defects or the initiation of cracking of the wafer. For the size of the defect, as in the above, it is usually used as a scan. A device that can accurately measure the size of a defect, such as an electron microscope or an optical microscope.
直徑為12英吋之晶圓通常正面及背面均施以鏡面拋光，但直徑較其小(例如6英吋、8英吋)之晶圓大多正面施以鏡面拋光，而背面為蝕刻加工之狀態、或者施以背側損傷(back side damage)。該被施以蝕刻加工或背側損傷之面與被施以鏡面拋光之面相比，於抗裂性等強度方面，易於變得不利。因此，對於該小徑之晶圓、尤其是6英吋、8英吋之晶圓，藉由對正面及背面均施以鏡面拋光，並且應用上述缺陷之大小、個數、及區域之基準，可大幅降低晶圓之翹曲或破裂等。又，藉由對端面施以鏡面拋光，亦與上述同樣地，可大幅降低晶圓之翹曲或破裂等。 Wafers with a diameter of 12 inches are usually mirror-polished on the front and back sides, but wafers with smaller diameters (eg, 6 inches, 8 inches) are mostly mirror-polished on the front side and etched on the back side. Or apply back side damage. The surface to which the etching process or the back side is applied is more likely to be disadvantageous in terms of strength such as crack resistance as compared with the surface to which the mirror polishing is applied. Therefore, for the wafer of the small diameter, especially the 6-inch, 8-inch wafer, the front and back surfaces are mirror-polished, and the size, number, and area of the defects are applied. Can significantly reduce the warpage or cracking of the wafer. Further, by performing mirror polishing on the end surface, warpage, cracking, and the like of the wafer can be greatly reduced as described above.
於本發明中，以如下方式構成矽晶圓：使矽晶圓之斜角中之第一傾斜面之沿正面之第一投影長、第二傾斜面之沿背面之第二投影長、第一傾斜面距上述正面之第一傾斜角、及第二傾斜面距上述背面之第二傾斜角成為特定之關係式之範圍內。藉由使用滿足該關係式之晶圓，可跨及磊晶成長步驟之整體而抑制晶圓之破裂或翹曲、裂痕等缺陷所導致之滑移之產生，從而可確保較高之製造良率。 In the present invention, the germanium wafer is formed in such a manner that the first projection length of the first inclined surface of the tantalum wafer along the front surface is long, and the second projection length of the second inclined surface along the back surface is long, first The first inclined angle of the inclined surface from the front surface and the second inclined angle of the second inclined surface from the back surface are within a specific relationship. By using a wafer that satisfies the relationship, it is possible to suppress the occurrence of slippage caused by defects such as cracking or warping or cracking of the wafer across the entire epitaxial growth step, thereby ensuring high manufacturing yield. .
或者，於本發明中，構成將特定區域(晶圓之中心附近區域)之缺陷之大小及個數控制為特定值以下之晶圓。藉由使用以此方式構成之晶圓，與上述同樣地，可跨及磊晶成長步驟之整體而抑制晶圓之翹曲或破裂、裂痕等缺陷所導致之滑移之產生，從而可確保較高之製造良率。 Alternatively, in the present invention, a wafer having a size and a number of defects in a specific region (a region near the center of the wafer) is controlled to a specific value or less. By using the wafer formed in this manner, as in the above, it is possible to suppress the occurrence of slippage caused by defects such as warpage, cracking, cracks, and the like of the wafer, as a whole, and to prevent the occurrence of slippage caused by defects such as warpage, cracks, and the like of the wafer. High manufacturing yield.
1‧‧‧斜角 1‧‧‧bevel
1a‧‧‧斜角 1a‧‧‧bevel
1b‧‧‧斜角 1b‧‧‧bevel
2‧‧‧氮化物半導體層(磊晶層) 2‧‧‧ nitride semiconductor layer (epi layer)
3‧‧‧正面 3‧‧‧ Positive
4‧‧‧背面 4‧‧‧Back
5‧‧‧端面 5‧‧‧ end face
6‧‧‧第一傾斜面 6‧‧‧First inclined surface
7‧‧‧第二傾斜面 7‧‧‧Second inclined surface
8‧‧‧曲端面 8‧‧‧ curved end face
9‧‧‧缺陷 9‧‧‧ Defects
a1‧‧‧第一投影長 A1‧‧‧first projection length
a2‧‧‧第二投影長 A2‧‧‧second projection length
b‧‧‧滑動方向 b‧‧‧Swing direction
F‧‧‧應力 F‧‧‧stress
n‧‧‧Si晶體之滑動面之方向 n‧‧‧Si direction of the sliding surface of the Si crystal
t‧‧‧磊晶厚度 T‧‧‧ epitaxial thickness
θ‧‧‧角 Θ‧‧‧ corner
θ1‧‧‧第一傾斜角 Θ1‧‧‧first tilt angle
θ2‧‧‧第二傾斜角 Θ2‧‧‧second tilt angle
Φ‧‧‧角 Φ‧‧‧ corner
圖1係表示本發明之晶圓之端部之縱剖視圖，(a)為已施以錐形加工之情形，(b)為已施以圓形加工之情形。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a longitudinal sectional view showing the end portion of a wafer of the present invention, wherein (a) is a case where a tapered process has been applied, and (b) is a case where a circular process has been applied.
圖2係表示於圖1所示之晶圓上形成有氮化鎵半導體層時之斜角 形狀值與破裂率之關係之圖。 2 is a perspective view showing a bevel angle when a gallium nitride semiconductor layer is formed on the wafer shown in FIG. 1. A plot of shape values versus crack rate.
圖3係表示晶圓之背面存在之缺陷之數量與磊晶後之翹曲量之關係之圖。 Figure 3 is a graph showing the relationship between the number of defects present on the back side of the wafer and the amount of warpage after epitaxy.
圖4係表示滑移自缺陷之伸展之剖視圖，(a)為磊晶前，(b)為磊晶成膜中，(c)為磊晶後。 Fig. 4 is a cross-sectional view showing the extension of slip from the defect, (a) before epitaxy, (b) in epitaxial film formation, and (c) after epitaxy.
圖5係表示結晶方位、滑動方向及應力方向之關係之立體圖。 Fig. 5 is a perspective view showing the relationship between the crystal orientation, the sliding direction, and the stress direction.
圖6係表示凹口之形成位置與磊晶後之翹曲量之關係之圖。 Fig. 6 is a view showing the relationship between the position at which the notch is formed and the amount of warpage after epitaxy.
(1)關於斜角形狀之影響 (1) About the influence of the shape of the bevel
使用圖式對變更斜角形狀所得之晶圓之實施形態進行說明。 An embodiment of a wafer obtained by changing a bevel shape will be described using a drawing.
於圖1(a)、(b)中，表示利用丘克拉斯基法(CZ法：Czochralski method)而結晶育成之晶圓之端部(斜角1)之縱剖視圖。圖1(a)之斜角1a係包含連續之複數個平面之錐形形狀者，圖1(b)之斜角1b係於其端部具有曲面之圓形形狀者。 1(a) and 1(b) are longitudinal cross-sectional views showing the end portion (bevel 1) of a wafer which is crystallized by the Czochralski method using the Czochralski method. The oblique angle 1a of Fig. 1(a) is a conical shape including a plurality of continuous planes, and the oblique angle 1b of Fig. 1(b) is a circular shape having a curved surface at its end.
圖1(a)所示之錐形形狀之斜角1a包含：正面3，其供GaN等氮化物半導體層2(以下，適當稱為磊晶層)形成；背面4，其與該正面3平行；端面5，其具有與正面3之面法線垂直之面法線，且構成晶圓外周部；第一傾斜面6，其與正面3及端面5連續，且與正面3呈傾斜；及第二傾斜面7，其與背面4及端面5連續，且與背面4呈傾斜。將端面5與第一傾斜面6之交點和正面3與第一傾斜面6之交點之間的沿正面3之方向之第一投影長設為a1μm，將端面5與第二傾斜面7之交點和背面4與第二傾斜面7之交點之間的沿背面4之方向之第二投影長設為a2μm，將第一傾斜面6距正面3之第一傾斜角設為θ1，將第二傾斜面7距背面4之第二傾斜角設為θ2，將正面3與背面4之面間隔(以下，稱為晶圓厚度)設為Tμm，根據各參數之值，算出由式a1．tanθ1-a2．tanθ2定義之斜角之形狀值。 The oblique angle 1a of the tapered shape shown in Fig. 1(a) includes a front surface 3 formed of a nitride semiconductor layer 2 such as GaN (hereinafter, appropriately referred to as an epitaxial layer), and a back surface 4 which is parallel to the front surface 3. An end surface 5 having a surface normal perpendicular to a surface normal to the front surface 3 and constituting an outer peripheral portion of the wafer; a first inclined surface 6 continuous with the front surface 3 and the end surface 5 and inclined to the front surface 3; The two inclined faces 7 are continuous with the back face 4 and the end face 5 and are inclined with respect to the back face 4. The first projection length in the direction of the front surface 3 between the intersection of the end surface 5 and the first inclined surface 6 and the intersection of the front surface 3 and the first inclined surface 6 is set to a1 μm, and the intersection of the end surface 5 and the second inclined surface 7 The second projection length in the direction of the back surface 4 between the intersection of the back surface 4 and the second inclined surface 7 is set to a2 μm, and the first inclination angle of the first inclined surface 6 from the front surface 3 is set to θ1, and the second inclination is The second inclination angle of the surface 7 from the back surface 4 is θ2, and the surface of the front surface 3 and the back surface 4 (hereinafter referred to as wafer thickness) is set to T μm, and the value of each parameter is calculated from the equation a1. Tanθ1-a2. The shape value of the oblique angle defined by tan θ2.
圖1(b)所示之圓形形狀之斜角1b包含：正面3，其供GaN等氮化物半導體層2形成；背面4，其與該正面3平行；曲端面8，其具有相對於正面3之面法線而連續地變化之面法線，且構成晶圓外周部；第一傾斜面6，其與正面3及曲端面8連續，且與正面3呈傾斜；及第二傾斜面7，其與背面4及曲端面8連續，且與背面4呈傾斜。將曲端面8之最外端和正面3與第一傾斜面6之交點之間的沿正面3之方向之第一投影長設為a1μm，將曲端面8之最外端和背面4與第二傾斜面7之交點之間的沿背面4之方向之第二投影長設為a2μm，將第一傾斜面6距正面之第一傾斜角設為θ1，將第二傾斜面7距背面4之第二傾斜角設為θ2，將晶圓厚度設為Tμm，根據各參數之值，算出由式a1．tanθ1-a2．tanθ2定義之斜角之形狀值。 The oblique shape 1b of the circular shape shown in Fig. 1(b) includes a front surface 3 formed of a nitride semiconductor layer 2 such as GaN, a back surface 4 which is parallel to the front surface 3, and a curved end surface 8 which has a front surface opposite to the front surface The surface normal of the surface of the 3 is continuously changed, and constitutes the outer peripheral portion of the wafer; the first inclined surface 6 is continuous with the front surface 3 and the curved end surface 8 and inclined with the front surface 3; and the second inclined surface 7 It is continuous with the back surface 4 and the curved end surface 8, and is inclined to the back surface 4. The first projection length in the direction of the front surface 3 between the outermost end of the curved end face 8 and the intersection of the front face 3 and the first inclined face 6 is set to a1 μm, and the outermost end and the back face 4 of the curved end face 8 are second and second. The second projection length in the direction of the back surface 4 between the intersections of the inclined faces 7 is set to a2 μm, the first inclined angle of the first inclined surface 6 from the front surface is set to θ1, and the second inclined surface 7 is set to the front surface 4 The two tilt angles are set to θ2, and the wafer thickness is set to Tμm, and the equation a1 is calculated according to the values of the respective parameters. Tanθ1-a2. The shape value of the oblique angle defined by tan θ2.
此處算出之形狀值成為斜角1(1a、1b)之縱剖面之對稱性之指標。即，於斜角1(1a、1b)之縱剖面，若正面3與背面4側之形狀完全對稱，則形狀值為0，正面3與背面4側之形狀之非對稱性越大則形狀值之絕對值越大。 The shape value calculated here is an index of the symmetry of the longitudinal section of the oblique angle 1 (1a, 1b). That is, in the longitudinal section of the oblique angle 1 (1a, 1b), if the shape of the front surface 3 and the back surface 4 side are completely symmetrical, the shape value is 0, and the shape of the front surface 3 and the back surface 4 side is larger, and the shape value is larger. The greater the absolute value.
再者，於圖1(a)、(b)中，為易於觀察到形成於晶圓之正面3側之磊晶層2，而誇大繪製該磊晶層2之厚度，實際之磊晶層2之厚度為數μm至數十μm左右，與晶圓厚度T(600~800μm左右)相比充分小。因此，應視為於磊晶層2之形成前後，第一投影長a1及第一傾斜角θ1幾乎不變化而進行處理。 Further, in FIGS. 1(a) and 1(b), in order to easily observe the epitaxial layer 2 formed on the front surface 3 side of the wafer, the thickness of the epitaxial layer 2 is exaggerated, and the actual epitaxial layer 2 is The thickness is from several μm to several tens of μm, and is sufficiently smaller than the wafer thickness T (about 600 to 800 μm). Therefore, it should be considered that the first projection length a1 and the first inclination angle θ1 are processed without any change before and after the formation of the epitaxial layer 2.
晶圓係以背面4朝下之狀態載置於MOCVD(Metal Organic Chemical Vapor Deposition，有機金屬化學氣相沈積)裝置之基座(未圖示)。該晶圓之正面3及背面4兩面已施以鏡面拋光。於基座形成有鑽孔，晶圓恰好嵌入於該鑽孔中。於將晶圓載置於基座之狀態下，向裝置內導入原料氣體，一面將晶圓加熱至1000~1200℃，一面使磊晶層2成長。此時，如圖1(a)、(b)所示，於被充分地供給原料氣體之正面3 側，磊晶層2成長，另一方面，於與基座相接而原料氣體不易流入之背面4側，磊晶層2幾乎不成長。 The wafer is placed on a pedestal (not shown) of an MOCVD (Metal Organic Chemical Vapor Deposition) device with the back surface 4 facing downward. The front side 3 and the back side 4 of the wafer have been mirror polished. A bore is formed in the base, and the wafer is just embedded in the bore. The wafer layer is placed on the susceptor, and the material gas is introduced into the apparatus, and the epitaxial layer 2 is grown while heating the wafer to 1000 to 1200 °C. At this time, as shown in FIGS. 1(a) and 1(b), the front surface 3 of the material gas is sufficiently supplied. On the other hand, the epitaxial layer 2 grows, and on the other hand, the epitaxial layer 2 hardly grows on the side of the back surface 4 which is in contact with the susceptor and the source gas does not easily flow.
針對形成有圖1(a)、(b)所示之斜角1a、1b且直徑6英吋(約150mm)、厚度625μm之具有(111)面方位之矽晶圓，評價形成有5μm包含氮化鎵半導體(GaN)之磊晶層2時之晶圓之破裂發生狀況。將其評價結果示於圖2中。橫軸表示根據GaN成膜前之斜角形狀而算出之形狀值(a1．tanθ1-a2．tanθ2)(μm)，縱軸表示GaN成膜後之晶圓破裂率(%)。於斜角形狀為錐形形狀及為圓形形狀之任一情形時，均藉由減小形狀值，即，使斜角1a、1b之縱剖面形狀於正面3與背面4側對稱地接近，而可達成較低之破裂率(0.1%以下)。另一方面可知，於錐形形狀之情形時若形狀值超過30、於圓形形狀之情形時若形狀值超過40，則破裂率急遽上升。其原因可能在於，形狀值越接近0，則作用於斜角1a、1b之與基座之接觸應力越均等地分散於斜角1a、1b之正面3與背面4側，而可緩和該應力，與此相對，形狀值之絕對值越大，則該接觸應力越易集中於斜角1a、1b之正面3側或背面4側之任一側。 For a silicon wafer having a (111) plane orientation with a bevel angle 1a, 1b shown in Figs. 1 (a) and (b) and a diameter of 6 inches (about 150 mm) and a thickness of 625 μm, it was evaluated that 5 μm of nitrogen was formed. The occurrence of cracking of the wafer when the epitaxial layer 2 of the gallium semiconductor (GaN) is formed. The evaluation results are shown in Fig. 2 . The horizontal axis represents the shape value (a1.tan θ1 - a2.tan θ2) (μm) calculated from the oblique shape before GaN film formation, and the vertical axis represents the wafer fracture rate (%) after GaN film formation. In any case where the oblique shape is a tapered shape and a circular shape, the shape value is reduced, that is, the longitudinal cross-sectional shape of the oblique angles 1a and 1b is symmetrically approached on the front surface 3 and the back surface 4 side. A lower crack rate (less than 0.1%) can be achieved. On the other hand, in the case of a tapered shape, when the shape value exceeds 30 and the shape value exceeds 40 in the case of a circular shape, the crack rate rapidly increases. The reason for this may be that the closer the shape value is to 0, the more the contact stress with the pedestal acting on the slant angles 1a and 1b is evenly distributed on the front surface 3 and the back surface 4 side of the oblique angles 1a and 1b, and the stress can be alleviated. On the other hand, the larger the absolute value of the shape value, the more easily the contact stress concentrates on either the front side 3 side or the back side 4 side of the oblique angles 1a and 1b.
根據圖2所示之結果可謂，於將製造線上之破裂率管理值設為例如0.1%以下之情形時，當斜角1a、1b為錐形形狀時，需要將形狀值設為30以下，當為圓形形狀時，需要將形狀值設為40以下。針對破裂之晶圓強度與其厚度成正比，因此可將使用厚度625μm之晶圓而獲得之形狀值之閾值(於錐形形狀之情形時為30，於圓形形狀之情形時為40)擴展至任意之晶圓厚度T。即，用以達成上述破裂率管理值(0.1%以下)之形狀值之閾值於錐形形狀之情形時成為30/625×T=0.048T，於圓形形狀之情形時成為40/625×T=0.064T。藉此，若算出直徑8英吋、厚度725μm之具有(111)面方位之晶圓之形狀值之閾值，則於錐形形狀之情形時成為34.8，於圓形形狀之情形時成為46.4。若該破裂率管理值被變更，則斜角1a、1b之形狀值之閾值亦依照圖2所示之結 果而變化。再者，藉由一面使晶圓之直徑相同一面使晶圓厚度T進一步增加，亦可提高上述閾值，而進一步提高晶圓之抗裂性。 According to the results shown in FIG. 2, when the fracture rate management value on the manufacturing line is, for example, 0.1% or less, when the oblique angles 1a and 1b are tapered, it is necessary to set the shape value to 30 or less. When it is a circular shape, you need to set the shape value to 40 or less. The strength of the wafer for cracking is proportional to its thickness, so the threshold value of the shape value obtained by using a wafer having a thickness of 625 μm (30 in the case of a tapered shape and 40 in the case of a circular shape) can be extended to Any wafer thickness T. In other words, the threshold value of the shape value for achieving the above-described fracture rate management value (0.1% or less) is 30/625×T=0.048T in the case of a tapered shape, and 40/625×T in the case of a circular shape. =0.064T. Therefore, when the threshold value of the shape value of the wafer having the (111) plane orientation of 8 inches in diameter and 725 μm in thickness is calculated, it is 34.8 in the case of a tapered shape and 46.4 in the case of a circular shape. If the damage rate management value is changed, the threshold values of the shape values of the oblique angles 1a and 1b are also in accordance with the knot shown in FIG. It changes. Furthermore, by increasing the wafer thickness T while making the diameters of the wafers the same, the threshold value can be increased to further improve the crack resistance of the wafer.
將改變第一及第二投影長a1、a2、第一及第二傾斜角θ1、θ2時之斜角形狀值(磊晶前、磊晶後)、以及使GaN於該等晶圓上磊晶成長時之實際之破裂率分別匯總於表1(錐形形狀，直徑6英吋)、表2(圓形形狀，直徑6英吋)、表3(錐形形狀，直徑8英吋(約200mm))、及表4(圓形形狀，直徑8英吋)中。再者，磊晶前之斜角形狀值係使用上述式a1．tanθ1-a2．tanθ2而計算，磊晶後之斜角形狀值係使用式(a1．tanθ1+t)-a2．tanθ2(t為磊晶厚度)而計算。 The first and second projection lengths a1, a2, the first and second inclination angles θ1, θ2, the oblique shape values (before epitaxial, post-epitaxial), and GaN on the wafers are changed. The actual rupture rates during growth are summarized in Table 1 (conical shape, diameter 6 inches), Table 2 (circular shape, diameter 6 inches), and Table 3 (tapered shape, diameter 8 inches (about 200 mm). )), and Table 4 (circular shape, diameter 8 inches). Furthermore, the value of the bevel shape before the epitaxy is the above formula a1. Tanθ1-a2. Calculated by tan θ2, the value of the oblique shape after epitaxy is expressed by the formula (a1.tan θ1+t)-a2. Tan θ2 (t is the epitaxial thickness) is calculated.
如此，關於具有任意之第一及第二投影長、第一及第二傾斜角、晶圓直徑、磊晶厚度之晶圓，可知：藉由將斜角形狀值與上述閾值進行比較，可對破裂之發生進行預測。又，可知：如表1~4之比較例所示，即便斜角形狀值為閾值以下，當第一及第二投影長a1、a2不處於50μm以上1000μm以下之範圍內時，破裂率亦超過破裂率管理值之0.1%。 Thus, regarding a wafer having arbitrary first and second projection lengths, first and second tilt angles, wafer diameter, and epitaxial thickness, it can be seen that by comparing the bevel shape value with the threshold value, The occurrence of rupture is predicted. Further, as shown in the comparative examples of Tables 1 to 4, even when the bevel shape value is equal to or less than the threshold value, when the first and second projection lengths a1 and a2 are not in the range of 50 μm or more and 1000 μm or less, the crack rate is exceeded. 0.1% of the burst rate management value.
於明確磊晶後之使用目的(所製造之元件之種類)，且已知大概之 磊晶厚度t之情形時，亦可預先自上述式之右邊側減去相當於該磊晶厚度t之閾值部分，使上述式之左邊與右邊之絕對值不同。例如，於所欲成膜之磊晶層之最大厚度為10μm，且斜角為錐形形狀之情形時，上述式之右邊(形狀值之最大值)自0.048T×(10/30)變為0.032T，於斜角為圓形形狀之情形時，上述式之右邊自0.064T×(10/40)變為0.048T。若以此方式決定右邊，則可防止於磊晶層之成膜後形狀值超過閾值，從而可確實地防止晶圓於磊晶層之成膜後破裂之問題。 The purpose of use after the clear epitaxial (the type of components manufactured), and known In the case of the epitaxial thickness t, the threshold portion corresponding to the epitaxial thickness t may be subtracted from the right side of the above equation in advance so that the absolute values of the left and right sides of the above equation are different. For example, when the maximum thickness of the epitaxial layer to be formed is 10 μm and the oblique angle is a tapered shape, the right side of the above formula (the maximum value of the shape value) is changed from 0.048T×(10/30). 0.032T, when the oblique angle is a circular shape, the right side of the above formula is changed from 0.064T × (10/40) to 0.048T. If the right side is determined in this manner, it is possible to prevent the shape value after the film formation of the epitaxial layer from exceeding the threshold value, thereby reliably preventing the wafer from being broken after the film formation of the epitaxial layer.
(2)關於晶圓背面之缺陷之大小、個數、及缺陷位置之影響 (2) Regarding the size, number, and location of defects on the back side of the wafer
於晶圓背面之缺陷之大小、個數、及缺陷位置不同之晶圓之表面成膜GaN層，並對成膜後之晶圓之翹曲量進行評價。GaN層之成膜條件與上述項目(1)中已說明之內容相同。 The GaN layer was formed on the surface of the wafer with different defects, the number of defects, and the surface of the defect, and the amount of warpage of the formed wafer was evaluated. The film formation conditions of the GaN layer are the same as those described in the above item (1).
於該GaN層之成膜之前，進行晶圓背面側之缺陷評價。於缺陷評價中，使用Surfscan SP1、或Surfscan SP2(均為KLA-Tencor公司製造)(以下，分別稱為SP1、SP2)、與掃描式電子顯微鏡(Scanning Electron Microscope)(以下，稱為SEM)或光學顯微鏡。利用SP1或SP2特定出缺陷於晶圓面內之位置，利用SEM或光學顯微鏡觀察該特定出之位置，測定該缺陷之大小。再者，該缺陷之大小為數μm~數十μm左右，非常小，而且於晶圓面內，其數量為數個~數十個左右，較少，因此基本上不可能不利用SP1等特定出缺陷之位置便利用SEM等進行直接觀察，而必須於直接觀察之前，利用SP1或SP2事先特定出缺陷之位置。 The defect evaluation on the back side of the wafer was performed before the film formation of the GaN layer. In the defect evaluation, Surfscan SP1 or Surfscan SP2 (both manufactured by KLA-Tencor Co., Ltd.) (hereinafter referred to as SP1 and SP2, respectively) and Scanning Electron Microscope (hereinafter referred to as SEM) or Optical microscope. The position of the defect in the wafer surface is specified by SP1 or SP2, and the specific position is observed by SEM or an optical microscope, and the size of the defect is measured. Furthermore, the size of the defect is about several μm to several tens of μm, which is very small, and the number of the defects is several to several tens of or less in the wafer surface, so it is basically impossible to not use the specific defect such as SP1. The position is convenient for direct observation by SEM or the like, and it is necessary to specify the position of the defect in advance by SP1 or SP2 before direct observation.
SP1、SP2具備：雙系統之入射光學系統，其向晶圓垂直入射或傾斜入射雷射；及雙系統之聚光光學系統，其分別將因晶圓之表面存在之缺陷而漫反射之入射光之散射光中的、靠近晶圓之面法線之散射光(窄通道側)與較上述窄通道側更為廣角側之散射光(寬通道側)聚光。SP1用於直徑為6英吋及8英吋之晶圓之測定，SP2用於直徑為8英 吋及12英吋之晶圓之測定。 SP1, SP2 are: a dual-system incident optical system that is incident perpendicular to the wafer or obliquely incident on the laser; and a dual-system concentrating optical system that separately reflects incident light that is diffusely reflected by defects on the surface of the wafer. The scattered light (narrow channel side) of the scattered light near the surface normal of the wafer is condensed with the scattered light (wide channel side) on the wider angle side than the narrow channel side. SP1 is used for the determination of wafers with a diameter of 6 inches and 8 inches, and SP2 is used for a diameter of 8 inches. Determination of 吋 and 12-inch wafers.
SP1與SP2於所使用之雷射之波長方面不同，但其測定原理相同，可特定出缺陷於晶圓面內之位置，並且可根據所檢測出之散射光之強度，對缺陷之大小進行評價。該缺陷之大小並非缺陷之實際大小，而為藉由如下方式導出之外觀上之大小：使用直徑不同之PSL(Polystyrene Latex，聚苯乙烯乳膠)之標準粒子，預先製作散射光強度與標準粒子之直徑之間之校準曲線，根據該校準曲線，換算成PSL標準粒子之直徑。一面旋轉晶圓一面使雷射於其面內移動而進行掃描，藉此可進行缺陷位置及大小之晶圓面內測繪。 SP1 and SP2 are different in the wavelength of the laser used, but the measurement principle is the same, the defect can be specified in the plane of the wafer, and the size of the defect can be evaluated according to the intensity of the detected scattered light. . The size of the defect is not the actual size of the defect, but is the apparent size derived by using standard particles of PSL (Polystyrene Latex) having different diameters to pre-produce scattered light intensity and standard particles. The calibration curve between the diameters is converted into the diameter of the PSL standard particles according to the calibration curve. The wafer is rotated while rotating the wafer to scan the surface of the wafer, thereby enabling in-plane mapping of the defect position and size.
於寬通道，主要檢測相對較小之缺陷；於窄通道，主要檢測相對較大之缺陷。於此次之缺陷評價中，如表5(SP1用)及表6(SP2用)所示，將寬通道之範圍設定為0.1~1.0μm，將窄通道之範圍設定為0.295~50μm。又，選擇具有雙系統之入射光學系統中之向晶圓垂直入射之入射光學系統。再者，表5及表6中所示之SP1、SP2之測定條件僅為一例，可考慮晶圓之表面狀態、成為測定對象之缺陷之大小等各種因素，而適當進行變更。又，亦可採用傾斜入射之入射光學系統代替垂直入射之入射光學系統。 In the wide channel, the relatively small defects are mainly detected; in the narrow channel, the relatively large defects are mainly detected. In the defect evaluation, as shown in Table 5 (for SP1) and Table 6 (for SP2), the range of the wide channel is set to 0.1 to 1.0 μm, and the range of the narrow channel is set to 0.295 to 50 μm. Further, an incident optical system that is incident perpendicular to the wafer in the incident optical system having the dual system is selected. In addition, the measurement conditions of SP1 and SP2 shown in Tables 5 and 6 are only an example, and various factors such as the surface state of the wafer and the size of the defect to be measured may be appropriately changed. Alternatively, an obliquely incident optical system may be used instead of the normally incident optical system.
於晶圓之表面，不僅存在裂痕或破碎層痕等凹狀之缺陷，亦存在微粒等凸狀之附著物。該缺陷與附著物因其大小或形狀(凹狀或凸狀)存在差異，故於SP1或SP2之測定中可明確地加以區分。 On the surface of the wafer, there are not only concave defects such as cracks or broken layer marks, but also convex objects such as particles. Since the defect and the attached matter differ in size or shape (concave or convex), they can be clearly distinguished in the measurement of SP1 or SP2.
例如表7所示，成為晶圓之破裂之直接原因的晶圓表面之缺陷於多數情況下被檢測出與附著物相比相對較大，且於窄通道側及寬通道側之兩者均可被檢測到，而且，於對相對較小之缺陷進行檢測之寬通道側，易於成為判斷為其大小超過範圍上限之1.0μm之飽和狀態(Saturated)。此時，如缺陷編號1、3所示，有於寬通道側成為飽和狀態，而於窄通道側判斷為小於1.0μm之情形。其原因可能在於：作為該缺陷之實態之破碎層痕形成為凹狀，與廣角側之寬通道相比，於窄通道難以檢測到散射光。 For example, as shown in Table 7, the defect of the wafer surface which is the direct cause of the crack of the wafer is detected to be relatively large in comparison with the deposit in many cases, and both on the narrow channel side and the wide channel side. It is detected, and on the wide channel side where the relatively small defect is detected, it is easy to be a saturated state (saturated) of 1.0 μm whose size exceeds the upper limit of the range. At this time, as shown by the defect numbers 1 and 3, the wide channel side is saturated, and the narrow channel side is judged to be less than 1.0 μm. The reason may be that the fracture layer trace which is the actual state of the defect is formed in a concave shape, and it is difficult to detect the scattered light in the narrow channel as compared with the wide channel on the wide angle side.
與此相對，如表8所示，不易成為破裂之直接原因的晶圓表面之附著物於多數情況下被檢測出與裂痕等缺陷相比相對較小，且於多數情況下僅於寬通道側被檢測到，而於窄通道側未檢測到(ND)。若該附著物之大小以某種程度變大，則如缺陷編號5、6所示，於窄通道側及寬通道側之兩者均被檢測到。於該情形時，存在窄通道側之大小被檢測出較寬通道側之大小更大之傾向。其原因可能在於：作為該缺陷之實態之微粒形成為凸狀，與凹狀之缺陷相反，與廣角側之寬通道相比，於窄通道易於檢測到散射光。如缺陷編號4所示，當為如跨及複數個測定區域之特大附著物時，亦存在如下情形：於寬通道側判斷為缺陷之集合體(Clustering)；於窄通道側判斷為飽和狀態。 On the other hand, as shown in Table 8, the adherend of the wafer surface which is not easily caused as a direct cause of cracking is often detected to be relatively small compared with defects such as cracks, and in many cases, only on the wide channel side. It was detected and not detected (ND) on the narrow channel side. If the size of the deposit is increased to some extent, both of the narrow channel side and the wide channel side are detected as indicated by the defect numbers 5 and 6. In this case, there is a tendency that the size of the narrow channel side is detected to be larger on the wider channel side. The reason may be that the particles which are the actual state of the defect are formed in a convex shape, and contrary to the concave defect, the scattered light is easily detected in the narrow channel as compared with the wide channel on the wide-angle side. As shown in the defect number 4, when it is an extra large attachment such as a span and a plurality of measurement areas, there is also a case where it is judged to be a cluster of defects on the wide channel side and a saturated state on the narrow channel side.
如此，於SP1及SP2之測定中，因於凹狀之缺陷與凸狀之附著物之間，窄通道與寬通道中所檢測出之大小存在差異，故可對兩者加以區分而進行檢測。但，利用SP1或SP2測定出之缺陷之大小僅用於凹狀之缺陷或凸狀之附著物之區分，於對與晶圓之翹曲或破裂之關係進行評價時，設為使用利用SEM或光學顯微鏡而獲得之實測值。 As described above, in the measurement of SP1 and SP2, since the size detected by the narrow channel and the wide channel differs between the concave defect and the convex attachment, the two can be distinguished and detected. However, the size of the defect measured by SP1 or SP2 is only used for the difference between the concave defect or the convex attachment. When evaluating the relationship with the warpage or crack of the wafer, it is used to use SEM or The measured value obtained by optical microscopy.
將於晶圓背面存在缺陷之晶圓上成膜有GaN時之晶圓之翹曲量之測定結果示於圖3。以下所示之缺陷之大小係利用SEM或光學顯微鏡而測定之實測值。該測定中所使用之晶圓之直徑為6英吋，厚度為625μm，其正面及背面之兩面均成為鏡面拋光。橫軸表示距晶圓背面側之中心為22.5mm(晶圓半徑之30%)之區域內的1μm以上之大小之缺陷之數量，縱軸表示磊晶後之晶圓之翹曲量。於利用SEM或光學顯微鏡進行測定之前所進行之SP1之測定條件如表5所示。利用SEM或光學顯微鏡而測定出之缺陷分佈於2μm至30μm之大小範圍內。 The measurement result of the warpage amount of the wafer when GaN is formed on the wafer having defects on the back surface of the wafer is shown in FIG. The size of the defects shown below is the measured value measured by SEM or optical microscopy. The wafer used in this measurement has a diameter of 6 inches and a thickness of 625 μm, and both sides of the front and back surfaces are mirror-polished. The horizontal axis represents the number of defects of 1 μm or more in a region of 22.5 mm (30% of the wafer radius) from the center of the wafer back side, and the vertical axis represents the amount of warpage of the wafer after epitaxy. The measurement conditions of SP1 performed before the measurement by SEM or optical microscopy are shown in Table 5. The defects measured by SEM or optical microscopy are distributed in the range of 2 μm to 30 μm.
由該測定結果可知，缺陷之數量越多，則翹曲量越大。認為其原因在於：如圖4(a)~(c)所示，若於磊晶層之形成中，拉伸應力作用於晶圓之背面存在之缺陷9(參照本圖(a))，則滑移自該缺陷9伸展(參照本圖(b))，且該滑移向晶圓之正面側移出(參照本圖(c))，藉此引起較大之翹曲。例如，可知於將翹曲量之管理值設為20μm以下之情形 時，藉由使缺陷數量為5個以下，可使磊晶後之翹曲量為該管理值範圍內。 From the measurement results, it is understood that the larger the number of defects, the larger the amount of warpage. The reason is considered to be that, as shown in FIGS. 4(a) to 4(c), when the tensile stress acts on the back surface of the wafer (see FIG. (a)), the tensile stress acts on the back surface of the wafer. The slip extends from the defect 9 (refer to Fig. (b)), and the slip is removed toward the front side of the wafer (refer to Fig. (c)), thereby causing a large warpage. For example, it can be seen that the management value of the amount of warpage is set to 20 μm or less. When the number of defects is 5 or less, the amount of warpage after the epitaxy can be made within the range of the management value.
雖於本圖中未顯示，但亦可確認到即便於距中心為22.5mm之範圍外存在1μm以上之缺陷，亦幾乎不對晶圓之翹曲量造成影響。其原因在於：較大之拉伸應力於距晶圓之中心為22.5mm之範圍內作用，另一方面，於該範圍外，該拉伸應力相對變小，即便假設存在缺陷，亦不會成為滑移源。又，亦可確認到即便於距中心為22.5mm之範圍內存在小於1μm之缺陷，亦幾乎不對晶圓之翹曲量造成影響。推定其原因在於：有於負擔應力時會成為滑移源之缺陷之大小之最小閾值。 Although not shown in the figure, it has been confirmed that even if there is a defect of 1 μm or more outside the range of 22.5 mm from the center, the amount of warpage of the wafer is hardly affected. The reason is that a large tensile stress acts in a range of 22.5 mm from the center of the wafer, and on the other hand, outside the range, the tensile stress is relatively small, and even if a defect is assumed, it does not become. Slip source. Further, it was confirmed that even if there is a defect of less than 1 μm in the range of 22.5 mm from the center, the amount of warpage of the wafer is hardly affected. The reason for this is that it is the minimum threshold for the size of the defect that will become the source of the slip when the stress is stressed.
藉由以此方式管理缺陷之大小，亦可謀求晶圓之破裂之抑制。其原因在於，已知缺陷之大小越大(作為標準為30μm以上)，則越易於產生破裂，若為上述缺陷之大小(1μm)，則充分低於上述標準。 By managing the size of the defect in this way, it is also possible to suppress the crack of the wafer. The reason for this is that the larger the size of the known defect (as a standard of 30 μm or more), the more likely the crack is generated, and if it is the size of the above defect (1 μm), it is sufficiently lower than the above standard.
又，雖於本圖中未顯示，但亦可確認到當於晶圓面內存在大致相同數量之缺陷之情形時，該缺陷之大小越大，則翹曲量越大。 Further, although not shown in the figure, it is also confirmed that when there are substantially the same number of defects on the wafer surface, the larger the size of the defect, the larger the amount of warpage.
圖3表示直徑為6英吋之晶圓之結果，但對於直徑為8英吋及12英吋之晶圓，亦可藉由在距中心為30mm(8英吋之情形)、或距中心為45mm(12英吋之情形)之區域內，將1μm以上之大小之缺陷之個數設為5個以下，而使磊晶後之翹曲量為該管理值範圍內。若該翹曲量之管理值被變更，則於距中心為30%之區域內容許存在之缺陷之數量亦依照圖3所示之結果而變化。 Figure 3 shows the result of a 6-inch diameter wafer, but for a diameter of 8 inches and 12 inches, it can also be 30mm (8 inches) from the center, or from the center. In the region of 45 mm (in the case of 12 inches), the number of defects having a size of 1 μm or more is set to 5 or less, and the amount of warpage after the epitaxy is within the range of the management value. If the management value of the warpage amount is changed, the number of defects allowed to exist in the area of 30% from the center also changes according to the result shown in FIG.
又，於上文中，將缺陷之大小之基準設為1μm以上，但於使用光學顯微鏡之情形時，亦容許當其解像度未達1μm時，將缺陷之大小之基準變更為2μm以上、3μm以上、5μm以上、10μm以上等，並且變更於距中心為30%之區域內容許存在之缺陷之數量。再者，藉由以如上方式控制缺陷之大小與數量，並且一面使晶圓之直徑相同一面使晶圓厚度進一步增加，亦可進一步降低翹曲量。 In addition, in the above, the reference of the size of the defect is set to 1 μm or more. However, when the optical microscope is used, when the resolution is less than 1 μm, the reference of the size of the defect is changed to 2 μm or more and 3 μm or more. 5 μm or more, 10 μm or more, etc., and the number of defects allowed to exist in an area of 30% from the center. Furthermore, by controlling the size and number of defects as described above and further increasing the wafer thickness while making the diameters of the wafers the same, the amount of warpage can be further reduced.
(3)關於晶格間氧及添加物之濃度之影響 (3) Effect on the concentration of oxygen and additives in the lattice
於晶圓中，含有於結晶育成時自石英坩堝導入之晶格間氧、作為p型半導體之摻雜物之硼、用以謀求晶圓中之Si氧化物之析出促進之氮、碳等添加元素。該等添加元素凝集於作為結晶缺陷之一種之位錯之附近而阻止位錯之移動，或與Si氧化物進行移動之位錯發生作用而阻止該移動，藉此發揮抑制因位錯之移動而產生之滑移之發生或晶圓之破裂的作用。 In the wafer, inter-lattice oxygen introduced from the quartz crucible during the crystal growth, boron as a dopant of the p-type semiconductor, and nitrogen or carbon added for promoting the precipitation of the Si oxide in the wafer are contained. element. These additive elements are aggregated in the vicinity of dislocations which are one type of crystal defects to prevent the movement of dislocations, or to act on dislocations in which the Si oxide moves to prevent the movement, thereby suppressing the movement due to dislocations. The occurrence of slippage or the rupture of the wafer.
基本上，添加元素之濃度越高，則位錯之移動阻止作用越有效地發揮作用，但較佳為晶格間氧設為1~12×1017/cm3、硼設為1~100×1018/cm3、氮設為1~10×1014/cm3、碳設為1~10×1016/cm3之範圍內。設定各添加元素之濃度範圍之下限之原因在於：若添加濃度為其以下，則無法充分地發揮位錯之移動阻止作用。設定晶格間氧之濃度範圍之上限之原因在於：若為其以上之濃度，則Si氧化物過度析出及成長，而自該Si氧化物本身發生位錯，會成為強度降低之原因。設定硼之濃度範圍之上限之原因在於：若設為其以上之添加濃度，則會成為對晶圓通常要求之特定之電阻率之範圍外。設定氮及碳之濃度範圍之上限之原因在於：若設為其以上之添加濃度，則過度促進Si氧化物之析出，會成為對元件特性造成不良影響之原因。 Basically, the higher the concentration of the added element, the more effective the action of preventing the movement of the dislocation, but it is preferable that the inter-lattice oxygen is set to 1 to 12 × 10 17 /cm 3 and the boron is set to 1 to 100 ×. 10 18 /cm 3 , nitrogen is set to 1 to 10 × 10 14 /cm 3 , and carbon is set to be in the range of 1 to 10 × 10 16 /cm 3 . The reason why the lower limit of the concentration range of each of the added elements is set is that if the concentration is less than or equal to the above, the movement prevention effect of the dislocation cannot be sufficiently exerted. The reason for setting the upper limit of the oxygen concentration range between the crystal lattices is that if the concentration is higher than the above, the Si oxide excessively precipitates and grows, and dislocations occur from the Si oxide itself, which causes a decrease in strength. The reason for setting the upper limit of the concentration range of boron is that if it is set to be higher than the above, it will be outside the range of the specific resistivity normally required for the wafer. The reason for setting the upper limit of the concentration range of nitrogen and carbon is that if the concentration is more than the above, the precipitation of the Si oxide is excessively promoted, which may adversely affect the device characteristics.
可考慮必要之晶圓特性而於上述濃度範圍內適當決定各添加元素之濃度，但尤佳為將晶格間氧設為10×1017/cm3，將硼設為10×1018/cm3，將碳設為0.8×1016/cm3，將氮設為5×1014/cm3。自提高晶圓之強度之觀點而言，較佳為遍及晶圓整體，將各添加元素設為上述濃度(濃度範圍內)，但由於如上述項目(2)中已說明般，於晶圓背面中心附近產生較高之拉伸應力，故而尤佳為至少於基板背面中之距中心為半徑之30%以內之區域內，為上述濃度範圍內。 The concentration of each additive element may be appropriately determined within the above concentration range in consideration of the necessary wafer characteristics, but it is particularly preferable to set the inter-lattice oxygen to 10 × 10 17 /cm 3 and the boron to 10 × 10 18 /cm. 3 , the carbon was set to 0.8 × 10 16 /cm 3 , and the nitrogen was set to 5 × 10 14 /cm 3 . From the viewpoint of increasing the strength of the wafer, it is preferable to set each additive element to the above concentration (within the concentration range) throughout the entire wafer, but as described in the above item (2), on the back side of the wafer A high tensile stress is generated in the vicinity of the center, and it is particularly preferably in a range of the above concentration range at least in a region within 30% of the radius from the center in the back surface of the substrate.
(4)關於使端面成為鏡面拋光之影響 (4) Regarding the effect of making the end face mirror finish
藉由使晶圓之背面成為鏡面拋光，並且端面亦成為鏡面拋光而將該端面之缺陷除去，可謀求晶圓之破裂及翹曲量之進一步降低。對該一連串之與鏡面拋光相關之步驟之一例進行說明。首先，對切割晶錠而獲得之晶圓進行粗研磨(磨削)，去除晶圓表面之機械損傷。於該粗研磨之步驟之前或之後，進行端面(斜角)之倒角加工。其次，進行晶圓之正面及背面之鏡面研磨(Double Side Polish：DSP，雙面拋光)，繼而進行端面研磨(Polishing Corner Rounding：PCR，圓角拋光)，使該端面成為鏡面。最後，作為最後加工，利用單片式之研磨裝置進行晶圓表面之鏡面研磨，經過洗淨、檢查而完成一連串之步驟。 By making the back surface of the wafer mirror-polished and the end surface is also mirror-polished, the defects of the end surface are removed, and the crack of the wafer and the amount of warpage can be further reduced. An example of a series of steps related to mirror polishing will be described. First, the wafer obtained by cutting the ingot is subjected to rough grinding (grinding) to remove mechanical damage on the wafer surface. The chamfering of the end face (bevel) is performed before or after the step of coarse grinding. Next, mirror polishing (Double Side Polish: DSP, double-sided polishing) on the front and back sides of the wafer is performed, followed by face grinding (Polishing Corner Rounding: PCR) to make the end face a mirror surface. Finally, as a final process, the surface of the wafer is mirror-polished using a monolithic polishing apparatus, and a series of steps are completed after washing and inspection.
(5)關於凹口製作位置之影響 (5) Influence on the position of the notch making
於晶圓之邊緣形成有用以表示結晶方位之凹口，該凹口形成為朝向晶圓中心方向之凹狀，因此有於製程中發生應力集中而成為滑移之起點之情況。而且，因該滑移伸展，而引起磊晶後之晶圓之翹曲。關於成為滑移之起點之容易度，如圖5所示，當將作用於晶圓之應力F之方向與Si晶體之滑動面((111)面)之方向n所成之角設為θ，將應力F與滑動方向(<110>方向)b所成之角設為Φ時，根據由cosθ．cosΦ定義之實密因子(Schmid factor)S之大小而決定，且判斷為該實密因子S越大，則越易發生位錯於滑動面之滑動(越易發生滑移)。 A notch for indicating a crystal orientation is formed at the edge of the wafer, and the notch is formed in a concave shape toward the center of the wafer, so that stress concentration occurs in the process and becomes a starting point of slip. Moreover, the warpage of the wafer after epitaxialization is caused by the slip stretching. As for the ease of becoming the starting point of the slip, as shown in FIG. 5, the angle formed by the direction of the stress F acting on the wafer and the direction n of the sliding surface ((111) plane) of the Si crystal is θ, When the angle formed by the stress F and the sliding direction (<110> direction) b is Φ, according to cos θ. The size of the Schmid factor S defined by cosΦ is determined, and it is judged that the larger the solid factor S is, the more easily the dislocation is slipped on the sliding surface (the slippage is more likely to occur).
該實密因子S於沿<110>方向形成凹口時最小，越自該<110>方向偏移則變得越大。於圖6中，表示以與上述項目(1)相同之成膜條件於使凹口之形成位置自<110>方向繞晶圓之外周移位之晶圓上形成有GaN時的磊晶後之晶圓之翹曲量。於斜角為圓形形狀及為錐形形狀之任一情形時，翹曲量均隨凹口之形成位置自<110>方向偏移而增大。可知例如若將翹曲量之管理值設為20μm，則於為圓形形狀之情形時，必須於距<110>方向為20度以內形成凹口，於為錐形形狀 之情形時，必須於大致正<110>方向上形成凹口。 The solid factor S is the smallest when the notch is formed in the <110> direction, and becomes larger as it shifts from the <110> direction. In FIG. 6, the same film formation conditions as in the above item (1) are shown after epitaxial formation in which GaN is formed on a wafer in which the formation position of the notch is displaced from the <110> direction around the wafer. The amount of warpage of the wafer. In the case where the oblique angle is a circular shape and a tapered shape, the amount of warpage increases as the position at which the notch is formed is shifted from the <110> direction. For example, when the management value of the amount of warpage is 20 μm, it is necessary to form a notch within 20 degrees from the <110> direction in the case of a circular shape, and it is tapered. In the case of the case, it is necessary to form a notch in the substantially positive <110> direction.
上述各實施例僅為一例，只要可解決本案發明之課題，便容許適當變更其構成，上述課題為抑制當使氮化物半導體層於矽晶圓上磊晶成長時，晶圓破裂、或位錯伸展而產生較大之翹曲。 Each of the above-described embodiments is merely an example, and as long as the object of the present invention can be solved, the configuration can be appropriately changed. The above problem is to suppress wafer cracking or dislocation when the nitride semiconductor layer is epitaxially grown on a germanium wafer. Stretching produces a large warp.
1a‧‧‧斜角 1a‧‧‧bevel
1b‧‧‧斜角 1b‧‧‧bevel
2‧‧‧氮化物半導體層(磊晶層) 2‧‧‧ nitride semiconductor layer (epi layer)
3‧‧‧正面 3‧‧‧ Positive
4‧‧‧背面 4‧‧‧Back
5‧‧‧端面 5‧‧‧ end face
6‧‧‧第一傾斜面 6‧‧‧First inclined surface
7‧‧‧第二傾斜面 7‧‧‧Second inclined surface
8‧‧‧曲端面 8‧‧‧ curved end face
a1‧‧‧第一投影長 A1‧‧‧first projection length
a2‧‧‧第二投影長 A2‧‧‧second projection length
t‧‧‧磊晶厚度 T‧‧‧ epitaxial thickness
θ1‧‧‧第一傾斜角 Θ1‧‧‧first tilt angle
θ2‧‧‧第二傾斜角 Θ2‧‧‧second tilt angle
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| TW201311417A (en) * | 2011-08-04 | 2013-03-16 | Sumitomo Electric Industries | Method for manufacturing group-iii nitride crystal substrate |
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| TW201542853A (en) | 2015-11-16 |
| CN105814245A (en) | 2016-07-27 |
| CN105814245B (en) | 2018-09-04 |
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| CN108461384A (en) | 2018-08-28 |
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