TWI568161B - A full - bridge phase - shifting converter for digital multi - mode control - Google Patents
A full - bridge phase - shifting converter for digital multi - mode control Download PDFInfo
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本發明係有關於全橋相移轉換器(phase shift full bridge converter,PSFBC)，特別是關於一種適用於低壓大電流輸出之全橋相移轉換器。 The present invention relates to a phase shift full bridge converter (PSFBC), and more particularly to a full bridge phase shift converter suitable for low voltage and high current output.
現今科技快速發展，在雲端伺服器、通訊、醫療等領域中對於分散式高效率電源皆有強勁的需求。為了要符合高功率密度、高效率的需求，模組化及諧振式的切換式電源供應器已成為未來的發展趨勢。 With the rapid development of technology, there is a strong demand for decentralized high-efficiency power supplies in the fields of cloud server, communication, and medical. In order to meet the requirements of high power density and high efficiency, modular and resonant switching power supplies have become the future development trend.
切換式電源供應器若採用傳統的硬切換(hard switching)，功率元件在開啟與關閉時，易衍生切換損失，而切換損失會使溫度上升、效率降低，也會產生電磁干擾。圖1(a)-1(b)為硬性切換與柔性切換(soft switching)之示意圖。為了有效的減少切換損失，零電壓切換(zero voltage switching；ZVS)、零電流切換(zero current switching；ZCS)等具柔切特性的架構被廣泛地討論與應用。柔性切換技術係藉由使開關零電壓切換或零電流切換，進而降低切換損失、提升電源轉換效率、並改善電磁干擾(electromagnetic interference；EMI)問題。在具柔切功能之轉換器中，相移式全橋轉換器因具有零電壓切換的優點，當功率開關導通之前，開關上的電壓V DS 已經下降至零，開關上面的電流I D 才開始上升，使得導通時功率開關上的V DS 與I D 交越面積為零，因此乃被廣泛的應用在中高功率的場合上。 If the switching power supply adopts the traditional hard switching, when the power components are turned on and off, the switching loss is easily derived, and the switching loss causes the temperature to rise, the efficiency is lowered, and electromagnetic interference is also generated. 1(a)-1(b) are schematic diagrams of hard switching and soft switching. In order to effectively reduce switching losses, architectures with soft-cut characteristics such as zero voltage switching (ZVS) and zero current switching (ZCS) are widely discussed and applied. Flexible switching technology reduces switching losses, improves power conversion efficiency, and improves electromagnetic interference (EMI) by switching zero voltage switching or zero current switching. In a converter with a soft-cut function, the phase-shifted full-bridge converter has the advantage of zero voltage switching. Before the power switch is turned on, the voltage V DS on the switch has dropped to zero, and the current I D on the switch begins. Ascending, the crossover area of V DS and I D on the power switch at the time of conduction is zero, so it is widely used in medium and high power applications.
相同輸出功率下，全橋轉換器其每個功率元件所承受的電壓與電流應力比其他轉換器小，故適用於高功率及高輸入電壓的場合。傳統全橋轉換器的功率開關操作在硬切換，容易造成切換損失過大，導致重載效率不佳。為了解決全橋轉換器切換損失過大的問題，前人提出一種全橋轉換器的相移控制技術，利用變壓器的漏感以及初級側的諧振電感和功率開關上的寄生電容達到共振，使得功率開關能在導通之前，先將開關上的電壓下降至零電位，以達到零電壓導通的目的。 At the same output power, the full-bridge converter has a lower voltage and current stress than other converters, so it is suitable for high power and high input voltage. The power switching operation of the traditional full-bridge converter is hard switching, which is likely to cause excessive switching loss, resulting in poor heavy load efficiency. In order to solve the problem of excessive switching loss of the full-bridge converter, a phase shift control technique of a full-bridge converter is proposed, which uses the leakage inductance of the transformer and the resonant inductance on the primary side and the parasitic capacitance on the power switch to achieve resonance, so that the power switch Before the conduction, the voltage on the switch can be lowered to zero potential to achieve zero voltage conduction.
也有文獻針對相移式全橋轉換器領先臂與落後臂之功率開關損耗分析進行探討，並說明操作於不同負載條件與不同操作模式轉換器主要損耗分佈。針對相移式全橋轉換器在不同頻率下之損耗進行分析，在輕載時損耗主要在切換損失部分，因此在輕載便降低切換頻率，而在中載時損耗主要在磁性元件部分，因此提高切換頻率以降低鐵芯損，在重載則為了降低切換損失而降低切換頻率。相移式全橋轉換器在輕載時，因諧振電流較低而無法達到零電壓切換，造成相移式全橋轉換器在輕載時效率較差，因此如何提升相移式全橋轉換器的輕載效率一直是相移式全橋轉換器研究目標之一，例如在電路架構上增加一些電容與電感等被動元件，讓電路能在輕載時達成如零電流切換，或者增加諧振電感感值讓功率開關能在輕載時能零電壓切換。這些方法確實可以有效增加相移式全橋轉換器的輕載轉換效率，然而卻必須付出額外的電路成本及體積。因此亦有文獻提出調整輕載時的盲時(Dead Time)，藉由延長轉換器的雜散電容放電的時間，達到降低開關元件切換電壓以減少電路上的切換損失之目的，同時調整盲時時間提升輕載效率時，並不會造成額外的電路成本。 There is also a literature on the power switching loss analysis of the leading-edge and trailing arm of the phase-shifted full-bridge converter, and shows the main loss distribution of the converter operating under different load conditions and different operating modes. For the phase-shift full-bridge converter, the loss at different frequencies is analyzed. At light load, the loss is mainly in the switching loss part, so the switching frequency is reduced at light load, and the loss is mainly in the magnetic component part at the middle load. Increase the switching frequency to reduce the core loss, and reduce the switching frequency to reduce the switching loss during heavy load. Phase-shifted full-bridge converters cannot achieve zero-voltage switching due to low resonant current at light loads, resulting in a phase-shifted full-bridge converter that is less efficient at light loads, so how to improve the phase-shifted full-bridge converter Light-load efficiency has always been one of the research goals of phase-shifted full-bridge converters. For example, passive components such as capacitors and inductors are added to the circuit architecture to allow the circuit to achieve zero current switching at light loads or to increase the resonant inductance. Allows the power switch to switch between zero voltages at light loads. These methods can effectively increase the light load conversion efficiency of phase-shifted full-bridge converters, but they must pay extra circuit cost and volume. Therefore, some literatures have proposed to adjust the dead time of the light load. By extending the time of the stray capacitance discharge of the converter, the switching voltage of the switching element can be reduced to reduce the switching loss on the circuit, and the blind time is adjusted. When time increases light load efficiency, it does not incur additional circuit costs.
本發明之主要目的在於提出一數位控制多模式切換之全橋相移轉換器，其可根據負載大小切換不同的工作模式(依輸出電流的大小決定)：在空載時提供在一突衝模式(burst mode)；輕載時提供一脈波寬度調變模式(PWM mode)；重載時則提供一變動盲時相移模式(adaptive dead time phase shift mode)。 The main purpose of the present invention is to propose a full-bridge phase-shift converter for controlling multi-mode switching, which can switch different operating modes according to the load size (depending on the magnitude of the output current): providing a burst mode at no load. (burst mode); provides a pulse width modulation mode (PWM mode) at light load; provides an adaptive dead time phase shift mode when reloaded.
為達到上述目的，一種數位多模式控制之全橋相移轉換器乃被提出，其具有：一全橋式開關電路，具有二輸入端以與一輸入電壓耦接，四控制端以分別與一第一控制信號、一第二控制信號、一第三控制信號、以及一第四控制信號耦接，且該第一控制信號係與該第二控制信號的作用電位互補且該第三控制信號係與該第四控制信號的作用電位互補； 一變壓器單元，具有一諧振電感及一變壓器，該變壓器具有一第一線圈及一第二線圈，且該諧振電感之一端係與該全橋式開關電路之一輸出端耦接，另一端則經由該第一線圈耦接至該全橋式開關電路之另一輸出端；一橋式整流電路，具有二輸入端以與該第二線圈耦接；一電感-電容濾波電路，與該橋式整流電路之二輸出端耦接以提供一輸出電壓及一輸出電流至一負載；一回授電路，用以依該輸出電壓及該輸出電流分別產生一電壓回授信號及一電流回授信號；以及一控制單元，儲存有一韌體程式，用以執行一控制信號產生程序，該控制信號產生程序包含藉由一比例-積分-微分運算調整該第一控制信號和該第三控制信號間之一相移角以產生該第一控制信號、該第二控制信號、該第三控制信號、以及該第四控制信號，其中，該控制信號產生程序係依該電壓回授信號調整該相移角，且該控制信號產生程序係在該電流回授信號小於一第一預設值時提供一突衝模式，在該電流回授信號大於該第一預設值且小於一第二預設值時提供一脈波寬度調變模式，以及在該電流回授信號大於該第二預設值時提供一變動盲時相移模式。 In order to achieve the above object, a digital multi-mode controlled full-bridge phase shift converter is proposed, which has: a full bridge switching circuit having two inputs for coupling with an input voltage, and four control terminals for respectively The first control signal, a second control signal, a third control signal, and a fourth control signal are coupled, and the first control signal is complementary to the action potential of the second control signal and the third control signal is Complementing the action potential of the fourth control signal; a transformer unit having a resonant inductor and a transformer, the transformer having a first coil and a second coil, and one end of the resonant inductor is coupled to one of the output ends of the full bridge switch circuit, and the other end is via The first coil is coupled to the other output end of the full bridge switch circuit; a bridge rectifier circuit having two input ends for coupling with the second coil; an inductor-capacitor filter circuit, and the bridge rectifier circuit The output end is coupled to provide an output voltage and an output current to a load; a feedback circuit for generating a voltage feedback signal and a current feedback signal according to the output voltage and the output current; The control unit stores a firmware program for executing a control signal generating program, the control signal generating program including adjusting a phase shift between the first control signal and the third control signal by a proportional-integral-differential operation An angle to generate the first control signal, the second control signal, the third control signal, and the fourth control signal, wherein the control signal generating program is dependent on the voltage The signal is adjusted to adjust the phase shift angle, and the control signal generating program provides a burst mode when the current feedback signal is less than a first preset value, where the current feedback signal is greater than the first preset value and less than A pulse width modulation mode is provided for a second preset value, and a variable blind phase shift mode is provided when the current feedback signal is greater than the second predetermined value.
在一實施例中，該全橋式開關電路包含四顆功率開關。 In an embodiment, the full bridge switching circuit includes four power switches.
在一實施例中，該控制信號產生程序包含一類比至數位轉換運算。 In one embodiment, the control signal generation program includes an analog to digital conversion operation.
在一實施例中，該控制信號產生程序進一步包含一濾波運算。 In an embodiment, the control signal generation program further includes a filtering operation.
在一實施例中，該控制單元包含一脈波寬度調變模組以提供該第一控制信號、該第二控制信號、該第三控制信號、以及該第四控制信號。 In an embodiment, the control unit includes a pulse width modulation module to provide the first control signal, the second control signal, the third control signal, and the fourth control signal.
為使 貴審查委員能進一步瞭解本發明之結構、特徵及其目的，茲附以圖式及較佳具體實施例之詳細說明如后。 The detailed description of the drawings and the preferred embodiments are set forth in the accompanying drawings.
100‧‧‧全橋式開關電路 100‧‧‧Full bridge switching circuit
110‧‧‧變壓器單元 110‧‧‧Transformer unit
120‧‧‧橋式整流電路 120‧‧‧Bridge rectifier circuit
130‧‧‧電感-電容濾波電路 130‧‧‧Inductance-capacitor filter circuit
140‧‧‧回授電路 140‧‧‧Responsive circuit
150‧‧‧控制單元 150‧‧‧Control unit
111‧‧‧諧振電感 111‧‧‧Resonant inductance
112‧‧‧變壓器 112‧‧‧Transformers
151‧‧‧類比至數位轉換單元 151‧‧‧ analog to digital conversion unit
152‧‧‧濾波運算單元 152‧‧‧Filtering unit
153‧‧‧比例-積分-微分運算單元 153‧‧‧Proportional-Integral-Derivative Unit
154‧‧‧脈衝寬度調變運算單元 154‧‧‧ pulse width modulation unit
155‧‧‧驅動單元 155‧‧‧ drive unit
200‧‧‧負載 200‧‧‧load
圖1(a)-1(b)為硬性切換與柔性切換(soft switching)之示意圖。 1(a)-1(b) are schematic diagrams of hard switching and soft switching.
圖2繪示本發明之數位多模式控制之全橋相移轉換器之一實施例。 2 illustrates an embodiment of a digital multi-mode controlled full bridge phase shift converter of the present invention.
圖3繪示本發明之全橋轉換器電路架構。 3 illustrates the full bridge converter circuit architecture of the present invention.
圖4繪示本發明所採之一PWM控制法之波形圖。 FIG. 4 is a waveform diagram of a PWM control method adopted by the present invention.
圖5繪示本發明所採之一相移式控制法之波形圖。 FIG. 5 is a waveform diagram of a phase shift control method adopted by the present invention.
圖6繪示為本發明所採之相移式全橋轉換器之初級與次級側之電流、電壓的理論波形。 6 is a theoretical waveform of current and voltage on the primary and secondary sides of the phase-shifted full-bridge converter of the present invention.
圖7繪示與圖6所示之一領先臂諧振區間相對應之一等效電路。 FIG. 7 illustrates an equivalent circuit corresponding to one of the leading arm resonance intervals shown in FIG. 6.
圖8繪示與圖6所示之一落後臂諧振區間相對應之一等效電路。 FIG. 8 illustrates an equivalent circuit corresponding to one of the backward arm resonance intervals shown in FIG. 6.
圖9繪示本發明之可變盲時與輸出電流之一對照圖。 Figure 9 is a graph showing a comparison of the variable blind time and the output current of the present invention.
圖10(a)-10(b)繪示本發明之一ADC中斷副程式流程圖。 10(a)-10(b) are flow diagrams showing an ADC interrupt subroutine of the present invention.
圖11繪示本發明之一PID控制原理方塊圖。 Figure 11 is a block diagram showing the principle of PID control of the present invention.
圖12繪示本發明之一增量型PID程式流程圖。 FIG. 12 is a flow chart of an incremental PID program of the present invention.
圖13繪示本發明所量到之功率開關控制訊號之二波形圖。 FIG. 13 is a second waveform diagram of the power switch control signal measured by the present invention.
圖14繪示本發明在輸入電壓360V、輸出電流1A時所量到之V gs3、V gs4及變壓器之電壓V p 和電流I p 的波形。 FIG. 14 is a graph showing waveforms of V gs 3 , V gs 4 and voltages V p and I p of the transformer when the input voltage is 360 V and the output current is 1 A.
圖15繪示本發明在輸出電流小於0.5A時所啟動之一突衝模式波形圖。 Figure 15 is a waveform diagram showing one of the burst modes initiated by the present invention when the output current is less than 0.5A.
圖16(a)-16(b)繪示本發明在傳統全橋模式和相移式全橋轉換模式之間的轉換。 16(a)-16(b) illustrate the transition of the present invention between a conventional full bridge mode and a phase shift full bridge conversion mode.
圖17為本發明之全橋轉換器之多模式切換示意圖。 Figure 17 is a schematic diagram of multi-mode switching of the full bridge converter of the present invention.
圖18繪示本發明的多模式控制與傳統PWM控制和固定盲時控制之全橋轉換效率比較圖。 Figure 18 is a graph showing the comparison of full-bridge conversion efficiency of the multi-mode control of the present invention with conventional PWM control and fixed blind time control.
請參照圖2，其繪示本發明之數位多模式控制之全橋相移轉換器之一實施例。如圖2所示，該全橋相移轉換器具有一全橋式開關電路100、一變壓器單元110、一橋式整流電路120、一電感-電容濾波電路130、一回授電路140、以及一控制單元150。 Referring to FIG. 2, an embodiment of a digital multi-mode controlled full bridge phase shift converter of the present invention is illustrated. As shown in FIG. 2, the full bridge phase shift converter has a full bridge switching circuit 100, a transformer unit 110, a bridge rectifier circuit 120, an inductor-capacitor filter circuit 130, a feedback circuit 140, and a control unit. 150.
全橋式開關電路100，可由四顆功率開關構成，具有二輸入端A、B以與一輸入電壓VIN耦接，四控制端以分別與一第一控制信號S1、一第二控制信號S2、一第三控制信號S3、以及一第四控制信號S4耦接，且該第一控制信號S1係 與該第二控制信號S2的作用電位互補且該第三控制信號S3係與該第四控制信號S4的作用電位互補。 The full-bridge switching circuit 100 can be composed of four power switches, having two input terminals A and B coupled to an input voltage V IN , and four control terminals respectively for a first control signal S 1 and a second control signal. S 2 , a third control signal S 3 , and a fourth control signal S 4 are coupled, and the first control signal S 1 is complementary to the action potential of the second control signal S 2 and the third control signal S The 3 series is complementary to the action potential of the fourth control signal S 4 .
變壓器單元110具有一諧振電感111及一變壓器112，該變壓器112具有一第一線圈及一第二線圈，且該諧振電感111之一端係與該全橋式開關電路100之一輸出端耦接，另一端則經由該第一線圈耦接至該全橋式開關電路100之另一輸出端。 The transformer unit 110 has a resonant inductor 111 and a transformer 112. The transformer 112 has a first coil and a second coil, and one end of the resonant inductor 111 is coupled to an output end of the full-bridge switching circuit 100. The other end is coupled to the other output end of the full bridge switching circuit 100 via the first coil.
橋式整流電路120具有二輸入端以與變壓器單元110之所述第二線圈耦接。 The bridge rectifier circuit 120 has two inputs for coupling to the second coil of the transformer unit 110.
電感-電容濾波電路130係與該橋式整流電路120之二輸出端耦接以提供一輸出電壓VO及一輸出電流IO至一負載200。 The inductor-capacitor filter circuit 130 is coupled to the output terminals of the bridge rectifier circuit 120 to provide an output voltage V O and an output current I O to a load 200.
回授電路140係用以依該輸出電壓VO及該輸出電流IO分別產生一電壓回授信號SV及一電流回授信號SI。 The feedback circuit 140 is configured to generate a voltage feedback signal S V and a current feedback signal S I according to the output voltage V O and the output current I O , respectively.
控制單元150儲存有一韌體程式，係用以執行一控制信號產生程序，包含一類比至數位轉換單元151、一濾波運算單元152、一比例-積分-微分運算單元153、一脈衝寬度調變運算單元154、以及一驅動單元155。 The control unit 150 stores a firmware program for executing a control signal generating program, including an analog-to-digital conversion unit 151, a filtering operation unit 152, a proportional-integral-derivative operation unit 153, and a pulse width modulation operation. Unit 154, and a drive unit 155.
類比至數位轉換單元151係用以對電壓回授信號SV或及電流回授信號SI執行一類比至數位轉換運算；濾波運算單元152係用以對類比至數位轉換單元151之輸出執行一濾波運算；比例-積分-微分運算單元153係用以調整該第一控制信號S1和該第三控制信號S3間之一相移角以驅動該全橋式開關電路100；脈衝寬度調變運算單元154係用以提供該第一控制信號、該第二控制信號、該第三控制信號、以及該第四控制信號，其中，該控制信號產生程序係依該電壓回授信號SV調整該相移角，且該控制信號產生程序係在該電流回授信號SI小於一第一預設值時提供一突衝模式，在該電流回授信號SI大於該第一預設值且小於一第二預設值時提供一脈波寬度調變模式，以及在該電流回授信號SI大於該第二預設值時提供一變動盲時相移模式。 The analog-to-digital conversion unit 151 is configured to perform an analog-to-digital conversion operation on the voltage feedback signal S V or the current feedback signal S I ; the filtering operation unit 152 is configured to perform an analog to digital output of the digital conversion unit 151 a filter operation; the proportional-integral-differential operation unit 153 is configured to adjust a phase shift angle between the first control signal S 1 and the third control signal S 3 to drive the full bridge switch circuit 100; pulse width modulation The operation unit 154 is configured to provide the first control signal, the second control signal, the third control signal, and the fourth control signal, wherein the control signal generating program adjusts the signal according to the voltage feedback signal S V a phase shift angle, and the control signal generating program provides a burst mode when the current feedback signal S I is less than a first preset value, wherein the current feedback signal S I is greater than the first preset value and less than A pulse width modulation mode is provided for a second preset value, and a variable blind phase shift mode is provided when the current feedback signal S I is greater than the second predetermined value.
依此，本發明即可根據負載大小切換不同的工作模式：在空載時提供在一突衝模式；輕載時提供一脈波寬度調變模式；以及重載時則提供一變動盲時相移模式，從而提升電源轉換效率。 Accordingly, the present invention can switch between different operating modes according to the load size: providing a burst mode when no load is provided; providing a pulse width modulation mode when light load; and providing a variable blind phase when overloading Move mode to improve power conversion efficiency.
以下將對本發明的原理做詳細說明。 The principle of the invention will be described in detail below.
I.電路硬體架構與操作分析 I. Circuit hardware architecture and operational analysis
1.1功率級電路 1.1 power stage circuit
本發明所採之全橋轉換器電路架構如圖3所示，初級側由四個功率開關組成全橋架構，功率開關旁存在寄生電容與本體二極體(Body Diode)，其中S 1與S 2及S 3與S 4不可同時作用，並在初級側加入諧振電感L r ，使初級側功率開關容易達成零電壓切換，主變壓器則負責初級與次級側之電壓轉換與能量傳遞。電路次級側採用全橋整流電路，其中D A 、D B 、D C 、D D 為蕭特基整流二極體，L O 為輸出濾波電感，C o 為輸出濾波電容，主變壓器將能量傳遞到次級側之電壓進行整流之後，再經由L o 電感與C o 電容進行濾波得到一穩定的直流電壓。 The full-bridge converter circuit architecture adopted in the present invention is shown in FIG. 3. The primary side is composed of four power switches and constitutes a full-bridge architecture. Parasitic capacitance and body diodes (Sody Diode) are present next to the power switch, where S 1 and S 2 and S 3 and S 4 can not work at the same time, and the resonant inductor L r is added on the primary side, so that the primary side power switch can easily achieve zero voltage switching, and the main transformer is responsible for voltage conversion and energy transfer of the primary and secondary sides. The secondary side of the circuit uses a full-bridge rectifier circuit, where D A , D B , D C , D D are Schottky rectifier diodes, L O is the output filter inductor, C o is the output filter capacitor, and the main transformer transfers energy. After the voltage on the secondary side is rectified, it is filtered by the L o inductor and the C o capacitor to obtain a stable DC voltage.
1.2控制方法 1.2 control method
1.2.1 PWM控制法 1.2.1 PWM control method
圖4繪示本發明所採之一PWM控制法之波形圖，其中S1與S2及S3與S4之間存在一個盲時時間，以避免其同時作用，且責任週期不得大於50%。 4 is a waveform diagram of a PWM control method taken by the present invention, wherein there is a blind time between S 1 and S 2 and S 3 and S 4 to avoid simultaneous action, and the duty cycle must not exceed 50%. .
1.2.2 相移式控制法 1.2.2 Phase shift control method
圖5繪示本發明所採之一相移式控制法之波形圖。相移式控制法主要由一般傳統全橋轉換器演變而成，其控制方式採固定頻率及50%的固定責任週期，兩臂的訊號錯開一個α相位，並利用此相位來控制初級側傳送能量的時間。即在S 1、S 4與S 2、S 3的作用時間重疊處才有輸入電壓落於變壓器上，且S 1、S 2與S 3、S 4間為互補關係加上一段盲時時間。透過S 1、S 2與S 3、S 4間的盲時時間，及經由變壓器的漏感及諧振電感和功率開關上的雜散電容所形成的諧振，功率開關乃可以零電壓切換。此控制的優點不但可以降低功率開關切換時的應力，同時也可在不需要外加緩振電路(Snubber)的情況下降低切換損失及電磁干擾。 FIG. 5 is a waveform diagram of a phase shift control method adopted by the present invention. The phase shift control method is mainly developed from a general traditional full-bridge converter. The control method adopts a fixed frequency and a fixed duty cycle of 50%. The signals of the two arms are staggered by an α phase, and the phase is used to control the primary side to transmit energy. time. That is, when the interaction time of S 1 , S 4 and S 2 , S 3 overlaps, the input voltage falls on the transformer, and S 1 , S 2 and S 3 , S 4 have a complementary relationship plus a blind time. The power switch can be switched by zero voltage through the blind time between S 1 , S 2 and S 3 , S 4 , and the resonance formed by the leakage inductance of the transformer and the stray capacitance of the resonant inductor and the power switch. The advantages of this control not only reduce the stress during power switch switching, but also reduce switching losses and electromagnetic interference without the need for an external damping circuit (Snubber).
1.3全橋相移式轉換器諧振電流推導 1.3 Full-bridge phase-shift converter resonant current derivation
相移式全橋轉換器具有固定的切換頻率與責任週期，其兩臂的控制訊號錯開一個相位角，無論操作在哪一個階段，皆會有開關處於導通狀態，且通過諧振電感上的諧振電流i p 會有連續性。圖6所示為相移式全橋轉換器初級與次級側之電流、電壓理論波形。 The phase-shifted full-bridge converter has a fixed switching frequency and duty cycle, and the control signals of the two arms are staggered by a phase angle. At any stage of operation, the switch is in an on state and the resonant current is passed through the resonant inductor. i p will have continuity. Figure 6 shows the theoretical waveforms of current and voltage on the primary and secondary sides of a phase-shifted full-bridge converter.
相移式全橋轉換器的電壓增益為：
其中n為變壓器匝數比(Ns/Np)，D eff 為有效責任週期。 Where n is the transformer turns ratio (N s /N p ) and D eff is the effective duty cycle.
D=△D+D eff (2) D = △ D + D eff (2)
其中D為責任週期，而△D則為次級側導通率損失，由圖6可得到次級側導通率損失△D為：
由圖6可推得初級側的電流I 1為I o 峰值再減去輸出電感電流的下降斜率映射回變壓器初級側的量，如方程式(4)所示：
其中△I o 為輸出電流之漣波電流，T s 為切換週期，V o 為輸出電壓。 Where Δ I o is the chopping current of the output current, T s is the switching period, and V o is the output voltage.
由圖6可知初級側的電流I 2為I o 最小值映射回變壓器初級側之值，如方程式(5)所示：
由圖6可以看到，當諧振電流從I 2點到I 3點，此階段S 1與S 4導通，故此時變壓器的次級側上的電壓為nV in ，而輸出電壓為V o ，此時電感電壓可表示為：
由方程式(6)，當電感電壓為定值時，此時電流斜率為一條斜直線，故I 3可以表示為：
電流I 3點到I 4點間，此時電路操作於領先臂諧振區間，等效電路如圖7所示。此時若忽略電路上的電阻則可等效視為一LC共振，則此階段i p 可由方程式(8)表示為：
其中L r 為初級側諧振電感，V in 為輸入電壓，C r1為S 1與S 2上的雜散電容與變壓器初級側間的電容C th 所組成，可表示為：
而諧振頻率可以表示為
將初始值V o 代入雜散電容上的初始電壓V in ，而初始電流I 0為I 3點電流，則可得到t 3到t 4期間之電流如方程式(11)所示。 Substituting the initial value V o into the initial voltage V in the stray capacitance, and the initial current I 0 is the I 3 point current, the current during t 3 to t 4 can be obtained as shown in the equation (11).
將方程式(7)代入，方程式(11)可化簡為：
由方程式(12)可推導得I 4點電流為：
I 5電流實際為I 1反向，故可得
電流I 5點到I 6點間，此時電路操作於落後臂諧振區間，等效電路如圖8所示，此時忽略電路上的阻抗則可等效視為一LC共振，則此階段的I p 可由方程式(15)表示為：
L r 為初級側諧振電感，L o 為輸出電感，V in 為輸入電壓，C r2為S3與S 4上的雜散電容與變壓器初級側間的電容C th 所組成，可表示為：
而諧振頻率可以表示為
將初始值V 0代入雜散電容上的初始電壓V in ，而初始電流I 0為I 5點電流，則可得到方程式(18)：
將方程式(14)的I 5代入，方程式(18)可化簡為：
由方程式(19)推導可得I 6點電流：
I 7電流實際為I 2反向，故可得
相移式全橋轉換器零電壓切換是由開關上的雜散電容與變壓器上的漏感、初級側諧振電感與輸出電感映射回初級側進行共振，其初級側領先臂諧振電流I 3與落後臂諧振電流I 5的大小會影響零電壓切換，因此相移式全橋轉 換器在輕載時，往往會因為諧振電流太小而無法達成零電壓切換，故相移式全橋轉換器於輕載運轉效率較差。 Phase-shifted full-bridge converter zero-voltage switching is caused by the stray capacitance on the switch and the leakage inductance on the transformer, the primary side resonant inductor and the output inductor are mapped back to the primary side for resonance, and the primary side leading arm resonant current I 3 and backward The magnitude of the arm resonant current I 5 affects the zero voltage switching. Therefore, when the phase shifting full-bridge converter is lightly loaded, the zero-voltage switching cannot be achieved because the resonant current is too small, so the phase-shifting full-bridge converter is light. The operation efficiency is poor.
Ⅱ.本案所提的提升效率的控制方法II. Control method for improving efficiency in this case
相移式全橋轉換器的開關元件具有零電壓切換的特性，其主要是藉由變壓器上的漏感及初級側的諧振電感與映射回初級側的輸出電感來達成領先臂和落後臂的零電壓切換，所以相移式全橋轉換器在輕載時，會因為諧振電流太小而無法達成零電壓切換，導致輕載運轉效率較差。此外初級側循環能量損失、次級側的導通率損失、振鈴現象等，這些皆是相移式全橋轉換器所必須改善的問題。一般相移式全橋轉換器效率提升主要可分成兩個方向：其一是針對電路架構進行改變或增加額外電路，其二則是改變輕載時之控制策略，以達成輕載效率提升。因此本案提出效率提升的控制方法及改良型的電路。 The switching element of the phase-shifted full-bridge converter has zero-voltage switching characteristics, which mainly achieves the leading and trailing arm zeros by the leakage inductance on the transformer and the resonant inductance on the primary side and the output inductance mapped back to the primary side. Voltage switching, so the phase-shifting full-bridge converter will not achieve zero-voltage switching because the resonant current is too small at light load, resulting in poor light-load operation. In addition, primary side cycle energy loss, secondary side conduction loss, ringing phenomenon, etc., are all problems that must be improved by phase-shifted full-bridge converters. The general phase-shift full-bridge converter efficiency improvement can be divided into two main directions: one is to change or add additional circuits for the circuit architecture, and the other is to change the control strategy at light load to achieve light load efficiency improvement. Therefore, this case proposes a control method for improving efficiency and an improved circuit.
2.1有效責任週期推導2.1 Derivation of effective responsibility cycle
將(4)式與(5)式代入(3)式可得到：
將(22)式代入(2)式可得到有效導通率為：
通常輸出電感L o 都遠大於變壓器的漏感L r ，所以(23)式化簡可表示為：
由(24)式可得知，當L r 越大時D eff 也越小，所以增加諧振電感後△D會越來越大，使次級側導通率損失增加，因此需要更多變壓器匝數比才可讓輸出電壓穩定。 It can be known from equation (24) that the smaller the L r is, the smaller the D eff is. Therefore, after increasing the resonant inductance, the Δ D will become larger and larger, and the secondary side conduction loss will increase, so more transformer turns are needed. The ratio allows the output voltage to stabilize.
2.2領先臂達成ZVS所需之盲時時間2.2 Leading arm to achieve the blind time required for ZVS
相移式全橋轉換器領先臂藉由開關上的雜散電容與變壓器上的漏感、初級側諧振電感與耦合到初級側的輸出電感L o 進行共振，將領先臂的雜散電容放電至零電壓，所需的時間為：
其中I p_lead 為領先臂初級側諧振電流，V in 為輸入電壓，C r2為S 3與S 4上的雜散電容與變壓器初級側間的電容C th 所組成，可表示為：
△t lead 為領先臂零電壓切換所需之盲時時間，透過方程式(7)可計算得知領先臂諧振時之電流大小，因此將I 3代入(26)之後可得領先臂達成ZVS所需盲時為：
2.3落後臂達成ZVS所需之盲時時間2.3 The blind time required for the backward arm to reach ZVS
落後臂則藉由開關上的雜散電容與變壓器上的漏感、初級側諧振電感進行共振，其零電壓導通條件可表示為：
其中I p_lag 為落後臂初級側諧振電流，C r1為S 1與S 2上的雜散電容與變壓器初級側間的電容C th 所組成，可表示為：
△t lag 為落後臂零電壓切換所需之盲時時間，透過方程式(14)可計算得知落後臂諧振時之電流大小，因此將I 5代入(30)之後可得落後臂達成ZVS所需盲時為：
2.4本案之全橋轉換器控制方式2.4 The full bridge converter control method of this case
本案將全橋轉換器操作在最佳效率點，根據本案所設計之轉換器規格，其在輸出電流0.5A以前使用突衝模式，輸出電流0.5-2.5A之間使用傳統全橋模式控制，而輸出電流2.5A之後使用相移式全橋模式控制。其中相移式全橋模式控制之採用可變盲時其原理如下所述：由方程式(7)、(14)可得知I 3與I 5的電流方程式，由圖6可知I 3為領先臂、I 5為落後臂電流，再將I 3、I 5代入方程式(26)、(30)可得知領先臂與落後臂零電壓切換所需時間，而其中最大盲時時間設定為四分之一的C r 及L r 的諧振時間為320ns，其最小盲時時間為150ns，其為防止功率元件同時導通所需之時間，並將所計算的△t lead 、△t lag 加上10ns為功率開關之上升時間，並建表將其值寫入處理器中，藉由輸出電流判斷△t lead 、△t lag 以達到可變盲時之效果，可變盲時之值與輸出電流之對照如圖9所示。 In this case, the full-bridge converter operates at the optimum efficiency point. According to the converter specification designed in this case, it uses the overshoot mode before the output current is 0.5A, and the output current is between 0.5-2.5A using the traditional full-bridge mode control. Phase-shift full-bridge mode control is used after the output current is 2.5A. The principle of phase shifting full-bridge mode control using variable blindness is as follows: Equations (7) and (14) can be used to find the current equations of I 3 and I 5 , and Figure 6 shows that I 3 is the leading arm. I 5 is the backward arm current, and then I 3 and I 5 are substituted into equations (26) and (30) to know the time required for the leading arm and the trailing arm to switch between zero voltages, and the maximum blind time is set to four. The resonance time of C r and L r is 320 ns, and the minimum blind time is 150 ns, which is the time required to prevent the power components from being simultaneously turned on, and the calculated Δ t lead , Δ t lag plus 10 ns is the power. the rise time of the switch, and the construction of the table to write the value to the processor, the output current is determined by △ t lead, △ t lag to achieve the effect of a variable dead time, when the control value of the output current of the variable such as blindness and Figure 9 shows.
2.5控制系統和韌體程式2.5 control system and firmware program
為了達成數位化之設計，本案使用Microchip公司所推出的dsPIC33FJ16GS502作為控制核心以實現相移式全橋轉換器之控制。將輸出電壓取樣資訊送至微處理器，再經由微處理器內部類比對數位轉換器(Analog-to-Digital Converter,ADC)轉成數位資料，接著將轉換後的輸出資料經過數位濾波器濾波，同時將濾波結果透過數位比例、積分、微分(Proportional、Integrating、Differentiation,PID)補償器運算，依據PID補償器產生之運算結果輸出適當之相位移，再送入PWM模組以產生控制訊號來驅動功率開關，藉由此方式來達到相移式全橋轉換器多模式數位化控制。 In order to achieve the digital design, the case uses Microchip's dsPIC33FJ16GS502 as the control core to realize the control of the phase-shifted full-bridge converter. The output voltage sampling information is sent to the microprocessor, and then converted into digital data by an internal analog-to-digital converter (ADC) of the microprocessor, and then the converted output data is filtered by a digital filter. At the same time, the filtering result is calculated by the digital proportional, integral, differential (Proportional, Integration, Differentiation, PID) compensator, and the appropriate phase shift is output according to the operation result generated by the PID compensator, and then sent to the PWM module to generate a control signal to drive the power. Switch, in this way to achieve phase shift full-bridge converter multi-mode digital control.
韌體程式分為主程式及類比對數位轉換中斷副程式兩部份。主程式負責對所需的全域變數(Global Variable)與區域變數(Local Variable)作宣告，先設定變數名稱、暫存器初始化、暫存器初始值設定、輸出輸入埠設定、模組(PWM、ADC、TIMER等)致能及中斷向量設定，之後進入無窮迴圈等待中斷向量旗標發生。ADC中斷副程式流程圖如圖10(a)、(b)所示，當ADC中斷一旦觸發將會進入ADC中斷副程式，執行ADC轉換、有限脈衝(FIR)濾波以及PID回授補償達成相移控制，程式的最後將會清除ADC中斷旗標，結束ADC中斷程式並進入無窮迴圈等待下一個ADC中斷。ADC中斷又可細分取樣濾波及增量型PID計算兩段。 The firmware program is divided into two parts: the main program and the analog-to-digital conversion interrupt subroutine. The main program is responsible for declaring the required Global Variable and Local Variable. First, set the variable name, register initialization, register initial value setting, output input setting, module (PWM, ADC, TIMER, etc. enable and interrupt vector settings, then enter the infinite loop and wait for the interrupt vector flag to occur. The ADC interrupt subroutine flow chart is shown in Figure 10(a) and (b). When the ADC interrupt is triggered, it will enter the ADC interrupt subroutine, perform ADC conversion, finite pulse (FIR) filtering and PID feedback compensation to achieve phase shift. Control, the end of the program will clear the ADC interrupt flag, end the ADC interrupt program and enter the infinite loop to wait for the next ADC interrupt. The ADC interrupt can subdivide the sampling filter and the incremental PID calculation.
2.6 PID控制器2.6 PID controller
PID控制器可表示如(33)式所示，其中u(t)表示控制器之輸出、e(t)表示輸入之誤差量、K P 、K I 、K D 分別表示為比例增益、積分增益和微分增益。在數位PID控制器方面，依據系統的誤差量透過比例、積分及微分之線性組合構成的控制量對受控體進行控制。PID控制器有結構簡單、調整方便及穩定性佳等優點，故常見於各種應用場合。本案使用微處理器實現PID控制，不單省去硬體上的元件成本與功耗，最大優點是令PID控制可以更加靈活具有彈性。圖11為PID控制原理方塊圖，根據命令值x(t)減去輸出回授量y(t)後得到一誤差量e(t)，再經過PID控制器運算出新的控制量u(t)，經由新的控制量u(t)對受控體進行調整，使受控體達到穩定。 The PID controller can be expressed as shown in equation (33), where u ( t ) represents the output of the controller, e ( t ) represents the error amount of the input, K P , K I , K D are expressed as proportional gain, integral gain, respectively. And differential gain. In the case of a digital PID controller, the controlled body is controlled by a control amount composed of a linear combination of proportional, integral, and derivative according to the error amount of the system. The PID controller has the advantages of simple structure, convenient adjustment and good stability, so it is common in various applications. In this case, the microprocessor is used to implement PID control, which not only saves the component cost and power consumption on the hardware, but also has the greatest advantage that the PID control can be more flexible and flexible. Figure 11 is a block diagram of the PID control principle. After subtracting the output feedback amount y ( t ) from the command value x ( t ), an error amount e ( t ) is obtained, and then a new control amount u ( t ) is calculated by the PID controller. ), the controlled body is adjusted via a new control quantity u ( t ) to stabilize the controlled body.
數位控制系統是以固定間隔的離散時間來處理輸入與輸出信號，根據取樣點與輸入命令之誤差量計算輸出控制量，因此(33)式之連續型PID控制演算法無法直接使用，需要採用離散化的方法針對數位取樣值進行計算。離散型PID表示式如(34)式所示，其中e(n)為目前系統誤差量、e(n-1)為系統前一次誤差量、T為取樣週期。 The digital control system processes the input and output signals at discrete intervals of fixed interval, and calculates the output control amount according to the error amount between the sampling point and the input command. Therefore, the continuous PID control algorithm of (33) cannot be directly used, and discrete The method is calculated for digital sample values. The discrete PID expression is as shown in equation (34), where e ( n ) is the current systematic error amount, e ( n -1) is the previous error amount of the system, and T is the sampling period.
若以數位微處理器實現(34)式之數位PID控制時，因其含有積分項，故需要考慮到積分飽和問題，當系統持續存在某個固定方向之誤差時，積分項會持續累加達到累加器所能表示之最大值，此時積分量可能早就超過開關可調相位移量的上下限值。因此在考量微處理機記憶體寬度所能表示的數值範圍是有限的情況下，同時為了降低微處理機的運算量及提升運算效能，本案採用增量型PID控制方法。增量型PID的輸出只針對現在、前一次與前兩次的誤差有關，因此不會有積分飽和的問題。增量型PID的表示式可經由式(35)推導出，由式(35)可知第n-1次取樣時間的取樣值為
控制增量△u(n)，其表示式如下：△u(n)=u(n)-u(n-1) (36) The control increment Δ u ( n ) is expressed as follows: Δ u ( n )= u ( n )- u ( n -1) (36)
將(34)式與(35)式代入式(36)可整理如下所式△u(n)=K P [e(n)-e(n-1)]+K I e(n)+K D [e(n)-2e(n-1)+e(n-2)] (37) Substituting equations (34) and (35) into equation (36) can be organized as follows: Δ u ( n )= K P [ e ( n )- e ( n -1)]+ K I e ( n )+ K D [ e ( n )-2 e ( n -1)+ e ( n -2)] (37)
(37)式可簡化為△u(n)=K P A+K IB+K D C，其中：A=e(n)-e(n-1)、B=e(n)及C=e(n)-2e(n-1)+e(n-2)。 Equation (37) can be simplified as Δ u ( n )= K P A+ K I B+ K D C, where: A= e ( n )- e ( n -1), B= e ( n ), and C= e ( n ) - 2 e ( n -1) + e ( n -2).
增量型PID程式流程如圖12所示，其係先將輸出命令值與FIR濾波器輸出取樣值相減以得誤差值e(n)=ERROR0，再與前一次的誤差值e(n-1)=ERROR1及前兩次的誤差值e(n-2)=ERROR2分別運算以得A=ERROR0-ERROR1、B=ERROR0、C=ERROR0-2*ERROR1+ERROR2，依序乘上K P 、K I、K D 後相加，即得到輸出變動量△u，其PID輸出結果PID out 等於△u，接著與原相位角度PHASE相加。若輸出結果小於最小相位角度PHASEmin或大於最大相位角度PHASEmax，則輸出結果分別等於最小相位角度PHASEmin或最大相位角度PHASEmax，最後將其輸出結果存於PWM模組之PHASE暫存器中，以達到穩定輸出電壓之目的。 The incremental PID program flow is shown in Figure 12, which first subtracts the output command value from the FIR filter output sample value to obtain the error value e ( n ) = ERROR 0 , and then the previous error value e ( n -1)=ERROR 1 and the first two error values e ( n -2)=ERROR 2 are calculated separately to get A=ERROR 0 -ERROR 1 , B=ERROR 0 , C=ERROR 0 -2*ERROR 1 +ERROR 2 , sequentially multiplying K P , K I , K D and then adding, that is, the output variation Δ u is obtained, and the PID output result PID out is equal to Δ u , and then added to the original phase angle PHASE. If the output result is less than the minimum phase angle PHASE min or greater than the maximum phase angle PHASE max , the output result is equal to the minimum phase angle PHASE min or the maximum phase angle PHASE max , respectively, and finally the output result is stored in the PHASE register of the PWM module. To achieve a stable output voltage.
Ⅲ.實驗結果III. Experimental results
本節將經由實驗結果證明所提出之多模式控制相移式全橋轉換器硬體架構與數位化控制方式之可行性與正確性，驗證項目包含轉換器操作於 不同之控制模式以及盲時時間控制策略之效率比較及數位相移控制方法等，最後將實際量測所得之實驗波形及數據加以說明分析。實驗的電路規格如下：輸入電壓(V in )為360Vdc。 In this section, the experimental results demonstrate the feasibility and correctness of the proposed multi-mode control phase-shifting full-bridge converter hardware architecture and digital control. The verification project includes converter operation in different control modes and blind time control. The efficiency comparison of the strategy and the digital phase shift control method, etc., finally analyze and analyze the experimental waveforms and data obtained from the actual measurement. The experimental circuit specifications are as follows: The input voltage ( V in ) is 360V dc .
輸出電壓(V out )為48Vdc。 The output voltage ( V out ) is 48V dc .
輸出電流(I out )為1A~10A。 The output current ( I out ) is 1A~10A.
輸出功率(P out )為480W。 The output power ( P out ) is 480W.
切換頻率(F s )為75kHz。 The switching frequency ( F s ) is 75 kHz.
滿載有效工作週期(D eff )為0.7。 The full load effective duty cycle ( D eff ) is 0.7.
變壓器繞組圈比(N p ：N s )為22：4。 The transformer winding ratio ( N p : N s ) is 22:4.
諧振電感(L r )為30μH。 The resonant inductance ( L r ) is 30 μH.
初級側功率開關(S 1~S 4)的型號為IPP65R110CFD。 The primary side power switch ( S 1 ~ S 4 ) is model IPP65R110CFD.
輸出電感(L o )為76μH。 The output inductance ( L o ) is 76μH.
次級側整流二極體(D A ~D D )的型號為STTH6002C。 The model of the secondary side rectifying diode ( D A ~ D D ) is STTH6002C.
圖13所示為本發明所量到之功率開關控制訊號之二波形圖，圖中V gs1、V gs2、V gs3、V gs4分別是用來驅動初級側的四個功率開關，其間具有一個盲時時間317ns，以防止領先臂之功率開關及落後臂之功率開關同時導通進而造成功率元件的損壞。 Figure 13 is a waveform diagram of the power switch control signal of the present invention. In the figure, V gs 1 , V gs 2 , V gs 3 , and V gs 4 are respectively used to drive the four power switches on the primary side. There is a blind time of 317ns in between to prevent the power switch of the leading arm and the power switch of the trailing arm from being turned on at the same time, thereby causing damage to the power component.
圖14為本發明在輸入電壓360V、輸出電流1A時所量到之V gs3、V gs4及變壓器之電壓V p 和電流I p 的波形。 Figure 14 is a waveform of V gs 3 , V gs 4 and the voltages V p and I p of the transformer when the input voltage is 360V and the output current is 1A.
相移式全橋轉換器在輕載時，因諧振電流較低而無法達成零電壓切換，造成相移全橋轉換器在輕載時轉換效率欠佳。因此本發明在輸出電流小於0.5A時會啟動突衝模式藉以提高空載效率，如圖15所示。在輸出電流介於0.5-2.5A之間啟動傳統全橋模式而在2.5A之後則啟動相移式全橋轉換模式，而本發明在傳統全橋模式和相移式全橋轉換模式之間的模式轉換開關控制信號請參照圖16(a)及圖16(b)。 Phase-shifted full-bridge converters cannot achieve zero voltage switching due to low resonant current at light loads, resulting in poor conversion efficiency of phase-shifted full-bridge converters at light loads. Therefore, the present invention activates the kick mode when the output current is less than 0.5A, thereby improving the no-load efficiency, as shown in FIG. The conventional full-bridge mode is initiated between an output current of between 0.5 and 2.5 A and the phase-shifted full-bridge conversion mode is initiated after 2.5 A, while the present invention is between a conventional full-bridge mode and a phase-shifted full-bridge conversion mode. Refer to Fig. 16 (a) and Fig. 16 (b) for the mode changeover switch control signal.
圖17為本發明之全橋轉換器之多模式切換示意圖。如圖17所示，根據本案所設計之轉換器規格，在輸出電流0.5A之前為突衝模式，輸出電流介於 0.5-2.5A之間為傳統全橋模式控制，而在輸出電流2.5A之後則為相移式全橋模式。圖18所示為本發明的多模式控制與傳統PWM控制和固定盲時控制之全橋轉換效率比較圖。由圖18可看出本發明之多模式控制在所有負載範圍皆擁有最高的效率。 Figure 17 is a schematic diagram of multi-mode switching of the full bridge converter of the present invention. As shown in Figure 17, according to the converter specification designed in this case, the output current is between the output current of 0.5A and the output current is between The traditional full-bridge mode control between 0.5-2.5A and the phase-shifted full-bridge mode after the output current of 2.5A. Figure 18 is a diagram showing the comparison of the full-bridge conversion efficiency of the multi-mode control and the conventional PWM control and the fixed blind time control of the present invention. It can be seen from Figure 18 that the multi-mode control of the present invention has the highest efficiency across all load ranges.
本案所揭示者，乃較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。 The disclosure of the present invention is a preferred embodiment. Any change or modification of the present invention originating from the technical idea of the present invention and being easily inferred by those skilled in the art will not deviate from the scope of patent rights of the present invention.
綜上所陳，本案無論就目的、手段與功效，在在顯示其迥異於習知之技術特徵，且其首先發明合於實用，亦在在符合發明之專利要件，懇請 貴審查委員明察，並祈早日賜予專利，俾嘉惠社會，實感德便。 In summary, this case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first invention is practical and practical, and it is also in compliance with the patent requirements of the invention. I will be granted a patent at an early date.
100‧‧‧全橋式開關電路 100‧‧‧Full bridge switching circuit
110‧‧‧變壓器單元 110‧‧‧Transformer unit
120‧‧‧橋式整流電路 120‧‧‧Bridge rectifier circuit
130‧‧‧電感-電容濾波電路 130‧‧‧Inductance-capacitor filter circuit
140‧‧‧回授電路 140‧‧‧Responsive circuit
150‧‧‧控制單元 150‧‧‧Control unit
111‧‧‧諧振電感 111‧‧‧Resonant inductance
112‧‧‧變壓器 112‧‧‧Transformers
151‧‧‧類比至數位轉換單元 151‧‧‧ analog to digital conversion unit
152‧‧‧濾波運算單元 152‧‧‧Filtering unit
153‧‧‧比例-積分-微分運算單元 153‧‧‧Proportional-Integral-Derivative Unit
154‧‧‧脈衝寬度調變運算單元 154‧‧‧ pulse width modulation unit
155‧‧‧驅動單元 155‧‧‧ drive unit
200‧‧‧負載 200‧‧‧load
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| TW200516839A (en) * | 2005-01-28 | 2005-05-16 | Univ Chang Gung | Modified phase-shift-modulation technique applied in the design of DC-AC single-phase full-bridge inverter |
| TW201123699A (en) * | 2009-12-17 | 2011-07-01 | Univ Nat Taipei Technology | Phase-shift full-bridge power converting system and control method thereof. |
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| TW201123699A (en) * | 2009-12-17 | 2011-07-01 | Univ Nat Taipei Technology | Phase-shift full-bridge power converting system and control method thereof. |
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