TWI567941B - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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Description
本揭露係有關於一種半導體記憶裝置及其製造方法，且特別係有關於一種接觸窗及其製造方法。 The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and in particular to a contact window and a method of fabricating the same.
動態隨機存取記憶體(dynamic random access memory,DRAM)主要是由一個電容器和一個電晶體組成。隨著電子產品日漸小型化之趨勢，對於記憶體裝置亦有逐漸小型化的需求。 A dynamic random access memory (DRAM) is mainly composed of a capacitor and a transistor. With the trend toward miniaturization of electronic products, there is also a need for a miniaturization of memory devices.
對習知動態隨機存取記憶體而言，接觸窗的底部與主動區接觸的面積越大，重刷新時間(refresh time)越短，有利於提升裝置反應速度。然而，接觸窗底部與主動區接觸的面積越大，接觸窗頂部的間距就越小，如此一來將導致相鄰接觸窗的短路，將不利於裝置體積的小型化。因此，仍有需要對動態隨機存取記憶體進行改良，以使其具有更小的臨界尺寸及更快的反應速度。 For the conventional dynamic random access memory, the larger the area of the bottom of the contact window in contact with the active area, the shorter the refresh time, which is advantageous for increasing the reaction speed of the device. However, the larger the area of the bottom of the contact window in contact with the active area, the smaller the pitch of the top of the contact window, which will result in short circuit of adjacent contact windows, which will be disadvantageous for miniaturization of the device volume. Therefore, there is still a need to improve the dynamic random access memory to have a smaller critical size and a faster response speed.
本揭露之一實施例係提供一種半導體裝置，包括：半導體基板，其中此半導體基板上包括第一絕緣材料層及多條位元線位於第一絕緣材料層中，其中位元線彼此平行且沿著第一方向延伸；第二絕緣材料條狀結構橫跨上述位元線，形 成於第一絕緣材料層中且沿著垂直於第一方向的第二方向延伸；兩列接觸窗溝槽，分別形成於第二絕緣材料條狀結構兩側，其中接觸窗溝槽係垂直於上述位元線且被位元線分隔成為多個接觸窗，且其中接觸窗在第一方向上的兩側壁分別鄰接於第一絕緣材料層及第二絕緣材料條狀結構。 An embodiment of the present disclosure provides a semiconductor device including: a semiconductor substrate, wherein the semiconductor substrate includes a first insulating material layer and a plurality of bit lines in the first insulating material layer, wherein the bit lines are parallel to each other and along Extending in a first direction; a strip of second insulating material spans the bit line, Forming in the first insulating material layer and extending along a second direction perpendicular to the first direction; two rows of contact window trenches respectively formed on two sides of the second insulating material strip structure, wherein the contact window trench is perpendicular to The bit line is divided by the bit line into a plurality of contact windows, and wherein the two sidewalls of the contact window in the first direction are respectively adjacent to the first insulating material layer and the second insulating material strip structure.
本揭露之另一實施例係提供一種半導體裝置之形成方法，包括：提供半導體基板，其中半導體基板上包括第一絕緣材料層及多條位元線位於第一絕緣材料層中，其中位元線彼此平行且沿著第一方向延伸；沉積第二絕緣材料，以形成第二絕緣材料層於第一絕緣材料層上；形成犧牲層於第二絕緣材料層上；形成穿過上述犧牲層、第二絕緣材料層及第一絕緣材料層的溝槽，其中此溝槽沿著垂直於第一方向的第二方向延伸且橫跨上述位元線；沉積第二絕緣材料於溝槽中，以形成第二絕緣材料條狀結構於第一絕緣材料層中；進行蝕刻製程穿過第一絕緣材料層，以在上述第二絕緣材料條狀結構兩側分別形成一列接觸窗溝槽，其中接觸窗溝槽係垂直於上述位元線且被位元線分隔成為多個接觸窗；以及拓寬接觸窗溝槽底部的口徑，以使上述接觸窗在第一方向上的兩側壁分別鄰接於第一絕緣材料層及第二絕緣材料層。 Another embodiment of the present disclosure provides a method of forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate includes a first insulating material layer and a plurality of bit lines in the first insulating material layer, wherein the bit lines Parallel to each other and extending along the first direction; depositing a second insulating material to form a second insulating material layer on the first insulating material layer; forming a sacrificial layer on the second insulating material layer; forming through the sacrificial layer, a second insulating material layer and a trench of the first insulating material layer, wherein the trench extends in a second direction perpendicular to the first direction and spans the bit line; depositing a second insulating material in the trench to form a second insulating material strip structure is in the first insulating material layer; an etching process is performed through the first insulating material layer to form a row of contact window trenches on both sides of the second insulating material strip structure, wherein the contact window trench The slot is perpendicular to the bit line and separated by the bit line into a plurality of contact windows; and the aperture of the bottom of the contact window trench is widened so that the contact window is in the first direction Walls respectively adjacent to the first insulating material layer and the second layer of insulating material.
本揭露之又一實施例係提供一種半導體裝置，包括：基板，此基板包括至少兩條位元線，其中位元線彼此平行且沿著第一方向延伸；以及接觸窗，設置於上述兩條位元線之間，其中此接觸窗在該第一方向上的兩側壁係為不同材質的第一絕緣層及第二絕緣層，且其中第二絕緣層具有朝向該基板逐 漸縮窄的下部。 A further embodiment of the present disclosure provides a semiconductor device including: a substrate including at least two bit lines, wherein the bit lines are parallel to each other and extend along a first direction; and a contact window disposed on the two Between the bit lines, wherein the two sidewalls of the contact window in the first direction are a first insulating layer and a second insulating layer of different materials, and wherein the second insulating layer has a direction toward the substrate Shrink the narrow lower part.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，作詳細說明如下： The above and other objects, features, and advantages of the present invention will become more apparent and understood.
10‧‧‧第一方向 10‧‧‧First direction
20‧‧‧第二方向 20‧‧‧second direction
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
102‧‧‧基板 102‧‧‧Substrate
104‧‧‧接觸蝕刻停止層 104‧‧‧Contact etch stop layer
106‧‧‧第一絕緣材料層 106‧‧‧First insulating material layer
106a‧‧‧第一膜層 106a‧‧‧First film
106b‧‧‧第二膜層 106b‧‧‧Second film
106c‧‧‧第三膜層 106c‧‧‧ third film
108‧‧‧位元線 108‧‧‧ bit line
110‧‧‧絕緣襯層 110‧‧‧Insulation lining
111‧‧‧蓋層 111‧‧‧ cover
112‧‧‧第二絕緣材料層 112‧‧‧Second layer of insulating material
112F‧‧‧第二絕緣材料柵狀膜層 112F‧‧‧Second insulating material grid layer
112R‧‧‧第二絕緣材料條狀結構 112R‧‧‧Second insulation strip structure
112P‧‧‧突出部 112P‧‧‧Protruding
112a‧‧‧上部分 112a‧‧‧上上
112b‧‧‧下部分 112b‧‧‧下下
114‧‧‧犧牲層 114‧‧‧ Sacrifice layer
116‧‧‧碳化物層 116‧‧‧Carbide layer
118‧‧‧氮氧化矽層 118‧‧‧Nitrogen oxide layer
120‧‧‧圖案化光阻層 120‧‧‧ patterned photoresist layer
122‧‧‧溝槽圖案 122‧‧‧Slot pattern
124‧‧‧溝槽圖案 124‧‧‧ Groove pattern
126‧‧‧溝槽 126‧‧‧ trench
128‧‧‧第三絕緣材料層 128‧‧‧ Third insulating material layer
130‧‧‧罩幕層 130‧‧‧ Cover layer
135‧‧‧接觸窗溝槽 135‧‧‧Contact window trench
150‧‧‧接觸窗 150‧‧‧Contact window
150a‧‧‧第一側壁 150a‧‧‧first side wall
150b‧‧‧第二側壁 150b‧‧‧second side wall
第1圖為本揭露一些實施例之半導體裝置的上視示意圖。 FIG. 1 is a top plan view of a semiconductor device according to some embodiments of the present disclosure.
第2A圖至第2O圖為本揭露一些實施例之半導體裝置的製程剖面示意圖。 2A to 2O are schematic cross-sectional views showing a process of a semiconductor device according to some embodiments of the present disclosure.
第3A圖至第3K圖為本揭露一些實施例之半導體裝置的製程剖面示意圖。 3A to 3K are schematic cross-sectional views showing a process of a semiconductor device according to some embodiments of the present disclosure.
第4圖為本揭露一些實施例之半導體裝置的上視示意圖。 FIG. 4 is a top plan view of a semiconductor device according to some embodiments of the present disclosure.
為使本發明之上述和其他目的、特徵、優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。然而，任何所屬技術領域中具有通常知識者將會瞭解本發明中各種特徵結構僅用於說明，並未依照比例描繪。事實上，為了使說明更加清晰，可任意增減各種特徵結構的相對尺寸比例。在說明書全文及所有圖式中，相同的參考標號是指相同的特徵結構。 The above and other objects, features and advantages of the present invention will become more <RTIgt; However, it will be understood by those of ordinary skill in the art that the description In fact, in order to make the description clearer, the relative size ratio of various feature structures can be arbitrarily increased or decreased. Throughout the specification and in all figures, the same reference numerals refer to the same features.
本揭露提供一種半導體裝置及其製造方法，第1圖為本揭露一些實施例之半導體裝置100的上視示意圖。在一些實施例中，半導體裝置100可為記憶體裝置。在本實施例中，半導體裝置100為動態隨機存取記憶體，因此，在下文中半導體裝置100亦被稱為動態隨機存取記憶體100。 The present disclosure provides a semiconductor device and a method of fabricating the same. FIG. 1 is a top plan view of a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, semiconductor device 100 can be a memory device. In the present embodiment, the semiconductor device 100 is a dynamic random access memory. Therefore, the semiconductor device 100 is also referred to as a dynamic random access memory 100 hereinafter.
請參照第1圖，動態隨機存取記憶體100包括多條彼此平行且沿著第一方向10延伸的位元線108，以及多條彼此平行且沿著第二方向20延伸的接觸窗溝槽135，其中第一方向10垂直於第二方向20。如第1圖所示，接觸窗溝槽135橫跨位元線108且被位元線108分隔成多個接觸窗150。依據本揭露之一些實施例，動態隨機存取記憶體100可具有更小的臨界尺寸及更快的反應速度，此部分將於下文中詳細討論。 Referring to FIG. 1 , the DRAM 100 includes a plurality of bit lines 108 that are parallel to each other and extend along the first direction 10 , and a plurality of contact window trenches that are parallel to each other and extend along the second direction 20 . 135, wherein the first direction 10 is perpendicular to the second direction 20. As shown in FIG. 1, contact window trench 135 spans bit line 108 and is separated by bit line 108 into a plurality of contact windows 150. In accordance with some embodiments of the present disclosure, the dynamic random access memory 100 can have a smaller critical dimension and a faster response speed, as discussed in more detail below.
第2A圖至第2O圖與第3A圖至第3K圖為本揭露一些實施例之半導體裝置100的製程剖面示意圖。第2A圖至第2O圖係沿著第一方向10(即，第1圖的AA’剖線)所繪製；且第3A圖至第3K圖係沿著第二方向20(即，第1圖的BB’剖線)所繪製。 2A to 2O and 3A to 3K are schematic cross-sectional views showing a process of the semiconductor device 100 according to some embodiments of the present disclosure. 2A to 2O are drawn along the first direction 10 (ie, the AA' line of FIG. 1); and 3A to 3K are along the second direction 20 (ie, FIG. 1) The BB's line is drawn.
請參照第2A圖及第3A圖，提供基板102。基板102可由半導體材料所形成，因此亦可稱為半導體基板102。半導體基板102的材料可包括矽、砷化鎵、氮化鎵、矽化鍺、絕緣層上覆矽(silicon on insulator,SOI)、其他合適之材料或上述材料之組合。在一些實施例中，半導體基板102為矽基板。 Referring to FIGS. 2A and 3A, a substrate 102 is provided. The substrate 102 may be formed of a semiconductor material and thus may also be referred to as a semiconductor substrate 102. The material of the semiconductor substrate 102 may include germanium, gallium arsenide, gallium nitride, germanium germanium, silicon on insulator (SOI), other suitable materials, or a combination thereof. In some embodiments, the semiconductor substrate 102 is a germanium substrate.
仍請參照第2A圖及第3A圖，在半導體基板102上可具有接觸蝕刻停止層(contact etch stop layer,CESL)104及位於接觸蝕刻停止層104之上的第一絕緣材料層106。接觸蝕刻停止層104可包括氮化物、氮氧化物、其他合適的材料或上述材料之組合。在一些實施例中，接觸蝕刻停止層104可為氮化矽層，且可藉由化學氣相沉積(CVD)製程或其他合適的製程所形成。 Still referring to FIGS. 2A and 3A , the semiconductor substrate 102 may have a contact etch stop layer (CESL) 104 and a first insulating material layer 106 on the contact etch stop layer 104 . Contact etch stop layer 104 can include nitrides, oxynitrides, other suitable materials, or combinations of the foregoing. In some embodiments, the contact etch stop layer 104 can be a tantalum nitride layer and can be formed by a chemical vapor deposition (CVD) process or other suitable process.
第一絕緣材料層106可為單層結構或多層結構。此外，為了有利於後續形成接觸窗，第一絕緣材料層106可選用 與接觸蝕刻停止層104不同的第一絕緣材料。在一些實施例中，第一絕緣材料可包括硼磷矽玻璃(borophosphosilicate glass,BPSG)、磷矽玻璃(phosphosilicate glass,PSG)、旋塗玻璃(spin-on glass,SOG)、氧化物、低介電常數(low k)介電材料、其他合適的材料或上述材料之組合。在一些實施例中，第一絕緣材料層106為二氧化矽的單層結構，且可藉由合適的沉積製程所形成。在本實施例中，第一絕緣材料層106可包括由下而上依序堆疊的第一膜層106a、第二膜層106b及第三膜層106c，其中第一膜層106a、第二膜層106b及第三膜層106c分別包括由化學氣相沉積製程所形成的二氧化矽、旋塗玻璃及由化學氣相沉積製程所形成的二氧化矽。 The first insulating material layer 106 may be a single layer structure or a multilayer structure. In addition, in order to facilitate subsequent formation of the contact window, the first insulating material layer 106 can be selected. A first insulating material is different from the contact etch stop layer 104. In some embodiments, the first insulating material may include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG), oxide, low-medium. Electrical constant (low k) dielectric material, other suitable materials, or a combination of the above. In some embodiments, the first layer of insulating material 106 is a single layer structure of hafnium oxide and can be formed by a suitable deposition process. In this embodiment, the first insulating material layer 106 may include a first film layer 106a, a second film layer 106b, and a third film layer 106c which are sequentially stacked from bottom to top, wherein the first film layer 106a and the second film The layer 106b and the third film layer 106c respectively include cerium oxide formed by a chemical vapor deposition process, spin-on glass, and cerium oxide formed by a chemical vapor deposition process.
請參照第1圖及第3A圖，在第一絕緣材料層106中具有多條位元線結構。在本實施例中，第3A圖的第一絕緣材料層106相同於第2A圖的第一絕緣材料層106，係為三層結構，然而，為了簡化說明，第3A圖中僅標示106。如第3A圖所示，位元線結構可包括位元線108、位於位元線108側壁的絕緣襯層110、位於位元線108側壁的間隔物，以及位元線108上方的蓋層111。在一些實施例中，蓋層111及間隔物可包括與接觸蝕刻停止層104相同的材料，例如，氮化矽。如第1圖所示，基板102上可具有多條位元線108，位元線108彼此平行且沿著第一方向10延伸。 Referring to FIGS. 1 and 3A, the first insulating material layer 106 has a plurality of bit line structures. In the present embodiment, the first insulating material layer 106 of FIG. 3A is the same as the first insulating material layer 106 of FIG. 2A, and has a three-layer structure. However, for simplicity of explanation, only 106 is indicated in FIG. 3A. As shown in FIG. 3A, the bit line structure can include a bit line 108, an insulating liner 110 on the sidewall of the bit line 108, a spacer on the sidewall of the bit line 108, and a cap layer 111 over the bit line 108. . In some embodiments, the cap layer 111 and the spacers may comprise the same material as the contact etch stop layer 104, such as tantalum nitride. As shown in FIG. 1, the substrate 102 can have a plurality of bit lines 108 that are parallel to each other and extend along the first direction 10.
接著，請參照第2B圖及第3B圖，在第一絕緣材料層106之上依序形成第二絕緣材料層112、犧牲層114及蝕刻罩幕層。為了有利於後續形成接觸窗，第二絕緣材料層112可選 用與第一絕緣材料不同的第二絕緣材料。在一些實施例中，第二絕緣材料可包括氮化物、氮氧化物、其他合適的材料或上述材料之組合。在一些實施例中，第二絕緣材料相同於接觸蝕刻停止層104、蓋層111及間隔物的材料，例如，氮化矽。 Next, referring to FIGS. 2B and 3B, a second insulating material layer 112, a sacrificial layer 114, and an etching mask layer are sequentially formed on the first insulating material layer 106. In order to facilitate subsequent formation of the contact window, the second insulating material layer 112 is optional A second insulating material different from the first insulating material is used. In some embodiments, the second insulating material may comprise a nitride, an oxynitride, other suitable materials, or a combination of the foregoing. In some embodiments, the second insulating material is the same as the material contacting the etch stop layer 104, the cap layer 111, and the spacer, such as tantalum nitride.
為了有利於後續形成第二絕緣材料條狀結構112R，犧牲層114可選用與第二絕緣材料具有高蝕刻選擇比的材料。在第二絕緣材料層112為氮化物的實施例中，可選用氧化物作為犧牲層114。 In order to facilitate subsequent formation of the second insulating material strip structure 112R, the sacrificial layer 114 may select a material having a high etching selectivity ratio with the second insulating material. In embodiments where the second insulating material layer 112 is a nitride, an oxide may be selected as the sacrificial layer 114.
蝕刻罩幕層可為單層結構或多層結構。在一些實施例中，蝕刻罩幕層可為雙層結構，其包括碳化物層116及其上方的氮氧化矽層118。在本實施例中，碳化物層116為類鑽碳膜。在其他實施例中，碳化物層116可為碳化矽或其他碳化物。 The etch mask layer can be a single layer structure or a multilayer structure. In some embodiments, the etch mask layer can be a two-layer structure that includes a carbide layer 116 and a layer of yttrium oxynitride 118 thereon. In the present embodiment, the carbide layer 116 is a diamond-like carbon film. In other embodiments, the carbide layer 116 can be tantalum carbide or other carbides.
接著，形成圖案化光阻層120於蝕刻罩幕層之上。圖案化光阻層120在上視圖中具有多條溝槽圖案122，這些溝槽圖案122彼此平行且沿著垂直於第一方向10的第二方向20延伸。請參照第2B圖，在AA’剖線上可看出圖案化光阻層120具有多個溝槽圖案122，但在第3B圖中，由於BB’剖線是位於溝槽圖案122中，因此，在此位置的蝕刻罩幕層上沒有圖案化光阻層120。 Next, a patterned photoresist layer 120 is formed over the etch mask layer. The patterned photoresist layer 120 has a plurality of trench patterns 122 in a top view that are parallel to each other and extend along a second direction 20 that is perpendicular to the first direction 10. Referring to FIG. 2B, it can be seen that the patterned photoresist layer 120 has a plurality of trench patterns 122 on the AA' cross-section, but in FIG. 3B, since the BB' line is located in the trench pattern 122, There is no patterned photoresist layer 120 on the etch mask layer at this location.
請參照第2C圖，利用圖案化光阻層120為遮罩，進行第一蝕刻製程，以形成多條溝槽圖案124於碳化物層116及氮氧化矽層118中。另外，請參照第3C圖，由於沒有圖案化光阻層120在蝕刻罩幕層上，因此，碳化物層116及氮氧化矽層118在第一蝕刻製程中完全被移除。 Referring to FIG. 2C, a first etching process is performed using the patterned photoresist layer 120 as a mask to form a plurality of trench patterns 124 in the carbide layer 116 and the hafnium oxynitride layer 118. In addition, referring to FIG. 3C, since the patterned photoresist layer 120 is not on the etching mask layer, the carbide layer 116 and the hafnium oxynitride layer 118 are completely removed in the first etching process.
請參照第2D圖，利用碳化物層116及氮氧化矽層118為遮罩，繼續進行第一蝕刻製程，以形成多條溝槽126於犧牲層114中。當溝槽126形成於犧牲層114中之後，移除犧牲層114上的碳化物層116及氮氧化矽層118。第一蝕刻製程可包括乾式蝕刻或其他合適的製程。在一些實施例中，第一蝕刻製程為脈衝式反應性離子蝕刻(pulsed reactive ion etching)製程，並且利用氟取代的烴類分子(例如，C4F6、C5F8、C4F8、C3F8或其他類似之分子)作為蝕刻氣體。使用脈衝式反應性離子蝕刻製程的優點在於能夠蝕刻出具有較高深寬比的溝槽，因而有利於降低裝置的臨界尺寸。另外，請參照第3D圖，由於碳化物層116及氮氧化矽層118已完全被移除，因此犧牲層114也完全被第一蝕刻製程移除。 Referring to FIG. 2D, the first etching process is continued by using the carbide layer 116 and the yttrium oxynitride layer 118 as a mask to form a plurality of trenches 126 in the sacrificial layer 114. After the trenches 126 are formed in the sacrificial layer 114, the carbide layer 116 and the hafnium oxynitride layer 118 on the sacrificial layer 114 are removed. The first etch process can include dry etch or other suitable process. In some embodiments, the first etch process is a pulsed reactive ion etching process and utilizes fluorine-substituted hydrocarbon molecules (eg, C 4 F 6 , C 5 F 8 , C 4 F 8 , C 3 F 8 or other similar molecules) as an etching gas. The advantage of using a pulsed reactive ion etching process is the ability to etch trenches having a high aspect ratio, thereby facilitating a reduction in the critical dimensions of the device. In addition, referring to FIG. 3D, since the carbide layer 116 and the hafnium oxynitride layer 118 have been completely removed, the sacrificial layer 114 is also completely removed by the first etching process.
請參照第2E圖，利用犧牲層114為遮罩，繼續進行第一蝕刻製程，以使溝槽126穿過第二絕緣材料層112。應注意的是，為了有利於縮小裝置的臨界尺寸，溝槽126在犧牲層114中的兩側側壁必須儘可能垂直於半導體基板102的表面，此部分將於下文中詳細討論。 Referring to FIG. 2E, the sacrificial layer 114 is used as a mask, and the first etching process is continued to pass the trench 126 through the second insulating material layer 112. It should be noted that in order to facilitate shrinking the critical dimensions of the device, the sidewalls of the trenches 126 in both sides of the sacrificial layer 114 must be as perpendicular as possible to the surface of the semiconductor substrate 102, as will be discussed in detail below.
仍請參照第2E圖，當溝槽126穿過第二絕緣材料層112之後，接著進行第二蝕刻製程穿過第一絕緣材料層106，以加深溝槽126之深度。第二蝕刻製程可包括乾式蝕刻或其他合適的製程。在本實施例中，第二蝕刻製程與第一蝕刻製程相同，皆為脈衝式反應性離子蝕刻製程，並且可利用相同的氟取代的烴類分子作為蝕刻氣體。 Still referring to FIG. 2E, after the trench 126 passes through the second insulating material layer 112, a second etching process is then performed through the first insulating material layer 106 to deepen the depth of the trench 126. The second etch process can include dry etch or other suitable process. In this embodiment, the second etching process is the same as the first etching process, both of which are pulse-type reactive ion etching processes, and the same fluorine-substituted hydrocarbon molecules can be utilized as the etching gas.
另外，請參照第3E圖，在第一蝕刻製程完成之後， 第二絕緣材料層112已完全被移除，且在第二蝕刻製程完成之後，第一絕緣材料層106也完全被移除而暴露出位元線結構。應注意的是，在第3E圖中，為了避免殘留的第二絕緣材料層112導致第一絕緣材料層106殘留於位元線結構上，第一蝕刻製程須完全移除第二絕緣材料層112。再者，為了避免因移除位元線108側壁的間隔物及位元線108上方的蓋層111而使位元線結構受到損傷，第二蝕刻製程須對第一絕緣材料與蓋層111所使用的材料具有高蝕刻選擇比，也就是對第一絕緣材料的蝕刻速率大於對蓋層111的蝕刻速率。 In addition, please refer to FIG. 3E, after the first etching process is completed, The second insulating material layer 112 has been completely removed, and after the second etching process is completed, the first insulating material layer 106 is also completely removed to expose the bit line structure. It should be noted that in FIG. 3E, in order to prevent the residual second insulating material layer 112 from causing the first insulating material layer 106 to remain on the bit line structure, the first etching process must completely remove the second insulating material layer 112. . Moreover, in order to avoid damage to the bit line structure by removing the spacer on the sidewall of the bit line 108 and the cap layer 111 above the bit line 108, the second etching process must be performed on the first insulating material and the cap layer 111. The material used has a high etch selectivity ratio, that is, the etch rate for the first insulating material is greater than the etch rate for the cap layer 111.
如上文所述，當進行第一蝕刻製程時，提高蝕刻製程的偏壓以增加功率，同時提高氧氣流量以降低蝕刻氣體(即，上述氟取代的烴類分子)的濃度，藉此使蝕刻氣體的轟擊力道(bombardment)增強，並降低蝕刻製程對於氧化物與氮化物的選擇比。如此一來，能夠使犧牲層114中的溝槽126具有實質上垂直於基板102的側壁，並且能夠完全移除第3E圖中的第二絕緣材料層112。此處所述的「實質上垂直」係指溝槽126的側壁與基板102的上表面兩平面的夾角在85-95度的範圍之間。在一些實施例中，第一蝕刻製程對第一絕緣材料的蝕刻速率為R1，對第二絕緣材料的蝕刻速率為R2，且第一蝕刻製程具有蝕刻選擇比R1/R2為0.5-5。在本實施例中，第一蝕刻製程的蝕刻選擇比R1/R2為3~10。 As described above, when the first etching process is performed, the bias of the etching process is increased to increase the power, and the oxygen flow rate is increased to lower the concentration of the etching gas (ie, the fluorine-substituted hydrocarbon molecule), thereby making the etching gas The bombardment is enhanced and the etching process is selected for oxide to nitride selectivity. As such, the trench 126 in the sacrificial layer 114 can be made to be substantially perpendicular to the sidewall of the substrate 102, and the second insulating material layer 112 in FIG. 3E can be completely removed. As used herein, "substantially perpendicular" means that the angle between the sidewalls of the trench 126 and the upper surface of the substrate 102 is between 85-95 degrees. In some embodiments, the first etch process has an etch rate of R1 for the first insulating material, an etch rate for the second insulating material of R2, and the first etch process has an etch selectivity ratio R1/R2 of 0.5-5. In this embodiment, the etching selectivity ratio R1/R2 of the first etching process is 3-10.
在溝槽126的深度超過第二絕緣材料層112，且第3E圖中的第二絕緣材料層112完全被移除之後，即可進行第二蝕刻製程。此時，可降低蝕刻製程的偏壓以降低功率，並降低 氧氣流量以提升蝕刻氣體(即，上述氟取代的烴類分子)的濃度，藉此使蝕刻氣體的轟擊力道減弱，並提高蝕刻製程對於氧化物與氮化物的選擇比。如此一來，能夠使溝槽126的側壁具有朝向半導體基板102逐漸縮窄的下部分，並且能夠在不損傷位元線結構的前提下完全移除第3E圖中的第一絕緣材料層106。在一些實施例中，第二蝕刻製程對第一絕緣材料的蝕刻速率為R1，對第二絕緣材料的蝕刻速率為R2，且第二蝕刻製程具有蝕刻選擇比R1/R2為5-15。在本實施例中，第二蝕刻製程的蝕刻選擇比R1/R2為5~15。 After the depth of the trench 126 exceeds the second insulating material layer 112, and the second insulating material layer 112 in FIG. 3E is completely removed, a second etching process may be performed. At this time, the bias of the etching process can be lowered to reduce the power and reduce The oxygen flow rate increases the concentration of the etching gas (i.e., the fluorine-substituted hydrocarbon molecules described above), thereby weakening the bombardment force of the etching gas and increasing the selectivity of the etching process to the oxide to nitride. As a result, the sidewall of the trench 126 can have a lower portion that tapers toward the semiconductor substrate 102, and the first insulating material layer 106 in FIG. 3E can be completely removed without damaging the bit line structure. In some embodiments, the second etch process has an etch rate of R1 for the first insulating material, an etch rate of R2 for the second insulating material, and a second etch process with an etch selectivity ratio R1/R2 of 5-15. In this embodiment, the etching selectivity ratio R1/R2 of the second etching process is 5-15.
相較於使用相同參數條件的單一步驟蝕刻製程，本實施之第一蝕刻製程與第二蝕刻製程的優點在於可使溝槽126的側壁具有垂直的上部分及逐漸縮窄的下部分，如第2E圖所示。上述溝槽126之剖面輪廓在後續製程中可有利於後續接觸窗的形成，並且能夠提升裝置的反應速度。再者，相較於選用不同蝕刻方法及/或不同蝕刻氣體的蝕刻製程，本實施例之第一與第二蝕刻製程使用相同的蝕刻方法與蝕刻氣體，僅需藉由簡單調整蝕刻製程參數，即可得到所需的溝槽126之剖面輪廓並完全移除第3E圖中的第一絕緣材料層106及第二絕緣材料層112，因此可降低生產成本並簡化製程複雜度。 The first etching process and the second etching process of the present embodiment have an advantage in that the sidewall of the trench 126 has a vertical upper portion and a tapered lower portion, as compared to a single-step etching process using the same parameter conditions. Figure 2E shows. The cross-sectional profile of the trench 126 described above facilitates the formation of subsequent contact windows in subsequent processes and can increase the reaction speed of the device. Furthermore, the first etching process and the etching process of the first and second etching processes of the present embodiment use the same etching method and etching gas as compared with the etching process using different etching methods and/or different etching gases, only by simply adjusting the etching process parameters. The desired profile of the trench 126 is obtained and the first insulating material layer 106 and the second insulating material layer 112 in FIG. 3E are completely removed, thereby reducing production costs and simplifying process complexity.
請參照第2F圖，沉積第二絕緣材料於犧牲層114之上並填入溝槽126中，填入溝槽126中的第二絕緣材料與第二絕緣材料層112相連，因而形成第二絕緣材料柵狀膜層112F。另外，請參照第3F圖，在BB’剖線上第二絕緣材料沉積於位元線結構之上並覆蓋位元線結構。 Referring to FIG. 2F, a second insulating material is deposited on the sacrificial layer 114 and filled in the trench 126. The second insulating material filled in the trench 126 is connected to the second insulating material layer 112, thereby forming a second insulating layer. Material gate film layer 112F. In addition, referring to Figure 3F, a second insulating material is deposited over the bit line structure and over the bit line structure on the BB' line.
請參照第2G圖，利用化學機械研磨製程或回蝕刻移除位於犧牲層114上的第二絕緣材料，以暴露出犧牲層114的表面。 Referring to FIG. 2G, the second insulating material on the sacrificial layer 114 is removed by a chemical mechanical polishing process or etch back to expose the surface of the sacrificial layer 114.
請參照第2H圖，利用乾式或濕式蝕刻製程移除犧牲層114，以暴露出第二絕緣材料層112的上表面及第二絕緣材料柵狀膜層112F的多個突出部112P。另外，請參照第3G圖，當進行第2G圖及第2H圖的製程時，在BB’剖線上只有第二絕緣材料層112的厚度減少，其他元件並未受到影響。 Referring to FIG. 2H, the sacrificial layer 114 is removed by a dry or wet etching process to expose the upper surface of the second insulating material layer 112 and the plurality of protrusions 112P of the second insulating material gate film layer 112F. Further, referring to Fig. 3G, when the processes of the 2G and 2H are performed, only the thickness of the second insulating material layer 112 is reduced on the BB' line, and other elements are not affected.
請參照第2I圖，順應性地(conformably)沉積第三絕緣材料，以形成第三絕緣材料層128於第二絕緣材料柵狀膜層112F上。在後續的蝕刻製程中，第三絕緣材料與第二絕緣材料應具有高選擇比，以利於形成接觸窗溝槽。在本實施例中，第三絕緣材料可包括氧化物。 Referring to FIG. 2I, a third insulating material is conformally deposited to form a third insulating material layer 128 on the second insulating material gate film layer 112F. In the subsequent etching process, the third insulating material and the second insulating material should have a high selection ratio to facilitate the formation of the contact window trench. In this embodiment, the third insulating material may include an oxide.
請參照第2J圖，沉積罩幕層130於第三絕緣材料層128上。接著，以化學機械研磨製程或回蝕刻移除部分的罩幕層130，直到暴露第三絕緣材料層128，如第2K圖所示。 Referring to FIG. 2J, the mask layer 130 is deposited on the third insulating material layer 128. Next, a portion of the mask layer 130 is removed by a chemical mechanical polishing process or etch back until the third insulating material layer 128 is exposed, as shown in FIG. 2K.
請參照第2L圖，利用罩幕層130為遮罩，回蝕刻第三絕緣材料層128的暴露部分，以形成暴露出突出部112P及部分的第二絕緣材料層112的溝槽135。為了有利於溝槽135自對準地形成突出部112P的兩側，罩幕層130可選用蝕刻特性與第二絕緣材料相近的材料。在一些實施例中，罩幕層130可包括氮化物或多晶矽。在一些實施例中，形成溝槽135的回蝕刻製程可以是脈衝式反應性離子蝕刻製程，並且可利用相同的氟取代的烴類分子作為蝕刻氣體。 Referring to FIG. 2L, the exposed portion of the third insulating material layer 128 is etched back by using the mask layer 130 as a mask to form a trench 135 exposing the protruding portion 112P and a portion of the second insulating material layer 112. In order to facilitate the self-alignment of the trenches 135 to the sides of the protrusions 112P, the mask layer 130 may be selected from materials having etching characteristics similar to those of the second insulating material. In some embodiments, the mask layer 130 can include a nitride or polysilicon. In some embodiments, the etch back process for forming trenches 135 can be a pulsed reactive ion etch process, and the same fluorine-substituted hydrocarbon molecules can be utilized as the etch gas.
應注意的是，在第2E圖的製程步驟時，若溝槽126在犧牲層114中的兩側側壁並非垂直，而是朝向半導體基板102逐漸縮窄，則第2H圖到第2L圖的突出部112P的剖面將呈現倒梯形，而非矩形。如此一來，在沉積第三絕緣材料層128時，將使突出部112P兩側的第三絕緣材料層128厚度及緻密度不均勻，因而導致用以形成接觸窗之溝槽135的間距變大且口徑不均。因此，不利於降低記憶體裝置的臨界尺寸，也不利於提升產品良率。 It should be noted that, in the process step of FIG. 2E, if the sidewalls of the trench 126 on both sides of the sacrificial layer 114 are not perpendicular, but are gradually narrowed toward the semiconductor substrate 102, the protrusions of the 2Hth through 2nd are shown. The section of portion 112P will assume an inverted trapezoidal shape rather than a rectangular shape. As a result, when the third insulating material layer 128 is deposited, the thickness and density of the third insulating material layer 128 on both sides of the protruding portion 112P are made uneven, thereby causing the pitch of the trench 135 for forming the contact window to become larger. And the caliber is uneven. Therefore, it is not conducive to reducing the critical size of the memory device, and is not conducive to improving product yield.
另外，請參照第3H圖到3K圖，當進行第2I圖到第2L圖的製程時，在BB’剖線上只有第三絕緣材料層128及罩幕層130形成於第二絕緣材料層112上且接著被移除，其他元件並未受到影響。 In addition, referring to FIGS. 3H to 3K, when the processes of FIGS. 2I to 2L are performed, only the third insulating material layer 128 and the mask layer 130 are formed on the second insulating material layer 112 on the BB' line. And then removed, other components are not affected.
請參照第2M圖，進行第三蝕刻製程移除突出部112P兩側的第二絕緣材料層112，以使溝槽135穿過第二絕緣材料層112的暴露部分，並形成第二絕緣材料條狀結構112R。在溝槽135的深度超過第二絕緣材料層112之後，即可進行第四蝕刻製程，以使溝槽135穿過第一絕緣材料層106，而形成接觸窗溝槽135。 Referring to FIG. 2M, a third etching process is performed to remove the second insulating material layer 112 on both sides of the protruding portion 112P, so that the trench 135 passes through the exposed portion of the second insulating material layer 112, and forms a second insulating material strip. Shaped structure 112R. After the depth of the trench 135 exceeds the second insulating material layer 112, a fourth etching process may be performed to pass the trench 135 through the first insulating material layer 106 to form the contact window trench 135.
在一些實施例中，形成接觸窗溝槽135的回蝕刻製程、第三蝕刻製程及第四蝕刻製程三者皆可以是脈衝式反應性離子蝕刻製程，並且可利用相同的氟取代的烴類分子作為蝕刻氣體。應注意的是，在這些實施例中，回蝕刻製程、第三蝕刻製程及第四蝕刻製程可相似於上述第一及第二蝕刻製程，僅簡單調整蝕刻製程參數(例如，蝕刻功率及/或蝕刻氣體濃度)，即 可有效控制接觸窗溝槽135的剖面輪廓。在這些實施例中，當進行回蝕刻製程及第三蝕刻製程時，可採用與第一蝕刻製程相似的製程條件，以利於形成垂直的側壁並移除第二絕緣材料層112的暴露部分；當進行第四蝕刻製程時，則可採用與第二蝕刻製程相似的製程條件，以保護第二絕緣材料條狀結構112R不會受到損傷。 In some embodiments, the etch back process, the third etch process, and the fourth etch process for forming the contact trench 135 may be pulsed reactive ion etching processes, and the same fluorine-substituted hydrocarbon molecules may be utilized. As an etching gas. It should be noted that in these embodiments, the etch back process, the third etch process, and the fourth etch process may be similar to the first and second etch processes described above, and simply adjust the etch process parameters (eg, etch power and/or Etching gas concentration), ie The cross-sectional profile of the contact window trench 135 can be effectively controlled. In these embodiments, when the etch back process and the third etch process are performed, process conditions similar to those of the first etch process may be employed to facilitate forming vertical sidewalls and removing exposed portions of the second insulating material layer 112; When the fourth etching process is performed, process conditions similar to those of the second etching process may be employed to protect the second insulating material strip structure 112R from damage.
請參照第2N圖，形成接觸窗溝槽135之後，蝕刻移除罩幕層130。如第1圖所示，沿著第二方向20延伸的接觸窗溝槽135橫跨位元線108且被位元線108分隔成多個接觸窗150。因此，為簡化圖式，在第2O圖中並未標示接觸窗溝槽135，而是標示接觸窗150。 Referring to FIG. 2N, after the contact window trench 135 is formed, the mask layer 130 is removed by etching. As shown in FIG. 1, the contact window trench 135 extending along the second direction 20 spans the bit line 108 and is separated by the bit line 108 into a plurality of contact windows 150. Therefore, to simplify the drawing, the contact window groove 135 is not indicated in FIG. 2, but the contact window 150 is indicated.
請參照第2O圖，進行濕式蝕刻製程以拓寬接觸窗150底部的口徑，並且移除剩餘的第三絕緣材料層128。在一些實施例中，濕式蝕刻製程對第一絕緣材料及第三絕緣材料的蝕刻速率為R1’，對第二絕緣材料的蝕刻速率為R2’，且濕式蝕刻製程具有蝕刻選擇比R1’/R2’大於10。因此，可拓寬接觸窗150底部的口徑，同時保護第二絕緣材料條狀結構112R不會受到損傷。經過拓寬的接觸窗150可具有高深寬比。在一些實施例中，接觸窗150的深寬比為2-40。在一些實施例中，接觸窗150的深寬比為10-30。在一些實施例中，接觸窗150的深寬比為4-20。 Referring to FIG. 2O, a wet etching process is performed to widen the diameter of the bottom of the contact window 150, and the remaining third insulating material layer 128 is removed. In some embodiments, the wet etch process has an etch rate of R1 ′ for the first insulating material and the third insulating material, an etch rate for the second insulating material is R 2 ′, and the wet etch process has an etch selectivity ratio R 1 ′. /R2' is greater than 10. Therefore, the diameter of the bottom of the contact window 150 can be widened while protecting the second insulating material strip structure 112R from damage. The widened contact window 150 can have a high aspect ratio. In some embodiments, the contact window 150 has an aspect ratio of 2-40. In some embodiments, the contact window 150 has an aspect ratio of 10-30. In some embodiments, the contact window 150 has an aspect ratio of 4-20.
仍請參照第2O圖，在拓寬接觸窗150底部的口徑之後，移除位於接觸窗150底部的接觸蝕刻停止層104，以暴露出半導體基板102的表面。在後續的製程中，半導體基板102可與填入接觸窗150的導電材料電性連接。應注意的是，填入接觸 窗150的導電材料將形成接觸插塞，且此接觸插塞將電性連接至半導體基板102之主動區域(active area)中的各種結構。在一些實施例中，主動區域可包括源極結構、汲極結構、N型或P型摻雜區域、埋入式字元線結構或其他類似的結構。 Still referring to FIG. 2O, after widening the aperture at the bottom of the contact window 150, the contact etch stop layer 104 at the bottom of the contact window 150 is removed to expose the surface of the semiconductor substrate 102. In a subsequent process, the semiconductor substrate 102 can be electrically connected to a conductive material filled in the contact window 150. It should be noted that filling in contact The conductive material of window 150 will form a contact plug, and this contact plug will be electrically connected to various structures in the active area of semiconductor substrate 102. In some embodiments, the active region can include a source structure, a drain structure, an N-type or P-type doped region, a buried word line structure, or other similar structure.
本揭露所提供之半導體裝置100如第1、4圖之上視及示意圖第2O圖之剖面示意圖所示。 The semiconductor device 100 provided by the present disclosure is shown in a cross-sectional view of the top view of FIG. 1 and FIG. 4 and the second view of the schematic view.
請同時參照第1圖及第2O圖，動態隨機存取記憶體100包括基板102、接觸蝕刻停止層104、第一絕緣材料層106、第二絕緣材料層112、多條位元線108、多條第二絕緣材料條狀結構112R以及多個接觸窗150。基板102、接觸蝕刻停止層104、第一絕緣材料層106及第二絕緣材料層112依序由下往上堆疊。位元線108彼此平行且沿著第一方向10延伸。第二絕緣材料條狀結構112R橫跨位元線108，且沿著垂直於第一方向10的第二方向20延伸。接觸窗150位於第二絕緣材料條狀結構112R的兩側且沿著第二方向20排列。 Referring to FIG. 1 and FIG. 2O together, the DRAM 100 includes a substrate 102, a contact etch stop layer 104, a first insulating material layer 106, a second insulating material layer 112, a plurality of bit lines 108, and more. A strip of second insulating material strip 112R and a plurality of contact windows 150. The substrate 102, the contact etch stop layer 104, the first insulating material layer 106, and the second insulating material layer 112 are sequentially stacked from bottom to top. The bit lines 108 are parallel to each other and extend along the first direction 10. The second insulating material strip structure 112R spans the bit line 108 and extends along a second direction 20 that is perpendicular to the first direction 10. The contact windows 150 are located on both sides of the second insulating material strip structure 112R and are arranged along the second direction 20.
再者，請參照第4圖，其繪示本揭露一些實施例之半導體裝置100的上視示意圖。接觸窗150在沿著第一方向10的兩側分別鄰接於第一絕緣層106及第二絕緣材料條狀結構112R，其中第一絕緣層與第二絕緣材料條狀結構112R各自包括不同材質。 Furthermore, please refer to FIG. 4 , which is a top view of the semiconductor device 100 of some embodiments of the present disclosure. The contact window 150 is adjacent to the first insulating layer 106 and the second insulating material strip structure 112R on both sides along the first direction 10, wherein the first insulating layer and the second insulating material strip structure 112R each comprise different materials.
在習知技術中，並未形成本揭露的第二絕緣材料條狀結構112R，而是直接在第一絕緣材料層中形成接觸窗溝槽或接觸窗。然而，當高深寬比的接觸窗時，所形成的接觸窗將具有倒梯形的剖面輪廓。為了縮短重刷新時間，需要增加接觸 窗底部與半導體基板的接觸面積。如此一來，將導致接觸窗頂部的間距太小，因而使裝置因短路而電性失效。此外，為了避免短路，需要增加接觸窗頂部的間距。如此一來，將增加裝置的臨界尺寸，不利於裝置的小型化。 In the prior art, the second insulating material strip structure 112R is not formed, but a contact window trench or contact window is formed directly in the first insulating material layer. However, when a high aspect ratio contact window, the resulting contact window will have an inverted trapezoidal cross-sectional profile. In order to shorten the refresh time, you need to increase the contact The contact area between the bottom of the window and the semiconductor substrate. As a result, the spacing between the tops of the contact windows will be too small, thus causing the device to fail electrically due to a short circuit. In addition, in order to avoid short circuits, it is necessary to increase the pitch of the top of the contact window. As a result, the critical size of the device will be increased, which is disadvantageous for miniaturization of the device.
請參照第2O圖，接觸窗150在第一方向10的兩側壁150a及150b分別鄰接於由不同材質所組成的第一絕緣材料層106及第二絕緣材料條狀結構112R。亦即，接觸窗150在第一方向10的兩側壁係為不同的材質。由於第一絕緣材料與第二絕緣材料具有高蝕刻選擇比，因此當蝕刻或拓寬接觸窗溝槽時，第二絕緣材料條狀結構不後受到蝕刻。如此一來，可藉由調整第二絕緣材料條狀結構的口徑有效地控制接觸窗頂部的間距，因而可避免短路所造成的裝置失效。 Referring to FIG. 2O, the sidewalls 150a and 150b of the contact window 150 in the first direction 10 are respectively adjacent to the first insulating material layer 106 and the second insulating material strip structure 112R composed of different materials. That is, the two sides of the contact window 150 in the first direction 10 are made of different materials. Since the first insulating material and the second insulating material have a high etching selectivity, when the contact window trench is etched or widened, the second insulating material strip structure is not etched later. In this way, the spacing of the top of the contact window can be effectively controlled by adjusting the diameter of the strip structure of the second insulating material, thereby avoiding device failure caused by the short circuit.
仍請參照第2O圖，第二絕緣材料條狀結構112R在第一方向10包括垂直的上部分112a及朝向半導體基板102逐漸縮窄的下部分112b。因此，與第二絕緣材料條狀結構112R鄰接的接觸窗150在第一方向10亦具有上部分及下部分，其中接觸窗150的上部分具有均一的口徑，且下部分具有朝向上部分逐漸縮窄的口徑。如此一來，不需要拓寬接觸窗頂部的間距，即可增加接觸窗底部與半導體基板102的接觸面積，因而能夠降低阻抗，縮短重刷新時間。因此能夠提升裝置的反應速度，並且有利於裝置的小型化。 Still referring to FIG. 2O, the second insulating material strip structure 112R includes a vertical upper portion 112a and a lower portion 112b that is tapered toward the semiconductor substrate 102 in the first direction 10. Therefore, the contact window 150 adjacent to the second insulating material strip structure 112R also has an upper portion and a lower portion in the first direction 10, wherein the upper portion of the contact window 150 has a uniform caliber and the lower portion has a tapered portion toward the upper portion. Narrow caliber. In this way, the contact area between the bottom of the contact window and the semiconductor substrate 102 can be increased without widening the pitch of the top of the contact window, thereby reducing the impedance and shortening the refresh time. Therefore, the reaction speed of the device can be increased, and the miniaturization of the device is facilitated.
此外，第二絕緣材料條狀結構112R的下部分112b朝向半導體基板102逐漸縮窄，若無其他結構的支撐，則第二絕緣材料條狀結構112R容易傾斜或倒塌，進而降低產品良率。 請同時參照第2O圖及第3K圖，由於第二絕緣材料條狀結構112R橫跨位元線108，因此可得到位元線108的支撐而不會傾倒，如此一來可改善產品良率。 In addition, the lower portion 112b of the second insulating material strip structure 112R is gradually narrowed toward the semiconductor substrate 102. If there is no other structural support, the second insulating material strip structure 112R is easily inclined or collapsed, thereby reducing product yield. Referring to FIGS. 2O and 3K simultaneously, since the second insulating material strip structure 112R spans the bit line 108, the support of the bit line 108 can be obtained without tilting, thereby improving the product yield.
綜上所述，相較於習知技術，本揭露所提供之半導體裝置及其形成方法至少具有下述優點： In summary, the semiconductor device and the method of forming the same provided by the present disclosure have at least the following advantages compared to the prior art:
(1)藉由形成第二絕緣材料條狀結構，並在第二絕緣材料條狀結構兩側形成接觸窗，可控制接觸窗的間距在所需的範圍之內，藉以避免短路所造成的裝置失效。 (1) By forming a strip structure of the second insulating material and forming a contact window on both sides of the strip of the second insulating material, the distance between the contact windows can be controlled within a desired range, thereby avoiding the device caused by the short circuit. Invalid.
(2)藉由使接觸窗的上部分具有均一的口徑，且下部分具有朝向上部分逐漸縮窄的口徑，有助於裝置的反應速度與裝置的小型化。 (2) By making the upper portion of the contact window have a uniform aperture and the lower portion having a diameter that gradually narrows toward the upper portion, the reaction speed of the device and the miniaturization of the device are facilitated.
(3)利用位元線108支撐第二絕緣材料條狀結構112R，以改善產品良率。 (3) The second insulating material strip structure 112R is supported by the bit line 108 to improve the product yield.
(4)利用相同的蝕刻步驟形成第二絕緣材料條狀結構的蝕刻步驟與接觸窗溝槽，可在不增加製程設備的前提下，將形成第二絕緣材料條狀結構的步驟輕易整合到原有的製程中。因此，不會對製程的複雜度及成本造成太大的影響。 (4) forming the etching step of the strip structure of the second insulating material and the contact window trench by the same etching step, and the step of forming the strip structure of the second insulating material can be easily integrated into the original without increasing the processing equipment Some processes. Therefore, it will not have too much impact on the complexity and cost of the process.
(5)用以形成第二絕緣材料條狀結構的蝕刻步驟與接觸窗溝槽的蝕刻步驟，僅需藉由簡單調整蝕刻製程參數，即可得到所需的剖面輪廓，有利於降低生產成本並簡化製程複雜度。 (5) an etching step for forming a strip structure of the second insulating material and an etching step of the contact window trench, only by simply adjusting the etching process parameters, the desired profile profile can be obtained, which is advantageous for reducing the production cost and Simplify process complexity.
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the retouching, therefore, the scope of protection of the present invention is defined by the scope of the appended patent application. quasi.
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
102‧‧‧基板 102‧‧‧Substrate
104‧‧‧接觸蝕刻停止層 104‧‧‧Contact etch stop layer
106‧‧‧第一絕緣材料層 106‧‧‧First insulating material layer
106a‧‧‧第一膜層 106a‧‧‧First film
106b‧‧‧第二膜層 106b‧‧‧Second film
106c‧‧‧第三膜層 106c‧‧‧ third film
112‧‧‧第二絕緣材料層 112‧‧‧Second layer of insulating material
112R‧‧‧第二絕緣材料條狀結構 112R‧‧‧Second insulation strip structure
112a‧‧‧上部分 112a‧‧‧上上
112b‧‧‧下部分 112b‧‧‧下下
150‧‧‧接觸窗 150‧‧‧Contact window
150a‧‧‧第一側壁 150a‧‧‧first side wall
150b‧‧‧第二側壁 150b‧‧‧second side wall
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