TWI567715B - A display device, a driving method, a driving method of a display device, and an electronic device having a display device - Google Patents

A display device, a driving method, a driving method of a display device, and an electronic device having a display device Download PDF

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Publication number
TWI567715B
TWI567715B TW102144472A TW102144472A TWI567715B TW I567715 B TWI567715 B TW I567715B TW 102144472 A TW102144472 A TW 102144472A TW 102144472 A TW102144472 A TW 102144472A TW I567715 B TWI567715 B TW I567715B
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terminal
transistor
voltage
source
drain
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TW102144472A
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Chinese (zh)
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TW201428719A (en
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Naobumi Toyomura
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Joled Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electroluminescent Light Sources (AREA)

Description

顯示裝置、顯示驅動裝置、顯示裝置之驅動方法及具備顯示裝置之電子機器 Display device, display driving device, driving method of display device, and electronic device having display device

本揭示係關於具有電流驅動型之顯示元件之顯示裝置、用於如此之顯示裝置之顯示驅動裝置及驅動方法、以及具備如此之顯示裝置之電子機器。 The present disclosure relates to a display device having a current-driven display element, a display driving device and a driving method for such a display device, and an electronic device having such a display device.

近年來，在進行圖像顯示之顯示裝置之領域中，作為發光元件開發出使用根據流動之電流值變化發光亮度之電流驅動型之光學元件，例如有機EL(Electro Luminescence：電致發光)元件之顯示裝置(有機EL顯示裝置)，並逐步推進商品化。發光元件不同於液晶元件等係自發光元件，無需光源(背光)。因此，有機EL顯示裝置與需要光源之液晶顯示裝置相比，具有圖像之可見度較高、消耗電力較低、且元件之應答速度較快等之特徵。 In the field of display devices for image display, in recent years, as a light-emitting element, a current-driven optical element that uses a light-emitting luminance according to a current value of a flow, for example, an organic EL (Electro Luminescence) element has been developed. A display device (organic EL display device) was gradually commercialized. The light-emitting element is different from a self-luminous element such as a liquid crystal element, and does not require a light source (backlight). Therefore, the organic EL display device has a feature that the visibility of the image is higher, the power consumption is lower, and the response speed of the component is faster than that of the liquid crystal display device requiring a light source.

在顯示裝置中，驅動電路對矩陣狀配置之像素進行控制。例如，於專利文獻1中揭示有一種顯示面板，其具備掃描儀驅動，其具備位移暫存器、及連接於此位移暫存器之各輸出端子之轉換器。 In the display device, the drive circuit controls the pixels arranged in a matrix. For example, Patent Document 1 discloses a display panel including a scanner driver including a shift register and a converter connected to each output terminal of the shift register.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2008-58853號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-58853

但，驅動像素時，需要其驅動信號常為較大之振幅。因此，驅動電路宜為產生如此之振幅較大之驅動信號者。 However, when driving a pixel, its driving signal is often required to have a large amplitude. Therefore, the drive circuit should be such that a drive signal having such a large amplitude is generated.

因此，宜提供可產生振幅較大之驅動信號之顯示裝置、顯示驅動裝置、驅動方法、及電子機器。 Therefore, it is preferable to provide a display device, a display driving device, a driving method, and an electronic device which can generate a drive signal having a large amplitude.

本揭示之一實施形態之顯示裝置具備第1電晶體、第1電容元件、及單元像素。第1電晶體係具有閘極、汲極、及源極者。第1電容元件係具有第1端子、及連接於第1電晶體之汲極或源極之第2端子者。單元像素係基於第2端子之電壓而被驅動者。 A display device according to an embodiment of the present disclosure includes a first transistor, a first capacitor, and a unit pixel. The first electro-crystalline system has a gate, a drain, and a source. The first capacitive element has a first terminal and a second terminal connected to the drain or source of the first transistor. The unit pixel is driven based on the voltage of the second terminal.

本揭示之一實施形態之顯示驅動裝置具備第1電晶體、及第1電容元件。第1電晶體係具有閘極、汲極、及源極者。第1電容元件係具有第1端子、及連接於第1電晶體之汲極或源極之第2端子者。 A display driving device according to an embodiment of the present disclosure includes a first transistor and a first capacitor. The first electro-crystalline system has a gate, a drain, and a source. The first capacitive element has a first terminal and a second terminal connected to the drain or source of the first transistor.

本揭示之一實施形態之驅動方法係對第1電晶體之汲極或源極施加脈衝信號，對第1電容元件之第1端子施加其他之脈衝信號，並基於第2端子之電壓驅動單元像素者，其中上述第1電容元件具有第1端子、及連接於與第1電晶體之汲極及源極中之施加有脈衝信號之端子不同之端子之第2端子。 In the driving method according to one embodiment of the present disclosure, a pulse signal is applied to the drain or the source of the first transistor, another pulse signal is applied to the first terminal of the first capacitor, and the pixel is driven based on the voltage of the second terminal. The first capacitor element includes a first terminal and a second terminal connected to a terminal different from a terminal to which a pulse signal is applied to a drain and a source of the first transistor.

本揭示之一實施形態之電子機器係具備上述顯示裝置者，例如，電視裝置、數位相機、個人電腦、攝像機或移動電話等之便攜式終端裝置等符合。 An electronic device according to an embodiment of the present invention includes the display device, for example, a television device, a digital camera, a personal computer, a video camera, or a mobile terminal device such as a mobile phone.

在本揭示之一實施形態之顯示裝置、顯示驅動裝置、驅動方法、及電子機器中，第1電容元件之第2端子連接於第1電晶體之汲極或源極，並基於此第2端子之電壓驅動單元像素。此時，對與第1電晶體之汲極及源極中之第1電容元件所連接之端子不同之端子施加脈衝信號，且對第1電容元件之第1端子施加其他之脈衝信號。 In a display device, a display driving device, a driving method, and an electronic device according to an embodiment of the present disclosure, a second terminal of the first capacitive element is connected to a drain or a source of the first transistor, and based on the second terminal The voltage drives the unit pixels. At this time, a pulse signal is applied to a terminal different from the terminal to which the first capacitive element of the drain and the source of the first transistor is connected, and another pulse signal is applied to the first terminal of the first capacitive element.

根據本揭示之一實施形態之顯示裝置、顯示驅動裝置、驅動方法、及電子機器，因設置第1電晶體、與連接於第1電晶體之汲極或源極之第1電容元件，故可產生振幅較大之驅動信號。 According to the display device, the display driving device, the driving method, and the electronic device of the embodiment of the present disclosure, since the first transistor and the first capacitor element connected to the drain or the source of the first transistor are provided, A drive signal with a large amplitude is generated.

1‧‧‧顯示裝置 1‧‧‧ display device

1H1‧‧‧水平期間 1H1‧‧‧ horizontal period

10‧‧‧顯示部 10‧‧‧Display Department

11‧‧‧子像素 11‧‧‧Subpixel

20‧‧‧驅動部 20‧‧‧ Drive Department

21‧‧‧影像信號處理部 21‧‧‧Image Signal Processing Department

22‧‧‧時序產生部 22‧‧‧Time Generation Department

23‧‧‧掃描線驅動部 23‧‧‧Scanning line driver

26‧‧‧電源線驅動部 26‧‧‧Power cord drive department

26C‧‧‧電源線驅動部 26C‧‧‧Power cord drive department

27‧‧‧資料線驅動部 27‧‧‧Data Line Drive Department

30‧‧‧基板 30‧‧‧Substrate

31‧‧‧位移暫存器 31‧‧‧Displacement register

31C‧‧‧位移暫存器 31C‧‧‧Displacement register

32‧‧‧電荷泵電路 32‧‧‧Charge pump circuit

32B‧‧‧電荷泵電路 32B‧‧‧Charge pump circuit

32C‧‧‧電荷泵電路 32C‧‧‧Charge pump circuit

32C(k)‧‧‧電荷泵電路 32C(k)‧‧‧charge pump circuit

32(C)(k+1)‧‧‧電荷泵電路 32(C)(k+1)‧‧‧charge pump circuit

32(k)‧‧‧電荷泵電路 32(k)‧‧‧charge pump circuit

32(k-1)‧‧‧電荷泵電路 32(k-1)‧‧‧charge pump circuit

32(k+1)‧‧‧電荷泵電路 32(k+1)‧‧‧charge pump circuit

32(k+2)‧‧‧電荷泵電路 32(k+2)‧‧‧charge pump circuit

33‧‧‧電壓產生部 33‧‧‧Voltage Generation Department

34‧‧‧驅動電路 34‧‧‧Drive circuit

34(k)‧‧‧驅動電路 34(k)‧‧‧ drive circuit

510‧‧‧畫面部 510‧‧‧ Screen Department

511‧‧‧前面板 511‧‧‧ front panel

512‧‧‧濾光玻璃 512‧‧‧Filter glass

C1‧‧‧電容元件 C1‧‧‧Capacitive components

C2‧‧‧電容元件 C2‧‧‧Capacitive components

C4‧‧‧電容元件 C4‧‧‧Capacitive components

Cs‧‧‧電容元件 Cs‧‧‧capacitor components

Csub‧‧‧電容元件 Csub‧‧‧capacitor components

DRTr‧‧‧驅動電晶體 DRTr‧‧‧ drive transistor

DS‧‧‧電源信號 DS‧‧‧ power signal

DS(k)‧‧‧電源信號 DS(k)‧‧‧ power signal

DTL‧‧‧資料線 DTL‧‧‧ data line

Ids‧‧‧電流 Ids‧‧‧ Current

In‧‧‧輸入端子 In‧‧‧ input terminal

InH‧‧‧輸入端子 InH‧‧‧ input terminal

OLED‧‧‧有機EL元件 OLED‧‧ organic EL components

Out‧‧‧輸出端子 Out‧‧‧Output terminal

P1‧‧‧初始化期間 P1‧‧‧Initial period

P2‧‧‧Vth校正期間 P2‧‧‧Vth correction period

P3‧‧‧寫入‧μ校正期間 P3‧‧‧write ‧μ correction period

P4‧‧‧發光期間 P4‧‧‧Lighting period

Pix‧‧‧像素 Pix‧‧ ‧ pixels

PL‧‧‧電源線 PL‧‧‧Power cord

PL(k)‧‧‧電源線 PL(k)‧‧‧Power cord

PP1‧‧‧脈衝 PP1‧‧‧ pulse

PP2‧‧‧脈衝 PP2‧‧‧ pulse

Sdisp‧‧‧影像信號 Sdisp‧‧‧ image signal

Sdisp2‧‧‧影像信號 Sdisp2‧‧‧ image signal

Sig‧‧‧信號 Sig‧‧ signal

SR1‧‧‧輸入端子 SR1‧‧‧ input terminal

SR2‧‧‧輸入端子 SR2‧‧‧ input terminal

SR3‧‧‧輸入端子 SR3‧‧‧ input terminal

SR4‧‧‧輸入端子 SR4‧‧‧ input terminal

Ss‧‧‧掃描信號 Ss‧‧‧ scan signal

Ss(n)‧‧‧掃描信號 Ss(n)‧‧‧ scan signal

Ss(n-1)‧‧‧掃描信號 Ss(n-1)‧‧‧ scan signal

Ss(n+1)‧‧‧掃描信號 Ss(n+1)‧‧‧ scan signal

Ss(n+2)‧‧‧掃描信號 Ss(n+2)‧‧‧ scan signal

Ss(n+3)‧‧‧掃描信號 Ss(n+3)‧‧‧ scan signal

SSR1‧‧‧信號 SSR1‧‧‧ signal

SSR2‧‧‧信號 SSR2‧‧‧ signal

SSR3‧‧‧信號 SSR3‧‧‧ signal

SSR4‧‧‧信號 SSR4‧‧‧ signal

Ssync‧‧‧同步信號 Ssync‧‧‧ sync signal

St‧‧‧信號 St‧‧ signals

St(k)‧‧‧信號 St(k)‧‧‧ signal

St(k+1)‧‧‧信號 St(k+1)‧‧‧ signal

t0‧‧‧時序 T0‧‧‧ Timing

t1‧‧‧時序 T1‧‧‧ timing

t2‧‧‧時序 T2‧‧‧ timing

t3‧‧‧時序 T3‧‧‧ Timing

t4‧‧‧時序 T4‧‧‧ Timing

t5‧‧‧時序 T5‧‧‧ timing

t6‧‧‧時序 T6‧‧‧ timing

t7‧‧‧時序 T7‧‧‧ Timing

t8‧‧‧時序 T8‧‧‧ timing

t9‧‧‧時序 T9‧‧‧ Timing

t10‧‧‧時序 T10‧‧‧ Timing

t11‧‧‧時序 T11‧‧‧ Timing

t12‧‧‧時序 T12‧‧‧ Timing

t13‧‧‧時序 T13‧‧‧ timing

t14‧‧‧時序 T14‧‧‧ Timing

t15‧‧‧時序 T15‧‧‧ Timing

t16‧‧‧時序 T16‧‧‧ Timing

t17‧‧‧時序 T17‧‧‧ Timing

t18‧‧‧時序 T18‧‧‧ Timing

Tr1‧‧‧電晶體 Tr1‧‧‧O crystal

Tr2‧‧‧電晶體 Tr2‧‧‧O crystal

Tr3‧‧‧電晶體 Tr3‧‧‧O crystal

Tr4‧‧‧電晶體 Tr4‧‧‧O crystal

Tr5‧‧‧電晶體 Tr5‧‧‧O crystal

Tr7‧‧‧電晶體 Tr7‧‧‧O crystal

Tr8‧‧‧電晶體 Tr8‧‧‧O crystal

Vcath‧‧‧陰極電壓 Vcath‧‧‧ cathode voltage

Vccp‧‧‧電壓 Vccp‧‧‧ voltage

Vel‧‧‧閾值電壓 Vel‧‧‧ threshold voltage

Vemi‧‧‧電壓 Vemi‧‧‧ voltage

VH‧‧‧高位準電壓 VH‧‧‧ high level voltage

Vg‧‧‧閘極電壓 Vg‧‧‧ gate voltage

VG1‧‧‧電壓 VG1‧‧‧ voltage

Vgs‧‧‧電壓 Vgs‧‧‧ voltage

Vini‧‧‧電壓 Vini‧‧‧ voltage

VL‧‧‧低位準電壓 VL‧‧‧low level voltage

VN1‧‧‧節點電壓 VN1‧‧‧ node voltage

VN2‧‧‧節點電壓 VN2‧‧‧ node voltage

Vofs‧‧‧電壓 Vofs‧‧‧ voltage

Vs‧‧‧源極電壓 Vs‧‧‧ source voltage

Vsig‧‧‧像素電壓 Vsig‧‧‧ pixel voltage

Vth‧‧‧閾值電壓 Vth‧‧‧ threshold voltage

WS‧‧‧掃描信號 WS‧‧‧ scan signal

WS(k)‧‧‧掃描信號 WS(k)‧‧‧ scan signal

WS(k+1)‧‧‧掃描信號 WS(k+1)‧‧‧ scan signal

WS(k+2)‧‧‧掃描信號 WS (k + 2) ‧ ‧ scan signal

WS(k+3)‧‧‧掃描信號 WS (k + 3) ‧ ‧ scan signal

WSL‧‧‧掃描線 WSL‧‧‧ scan line

WSTr‧‧‧寫入電晶體 WSTr‧‧‧Write transistor

圖1係表示本揭示之實施形態之顯示裝置之一構成例之方塊圖。 Fig. 1 is a block diagram showing a configuration example of a display device according to an embodiment of the present disclosure.

圖2係表示圖1所示之子像素之一構成例之電路圖。 Fig. 2 is a circuit diagram showing an example of the configuration of one of the sub-pixels shown in Fig. 1.

圖3係表示圖1所示之電源線驅動部之一構成例之方塊圖。 Fig. 3 is a block diagram showing an example of the configuration of a power line driving unit shown in Fig. 1.

圖4係表示圖3所示之電荷泵電路及驅動電路之一構成例之電路圖。 Fig. 4 is a circuit diagram showing an example of a configuration of a charge pump circuit and a drive circuit shown in Fig. 3.

圖5係表示顯示裝置之電源線驅動部之配置之說明圖。 Fig. 5 is an explanatory view showing the arrangement of a power line driving unit of the display device.

圖6(A)-(C)係表示圖1所示之驅動部之一動作例之時序波形圖。 6(A) to 6(C) are timing waveform diagrams showing an operation example of one of the driving units shown in Fig. 1.

圖7(A)-(E)係表示圖1所示之子像素之一動作例之時序波形圖。 7(A)-(E) are timing waveform diagrams showing an example of operation of one of the sub-pixels shown in Fig. 1.

圖8(A)-(H)係表示圖4所示之電荷泵電路及驅動電路之一動作例之時序波形圖。 8(A) to 8(H) are timing waveform diagrams showing an operation example of one of the charge pump circuit and the drive circuit shown in Fig. 4.

圖9係表示變化例之電荷泵電路之一構成例之電路圖。 Fig. 9 is a circuit diagram showing a configuration example of a charge pump circuit of a variation.

圖10係表示其他變化例之電源線驅動部之一構成例之方塊圖。 Fig. 10 is a block diagram showing an example of the configuration of a power line driving unit of another modification.

圖11係表示圖10所示之電荷泵電路之一構成例之電路圖。 Fig. 11 is a circuit diagram showing an example of the configuration of the charge pump circuit shown in Fig. 10.

圖12係表示應用實施形態之顯示裝置之電視裝置之外觀構成之立體圖。 Fig. 12 is a perspective view showing an appearance configuration of a television device to which the display device of the embodiment is applied.

圖13係表示其他變化例之子像素之一構成例之電路圖。 Fig. 13 is a circuit diagram showing an example of the configuration of one of the sub-pixels of the other modification.

以下，針對本揭示之實施形態參照圖式進行詳細地說明。另，說明按以下之順序進行。 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In addition, the description is made in the following order.

1.實施形態 1. Implementation

2.應用例 2. Application examples

〈1.實施形態〉 <1. Embodiment>

[構成例] [Configuration example]

圖1係表示實施形態之顯示裝置之一構成例者。顯示裝置1係使用有機EL元件之主動式矩陣方式之顯示裝置。另，因本揭示之實施形態之驅動裝置、驅動方法係藉由本實施形態而具體化，故一併進行 說明。此顯示裝置1具備顯示部10及驅動部20。 Fig. 1 is a view showing an example of a configuration of a display device according to an embodiment. The display device 1 is an active matrix type display device using an organic EL element. Further, since the driving device and the driving method according to the embodiment of the present disclosure are embodied by the present embodiment, they are collectively performed. Description. This display device 1 includes a display unit 10 and a drive unit 20.

顯示部10係複數個像素Pix配置為矩陣狀者。各像素Pix具有紅色、綠色、藍色之子像素11。顯示部10具有於行方向延伸之複數條掃描線WSL及複數條電源線PL、與於列方向延伸之複數條資料線DTL。此等掃描線WSL、電源線PL、及資料線DTL之一端連接於驅動部20。上述之各子像素11配置於掃描線WSL與資料線DTL之交叉部。 The display unit 10 is configured such that a plurality of pixels Pix are arranged in a matrix. Each of the pixels Pix has sub-pixels 11 of red, green, and blue. The display unit 10 has a plurality of scanning lines WSL extending in the row direction, a plurality of power supply lines PL, and a plurality of data lines DTL extending in the column direction. One of the scanning lines WSL, the power line PL, and the data line DTL is connected to the driving unit 20. Each of the sub-pixels 11 described above is disposed at an intersection of the scanning line WSL and the data line DTL.

圖2係表示子像素11之電路構成之一例。子像素11具備寫入電晶體WSTr、驅動電晶體DRTr、有機EL元件OLED、及電容元件Cs、Csub。即，在此例中，子像素11使用2個電晶體(寫入電晶體WSTr、驅動電晶體DRTr)及2個電容元件Cs、Csub而構成，即係具有「2Tr2C」之構成者。 FIG. 2 shows an example of the circuit configuration of the sub-pixel 11. The sub-pixel 11 includes a write transistor WSTr, a drive transistor DRTr, an organic EL element OLED, and capacitive elements Cs and Csub. In other words, in this example, the sub-pixel 11 is configured by using two transistors (writing transistor WSTr, driving transistor DRTr) and two capacitive elements Cs and Csub, that is, a component having "2Tr2C".

寫入電晶體WSTr及驅動電晶體DRTr例如係藉由N通道MOS(Metal Oxide Semiconductor：金屬氧化物半導體)型之TFT(Thin Film Transistor：薄膜電晶體)而構成者。寫入電晶體WSTr係閘極連接於掃描線WSL，源極連接於資料線DTL，汲極連接於驅動電晶體DRTr之閘極及電容元件Cs之一端。驅動電晶體DRTr係閘極連接於寫入電晶體WSTr之汲極及電容元件Cs之一端，汲極連接於電源線PL，源極連接於電容元件Cs之另一端及有機EL元件OLED之陽極等。 The write transistor WSTr and the drive transistor DRTr are formed by, for example, an N-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor). The write transistor WSTr is connected to the scan line WSL, the source is connected to the data line DTL, and the drain is connected to the gate of the drive transistor DRTr and one end of the capacitive element Cs. The driving transistor DRTr-based gate is connected to one end of the write transistor WSTr and one end of the capacitive element Cs, the drain is connected to the power line PL, the source is connected to the other end of the capacitive element Cs, and the anode of the organic EL element OLED is etc. .

電容元件Cs係一端連接於驅動電晶體DRTr之閘極等，另一端連接於驅動電晶體DRTr之源極等。電容元件Csub係一端連接於有機EL元件OLED之陽極，另一端連接於有機EL元件OLED之陰極。即，在此例中，電容元件Csub與有機EL元件OLED並聯連接。有機EL元件OLED係射出對應於各子像素11之顏色(紅色、綠色、藍色)之光之發光元件，陽極連接於驅動電晶體DRTr之源極等，對陰極藉由驅動部20而供給陰極電壓Vcath。 The capacitive element Cs has one end connected to the gate of the driving transistor DRTr, and the other end connected to the source of the driving transistor DRTr or the like. The capacitive element Csub is connected at one end to the anode of the organic EL element OLED, and at the other end to the cathode of the organic EL element OLED. That is, in this example, the capacitive element Csub is connected in parallel with the organic EL element OLED. The organic EL element OLED emits a light-emitting element that emits light corresponding to the color (red, green, and blue) of each sub-pixel 11, and the anode is connected to the source of the drive transistor DRTr, and the cathode is supplied to the cathode by the drive unit 20. Voltage Vcath.

驅動部20係基於自外部供給之影像信號Sdisp及同步信號Ssync， 而驅動顯示部10者。此驅動部20如圖1所示般具備影像信號處理部21、時序產生部22、掃描線驅動部23、電源線驅動部26、及資料線驅動部27。 The drive unit 20 is based on the image signal Sdisp and the synchronization signal Ssync supplied from the outside. The display unit 10 is driven. As shown in FIG. 1, the drive unit 20 includes a video signal processing unit 21, a timing generation unit 22, a scanning line drive unit 23, a power line drive unit 26, and a data line drive unit 27.

影像信號處理部21係對自外部供給之影像信號Sdisp進行特定之信號處理，而產生影像信號Sdisp2者。作為此特定之信號處理，例如可例舉出伽馬校正、加速驅動校正等。 The video signal processing unit 21 performs signal processing on the video signal Sdisp supplied from the outside to generate a video signal Sdisp2. As the specific signal processing, for example, gamma correction, acceleration drive correction, and the like can be exemplified.

時序產生部22係基於自外部所供給之同步信號Ssync，分別對掃描線驅動部23、電源線驅動部26、及資料線驅動部27供給控制信號，為使此等同步動作而進行控制之電路。 The timing generation unit 22 supplies a control signal to the scanning line driving unit 23, the power source line driving unit 26, and the data line driving unit 27 based on the synchronization signal Ssync supplied from the outside, and controls the circuit to perform these synchronous operations. .

掃描線驅動部23係根據自時序產生部22所供給之控制信號，對複數條掃描線WSL依序施加掃描信號WS，藉此依序以每行選擇子像素11者。 The scanning line driving unit 23 sequentially applies the scanning signal WS to the plurality of scanning lines WSL based on the control signal supplied from the timing generating unit 22, thereby sequentially selecting the sub-pixels 11 in each row.

電源線驅動部26係根據自時序產生部22所供給之控制信號，對複數條電源線PL依序施加電源信號DS，藉此，以每行進行子像素11之發光動作及淬熄動作之控制者。電源信號DS係在電壓Vccp與電壓Vini之間轉變者。如後述般，電壓Vini係用於使子像素11初始化之電壓，電壓Vccp係用於使電流Ids流動於驅動電晶體DRTr而使有機EL元件OLED發光之電壓。 The power supply line drive unit 26 sequentially applies the power supply signal DS to the plurality of power supply lines PL based on the control signal supplied from the timing generation unit 22, thereby controlling the light emission operation and the quenching operation of the sub-pixel 11 in each row. By. The power signal DS is converted between the voltage Vccp and the voltage Vini. As will be described later, the voltage Vini is a voltage for initializing the sub-pixel 11, and the voltage Vccp is a voltage for causing the current Ids to flow to the driving transistor DRTr to cause the organic EL element OLED to emit light.

圖3係表示電源線驅動部26之一構成例者。電源線驅動部26具有位移暫存器31、複數個電荷泵電路32、電壓產生部33、及複數個驅動電路34。 FIG. 3 shows an example of a configuration of the power line drive unit 26. The power line drive unit 26 includes a shift register 31, a plurality of charge pump circuits 32, a voltage generating unit 33, and a plurality of drive circuits 34.

位移暫存器31係基於自時序產生部22所供給之控制信號(未圖示)，產生用於選擇成為驅動對象之像素線之複數個掃描信號Ss(...、Ss(n-1)、Ss(n)、Ss(n+1)、Ss(n+2)、Ss(n+3)、...)者。各掃描信號Ss係供給至4個電荷泵電路32。具體而言，例如，掃描信號Ss(n+1)形成為供給至4個電荷泵電路32(k-1)、32(k)、32(k+1)、32(k+2)。各 掃描信號Ss係在高位準電壓VH與低位準電壓VL之間轉變之信號。高位準電壓VH係較電壓Vccp更低之電壓，低位準電壓VL係與電壓Vini相同程度之電壓。 The shift register 31 generates a plurality of scanning signals Ss (..., Ss(n-1) for selecting a pixel line to be driven based on a control signal (not shown) supplied from the timing generating unit 22. , Ss(n), Ss(n+1), Ss(n+2), Ss(n+3), ...). Each of the scanning signals Ss is supplied to the four charge pump circuits 32. Specifically, for example, the scan signal Ss(n+1) is formed to be supplied to the four charge pump circuits 32(k-1), 32(k), 32(k+1), and 32(k+2). each The scan signal Ss is a signal that transitions between the high level voltage VH and the low level voltage VL. The high level voltage VH is a voltage lower than the voltage Vccp, and the low level voltage VL is the same voltage as the voltage Vini.

各電荷泵電路32係基於4個掃描信號Ss，產生振幅大於此等掃描信號Ss之振幅之信號St者。具體而言，例如，電荷泵電路32基於4個掃描信號Ss(n-1)、Ss(n)、Ss(n+1)、Ss(n+2)而產生信號St(k)。各電荷泵電路32具有輸入4個掃描信號Ss之輸入端子SR1~SR4、與輸出信號St之輸出端子Out。例如，於電荷泵電路32(k)之輸入端子SR1中輸入掃描信號Ss(n-1)，於輸入端子SR2中輸入掃描信號Ss(n)，於輸入端子SR3中輸入掃描信號Ss(n+1)，於輸入端子SR4中輸入掃描信號Ss(n+2)。各電荷泵電路32對應於顯示部10之各像素線而設置。具體而言，例如，第k個電荷泵電路32(k)對應於第k行之像素線而設置。 Each of the charge pump circuits 32 generates a signal St having an amplitude larger than the amplitude of the scanning signals Ss based on the four scanning signals Ss. Specifically, for example, the charge pump circuit 32 generates a signal St(k) based on the four scanning signals Ss(n-1), Ss(n), Ss(n+1), and Ss(n+2). Each of the charge pump circuits 32 has input terminals SR1 to SR4 for inputting four scanning signals Ss and an output terminal Out for outputting signals St. For example, the scan signal Ss(n-1) is input to the input terminal SR1 of the charge pump circuit 32(k), the scan signal Ss(n) is input to the input terminal SR2, and the scan signal Ss (n+) is input to the input terminal SR3. 1) The scan signal Ss(n+2) is input to the input terminal SR4. Each of the charge pump circuits 32 is provided corresponding to each pixel line of the display unit 10. Specifically, for example, the kth charge pump circuit 32(k) is provided corresponding to the pixel line of the kth row.

電壓產生部33係產生電壓Vccp並將此電壓Vccp供給各驅動電路34者。 The voltage generating unit 33 generates a voltage Vccp and supplies the voltage Vccp to each of the drive circuits 34.

各驅動電路34係基於自電壓產生部33所供給之電壓Vccp、自電荷泵電路32所供給之信號St，而產生電源信號DS者。各驅動電路34具有輸入有電源Vccp之輸入端子InH、輸入有信號St之輸入端子In、及輸出電源信號DS之輸出端子Out。各驅動電路34對應於顯示部10之各像素線而設置。具體而言，例如，第k個驅動電路34(k)基於自電壓產生部33所供給之電壓Vccp、及自電荷泵電路32(k)所供給之信號St(k)，而產生第k個電源信號DS(k)。且，驅動電路34(k)形成為將此電源信號DS(k)施加於第k行之像素線之電源線PL(k)。 Each of the drive circuits 34 generates a power supply signal DS based on the voltage Vccp supplied from the voltage generating unit 33 and the signal St supplied from the charge pump circuit 32. Each of the drive circuits 34 has an input terminal InH to which the power supply Vccp is input, an input terminal In to which the signal St is input, and an output terminal Out to which the power supply signal DS is output. Each of the drive circuits 34 is provided corresponding to each pixel line of the display unit 10. Specifically, for example, the kth drive circuit 34(k) generates the kth based on the voltage Vccp supplied from the voltage generating unit 33 and the signal St(k) supplied from the charge pump circuit 32(k). Power signal DS(k). Further, the drive circuit 34(k) is formed to apply the power supply signal DS(k) to the power supply line PL(k) of the pixel line of the kth row.

圖4係表示電荷泵電路32及驅動電路34之一構成例者。電荷泵電路32具有電晶體Tr1~Tr3、及電容元件C1、C2。驅動電路34具有電晶體Tr4、Tr5。電晶體Tr1~Tr5係例如由N通道MOS型之TFT構成者。 FIG. 4 shows an example of the configuration of the charge pump circuit 32 and the drive circuit 34. The charge pump circuit 32 has transistors Tr1 to Tr3 and capacitance elements C1 and C2. The drive circuit 34 has transistors Tr4 and Tr5. The transistors Tr1 to Tr5 are composed of, for example, an N-channel MOS type TFT.

在電荷泵電路32中，對電晶體Tr1之閘極供給直流之電壓VG1， 汲極連接於輸入端子SR2，源極連接於電容元件C1之一端及電晶體Tr2之閘極。此電壓VG1係高於低位準電壓VL，且低於高位準電壓VH者(VH>VG1>VL)。電晶體Tr2之閘極連接於電晶體Tr1之源極及電容元件C1之一端，汲極連接於輸入端子SR1，源極連接於電容元件C2之一端且連接於輸出端子Out。電晶體Tr3之閘極連接於電容元件C1之另一端且連接於輸入端子SR3，汲極連接於輸入端子SR4，源極連接於電容元件C2之另一端。另，此等電晶體Tr1~Tr3亦可交替汲極與源極。電容元件C1之一端連接於電晶體Tr1之源極及電晶體Tr2之閘極，另一端連接於電晶體Tr3之閘極且連接於輸入端子SR3。電容元件C2之一端連接於電晶體Tr2之源極且連接於輸出端子Out，另一端連接於電晶體Tr3之源極。 In the charge pump circuit 32, a DC voltage VG1 is supplied to the gate of the transistor Tr1, The drain is connected to the input terminal SR2, and the source is connected to one end of the capacitive element C1 and the gate of the transistor Tr2. This voltage VG1 is higher than the low level voltage VL and lower than the high level voltage VH (VH>VG1>VL). The gate of the transistor Tr2 is connected to the source of the transistor Tr1 and one end of the capacitive element C1, the drain is connected to the input terminal SR1, and the source is connected to one end of the capacitive element C2 and connected to the output terminal Out. The gate of the transistor Tr3 is connected to the other end of the capacitive element C1 and is connected to the input terminal SR3, the drain is connected to the input terminal SR4, and the source is connected to the other end of the capacitive element C2. In addition, the transistors Tr1 to Tr3 may alternate between the drain and the source. One end of the capacitive element C1 is connected to the source of the transistor Tr1 and the gate of the transistor Tr2, and the other end is connected to the gate of the transistor Tr3 and is connected to the input terminal SR3. One end of the capacitive element C2 is connected to the source of the transistor Tr2 and connected to the output terminal Out, and the other end is connected to the source of the transistor Tr3.

在驅動電路34中，電晶體Tr4之閘極連接於電晶體Tr5之源極且連接於輸入端子In，汲極連接於輸入端子InH，源極連接於電晶體Tr5之閘極及汲極且連接於輸出端子Out。電晶體Tr5之閘極連接於電晶體Tr5之汲極及電晶體Tr4之源極且連接於輸出端子Out，源極連接於電晶體Tr4之閘極且連接於輸入端子In。 In the driving circuit 34, the gate of the transistor Tr4 is connected to the source of the transistor Tr5 and connected to the input terminal In, the drain is connected to the input terminal InH, and the source is connected to the gate and the drain of the transistor Tr5 and connected. At the output terminal Out. The gate of the transistor Tr5 is connected to the drain of the transistor Tr5 and the source of the transistor Tr4 and is connected to the output terminal Out. The source is connected to the gate of the transistor Tr4 and is connected to the input terminal In.

藉由此構成，電荷泵電路32及驅動電路34如後述般，形成為產生較掃描信號Ss之振幅(VH-VL)更大之振幅(Vccp-Vini)之電源信號DS。 With this configuration, the charge pump circuit 32 and the drive circuit 34 are formed as a power supply signal DS that generates an amplitude (Vccp - Vini) larger than the amplitude (VH - VL) of the scanning signal Ss as will be described later.

圖5係表示顯示裝置1之各區塊之配置者。在此例中，基板30中於形成有顯示部10之區域之左側之框架區域中配置掃描線驅動部23，於右側之框架區域中配置電源線驅動部26。即，電源線驅動部26與顯示部10或掃描線驅動部23相同地形成於基板30上。 FIG. 5 shows the configurator of each block of the display device 1. In this example, the scanning line driving unit 23 is disposed in the frame region on the left side of the region where the display portion 10 is formed in the substrate 30, and the power source line driving portion 26 is disposed in the frame region on the right side. In other words, the power line driving unit 26 is formed on the substrate 30 in the same manner as the display unit 10 or the scanning line driving unit 23.

在圖1中，資料線驅動部27係根據自影像信號處理部21所供給之影像信號Sdisp2及自時序產生部22所供給之控制信號，產生包含指示各子像素11之發光亮度之像素電壓Vsig、及用於進行後述之Vth校正 之電壓Vofs之信號Sig，並施加於各資料線DTL者 In FIG. 1, the data line drive unit 27 generates a pixel voltage Vsig including the light-emitting luminance indicating each sub-pixel 11 based on the video signal Sdisp2 supplied from the video signal processing unit 21 and the control signal supplied from the timing generating unit 22. And for performing Vth correction described later The signal Sig of the voltage Vofs is applied to each data line DTL

藉由此構成，驅動部20如後述般，對子像素11進行用於抑制驅動電晶體DRTr之元件不均一對畫質之影響之校正(Vth校正)。其後，對子像素11進行像素電壓Vsig之寫入，且進行不同於上述Vth校正之μ(移動率)校正。且，其後，子像素11之有機EL元件OLED以根據所寫入之像素電壓Vsig之亮度發光。 With this configuration, the drive unit 20 performs correction (Vth correction) for suppressing the influence of the component quality of the drive transistor DRTr on the pair of pixels, as will be described later. Thereafter, the sub-pixel 11 is written with the pixel voltage Vsig, and μ (movement rate) correction different from the Vth correction described above is performed. Then, the organic EL element OLED of the sub-pixel 11 emits light at a luminance according to the written pixel voltage Vsig.

此處，電晶體Tr2對應於本揭示之「第1電晶體」之一具體例。電晶體Tr1對應於本揭示之「第2電晶體」之一具體例。電晶體Tr3對應於本揭示之「第3電晶體」之一具體例。電容元件C2對應於本揭示之「第1電容元件」之一具體例。電容元件C1對應於本揭示之「第2電容元件」之一具體例。電晶體Tr4對應於本揭示之「開關」之一具體例。電晶體Tr5對應於本揭示之「非線形元件」之一具體例。子像素11對應於本揭示之「單元像素」之一具體例。 Here, the transistor Tr2 corresponds to a specific example of the "first transistor" of the present disclosure. The transistor Tr1 corresponds to a specific example of the "second transistor" of the present disclosure. The transistor Tr3 corresponds to a specific example of the "third transistor" of the present disclosure. The capacitive element C2 corresponds to a specific example of the "first capacitive element" of the present disclosure. The capacitive element C1 corresponds to a specific example of the "second capacitive element" of the present disclosure. The transistor Tr4 corresponds to a specific example of the "switch" of the present disclosure. The transistor Tr5 corresponds to a specific example of the "non-linear element" of the present disclosure. The sub-pixel 11 corresponds to a specific example of the "unit pixel" of the present disclosure.

[動作及作用] [Action and function]

接著，針對本實施形態之顯示裝置1之動作及作用進行說明。 Next, the operation and action of the display device 1 of the present embodiment will be described.

(整體動作概要) (Overview of overall action)

首先，參照圖1說明顯示裝置1之整體動作概要。影像信號處理部21對自外部供給之影像信號Sdisp進行特定之信號處理，而產生影像信號Sdisp2。時序產生部22基於自外部供給之同步信號Ssync，分別對掃描線驅動部23、電源線驅動部26及資料線驅動部27供給控制信號，並以使此等互相同步動作之方式進行控制。掃描線驅動部23根據自時序產生部22供給之控制信號，對複數條掃描線WSL依序施加掃描信號WS，藉此，以每行按順序選擇子像素11。電源線驅動部26根據自時序產生部22供給之控制信號，對複數條電源線PL依序施加電源信號DS，藉此以每行進行子像素11之發光動作及淬熄動作之控制。資料線驅動部27根據自影像信號處理部21供給之影像信號Sdisp2及時 序產生部22供給之控制信號，產生包含指示各子像素11之發光亮度之像素電壓Vsig、及用於進行Vth校正之電壓Vofs之信號Sig，並施加於各資料線DTL。顯示部10基於自驅動部20供給之掃描信號WS、電源信號DS、及信號Sig進行顯示。 First, an outline of the overall operation of the display device 1 will be described with reference to Fig. 1 . The video signal processing unit 21 performs specific signal processing on the video signal Sdisp supplied from the outside to generate the video signal Sdisp2. The timing generation unit 22 supplies control signals to the scanning line driving unit 23, the power source line driving unit 26, and the data line driving unit 27 based on the synchronization signal Ssync supplied from the outside, and controls the signals in synchronization with each other. The scanning line driving unit 23 sequentially applies the scanning signal WS to the plurality of scanning lines WSL based on the control signal supplied from the timing generating unit 22, whereby the sub-pixels 11 are sequentially selected for each line. The power supply line drive unit 26 sequentially applies the power supply signal DS to the plurality of power supply lines PL based on the control signal supplied from the timing generation unit 22, thereby controlling the light emission operation and the quenching operation of the sub-pixel 11 in each row. The data line drive unit 27 is in time based on the image signal Sdisp2 supplied from the video signal processing unit 21. The control signal supplied from the sequence generating unit 22 generates a signal Sig including a pixel voltage Vsig indicating the light emission luminance of each sub-pixel 11 and a voltage Vofs for performing Vth correction, and is applied to each data line DTL. The display unit 10 displays based on the scan signal WS, the power source signal DS, and the signal Sig supplied from the drive unit 20.

(詳細動作) (detailed action)

圖6係表示驅動部20之動作之時序圖者，(A)顯示掃描信號WS之波形，(B)顯示電源信號DS之波形，(C)顯示信號Sig之波形。在圖6(A)中，掃描信號WS(k)為驅動第k行之子像素11之掃描信號WS，同樣，掃描信號WS(k+1)、WS(k+2)、WS(k+3)分別為驅動第(k+1)行、第(k+2)行、第(k+3)行之子像素11之掃描信號WS。針對電源信號DS(圖6(B))亦相同。 6 is a timing chart showing the operation of the drive unit 20, (A) shows the waveform of the scan signal WS, (B) shows the waveform of the power supply signal DS, and (C) shows the waveform of the display signal Sig. In FIG. 6(A), the scanning signal WS(k) is the scanning signal WS for driving the sub-pixel 11 of the kth row, and similarly, the scanning signals WS(k+1), WS(k+2), WS(k+3) The scanning signals WS for driving the sub-pixels 11 of the (k+1)th, (k+2)th, and (k+3th)th rows, respectively. The same applies to the power signal DS (Fig. 6(B)).

驅動部20之掃描線驅動部23對掃描線WSL，依序施加具有2個脈衝PP1、PP2之掃描信號WS(圖6(A))。此時，掃描線驅動部23在1水平期間(1H)內，對1個掃描線WSL施加2個脈衝PP1、PP2。電源線驅動部26對電源線PL，施加包含脈衝PP1之開始時序(例如時序t1)之特定期間(例如時序t0~t2之期間)成為電壓Vini，其他之期間成為電壓Vccp之電源信號DS(圖6(B))。資料線驅動部27對資料線DTL，在包含脈衝PP2之特定期間(例如時序t4~t7之期間)內施加像素電壓Vsig，於其他之期間內施加電壓Vofs(圖6(C))。 The scanning line driving unit 23 of the driving unit 20 sequentially applies the scanning signals WS having the two pulses PP1 and PP2 to the scanning line WSL (FIG. 6(A)). At this time, the scanning line driving unit 23 applies two pulses PP1 and PP2 to one scanning line WSL in one horizontal period (1H). The power supply line drive unit 26 applies a power supply signal DS to the power supply line PL in a specific period (for example, a period t0 to t2) including the start timing of the pulse PP1 (for example, the period t0 to t2) to be the voltage Vini, and the other period to be the power supply signal DS of the voltage Vccp. 6(B)). The data line drive unit 27 applies the pixel voltage Vsig to the data line DTL for a specific period including the pulse PP2 (for example, during the period from t4 to t7), and applies the voltage Vofs during other periods (FIG. 6(C)).

如此般，驅動部20在1水平期間(例如時序t1~t7)內，驅動第k行之子像素11，在下一水平期間(例如時序t7~t8)內，驅動第(k+1)行之子像素11。且，驅動部20在1幀期間內，驅動顯示部10之全部之子像素11。 In this manner, the drive unit 20 drives the sub-pixels 11 of the kth row in one horizontal period (for example, the timings t1 to t7), and drives the sub-pixels of the (k+1)th row in the next horizontal period (for example, the timing t7 to t8). 11. Further, the drive unit 20 drives all of the sub-pixels 11 of the display unit 10 in one frame period.

圖7係表示時序t0~t7期間之子像素11之動作之時序圖者，(A)顯示掃描信號WS之波形，(B)顯示電源信號DS之波形，(C)顯示信號Sig之波形，(D)顯示驅動電晶體DRTr之閘極電壓Vg之波形，(E)顯示驅動 電晶體DRTr之源極電壓Vs之波形。在圖7(B)~(E)中，使用相同電壓軸來顯示各波形。 7 is a timing chart showing the operation of the sub-pixel 11 during the timing t0 to t7, (A) showing the waveform of the scanning signal WS, (B) showing the waveform of the power signal DS, and (C) the waveform of the display signal Sig, (D) ) shows the waveform of the gate voltage Vg of the driving transistor DRTr, (E) display drive The waveform of the source voltage Vs of the transistor DRTr. In FIGS. 7(B) to (E), the waveforms are displayed using the same voltage axis.

驅動部20在1水平期間(1H)內，進行子像素11之初始化(初始化期間P1)、進行用於抑制驅動電晶體DRTr之元件不均一對畫質之影響之Vth校正(Vth校正期間P2)、對子像素11進行像素電壓Vsig之寫入且進行μ校正(寫入‧μ校正期間P3)。且，其後，子像素11之有機EL元件OLED以根據所寫入之像素電壓Vsig之亮度發光(發光期間P4)。於以下進行其詳細之說明。 The drive unit 20 performs initialization (initialization period P1) of the sub-pixel 11 in one horizontal period (1H), and performs Vth correction (Vth correction period P2) for suppressing the influence of the component unevenness of the driving transistor DRTr. The sub-pixel 11 is written with the pixel voltage Vsig and subjected to μ correction (writing ‧ μ correction period P3). Then, the organic EL element OLED of the sub-pixel 11 emits light according to the luminance of the written pixel voltage Vsig (light-emitting period P4). A detailed description thereof will be given below.

首先，電源線驅動部26在先於初始化期間P1之時序t0中，使電源信號DS自電壓Vccp變為電壓Vini(圖7(B))。藉此，驅動電晶體DRTr成為接通狀態，且將驅動電晶體DRTr之源極電壓Vs設定成電壓Vini(圖7(E))。 First, the power supply line drive unit 26 changes the power supply signal DS from the voltage Vccp to the voltage Vini at the timing t0 before the initialization period P1 (FIG. 7(B)). Thereby, the driving transistor DRTr is turned on, and the source voltage Vs of the driving transistor DRTr is set to the voltage Vini (FIG. 7(E)).

接著，驅動部20在時序t1~t2之期間(初始化期間P1)，將子像素11初始化。具體而言，在時序t1中資料線驅動部27將信號Sig設定成電壓Vofs(圖7(C))，掃描線驅動部23使掃描信號WS之電壓自低位準變化為高位準(圖7(A))。藉此，寫入電晶體WSTr成為接通狀態，且將驅動電晶體DRTr之閘極電壓Vg設定成電壓Vofs(圖7(D))。如此般，藉由將驅動電晶體DRTr之閘極、源極間電壓Vgs(=Vofs-Vini)設定成大於驅動電晶體DRTr之閾值電壓Vth之電壓，以使子像素11初始化。 Next, the drive unit 20 initializes the sub-pixel 11 during the period t1 to t2 (initialization period P1). Specifically, at the timing t1, the data line driving unit 27 sets the signal Sig to the voltage Vofs (FIG. 7(C)), and the scanning line driving unit 23 changes the voltage of the scanning signal WS from a low level to a high level (FIG. 7 (FIG. 7) A)). Thereby, the write transistor WSTr is turned on, and the gate voltage Vg of the drive transistor DRTr is set to the voltage Vofs (FIG. 7(D)). In this manner, the sub-pixel 11 is initialized by setting the gate and source-to-source voltage Vgs (=Vofs-Vini) of the driving transistor DRTr to a voltage greater than the threshold voltage Vth of the driving transistor DRTr.

接著，驅動部20在時序t2~t3之期間(Vth校正期間P2)，進行Vth校正。具體而言，電源線驅動部26在時序t2中使電源信號DS自電壓Vini變化為電壓Vccp(圖7(B))。藉此，驅動電晶體DRTr在飽和區域動作，電流Ids自汲極流動於源極。藉由此電流Ids源極電壓Vs上升(圖7(E))。此時，由於源極電壓Vs低於有機EL元件OLED之陰極之電壓Vcath，故有機EL元件OLED維持逆向偏壓狀態，電流不流動於有機EL元件OLED。由於因如此般源極電壓Vs上升，閘極、源極間電壓 Vgs下降，故電流Ids下降。藉由此負反饋動作，電流Ids向「0」(零)收縮。換言之，為使驅動電晶體DRTr之閘極、源極間電壓Vgs與驅動電晶體DRTr之閾值電壓Vth相等(Vgs=Vth)而收縮。 Next, the drive unit 20 performs Vth correction during the period from t2 to t3 (Vth correction period P2). Specifically, the power supply line drive unit 26 changes the power supply signal DS from the voltage Vini to the voltage Vccp at the timing t2 (FIG. 7(B)). Thereby, the driving transistor DRTr operates in the saturation region, and the current Ids flows from the drain to the source. Thereby, the current Ids source voltage Vs rises (FIG. 7(E)). At this time, since the source voltage Vs is lower than the voltage Vcath of the cathode of the organic EL element OLED, the organic EL element OLED maintains a reverse bias state, and current does not flow to the organic EL element OLED. Since the source voltage Vs rises as a result, the voltage between the gate and the source As Vgs drops, the current Ids decreases. With this negative feedback action, the current Ids shrinks to "0" (zero). In other words, the gate and source-to-source voltage Vgs of the drive transistor DRTr are contracted by the threshold voltage Vth of the drive transistor DRTr (Vgs=Vth).

接著，掃描線驅動部23在時序t3中，使掃描信號WS之電壓自高位準變化為低位準(圖7(A))。藉此，寫入電晶體WSTr成為斷開狀態。且，資料線驅動部27在時序t4中將信號Sig設定成像素電壓Vsig(圖7(C))。 Next, at timing t3, the scanning line driving unit 23 changes the voltage of the scanning signal WS from a high level to a low level (FIG. 7(A)). Thereby, the write transistor WSTr is turned off. Further, the data line drive unit 27 sets the signal Sig to the pixel voltage Vsig at the timing t4 (FIG. 7(C)).

接著，驅動部20在時序t5~t6之期間(寫入、μ校正期間P3)，對子像素11進行像素電壓Vsig之寫入且進行μ校正。具體而言，掃描線驅動部23在時序t5中，使掃描信號WS之電壓自低位準變化為高位準(圖7(A))。藉此，寫入電晶體WSTt成為接通狀態，驅動電晶體DRTr之閘極電壓Vg自電壓Vofs上升至像素電壓Vsig(圖7(D))。此時，由於驅動電晶體DRTr之閘極、源極間電壓Vgs大於閾值電壓Vth(Vgs>Vth)，且電流Ids自汲極向源極流動，故驅動電晶體DRTr之源極電壓Vs上升(圖7(E))。藉由此種負反饋動作，抑制驅動電晶體DRTr之元件不均一之影響(μ(移動率)校正)，將驅動電晶體DRTr之閘極、源極間電壓Vgs設定成對應像素電壓Vsig之電壓Vemi。 Next, the drive unit 20 writes the pixel voltage Vsig to the sub-pixel 11 and performs μ correction during the period from t5 to t6 (write, μ correction period P3). Specifically, at timing t5, the scanning line driving unit 23 changes the voltage of the scanning signal WS from a low level to a high level (FIG. 7(A)). Thereby, the write transistor WSTt is turned on, and the gate voltage Vg of the drive transistor DRTr rises from the voltage Vofs to the pixel voltage Vsig (FIG. 7(D)). At this time, since the gate and source-to-source voltage Vgs of the driving transistor DRTr is larger than the threshold voltage Vth (Vgs>Vth), and the current Ids flows from the drain to the source, the source voltage Vs of the driving transistor DRTr rises ( Figure 7 (E)). By such a negative feedback action, the influence of the non-uniformity of the driving transistor DRTr (μ (movement rate) correction) is suppressed, and the gate and source voltage Vgs of the driving transistor DRTr are set to a voltage corresponding to the pixel voltage Vsig. Vemi.

其次，驅動部20在時序t6以後之期間(發光期間P4)，使子像素11發光。具體而言，在時序t6中，掃描線驅動部23使掃描信號WS之電壓自高位準變化為低位準(圖7(A))。藉此，由於寫入電晶體WSTr成為斷開狀態，驅動電晶體DRTr之閘極浮動，故此後維持電容元件Cs之端子間電壓，即驅動電晶體DRTr之閘極、源極間電壓Vgs。接著，電流Ids流動於驅動電晶體DRTr且驅動電晶體DRTr之源極電壓Vs上升(圖7(E))，隨之驅動電晶體DRTr之閘極電壓Vg亦上升(圖7(D))。且，當藉由此種自舉動作，驅動電晶體DRTr之源極電壓Vs大於有機EL元件OLED之閾值電壓Vel與電壓Vcath之和(Vel+Vcath)，則電流流動於 有機EL元件OLED之陽極、陰極間，從而有機EL元件OLED發光。即，源極電壓Vs根據有機EL元件OLED之元件不均一而上升，從而有機EL元件OLED發光。 Next, the drive unit 20 causes the sub-pixel 11 to emit light during the period after the timing t6 (light-emitting period P4). Specifically, at timing t6, the scanning line driving unit 23 changes the voltage of the scanning signal WS from a high level to a low level (FIG. 7(A)). As a result, since the write transistor WSTr is turned off and the gate of the drive transistor DRTr floats, the voltage between the terminals of the capacitor element Cs, that is, the gate and source-to-source voltage Vgs of the drive transistor DRTr is maintained. Then, the current Ids flows to the driving transistor DRTr and the source voltage Vs of the driving transistor DRTr rises (FIG. 7(E)), and the gate voltage Vg of the driving transistor DRTr also rises (FIG. 7(D)). Moreover, when the source voltage Vs of the driving transistor DRTr is larger than the sum of the threshold voltage Vel and the voltage Vcath of the organic EL element OLED (Vel+Vcath) by such a bootstrap action, the current flows The organic EL element OLED is between the anode and the cathode, whereby the organic EL element OLED emits light. That is, the source voltage Vs rises according to the non-uniformity of the elements of the organic EL element OLED, so that the organic EL element OLED emits light.

其後，在顯示裝置1中經過特定之期間(1幀期間)後，自發光期間P4向初始化期間P1過度。驅動部20以重複此一連串之動作之方式驅動。 Thereafter, after a predetermined period (one frame period) elapses in the display device 1, the self-light-emitting period P4 is excessive to the initialization period P1. The drive unit 20 is driven to repeat this series of actions.

如此般，在顯示裝置1中因係進行Vth校正及μ校正兩者，故可抑制起因於驅動電晶體DRTr之元件不均一之畫質之降低。又，在顯示裝置1中因係於發光期間P4，源極電壓Vs根據有機EL元件OLED之元件不均一而上升，故可抑制起因於有機EL元件OLED之元件不均一之畫質之降低。 In the display device 1, both the Vth correction and the μ correction are performed, so that the deterioration of the image quality due to the unevenness of the elements of the drive transistor DRTr can be suppressed. In addition, in the display device 1, the source voltage Vs rises in accordance with the non-uniformity of the elements of the organic EL element OLED, so that the deterioration of the image quality due to the unevenness of the elements of the organic EL element OLED can be suppressed.

(電荷泵電路32及驅動電路34之動作) (Operation of Charge Pump Circuit 32 and Drive Circuit 34)

接著，針對電荷泵電路32及驅動電路34之詳細動作進行說明。電荷泵電路32基於自位移暫存器31供給之4個掃描信號Ss，產生信號St。且，驅動電路34基於自電壓產生部33供給之電壓Vccp、及自電荷泵電路32供給之信號St，產生電源信號DS。 Next, detailed operations of the charge pump circuit 32 and the drive circuit 34 will be described. The charge pump circuit 32 generates a signal St based on the four scan signals Ss supplied from the shift register 31. Further, the drive circuit 34 generates the power supply signal DS based on the voltage Vccp supplied from the voltage generating unit 33 and the signal St supplied from the charge pump circuit 32.

圖8係表示電荷泵電路32及驅動電路34之動作之時序圖者，(A)~(D)分別顯示施加於電荷泵電路32之輸入端子SR1~SR4之信號SSR1~SSR4之波形，(E)顯示電晶體Tr1之源極之節點電壓VN1之波形，(F)顯示電晶體Tr3之源極之節點電壓VN2之波形，(G)顯示信號St之波形，(H)顯示電源信號DS之波形。 8 is a timing chart showing the operation of the charge pump circuit 32 and the drive circuit 34, and (A) to (D) respectively show waveforms of signals SSR1 to SSR4 applied to the input terminals SR1 to SR4 of the charge pump circuit 32, (E) The waveform of the node voltage VN1 of the source of the transistor Tr1 is displayed, (F) shows the waveform of the node voltage VN2 of the source of the transistor Tr3, (G) the waveform of the signal St is displayed, and (H) the waveform of the power signal DS is displayed. .

位移暫存器31對電荷泵電路32供給互相相位偏移之信號SSR1~SSR4。電荷泵電路32基於信號SSR1~SSR4，產生振幅大於信號SSR1~SSR4之振幅之信號St。驅動電路34基於信號St及電壓Vccp產生電源信號DS。以下，說明其詳細內容。 The shift register 31 supplies the charge pump circuit 32 with signals SSR1 to SSR4 which are mutually phase-shifted. The charge pump circuit 32 generates a signal St having an amplitude larger than the amplitudes of the signals SSR1 to SSR4 based on the signals SSR1 to SSR4. The drive circuit 34 generates a power supply signal DS based on the signal St and the voltage Vccp. The details will be described below.

首先，在時序t11中，信號SSR1之電壓自低位準電壓VL變化為高 位準電壓VH(圖8(A))。此時，電晶體Tr2之閘極電壓(節點電壓VN1)及源極電壓(信號St)皆為電壓VL(圖8(E)、(G))。即，電晶體Tr2之閘極、源極間電壓Vgs為0V，電晶體Tr2成為斷開狀態。 First, in the timing t11, the voltage of the signal SSR1 changes from the low level voltage VL to the high level. The level voltage VH (Fig. 8(A)). At this time, the gate voltage (node voltage VN1) and the source voltage (signal St) of the transistor Tr2 are both voltages VL (Figs. 8(E), (G)). In other words, the gate voltage and the source-to-source voltage Vgs of the transistor Tr2 are 0 V, and the transistor Tr2 is turned off.

接著，在時序t12中，信號SSR2之電壓自低位準電壓VL變化為高位準電壓VH(圖8(B))。藉此，電晶體Tr1瞬變成為接通狀態，電晶體Tr1之源極電壓(節點電壓VN1)變化為電壓V1(圖8(E))。此電壓V1以以下公式表示。 Next, at timing t12, the voltage of the signal SSR2 changes from the low level voltage VL to the high level voltage VH (Fig. 8(B)). Thereby, the transistor Tr1 is instantaneously turned on, and the source voltage (node voltage VN1) of the transistor Tr1 is changed to the voltage V1 (FIG. 8(E)). This voltage V1 is expressed by the following formula.

V1=VG1-Vth1‧‧‧(1) V1=VG1-Vth1‧‧‧(1)

此處，Vth1為電晶體Tr1之閾值電壓。即，電壓V1係較電晶體Tr1之閘極電壓(電壓VG1)低電晶體Tr1之閾值電壓Vth1之電壓。即，電晶體Tr1之閘極、源極間電壓Vgs等於電晶體Tr1之閾值電壓Vth1。 Here, Vth1 is the threshold voltage of the transistor Tr1. That is, the voltage V1 is lower than the gate voltage (voltage VG1) of the transistor Tr1 by the voltage of the threshold voltage Vth1 of the transistor Tr1. That is, the gate and source voltage Vgs of the transistor Tr1 is equal to the threshold voltage Vth1 of the transistor Tr1.

再者，根據此節點電壓VN1之變化，電晶體Tr2瞬變成為接通狀態，且電晶體Tr2之源極電壓(信號St)變化成電壓V2(圖8(G))。此電壓V2以以下公式表示。 Further, according to the change of the node voltage VN1, the transistor Tr2 is instantaneously turned on, and the source voltage (signal St) of the transistor Tr2 is changed to the voltage V2 (Fig. 8(G)). This voltage V2 is expressed by the following formula.

V2=V1-Vth2=VG1-Vth1-Vth2‧‧‧(2) V2=V1-Vth2=VG1-Vth1-Vth2‧‧‧(2)

此處，Vth2為電晶體Tr2之閾值電壓。即，電壓V2係較電晶體Tr2之閘極電壓(電壓V1)低電晶體Tr2之閾值電壓Vth2之電壓。即，電晶體Tr2之閘極、源極間電壓Vgs等於電晶體Tr2之閾值電壓Vth2。 Here, Vth2 is the threshold voltage of the transistor Tr2. That is, the voltage V2 is lower than the gate voltage (voltage V1) of the transistor Tr2 by the voltage of the threshold voltage Vth2 of the transistor Tr2. That is, the gate and source voltage Vgs of the transistor Tr2 is equal to the threshold voltage Vth2 of the transistor Tr2.

如此般，由於信號St之電壓位準較低，故在驅動電路34中電晶體Tr4、Tr5維持斷開狀態。藉此，維持電源信號DS之電壓(圖8(H))。 In this manner, since the voltage level of the signal St is low, the transistors Tr4 and Tr5 are maintained in the off state in the drive circuit 34. Thereby, the voltage of the power supply signal DS is maintained (Fig. 8(H)).

其次，在時序t13中，信號SSR3之電壓自低位準電壓VL變化為高位準電壓VH(圖8(C))。藉此，此電壓變化經由電容元件C1傳至電晶體Tr1之源極，從而電晶體Tr1之源極電壓(節點電壓VN1)變化成電壓V3(圖8(E))。此電壓V3以以下公式表示。 Next, at the timing t13, the voltage of the signal SSR3 changes from the low level voltage VL to the high level voltage VH (Fig. 8(C)). Thereby, this voltage change is transmitted to the source of the transistor Tr1 via the capacitive element C1, so that the source voltage (node voltage VN1) of the transistor Tr1 is changed to the voltage V3 (FIG. 8(E)). This voltage V3 is expressed by the following formula.

V3=V1+(VH-VL)×Gain1 =VG1-Vth1+(VH-VL)×Gain1‧‧‧(3) V3=V1+(VH-VL)×Gain1 =VG1-Vth1+(VH-VL)×Gain1‧‧‧(3)

此處，Gain1係表示電容元件C1之一端之電壓變化、與電容元件C1之另一端之電壓變化之比之增益，且係由電容元件C1之電容值及電晶體Tr1、Tr2之寄生電容等所決定者。如此般，藉由電晶體Tr1之源極電壓變高，電晶體Tr1之閘極、源極間電壓Vgs變得低於電晶體Tr1之閾值電壓Vth1，且電晶體Tr1成為斷開狀態。 Here, Gain1 is a gain indicating a ratio of a voltage change at one end of the capacitor element C1 to a voltage change at the other end of the capacitor element C1, and is a capacitance value of the capacitor element C1 and a parasitic capacitance of the transistors Tr1 and Tr2. decision maker. As a result, the source voltage of the transistor Tr1 becomes higher, the gate voltage Vgs of the transistor Tr1 becomes lower than the threshold voltage Vth1 of the transistor Tr1, and the transistor Tr1 is turned off.

再者，根據此節點電壓VN1之變化，電晶體Tr2瞬變成為接通狀態，且電晶體Tr2之源極電壓(信號St)變化成電壓V4(圖8(G))。此電壓V4以以下公式表示。 Further, according to the change of the node voltage VN1, the transistor Tr2 is instantaneously turned on, and the source voltage (signal St) of the transistor Tr2 is changed to the voltage V4 (Fig. 8(G)). This voltage V4 is expressed by the following formula.

V4=V3-Vth2=VG1-Vth1-Vth2+(VH-VL)×Gain1‧‧‧(4) V4=V3-Vth2=VG1-Vth1-Vth2+(VH-VL)×Gain1‧‧‧(4)

即，電壓V4係較電晶體Tr2之閘極電壓(電壓V3)低電晶體Tr2之閾值電壓Vth2之電壓。即，電晶體Tr2之閘極、源極間電壓Vgs等於電晶體Tr2之閾值電壓Vth2。 That is, the voltage V4 is lower than the gate voltage (voltage V3) of the transistor Tr2 by the voltage of the threshold voltage Vth2 of the transistor Tr2. That is, the gate and source voltage Vgs of the transistor Tr2 is equal to the threshold voltage Vth2 of the transistor Tr2.

如此般，藉由信號St之電壓變高，電源信號DS上升(圖8(H))。具體而言，在驅動電路34中，電晶體Tr4成為接通狀態且電晶體Tr5成為斷開狀態，電源信號DS向電壓Vccp上升。在此例中，由於電晶體Tr4之開啟電阻未充分地變低，故電源信號DS之電壓成為稍微低於電壓Vccp之位準。 In this manner, the power signal DS rises by the voltage of the signal St becoming high (Fig. 8(H)). Specifically, in the drive circuit 34, the transistor Tr4 is turned on and the transistor Tr5 is turned off, and the power supply signal DS rises toward the voltage Vccp. In this example, since the turn-on resistance of the transistor Tr4 is not sufficiently lowered, the voltage of the power supply signal DS becomes a level slightly lower than the voltage Vccp.

又，根據信號SSR3之變化，在電荷泵電路32中電晶體Tr3成為接通狀態，且電晶體Tr3之源極電壓(節點電壓VN2)變化為電壓VL(圖8(F))。 Further, according to the change of the signal SSR3, the transistor Tr3 is turned on in the charge pump circuit 32, and the source voltage (node voltage VN2) of the transistor Tr3 is changed to the voltage VL (Fig. 8(F)).

其次，在時序t14中，信號SSR4之電壓自低位準電壓VL變化為高位準電壓VH(圖8(D))。藉此，電晶體Tr3瞬變成為接通狀態，且電晶體Tr3之源極電壓(節點電壓VN2)變化為電壓V5(圖8(F))。此電壓V5以以下公式表示。 Next, at timing t14, the voltage of the signal SSR4 changes from the low level voltage VL to the high level voltage VH (Fig. 8(D)). Thereby, the transistor Tr3 is instantaneously turned on, and the source voltage (node voltage VN2) of the transistor Tr3 is changed to the voltage V5 (FIG. 8(F)). This voltage V5 is expressed by the following formula.

V5=VH-Vth3‧‧‧(5) V5=VH-Vth3‧‧‧(5)

此處，Vth3為電晶體Tr3之閾值電壓。即，電壓V5係較電晶體Tr3之閘極電壓(電壓VH)低電晶體Tr3之閾值電壓Vth3之電壓。即，電晶體Tr3之閘極、源極間電壓Vgs等於電晶體Tr3之閾值電壓Vth3。 Here, Vth3 is the threshold voltage of the transistor Tr3. That is, the voltage V5 is lower than the gate voltage (voltage VH) of the transistor Tr3 by the threshold voltage Vth3 of the transistor Tr3. That is, the gate and source voltage Vgs of the transistor Tr3 is equal to the threshold voltage Vth3 of the transistor Tr3.

再者，根據此節點電壓VN2之變化，此電壓變化經由電容元件C2傳至電晶體Tr2之源極，從而電晶體Tr2之源極電壓(信號St)變化為高於電壓VH之電壓V6(圖8(G))。此電壓V6以以下公式表示。 Furthermore, according to the change of the node voltage VN2, the voltage change is transmitted to the source of the transistor Tr2 via the capacitive element C2, so that the source voltage (signal St) of the transistor Tr2 changes to a voltage V6 higher than the voltage VH (Fig. 8(G)). This voltage V6 is expressed by the following formula.

V6=V4+(V5-VL)×Gain2=VG1-Vth1-Vth2+(VH-VL)×Gain1+(VH-VL-Vth3)×Gain2‧‧‧(6) V6=V4+(V5-VL)×Gain2=VG1-Vth1-Vth2+(VH-VL)×Gain1+(VH-VL-Vth3)×Gain2‧‧‧(6)

此處，Gain2係表示電容元件C2之一端之電壓變化、與電容元件C2之另一端之電壓變化之比之增益，且係由電容元件C2之電容值及電晶體Tr2、Tr4、Tr5之寄生電容等所決定者。在此例中，增益Gain1、Gain2係以使電壓V6成為高於電壓VH之電壓之方式設定。如此般，藉由電晶體Tr2之源極電壓變高，電晶體Tr2之閘極、源極間電壓Vgs變得低於電晶體Tr2之閾值電壓Vth2，且電晶體Tr2成為斷開狀態。 Here, Gain2 is a gain indicating a ratio of a voltage change at one end of the capacitive element C2 to a voltage change at the other end of the capacitive element C2, and is a capacitance value of the capacitive element C2 and a parasitic capacitance of the transistors Tr2, Tr4, and Tr5. Wait for the decision. In this example, the gains Gain1 and Gain2 are set such that the voltage V6 becomes a voltage higher than the voltage VH. As a result, the source voltage of the transistor Tr2 becomes higher, the gate voltage Vgs of the transistor Tr2 becomes lower than the threshold voltage Vth2 of the transistor Tr2, and the transistor Tr2 is turned off.

如此般，藉由信號St成為高於電壓VH之電壓V6，驅動電路34之電晶體Tr4之開啟電阻充分地變低，且電源信號DS成為電壓Vccp(圖8(H))。 As a result, by the signal St becoming the voltage V6 higher than the voltage VH, the turn-on resistance of the transistor Tr4 of the drive circuit 34 is sufficiently lowered, and the power supply signal DS becomes the voltage Vccp (Fig. 8(H)).

接著，在時序t15中信號SSR1之電壓自高位準電壓VH變化為低位準電壓VL(圖8(A))。藉此，電晶體Tr2成為接通狀態，且電晶體Tr2之源極電壓(信號St)變化為電壓VL(圖8(G))。 Next, at time t15, the voltage of the signal SSR1 changes from the high level voltage VH to the low level voltage VL (Fig. 8(A)). Thereby, the transistor Tr2 is turned on, and the source voltage (signal St) of the transistor Tr2 is changed to the voltage VL (FIG. 8(G)).

再者，根據此信號St之電壓之變化，電源信號DS下降(圖8(H))。具體而言，在驅動電路34中電晶體Tr4成為斷開狀態，且電晶體Tr5瞬變成為接通狀態，電源信號DS變化為電壓Vini。此處電壓Vini以以下 公式表示。 Further, according to the change in the voltage of the signal St, the power supply signal DS is lowered (Fig. 8(H)). Specifically, in the drive circuit 34, the transistor Tr4 is turned off, and the transistor Tr5 is instantaneously turned on, and the power supply signal DS is changed to the voltage Vini. Here the voltage Vini is below The formula is expressed.

Vini=VL+Vth5‧‧‧(7) Vini=VL+Vth5‧‧‧(7)

此處，Vth5為電晶體Tr5之閾值電壓。即，電壓Vini係較電晶體Tr5之源極電壓(電壓VL)高電晶體Tr5之閾值電壓Vth5之電壓。即，電晶體Tr5之閘極、源極間電壓Vgs等於電晶體Tr5之閾值電壓Vth5。 Here, Vth5 is the threshold voltage of the transistor Tr5. That is, the voltage Vini is higher than the source voltage (voltage VL) of the transistor Tr5 by the threshold voltage Vth5 of the transistor Tr5. That is, the gate and source voltage Vgs of the transistor Tr5 is equal to the threshold voltage Vth5 of the transistor Tr5.

接著，在時序t16中信號SSR2之電壓自高位準電壓VH變化為低位準電壓VL(圖8(B))。藉此，電晶體Tr1成為接通狀態，且電晶體Tr1之源極電壓(節點電壓VN1)變化為電壓VL(圖8(E))。 Next, at time t16, the voltage of the signal SSR2 changes from the high level voltage VH to the low level voltage VL (Fig. 8(B)). Thereby, the transistor Tr1 is turned on, and the source voltage (node voltage VN1) of the transistor Tr1 is changed to the voltage VL (FIG. 8(E)).

其次，在時序t17中，信號SSR3之電壓自高位準電壓VH變化為低位準電壓VL(圖8(C))。藉此，此電壓變化經由電容元件C1傳至電晶體Tr1之源極(節點電壓VN1)，藉此節點電壓VN1自電壓VL瞬變(圖8(E))。然而，由於電晶體Tr1為接通狀態，故此節點電壓VN1再次收縮至電壓VL。 Next, at the timing t17, the voltage of the signal SSR3 is changed from the high level voltage VH to the low level voltage VL (Fig. 8(C)). Thereby, this voltage change is transmitted to the source of the transistor Tr1 (node voltage VN1) via the capacitive element C1, whereby the node voltage VN1 is transiently changed from the voltage VL (FIG. 8(E)). However, since the transistor Tr1 is in an on state, the node voltage VN1 is again shrunk to the voltage VL.

又，藉由信號SSR3之電壓變化為低位準電壓VL，電晶體Tr3成為斷開狀態，且電晶體Tr3之源極成為高阻抗。藉此，維持電晶體Tr3之源極電壓(節點電壓VN2)(圖8(F))。 Further, when the voltage of the signal SSR3 changes to the low level voltage VL, the transistor Tr3 is turned off, and the source of the transistor Tr3 becomes high impedance. Thereby, the source voltage (node voltage VN2) of the transistor Tr3 is maintained (FIG. 8(F)).

接著，在時序t18中，信號SSR4之電壓自高位準電壓VH變化為低位準電壓VL(圖8(D))。此時，電晶體Tr3為維持斷開狀態，故維持電晶體Tr3之源極電壓(節點電壓VN2)(圖8(F))，且亦維持電晶體Tr2之源極電壓(信號St)(圖8(G))。 Next, at timing t18, the voltage of the signal SSR4 is changed from the high level voltage VH to the low level voltage VL (Fig. 8(D)). At this time, since the transistor Tr3 is maintained in the off state, the source voltage (node voltage VN2) of the transistor Tr3 is maintained (FIG. 8(F)), and the source voltage (signal St) of the transistor Tr2 is also maintained (FIG. 8). 8(G)).

電荷泵電路32及驅動電路34藉由重複以上之動作，接著產生電源信號DS。 The charge pump circuit 32 and the drive circuit 34 repeat the above operations, and then generate the power supply signal DS.

如此般，在顯示裝置1中因設置電荷泵電路32，故可將信號St之電壓升壓至高於高位準電壓VH之電壓V6，且可對驅動電路34供給振幅較大之信號St。藉此，驅動電路34將電壓Vccp作為電源信號DS輸出時，即使電壓Vccp較高之情形仍可充分地降低電晶體Tr4之開啟電 阻。即，驅動電路34可產生振幅較大之電源信號DS。 As described above, since the charge pump circuit 32 is provided in the display device 1, the voltage of the signal St can be boosted to a voltage V6 higher than the high level voltage VH, and the signal St having a large amplitude can be supplied to the drive circuit 34. Thereby, when the drive circuit 34 outputs the voltage Vccp as the power supply signal DS, the turn-on of the transistor Tr4 can be sufficiently reduced even if the voltage Vccp is high. Resistance. That is, the drive circuit 34 can generate the power supply signal DS having a large amplitude.

又，如此般，由於電荷泵電路32及驅動電路34基於振幅較小之掃描信號Ss，可產生振幅較大之電源信號DS，故例如，可降低位移暫存器31等之電源電壓，從而可降低顯示裝置1之消耗電力。 Further, since the charge pump circuit 32 and the drive circuit 34 can generate the power supply signal DS having a large amplitude based on the scan signal Ss having a small amplitude, for example, the power supply voltage of the shift register 31 can be reduced. The power consumption of the display device 1 is lowered.

又，在電荷泵電路32中因係設置2個電容元件C1、C2，故可產生振幅更大之信號St。即，在電荷泵電路32中，因係於時序t13中使用電容元件C1使信號St之電壓升壓，於時序t14中使用電容元件C2使信號St之電壓再次升壓，故與1次升壓之情形相比，可將信號St之電壓升壓至更高之位準，從而可產生振幅較大之信號St。 Further, since the two capacitor elements C1 and C2 are provided in the charge pump circuit 32, the signal St having a larger amplitude can be generated. In other words, in the charge pump circuit 32, the voltage of the signal St is boosted by the capacitive element C1 at the timing t13, and the voltage of the signal St is boosted again by the capacitive element C2 at the timing t14, so that the voltage is boosted once. In contrast, the voltage of the signal St can be boosted to a higher level, so that a signal St having a larger amplitude can be generated.

又，在電荷泵電路32中，因設置電晶體Tr3且於時序t17中將電晶體Tr3設為斷開狀態，故可使信號St不會因時序t18之信號SSR4之下降而變化。藉此，由於可降低電源信號DS之波形之混亂，故可降低顯示裝置1之畫質下降之可能。 Further, in the charge pump circuit 32, since the transistor Tr3 is provided and the transistor Tr3 is turned off at the timing t17, the signal St can be prevented from being changed by the decrease of the signal SSR4 at the timing t18. Thereby, since the waveform of the power signal DS can be reduced, the image quality of the display device 1 can be reduced.

[效果] [effect]

在以上之本實施形態中，因係設置電荷泵電路故可產生振幅較大之電源信號DS。 In the above embodiment, since the charge pump circuit is provided, the power supply signal DS having a large amplitude can be generated.

在本實施形態中，因係於電荷泵電路中設置2個電容元件，故可產生振幅較大之信號St。 In the present embodiment, since two capacitor elements are provided in the charge pump circuit, a signal St having a large amplitude can be generated.

在本實施形態中，因係於電荷泵電路中設置電晶體Tr3，故可降低電源信號之波形之混亂，從而可降低顯示裝置之畫質下降之可能。 In the present embodiment, since the transistor Tr3 is provided in the charge pump circuit, the waveform of the power supply signal can be reduced, and the image quality of the display device can be reduced.

[變化例1] [Variation 1]

雖在上述實施形態中，於電荷泵電路32中設置電晶體Tr3，但並非限定於此，亦可替代此，例如如圖9所示般省略電晶體Tr3。在此電荷泵電路32B中，電容元件C1之另一端連接於輸入端子SR3。又，電容元件C2之另一端連接於輸入端子SR4。此情形時，雖根據輸入於輸入端子SR4之信號SSR4之轉變，於信號St中存在瞬變，且電源信號DS 亦可能瞬時變化，但在允許此種變化之情形時可應用該構成。 In the above embodiment, the transistor Tr3 is provided in the charge pump circuit 32. However, the present invention is not limited thereto. Alternatively, for example, the transistor Tr3 may be omitted as shown in FIG. In this charge pump circuit 32B, the other end of the capacitive element C1 is connected to the input terminal SR3. Further, the other end of the capacitive element C2 is connected to the input terminal SR4. In this case, although there is a transient in the signal St according to the transition of the signal SSR4 input to the input terminal SR4, and the power supply signal DS It is also possible to change instantaneously, but this configuration can be applied when such a change is allowed.

[變化例2] [Variation 2]

雖在上述實施形態中，電荷泵電路32基於4個掃描信號Ss產生信號St，但並非限定於此，亦可替代此基於3個以下或5個以上之掃描信號Ss產生信號St。於以下，作為一例詳細地說明基於2個掃描信號Ss產生信號St之情形。 In the above embodiment, the charge pump circuit 32 generates the signal St based on the four scanning signals Ss. However, the present invention is not limited thereto, and instead of generating the signal St based on three or less or five or more scanning signals Ss. Hereinafter, a case where the signal St is generated based on the two scanning signals Ss will be described in detail as an example.

圖10係表示本變化例之電源線驅動部26C之一構成例者。電源驅動部26C具有位移暫存器31C、及複數個電荷泵電路32C。位移暫存器31C係具有與上述實施形態之位移暫存器31相同之功能者。各電荷泵電路32C係基於2個掃描信號Ss，產生振幅大於此等之掃描信號Ss之振幅之信號St者。具體而言，例如電荷泵電路32C(k)基於2個掃描信號Ss(n)、Ss(n+1)而產生信號St(k)。同樣，電荷泵電路32(C)(k+1)基於2個掃描信號Ss(n+1)、Ss(n+2)而產生信號St(k+1)。各電荷泵電路32C具有輸入有2個掃描信號Ss之輸入端子SR1、SR2、與輸出信號St之輸出端子Out。例如，於電荷泵電路32C(k)之輸入端子SR1中輸入掃描信號Ss(n)，於輸入端子SR2中輸入掃描信號Ss(n+1)。 Fig. 10 is a view showing an example of the configuration of the power line driving unit 26C of the present modification. The power source driving unit 26C has a shift register 31C and a plurality of charge pump circuits 32C. The displacement register 31C has the same function as the displacement register 31 of the above embodiment. Each of the charge pump circuits 32C generates a signal St having an amplitude larger than the amplitude of the scanning signal Ss based on the two scanning signals Ss. Specifically, for example, the charge pump circuit 32C(k) generates a signal St(k) based on the two scanning signals Ss(n) and Ss(n+1). Similarly, the charge pump circuit 32(C)(k+1) generates the signal St(k+1) based on the two scan signals Ss(n+1) and Ss(n+2). Each of the charge pump circuits 32C has an input terminal SR1, SR2 to which two scanning signals Ss are input, and an output terminal Out of the output signal St. For example, the scan signal Ss(n) is input to the input terminal SR1 of the charge pump circuit 32C(k), and the scan signal Ss(n+1) is input to the input terminal SR2.

圖11係表示電荷泵電路32C之一構成例者。電荷泵電路32C具有電晶體Tr7、Tr8、及電容元件C4。電晶體Tr7、Tr8係例如由N通道MOS型之TFT構成者。對電晶體Tr7之閘極供給直流之電壓VG1，汲極連接於輸入端子SR1，源極連接於電容元件C4之一端且連接於輸出端子Out。電晶體Tr8之閘極連接於輸入端子SR1，汲極連接於輸入端子SR2，源極連接於電容元件C4之另一端。電容元件C4之一端連接於電晶體Tr7之源極且連接於輸出端子Out，另一端連接於電晶體Tr8之源極。 Fig. 11 shows an example of a configuration of the charge pump circuit 32C. The charge pump circuit 32C has transistors Tr7 and Tr8 and a capacitor element C4. The transistors Tr7 and Tr8 are composed of, for example, an N-channel MOS type TFT. A DC voltage VG1 is supplied to the gate of the transistor Tr7, a drain is connected to the input terminal SR1, and a source is connected to one end of the capacitive element C4 and connected to the output terminal Out. The gate of the transistor Tr8 is connected to the input terminal SR1, the drain is connected to the input terminal SR2, and the source is connected to the other end of the capacitive element C4. One end of the capacitive element C4 is connected to the source of the transistor Tr7 and is connected to the output terminal Out, and the other end is connected to the source of the transistor Tr8.

即使為本變化例之電荷泵電路32C，仍可與上述實施形態之電荷泵電路32相同地供給振幅較大之信號St。 Even in the charge pump circuit 32C of the present modification, the signal St having a large amplitude can be supplied in the same manner as the charge pump circuit 32 of the above-described embodiment.

[變化例3] [Variation 3]

雖在上述實施形態中使用電荷泵電路32構成電源線驅動部26，但並非限定於此，亦可替代此，或除此之外，使用電荷泵電路32構成掃描線驅動部23。 Although the power source line driving unit 26 is configured by the charge pump circuit 32 in the above embodiment, the power line driving unit 26 is not limited thereto, and the scanning line driving unit 23 may be configured by using the charge pump circuit 32.

[變化例4] [Variation 4]

雖在上述實施形態中，將本技術應用於使用有機EL元件之顯示裝置，但並非限定於此，亦可替代此，例如應用於使用液晶顯示元件之顯示裝置。具體而言，例如可應用於選擇寫入像素電壓之像素之電路(相當於上述實施形態之掃描驅動部23)。 In the above embodiment, the present technology is applied to a display device using an organic EL element, but the present invention is not limited thereto, and may be applied to, for example, a display device using a liquid crystal display element. Specifically, for example, it can be applied to a circuit for selecting a pixel to which a pixel voltage is written (corresponding to the scan driving unit 23 of the above embodiment).

〈2.應用例〉 <2. Application examples>

接著，針對已在上述實施形態及變化例中說明之顯示裝置之應用例進行說明。 Next, an application example of the display device described in the above embodiments and modifications will be described.

圖12係表示應用上述實施形態等之顯示裝置之電視裝置之外觀者。此電視裝置例如具有包含前面板511及濾光玻璃512之影像顯示畫面部510，且此影像顯示畫面部510由上述實施形態等之顯示裝置構成。 Fig. 12 is a view showing an appearance of a television device to which the display device of the above-described embodiment and the like is applied. This television device has, for example, a video display screen portion 510 including a front panel 511 and a filter glass 512, and the video display screen portion 510 is constituted by a display device such as the above-described embodiment.

上述實施形態等之顯示裝置除如此之電視裝置外，可應用於數位相機、筆記型個人電腦、移動電話等之移動終端裝置、便攜式遊戲機、或攝像機等之所有領域之電子機器。換言之，上述實施形態之顯示裝置可應用於顯示影像之所有領域之電子機器。 The display device of the above-described embodiments and the like can be applied to electronic devices in all fields such as a digital camera, a notebook personal computer, a mobile phone device such as a mobile phone, a portable game machine, or a video camera, in addition to such a television device. In other words, the display device of the above embodiment can be applied to an electronic device that displays all fields of video.

以上，雖例舉了實施形態及變化例、以及應用於電子機器之應用例說明本技術，但本技術不限定於此等之實施形態等，可進行各種變化。 The present embodiment has been described with reference to the embodiments and the modifications, and the application examples applied to the electronic device. However, the present technology is not limited to the embodiments and the like, and various changes can be made.

例如，雖在上述各實施形態中於子像素11中設置電容元件Csub，但並非限定於此，亦可替代此，例如如圖13所示般，不於子像素11C中設置電容元件Csub。即，在此例中子像素11C係使用2個電晶 體(寫入電晶體WSTr、驅動電晶體DRTr)及1個電容元件Cs而構成，係所謂的具有「2Tr1C」之構成者。 For example, although the capacitive element Csub is provided in the sub-pixel 11 in each of the above embodiments, the present invention is not limited thereto. For example, as shown in FIG. 13, the capacitive element Csub is not provided in the sub-pixel 11C. That is, in this example, the sub-pixel 11C uses two electric crystals. The body (writing transistor WSTr, driving transistor DRTr) and one capacitive element Cs are configured to have a structure of "2Tr1C".

另，本技術可採用以下般之構成。 In addition, the present technology can be constructed as follows.

(1)一種顯示裝置，其具備：第1電晶體，其具有閘極、汲極、及源極；第1電容元件，其具有第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；及單元像素，其係基於上述第2端子之電壓而被驅動。 (1) A display device comprising: a first transistor having a gate, a drain, and a source; and a first capacitor having a first terminal and a second terminal, wherein the second terminal is connected to the first a drain or source of the transistor; and a unit pixel driven based on the voltage of the second terminal.

(2)如上述技術方案(1)之顯示裝置，其中進而具備：第2電晶體，其具有汲極及源極；及第2電容元件，其具有第3端子及第4端子，該第4端子連接於上述第2電晶體之汲極或源極、及上述第1電晶體之閘極。 (2) The display device according to the first aspect of the invention, further comprising: a second transistor having a drain and a source; and a second capacitor having a third terminal and a fourth terminal, the fourth The terminal is connected to a drain or a source of the second transistor and a gate of the first transistor.

(3)如上述技術方案(2)之顯示裝置，其中進而具備第3電晶體，其具有汲極、源極、及連接於上述第3端子之閘極。 (3) The display device according to the above aspect (2), further comprising a third transistor having a drain, a source, and a gate connected to the third terminal.

(4)如上述技術方案(3)之顯示裝置，其中對上述第1電晶體之汲極及源極中之與連接於上述第2端子之端子不同之端子施加第1脈衝信號；且對上述第2電晶體之汲極及源極中之與連接於上述第4端子之端子不同之端子施加第2脈衝信號；對上述第3端子施加第3脈衝信號；對上述第3電晶體之汲極及源極中之與連接於上述第1端子之端子不同之端子施加第4脈衝信號。 (4) The display device according to the above aspect (3), wherein the first pulse signal is applied to a terminal different from a terminal connected to the second terminal among the drain and the source of the first transistor; a second pulse signal is applied to a terminal different from a terminal connected to the fourth terminal of the drain and the source of the second transistor; a third pulse signal is applied to the third terminal; and a drain of the third transistor is applied A fourth pulse signal is applied to a terminal different from a terminal connected to the first terminal in the source.

(5)如上述技術方案(4)之顯示裝置，其中上述第2脈衝信號，係在上述第1脈衝信號進行第1極性之轉變後進行上述第1極性之轉變；且上述第3脈衝信號，係在上述第2脈衝信號進行上述第1極性之轉變後進行上述第1極性之轉變； 上述第4脈衝信號，係在上述第3脈衝信號進行上述第1極性之轉變後進行上述第1極性之轉變。 (5) The display device according to the above aspect (4), wherein the second pulse signal is subjected to the transition of the first polarity after the first pulse signal is converted, and the third pulse signal is caused by the transition of the first polarity; Performing the transition of the first polarity after the second pulse signal is converted into the first polarity; The fourth pulse signal is subjected to the transition of the first polarity after the third pulse signal is subjected to the transition of the first polarity.

(6)如上述技術方案(4)之顯示裝置，其中進而具備位移暫存器，其產生上述第1脈衝信號、上述第2脈衝信號、上述第3脈衝信號及上述第4脈衝信號。 (6) The display device according to the above aspect (4), further comprising: a displacement register that generates the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal.

(7)如上述技術方案(1)至(6)中任一項之顯示裝置，其中進而具備：開關，其基於上述第2端子之電壓，開關控制施加有直流信號之第5端子與連接於上述單元像素之第6端子之間；及非線形元件，其插設於上述第2端子與上述第6端子之間。 (7) The display device according to any one of the above aspects, further comprising: a switch that controls a fifth terminal to which a DC signal is applied based on a voltage of the second terminal, and is connected to The sixth terminal of the unit pixel and the non-linear element are interposed between the second terminal and the sixth terminal.

(8)如上述技術方案(7)之顯示裝置，其中上述非線形元件係第4電晶體，其具有連接於上述第2端子之源極；及連接於上述第6端子之汲極及閘極。 (8) The display device according to the above aspect (7), wherein the non-linear element is a fourth transistor having a source connected to the second terminal; and a drain and a gate connected to the sixth terminal.

(9)如上述技術方案(1)至(8)中任一項之顯示裝置，其中上述單元像素具有顯示元件、及對上述顯示元件供給驅動電流之驅動電晶體；且上述開關對上述驅動電晶體供給上述驅動電流。 (9) The display device according to any one of the above aspects, wherein the unit pixel has a display element and a driving transistor that supplies a driving current to the display element; and the switch has the driving power The crystal supplies the above drive current.

(10)一種顯示驅動裝置，其具備：第1電晶體，其具有閘極、汲極、及源極；及第1電容元件，其具有第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極。 (10) A display driving device comprising: a first transistor having a gate, a drain, and a source; and a first capacitor having a first terminal and a second terminal, wherein the second terminal is connected to The drain or source of the first transistor.

(11)一種驅動方法，其對第1電晶體之汲極或源極施加脈衝信號；且對具有第1端子、及連接於與上述第1電晶體之汲極及源極中之施加有上述脈衝信號之端子不同之端子之第2端子的第1電容元件之上述第1端子施加其他之脈衝信號；基於上述第2端子之電壓驅動單元像素。 (11) A driving method of applying a pulse signal to a drain or a source of a first transistor; and applying the first terminal to the drain and the source of the first transistor; Another pulse signal is applied to the first terminal of the first capacitive element of the second terminal of the terminal having a different terminal of the pulse signal, and the unit pixel is driven by the voltage of the second terminal.

(12)一種電子機器，其具備：顯示裝置；及控制部，其對上述顯示裝置進行動作控制；且上述顯示裝置包含：第1電晶體，其具有閘極、汲極、及源極；第1電容元件，其具有第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；及單元像素，其係基於上述第2端子之電壓而被驅動。 (12) An electronic device comprising: a display device; and a control unit that controls operation of the display device; and the display device includes: a first transistor having a gate, a drain, and a source; A capacitor element having a first terminal and a second terminal, wherein the second terminal is connected to a drain or a source of the first transistor; and a unit pixel driven based on a voltage of the second terminal.

本申請案係以2013年1月15日於日本專利庁所申請之日本專利申請案號2013-4542號為基礎，而主張優先權者，並藉由參照將該申請案之所有內容援用於本申請案。 The present application claims priority on the basis of Japanese Patent Application No. 2013-4542, filed on Jan. Application.

若為同業人士，則根據設計上之要求或其他因素，可想到各種修正、組合、次組合、及變更，但應理解該等係包含於附加之請求項之範圍或其均等物之範圍內者。 In the case of a person in the industry, various modifications, combinations, sub-combinations, and alterations are contemplated in light of the design requirements or other factors, but it should be understood that they are included within the scope of the appended claims or their equivalents. .

32‧‧‧電荷泵電路 32‧‧‧Charge pump circuit

34‧‧‧驅動電路 34‧‧‧Drive circuit

C1‧‧‧電容元件 C1‧‧‧Capacitive components

C2‧‧‧電容元件 C2‧‧‧Capacitive components

DS‧‧‧電源信號 DS‧‧‧ power signal

In‧‧‧輸入端子 In‧‧‧ input terminal

InH‧‧‧輸入端子 InH‧‧‧ input terminal

Out‧‧‧輸出端子 Out‧‧‧Output terminal

SR1‧‧‧輸入端子 SR1‧‧‧ input terminal

SR2‧‧‧輸入端子 SR2‧‧‧ input terminal

SR3‧‧‧輸入端子 SR3‧‧‧ input terminal

SR4‧‧‧輸入端子 SR4‧‧‧ input terminal

SSR1‧‧‧信號 SSR1‧‧‧ signal

SSR2‧‧‧信號 SSR2‧‧‧ signal

SSR3‧‧‧信號 SSR3‧‧‧ signal

SSR4‧‧‧信號 SSR4‧‧‧ signal

St‧‧‧信號 St‧‧ signals

Tr1‧‧‧電晶體 Tr1‧‧‧O crystal

Tr2‧‧‧電晶體 Tr2‧‧‧O crystal

Tr3‧‧‧電晶體 Tr3‧‧‧O crystal

Tr4‧‧‧電晶體 Tr4‧‧‧O crystal

Tr5‧‧‧電晶體 Tr5‧‧‧O crystal

Vccp‧‧‧電壓 Vccp‧‧‧ voltage

VG1‧‧‧電壓 VG1‧‧‧ voltage

VN1‧‧‧節點電壓 VN1‧‧‧ node voltage

VN2‧‧‧節點電壓 VN2‧‧‧ node voltage

Claims (10)

一種顯示裝置，其包含：第1電晶體，其包含閘極、汲極、及源極；第1電容元件，其包含第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；單元像素，其係基於上述第2端子之電壓而被驅動；第2電晶體，其包含汲極及源極；第2電容元件，其包含第3端子及第4端子，該第4端子連接於上述第2電晶體之汲極或源極、及上述第1電晶體之閘極；及第3電晶體，其包含汲極、源極、及連接於上述第3端子之閘極。 A display device includes: a first transistor including a gate, a drain, and a source; and a first capacitor including a first terminal and a second terminal, wherein the second terminal is connected to the first transistor a drain or a source; a unit pixel driven based on a voltage of the second terminal; a second transistor including a drain and a source; and a second capacitor including a third terminal and a fourth terminal The fourth terminal is connected to the drain or the source of the second transistor and the gate of the first transistor; and the third transistor includes a drain, a source, and a third terminal. The gate. 如請求項1之顯示裝置，其中上述第1電晶體之汲極及源極中之與連接於上述第2端子之端子不同之端子被施加有第1脈衝信號；且上述第2電晶體之汲極及源極中之與連接於上述第4端子之端子不同之端子被施加有第2脈衝信號；上述第3端子被施加有第3脈衝信號；上述第3電晶體之汲極及源極中之與連接於上述第1端子之端子不同之端子被施加有第4脈衝信號。 The display device according to claim 1, wherein a first pulse signal is applied to a terminal different from a terminal connected to the second terminal of the drain and the source of the first transistor; and the second transistor is A second pulse signal is applied to a terminal of the electrode and the source different from a terminal connected to the fourth terminal; a third pulse signal is applied to the third terminal; and a drain and a source of the third transistor are The fourth pulse signal is applied to a terminal different from the terminal connected to the first terminal. 如請求項2之顯示裝置，其中上述第2脈衝信號係在上述第1脈衝信號進行第1極性之轉變後進行上述第1極性之轉變；且上述第3脈衝信號係在上述第2脈衝信號進行上述第1極性之轉變後進行上述第1極性之轉變；上述第4脈衝信號係在上述第3脈衝信號進行上述第1極性之轉變後進行上述第1極性之轉變。 The display device according to claim 2, wherein the second pulse signal is subjected to the transition of the first polarity after the first pulse signal is converted by the first polarity, and the third pulse signal is performed by the second pulse signal. The transition of the first polarity is performed after the transition of the first polarity, and the transition of the first polarity is performed after the transition of the first polarity is performed by the third pulse signal. 如請求項2之顯示裝置，其中進而包含位移暫存器，其產生上述第1脈衝信號、上述第2脈衝信號、上述第3脈衝信號及上述第4脈衝信號。 The display device of claim 2, further comprising a shift register that generates the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal. 如請求項1之顯示裝置，其中進而包含：開關，其基於上述第2端子之電壓，開關控制施加有直流信號之第5端子與連接於上述單元像素之第6端子之間；及非線形元件，其插設於上述第2端子與上述第6端子之間。 The display device of claim 1, further comprising: a switch that controls a voltage between the fifth terminal to which the DC signal is applied and a sixth terminal connected to the unit pixel based on the voltage of the second terminal; and a non-linear element, It is interposed between the second terminal and the sixth terminal. 如請求項5之顯示裝置，其中上述非線形元件係第4電晶體，其包含連接於上述第2端子之源極及連接於上述第6端子之汲極及閘極。 The display device according to claim 5, wherein the non-linear element is a fourth transistor including a source connected to the second terminal and a drain and a gate connected to the sixth terminal. 如請求項1之顯示裝置，其中上述單元像素包含顯示元件、及對上述顯示元件供給驅動電流之驅動電晶體；且上述開關對上述驅動電晶體供給上述驅動電流。 The display device of claim 1, wherein the unit pixel includes a display element and a driving transistor that supplies a driving current to the display element; and the switch supplies the driving current to the driving transistor. 一種顯示驅動裝置，其包含：第1電晶體，其包含閘極、汲極、及源極；第1電容元件，其包含第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；第2電晶體，其包含汲極及源極；第2電容元件，其包含第3端子及第4端子，該第4端子連接於上述第2電晶體之汲極或源極、及上述第1電晶體之閘極；及第3電晶體，其包含汲極、源極、及連接於上述第3端子之閘極。 A display driving device includes: a first transistor including a gate, a drain, and a source; and a first capacitor including a first terminal and a second terminal, wherein the second terminal is connected to the first battery a drain or a source of the crystal; a second transistor including a drain and a source; a second capacitor including a third terminal and a fourth terminal, wherein the fourth terminal is connected to the drain of the second transistor Or a source and a gate of the first transistor; and a third transistor comprising a drain, a source, and a gate connected to the third terminal. 一種顯示裝置之驅動方法，上述顯示裝置包含：第1電晶體，其包含閘極、汲極、及源極；第1電容元件，其包含第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；第2電晶體，其包含汲極及源極；第2電容元件，其包含第3端子及第4端 子，該第4端子連接於上述第2電晶體之汲極或源極、及上述第1電晶體之閘極；及第3電晶體，其包含汲極、源極、及連接於上述第3端子之閘極；該驅動方法係：對上述第1電晶體之汲極及源極中之與連接於上述第2端子之端子不同之端子施加第1脈衝信號；且對上述第1電容元件之上述第1端子施加其他之脈衝信號；基於上述第2端子之電壓驅動單元像素；對上述第2電晶體之汲極及源極中之與連接於上述第4端子之端子不同之端子施加第2脈衝信號；對上述第3端子施加第3脈衝信號；對上述第3電晶體之汲極及源極中之與連接於上述第1端子之端子不同之端子施加第4脈衝信號。 A driving method of a display device, comprising: a first transistor including a gate, a drain, and a source; and a first capacitor including a first terminal and a second terminal, wherein the second terminal is connected to a drain or a source of the first transistor; a second transistor including a drain and a source; and a second capacitor including a third terminal and a fourth terminal The fourth terminal is connected to the drain or source of the second transistor and the gate of the first transistor; and the third transistor includes a drain, a source, and a third a driving method of applying a first pulse signal to a terminal different from a terminal connected to the second terminal among the drain and the source of the first transistor; and for the first capacitor element The first terminal applies another pulse signal; the voltage driving unit pixel based on the second terminal; and the second terminal of the second transistor that is different from the terminal connected to the fourth terminal in the drain and the source of the second transistor; a pulse signal; a third pulse signal is applied to the third terminal; and a fourth pulse signal is applied to a terminal different from a terminal connected to the first terminal among the drain and the source of the third transistor. 一種具備顯示裝置之電子機器，其包含：顯示裝置；及控制部，其對上述顯示裝置進行動作控制；且上述顯示裝置包含：第1電晶體，其包含閘極、汲極、及源極；第1電容元件，其包含第1端子及第2端子，該第2端子連接於上述第1電晶體之汲極或源極；單元像素，其係基於上述第2端子之電壓而被驅動；第2電晶體，其包含汲極及源極；第2電容元件，其包含第3端子及第4端子，該第4端子連接於上述第2電晶體之汲極或源極、及上述第1電晶體之閘極；及第3電晶體，其包含汲極、源極、及連接於上述第3端子之閘極。 An electronic device including a display device, comprising: a display device; and a control unit that controls operation of the display device; and the display device includes: a first transistor including a gate, a drain, and a source; a first capacitive element including a first terminal and a second terminal, wherein the second terminal is connected to a drain or a source of the first transistor; and the unit pixel is driven based on a voltage of the second terminal; a transistor comprising a drain and a source; a second capacitor comprising a third terminal and a fourth terminal, wherein the fourth terminal is connected to a drain or a source of the second transistor, and the first battery a gate of the crystal; and a third transistor comprising a drain, a source, and a gate connected to the third terminal.
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