TWI566024B - Thin film transistor - Google Patents
Thin film transistor Download PDFInfo
- Publication number
- TWI566024B TWI566024B TW104112727A TW104112727A TWI566024B TW I566024 B TWI566024 B TW I566024B TW 104112727 A TW104112727 A TW 104112727A TW 104112727 A TW104112727 A TW 104112727A TW I566024 B TWI566024 B TW I566024B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- semiconductor layer
- thin film
- film transistor
- substrate
- Prior art date
Links
Landscapes
- Thin Film Transistor (AREA)
Description
本發明係關於一種畫素結構與薄膜電晶體，尤指一種具有電容補償結構的畫素結構與薄膜電晶體。 The present invention relates to a pixel structure and a thin film transistor, and more particularly to a pixel structure and a thin film transistor having a capacitance compensation structure.
主動矩陣式(active matrix)顯示面板包括複數個呈矩陣排列的畫素結構所構成，且各畫素結構主要包括薄膜電晶體、顯示元件與儲存電容等元件。顯示面板的薄膜電晶體、顯示元件與儲存電容等元件之製作係將多層膜層包括例如導電層、半導體層與介電層等依序利用沉積、微影及蝕刻等製程加以形成。然而，由於微影製程無法避免地會具有對位誤差，因此實際製作出的元件之各膜層間的相對位置亦會產生一定的偏差。特別是對於大尺寸顯示面板而言，由於光罩的尺寸小於基板的尺寸，因此同一膜層的圖案必須經歷數次的微影製程才可定義出。在此狀況下，對於同一顯示面板而言，不同區域的畫素結構內的薄膜電晶體的特性或儲存電容值會因為對位誤差而不一致，而嚴重影響顯示品質。 The active matrix display panel comprises a plurality of pixel structures arranged in a matrix, and each pixel structure mainly comprises a thin film transistor, a display element and a storage capacitor. The fabrication of components such as thin film transistors, display elements, and storage capacitors of the display panel is performed by sequentially depositing, lithography, and etching a plurality of layers including, for example, a conductive layer, a semiconductor layer, and a dielectric layer. However, since the lithography process inevitably has a misalignment error, the relative position between the layers of the actually fabricated component also has a certain deviation. Especially for large-size display panels, since the size of the reticle is smaller than the size of the substrate, the pattern of the same film layer must be subjected to several lithography processes to be defined. Under this circumstance, for the same display panel, the characteristics or storage capacitance values of the thin film transistors in the pixel structure of different regions may be inconsistent due to the alignment error, which seriously affects the display quality.
本發明之目的之一在於提供一種具有電容補償結構的薄膜電晶體。 One of the objects of the present invention is to provide a thin film transistor having a capacitance compensation structure.
本發明之一實施例提供一種薄膜電晶體，包括一閘極、一電容補償結構、一半導體層、一介電層、一汲極，以及一源極。閘極設置於一基板 上且連接至一閘極線。電容補償結構設置於基板上，且電容補償結構電性連接至閘極，其中電容補償結構具有一第一側邊面對閘極以及一第二側邊遠離閘極。半導體層設置於基板上且覆蓋部份閘極，其中半導體層至少延伸重疊於電容補償結構之第一側邊。介電層設置於基板上，且介電層具有一第一開口及一第二開口分別暴露出位於閘極處之部份半導體層。汲極設置於基板上且經由第一開口接觸半導體層。源極設置於基板上且經由第二開口接觸半導體層。 One embodiment of the present invention provides a thin film transistor including a gate, a capacitor compensation structure, a semiconductor layer, a dielectric layer, a drain, and a source. The gate is disposed on a substrate Connected to a gate line. The capacitor compensation structure is disposed on the substrate, and the capacitor compensation structure is electrically connected to the gate, wherein the capacitor compensation structure has a first side facing the gate and a second side away from the gate. The semiconductor layer is disposed on the substrate and covers a portion of the gate, wherein the semiconductor layer extends at least over the first side of the capacitance compensation structure. The dielectric layer is disposed on the substrate, and the dielectric layer has a first opening and a second opening respectively exposing a portion of the semiconductor layer at the gate. The drain is disposed on the substrate and contacts the semiconductor layer via the first opening. The source is disposed on the substrate and contacts the semiconductor layer via the second opening.
10‧‧‧畫素結構 10‧‧‧ pixel structure
T1‧‧‧第一薄膜電晶體 T1‧‧‧ first film transistor
T2‧‧‧第二薄膜電晶體 T2‧‧‧second film transistor
Cst‧‧‧儲存電容 Cst‧‧‧ storage capacitor
1‧‧‧基板 1‧‧‧Substrate
G1‧‧‧第一閘極 G1‧‧‧ first gate
S1‧‧‧第一源極 S1‧‧‧first source
D1‧‧‧第一汲極 D1‧‧‧First bungee
11‧‧‧第一半導體層 11‧‧‧First semiconductor layer
G2‧‧‧第二閘極 G2‧‧‧second gate
S2‧‧‧第二源極 S2‧‧‧Second source
D2‧‧‧第二汲極 D2‧‧‧second bungee
12‧‧‧第二半導體層 12‧‧‧Second semiconductor layer
A1‧‧‧第一側邊 A1‧‧‧ first side
A2‧‧‧第二側邊 A2‧‧‧ second side
P1‧‧‧第一突出部 P1‧‧‧First protrusion
P2‧‧‧第二突出部 P2‧‧‧Second protrusion
14‧‧‧上電極 14‧‧‧Upper electrode
16‧‧‧下電極 16‧‧‧ lower electrode
18‧‧‧絕緣層 18‧‧‧Insulation
L‧‧‧通道長度 L‧‧‧ channel length
W‧‧‧通道寬度 W‧‧‧ channel width
GL‧‧‧閘極線 GL‧‧‧ gate line
DL‧‧‧資料線 DL‧‧‧ data line
PL‧‧‧電源線 PL‧‧‧Power cord
EL‧‧‧光電轉換元件 EL‧‧‧ photoelectric conversion components
L1‧‧‧第一長度 L1‧‧‧ first length
W1‧‧‧第一寬度 W1‧‧‧ first width
L2‧‧‧第二長度 L2‧‧‧ second length
W2‧‧‧第二寬度 W2‧‧‧ second width
d1‧‧‧第一方向 D1‧‧‧ first direction
d2‧‧‧第二方向 D2‧‧‧second direction
20‧‧‧介電層 20‧‧‧Dielectric layer
201‧‧‧開口 201‧‧‧ openings
202‧‧‧開口 202‧‧‧ openings
203‧‧‧開口 203‧‧‧ openings
204‧‧‧開口 204‧‧‧ openings
205‧‧‧開口 205‧‧‧ openings
206‧‧‧開口 206‧‧‧ openings
207‧‧‧開口 207‧‧‧ openings
Id‧‧‧電流 Id‧‧‧ Current
40‧‧‧薄膜電晶體 40‧‧‧film transistor
G‧‧‧閘極 G‧‧‧ gate
Cp‧‧‧電容補償結構 Cp‧‧‧Capacitor compensation structure
42‧‧‧半導體層 42‧‧‧Semiconductor layer
44‧‧‧介電層 44‧‧‧ dielectric layer
D‧‧‧汲極 D‧‧‧汲
S‧‧‧源極 S‧‧‧ source
46‧‧‧絕緣層 46‧‧‧Insulation
4‧‧‧基板 4‧‧‧Substrate
441‧‧‧第一開口 441‧‧‧ first opening
442‧‧‧第二開口 442‧‧‧ second opening
443‧‧‧第三開口 443‧‧‧ third opening
444‧‧‧第四開口 444‧‧‧fourth opening
X‧‧‧重疊區 X‧‧‧ overlap zone
L3‧‧‧長度 L3‧‧‧ length
W3‧‧‧寬度 W3‧‧‧Width
60‧‧‧薄膜電晶體 60‧‧‧film transistor
E1‧‧‧第一延伸部 E1‧‧‧First Extension
B1‧‧‧第一本體部 B1‧‧‧First Body Department
E2‧‧‧第二延伸部 E2‧‧‧Second extension
B2‧‧‧第二本體部 B2‧‧‧Second Body
g‧‧‧間隔 G‧‧‧ interval
第1圖繪示了本發明之第一實施例之畫素結構的等效電路圖。 Fig. 1 is a view showing an equivalent circuit diagram of a pixel structure of a first embodiment of the present invention.
第2圖繪示了第1圖之畫素結構的上視示意圖。 Fig. 2 is a top plan view showing the pixel structure of Fig. 1.
第3圖為第2圖之畫素結構沿剖線A-A’與B-B’所繪示的剖面示意圖。 Fig. 3 is a schematic cross-sectional view showing the pixel structure of Fig. 2 taken along line A-A' and B-B'.
第4圖繪示了本發明之第二實施例之薄膜電晶體的上視示意圖。 Fig. 4 is a top plan view showing a thin film transistor of a second embodiment of the present invention.
第5圖為第4圖之薄膜電晶體沿剖線C-C’所繪示之剖面示意圖。 Fig. 5 is a schematic cross-sectional view of the thin film transistor of Fig. 4 taken along line C-C'.
第6圖繪示了本發明之第二實施例之變化實施例的薄膜電晶體的上視示意圖。 Fig. 6 is a top plan view showing a thin film transistor of a modified embodiment of the second embodiment of the present invention.
第7圖為第6圖之薄膜電晶體沿剖線E-E’所繪示之剖面示意圖。 Fig. 7 is a schematic cross-sectional view of the thin film transistor of Fig. 6 taken along line E-E'.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。 The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .
請參考第1圖至第3圖。第1圖繪示了本發明之第一實施例之畫素結構的等效電路圖，第2圖繪示了第1圖之畫素結構的上視示意圖，而第 3圖為第2圖之畫素結構沿剖線A-A’與B-B’所繪示的剖面示意圖。本發明之畫素結構係以自發光顯示面板例如有機電激發光顯示面板之畫素結構為較佳範例說明，但不以此為限。本發明之畫素結構亦可為其它類型的自發光顯示面板例如電漿顯示面板、場發射顯示面板或其它合適的顯示面板的畫素結構，或是非自發光顯示面板例如液晶顯示面板(例如：水平電場驅動的液晶顯示面板、垂直電場驅動的液晶顯示面板、光學補償彎曲(optically compensated bend,OCB)液晶顯示面板、膽固醇液晶顯示面板、藍相液晶顯示面板、或其它合適的液晶顯示面板)、電泳顯示面板、電濕潤顯示面板、或其它合適的顯示面板之畫素結構。但需注意的是，非自發光顯示面板就需要額外的背光模組提供光源給予非自發光顯示面板，而自發光顯示面板因會自發光就不需要此額外的光源。 Please refer to Figures 1 to 3. 1 is a diagram showing an equivalent circuit diagram of a pixel structure of a first embodiment of the present invention, and FIG. 2 is a top view of a pixel structure of the first embodiment, and 3 is a schematic cross-sectional view of the pixel structure of Fig. 2 taken along line A-A' and B-B'. The pixel structure of the present invention is described as a preferred example of a pixel structure of a self-luminous display panel, such as an organic electroluminescent display panel, but is not limited thereto. The pixel structure of the present invention may also be a pixel structure of other types of self-luminous display panels such as a plasma display panel, a field emission display panel or other suitable display panel, or a non-self-luminous display panel such as a liquid crystal display panel (for example: a horizontal electric field driven liquid crystal display panel, a vertical electric field driven liquid crystal display panel, an optically compensated bend (OCB) liquid crystal display panel, a cholesteric liquid crystal display panel, a blue phase liquid crystal display panel, or other suitable liquid crystal display panel, A pixel structure of an electrophoretic display panel, an electrowetting display panel, or other suitable display panel. However, it should be noted that the non-self-luminous display panel requires an additional backlight module to provide a light source to the non-self-luminous display panel, and the self-luminous display panel does not require this additional light source because it will self-illuminate.
如第1圖所示，本實施例之畫素結構10包括一第一薄膜電晶體T1、一第二薄膜電晶體T2以及一儲存電容Cst，設置於一基板1上。本實施例之畫素結構10係以一2T1C架構(兩個薄膜電晶體與一個儲存電容的架構)之畫素結構為範例，其中第一薄膜電晶體T1係作為開關薄膜電晶體，而第二薄膜電晶體T2係作為驅動薄膜電晶體，但不以此為限。在其它變化實施例中，畫素結構可為具有兩個以上的薄膜電晶體的架構例如4T2C架構、2T2C架構、5T1C架構、6T1C架構或其它架構。如第2圖與第3圖所示，第一薄膜電晶體T1具有第一閘極G1、第一源極S1、第一汲極D1與第一半導體層11，且第一源極S1與第一汲極D1接觸第一半導體層11。第二薄膜電晶體T2具有第二閘極G2、第二源極S2、第二汲極D2與第二半導體層12，且第二源極S2與第二汲極D2接觸第二半導體層12。此外，第二閘極G2具有第一側邊A1面對第一閘極G1，以及第二側邊A2遠離第一閘極G1。第二閘極G2連接第一源極S1，第二半導體層12具有第一突出部P1與第二突出部P2沿第一方向d1分別突出於第二閘極G2之第一側邊A1與第二側邊A2，其中 第一突出部P1之面積實質上(substantially)小於第二突出部P2之面積，且第二半導體層12不與第一半導體層11接觸。另外，儲存電容Cst具有上電極14、下電極16與夾設於上電極14與下電極16間之絕緣層18，其中上電極14由第二源極S2與部份第二半導體層12所構成、下電極16由部份第二閘極G2所構成，而絕緣層18係作為電容介電層之用。由於上電極14的第二半導體層12較第二源極S2靠近下電極16，因此儲存電容Cst的電容值主要係由上電極14的第二半導體層12與下電極16(第二閘極G2)的重疊面積所決定，而不是上電極14的第二源極S2與下電極16(第二閘極G2)的重疊面積。第一半導體層11與第二半導體層12的材料較佳可為氧化物半導體例如氧化銦鎵鋅(indium gallium zinc oxide,IGZO)、氧化銦鎵(IGO)、氧化銦鋅(IZO)、氧化銦錫(indium tin oxide,ITO)、氧化鈦(titanium oxide,TiO)、氧化鋅(zinc oxide,ZnO)、氧化銦(indium oxide,InO)、氧化鎵(gallium oxide,GaO)、或其它合適的材料，理由在於氧化物半導體的特性相較於一般半導體(例如：非晶矽、多晶矽等等)更接近導體特性，因此作為儲存電容Cst的上電極14可具有較佳的導電性。而本發明的第一半導體層11與第二半導體層12的材料較佳以氧化銦鎵鋅IGZO)為範例。另外，第一半導體層11與第二半導體層12的材料可不限於氧化物半導體。例如，第一半導體層11與第二半導體層12的材料亦可為例如非晶半導體、多晶半導體、微晶半導體、單晶半導體、奈米晶半導體、有機半導體、或其它合適的半導體材料、或上述半導體材料的組合。絕緣層18的材料可為各式無機絕緣材料、有機絕緣材料或有機/無機混合絕緣材料。此外，絕緣層18更設置於第一薄膜電晶體T1之第一閘極G1與第一半導體層11之間以及設置於第二薄膜電晶體T2之第二閘極G2與第二半導體層12之間，以作為閘極絕緣層之用。 As shown in FIG. 1, the pixel structure 10 of the present embodiment includes a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst disposed on a substrate 1. The pixel structure 10 of this embodiment is exemplified by a pixel structure of a 2T1C architecture (two thin film transistors and a storage capacitor structure), wherein the first thin film transistor T1 is used as a switching thin film transistor, and the second The thin film transistor T2 is used as a driving thin film transistor, but is not limited thereto. In other variant embodiments, the pixel structure can be an architecture having more than two thin film transistors such as a 4T2C architecture, a 2T2C architecture, a 5T1C architecture, a 6T1C architecture, or other architecture. As shown in FIGS. 2 and 3, the first thin film transistor T1 has a first gate G1, a first source S1, a first drain D1 and a first semiconductor layer 11, and the first source S1 and the first A drain D1 contacts the first semiconductor layer 11. The second thin film transistor T2 has a second gate G2, a second source S2, a second drain D2 and a second semiconductor layer 12, and the second source S2 and the second drain D2 contact the second semiconductor layer 12. Further, the second gate G2 has a first side A1 facing the first gate G1 and a second side A2 being away from the first gate G1. The second gate G2 is connected to the first source S1, and the second semiconductor layer 12 has the first protrusion P1 and the second protrusion P2 protruding from the first side A1 and the second side of the second gate G2 in the first direction d1. Two sides A2, of which The area of the first protrusion P1 is substantially smaller than the area of the second protrusion P2, and the second semiconductor layer 12 is not in contact with the first semiconductor layer 11. In addition, the storage capacitor Cst has an upper electrode 14, a lower electrode 16 and an insulating layer 18 interposed between the upper electrode 14 and the lower electrode 16, wherein the upper electrode 14 is composed of a second source S2 and a portion of the second semiconductor layer 12. The lower electrode 16 is composed of a part of the second gate G2, and the insulating layer 18 is used as a capacitor dielectric layer. Since the second semiconductor layer 12 of the upper electrode 14 is closer to the lower electrode 16 than the second source S2, the capacitance value of the storage capacitor Cst is mainly from the second semiconductor layer 12 and the lower electrode 16 of the upper electrode 14 (the second gate G2) The overlapping area is determined instead of the overlapping area of the second source S2 of the upper electrode 14 and the lower electrode 16 (second gate G2). The material of the first semiconductor layer 11 and the second semiconductor layer 12 may preferably be an oxide semiconductor such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), or indium oxide. Indium tin oxide (ITO), titanium oxide (TiO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), or other suitable materials The reason is that the characteristics of the oxide semiconductor are closer to the conductor characteristics than the general semiconductor (for example, amorphous germanium, polysilicon, etc.), and therefore the upper electrode 14 as the storage capacitor Cst can have better conductivity. The material of the first semiconductor layer 11 and the second semiconductor layer 12 of the present invention is preferably exemplified by indium gallium zinc oxide (IGZO). In addition, the material of the first semiconductor layer 11 and the second semiconductor layer 12 may not be limited to an oxide semiconductor. For example, the material of the first semiconductor layer 11 and the second semiconductor layer 12 may also be, for example, an amorphous semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, a single crystal semiconductor, a nanocrystalline semiconductor, an organic semiconductor, or other suitable semiconductor material, Or a combination of the above semiconductor materials. The material of the insulating layer 18 may be various inorganic insulating materials, organic insulating materials or organic/inorganic hybrid insulating materials. In addition, the insulating layer 18 is disposed between the first gate G1 of the first thin film transistor T1 and the first semiconductor layer 11 and the second gate G2 and the second semiconductor layer 12 of the second thin film transistor T2. Used as a gate insulation layer.
在本實施例中，第一薄膜電晶體T1的第一半導體層11具有一通 道長度L與一通道寬度W，其中通道長度L是第一半導體層11在電流(或電子流)的流動方向上的長度，亦即第一半導體層11在第一源極S1與第一汲極D1之間的長度，而通道寬度W則是第一半導體層11在實質上垂直於通道長度L的方向上的寬度。另外，第二薄膜電晶體T2的第二半導體層12也可利用相同方式定義出通道長度與通道寬度的方向。在本實施例中，第一方向d1與通道寬度W的方向實質上平行。另外，第一薄膜電晶體T1之第一閘極G1係連接至一閘極線GL，第一汲極D1係連接至一資料線DL，且第二薄膜電晶體T2之第二汲極D2係連接至一電源線PL。另外，畫素結構10更包括一光電轉換元件EL例如有機發光二極體元件(如第1圖所示)與第二薄膜電晶體T2之第二源極S2連接。在本實施例中，第一閘極G1為矩形，其具有兩相對應的短邊與兩相對應的長邊，其中一個短邊係與閘極線GL連接，而另一個短邊則面對第二閘極G2。此外，第二薄膜電晶體T2的第二半導體層12的第一突出部P1係面對第一閘極G1的另一個短邊。也就是說，第一突出部P1最靠近第一閘極G1，而第二突出部P2則最遠離第一閘極G1。第一突出部P1具有第一長度L1與第一寬度W1，第二突出部P2具有第二長度L2與第二寬度W2。第一突出部P1之第一寬度W1實質上等於第二突出部P2之第二寬度W2，且第一突出部P1突出於第二閘極G2之第一側邊A1之第一長度L1實質上小於第二突出部P2突出於第二閘極G2之第二側邊A2之第二長度L2。第一突出部P1的第一長度L1較佳須大於第二半導體層12的對位誤差。舉例而言，在本實施例中，第一長度L1實質上介於1微米與5微米之間，較佳實質上介於1微米與3微米之間，且更佳實質上為2微米。或者，第一長度L1實質上介於2微米與5微米之間，但不以此為限。另外，第二長度L2實質上介於1微米與5微米之間，但不以此為限，且第二長度L2實質上大於第一長度L1。另外，在垂直於第一方向d1的第二方向d2上，第二閘極G2係突出於第二半導體層12的兩相對側，且第二閘極G2突出於第二半導體層12的長度較佳係大於第二半導體層12的對位誤差。 In this embodiment, the first semiconductor layer 11 of the first thin film transistor T1 has a pass. a track length L and a channel width W, wherein the channel length L is the length of the first semiconductor layer 11 in the flow direction of the current (or electron current), that is, the first semiconductor layer 11 is at the first source S1 and the first turn The length between the poles D1, and the channel width W is the width of the first semiconductor layer 11 in a direction substantially perpendicular to the length L of the channel. In addition, the second semiconductor layer 12 of the second thin film transistor T2 can also define the direction of the channel length and the channel width in the same manner. In the present embodiment, the first direction d1 is substantially parallel to the direction of the channel width W. In addition, the first gate G1 of the first thin film transistor T1 is connected to a gate line GL, the first drain D1 is connected to a data line DL, and the second drain D2 of the second thin film transistor T2 is Connected to a power line PL. In addition, the pixel structure 10 further includes a photoelectric conversion element EL such as an organic light emitting diode element (as shown in FIG. 1) connected to the second source S2 of the second thin film transistor T2. In this embodiment, the first gate G1 is rectangular, and has two corresponding short sides and two corresponding long sides, one of which is connected to the gate line GL and the other short side is faced. The second gate G2. Further, the first protrusion P1 of the second semiconductor layer 12 of the second thin film transistor T2 faces the other short side of the first gate G1. That is, the first protrusion P1 is closest to the first gate G1, and the second protrusion P2 is farthest from the first gate G1. The first protrusion P1 has a first length L1 and a first width W1, and the second protrusion P2 has a second length L2 and a second width W2. The first width W1 of the first protrusion P1 is substantially equal to the second width W2 of the second protrusion P2, and the first protrusion L1 protrudes from the first length L1 of the first side A1 of the second gate G2 substantially Less than the second protrusion P2 protrudes from the second length L2 of the second side A2 of the second gate G2. The first length L1 of the first protrusion P1 is preferably larger than the alignment error of the second semiconductor layer 12. For example, in the present embodiment, the first length L1 is substantially between 1 micrometer and 5 micrometers, preferably substantially between 1 micrometer and 3 micrometers, and more preferably substantially 2 micrometers. Alternatively, the first length L1 is substantially between 2 microns and 5 microns, but is not limited thereto. In addition, the second length L2 is substantially between 1 micrometer and 5 micrometers, but not limited thereto, and the second length L2 is substantially larger than the first length L1. In addition, in the second direction d2 perpendicular to the first direction d1, the second gate G2 protrudes from opposite sides of the second semiconductor layer 12, and the second gate G2 protrudes from the length of the second semiconductor layer 12 The better is greater than the alignment error of the second semiconductor layer 12.
在本實施例中，第一閘極G1、第二閘極G2與資料線DL係由同一層圖案化導電層例如第一金屬層(M1)所構成，第一源極S1、第一汲極D1、第二源極S2、第二汲極D2、閘極線GL與電源線PL係由另一層圖案化導電層例如第二金屬層(M2)所構成，但不以此為限。舉例而言，在其它變化實施例中，第一閘極G1、第二閘極G2、閘極線GL與電源線PL可由同一層圖案化導電層例如第一金屬層(M1)所構成，而第一源極S1、第一汲極D1、第二源極S2、第二汲極D2與資料線DL可由另一層圖案化導電層例如第二金屬層(M2)所構成。此外，第一薄膜電晶體T1、第二薄膜電晶體T2與儲存電容Cst皆更包括一介電層20，設置於第一薄膜電晶體T1之絕緣層18上、於第二薄膜電晶體T2之絕緣層18上以及於儲存電容Cst之絕緣層18上。介電層20會覆蓋第一半導體層11與第二半導體層12，用來避免第一半導體層11與第二半導體層12在蝕刻第一源極S1、第一汲極D1、第二源極S2、第二汲極D2時受損。介電層20的材料可為各式無機絕緣材料、有機絕緣材料或有機/無機混合絕緣材料。介電層20具有複數個開口201,202,203,204,205,206,207。開口201,202分別暴露出第一薄膜電晶體T1之部份第一半導體層11，以使得第一源極S1與第一汲極D1分別經由開口201,202與第一半導體層11接觸；開口203,204分別暴露出第二薄膜電晶體T2之部份第二半導體層12與儲存電容Cst之部份第二半導體層12，以使得第二源極S2與第二汲極D2經由開口203,204與第二半導體層12接觸；開口205更貫穿絕緣層18而暴露出資料線DL，以使得第一汲極D1經由開口205與資料線DL接觸；開口206更貫穿絕緣層18而暴露部分第二閘極G2，以使得第一源極S1經由開口206與第二閘極G2接觸；以及開口207更貫穿絕緣層18而暴露出第一閘極G1，以使得閘極線GL經由開口207(第3圖未示)與第一閘極G1接觸。 In this embodiment, the first gate G1, the second gate G2, and the data line DL are formed by the same patterned conductive layer, such as the first metal layer (M1), the first source S1 and the first drain D1, the second source S2, the second drain D2, the gate line GL, and the power line PL are formed of another patterned conductive layer such as the second metal layer (M2), but are not limited thereto. For example, in other variant embodiments, the first gate G1, the second gate G2, the gate line GL and the power line PL may be formed of the same layer of patterned conductive layer, such as the first metal layer (M1), and The first source S1, the first drain D1, the second source S2, the second drain D2, and the data line DL may be formed of another patterned conductive layer such as a second metal layer (M2). In addition, the first thin film transistor T1, the second thin film transistor T2 and the storage capacitor Cst further comprise a dielectric layer 20 disposed on the insulating layer 18 of the first thin film transistor T1 and on the second thin film transistor T2. The insulating layer 18 is on the insulating layer 18 of the storage capacitor Cst. The dielectric layer 20 covers the first semiconductor layer 11 and the second semiconductor layer 12 to prevent the first semiconductor layer 11 and the second semiconductor layer 12 from etching the first source S1, the first drain D1, and the second source. S2, the second bungee D2 is damaged. The material of the dielectric layer 20 may be various inorganic insulating materials, organic insulating materials or organic/inorganic hybrid insulating materials. Dielectric layer 20 has a plurality of openings 201, 202, 203, 204, 205, 206, 207. The openings 201, 202 respectively expose a portion of the first semiconductor layer 11 of the first thin film transistor T1 such that the first source S1 and the first drain D1 are in contact with the first semiconductor layer 11 via the openings 201, 202, respectively; the openings 203, 204 are respectively exposed a portion of the second semiconductor layer 12 of the second thin film transistor T2 and a portion of the second semiconductor layer 12 of the storage capacitor Cst such that the second source S2 and the second drain D2 are in contact with the second semiconductor layer 12 via the openings 203, 204 The opening 205 further penetrates the insulating layer 18 to expose the data line DL such that the first drain D1 contacts the data line DL via the opening 205; the opening 206 penetrates the insulating layer 18 to expose a portion of the second gate G2, so that A source S1 is in contact with the second gate G2 via the opening 206; and the opening 207 extends through the insulating layer 18 to expose the first gate G1 such that the gate line GL passes through the opening 207 (not shown in FIG. 3) A gate G1 contacts.
如第1圖所示，在畫素結構10中，光電轉換元件EL的亮度主要 係取決於流過第二薄膜電晶體T2的電流Id，而電流Id主要又取決於第二薄膜電晶體T2的第二閘極G2與第一薄膜電晶體T1的第一源極S1之間的壓差(Vgs)。因此，當儲存電容Cst的電容值(亦即第二閘極G2與第一源極S1之間的電容值)改變時，將會影響第二閘極G2與第一源極S1之間的壓差(Vgs)，進而再影響流過第二薄膜電晶體T2的電流Id，如此一來即會影響到光電轉換元件EL的亮度。換言之，為了使所有的光電轉換元件EL可提供一致具穩定的亮度，必須維持儲存電容Cst的電容值。在本實施例中，第二半導體層12的第一突出部P1與第二突出部P2係作為電容補償結構，其沿第一方向d1分別突出於第二閘極G2之第一側邊A1與第二側邊A2，且第一突出部P1的第一長度L1與第二突出部P2的第二長度L2均大於第二半導體層12的對位誤差。藉此，即使第二半導體層12因為製程的對位誤差而在第一方向d1產生偏移，第二半導體層12與第二閘極G2的重疊面積仍可維持恆定。此外，在第二方向d2上，第二閘極G2係突出於第二半導體層12的兩相對側，且第二閘極G2突出於第二半導體層12的長度大於第二半導體層12的對位誤差。藉此，即使第二半導體層12因為製程的對位誤差而在第二方向d2產生偏移，第二半導體層12與第二閘極G2的重疊面積仍可維持恆定。此外，由於用來連接第二汲極D2與第二半導體層12的開口204係位於第二突出部P2的位置，因此第二突出部P2的第二長度L2較佳應大於開口204的尺寸。 As shown in Fig. 1, in the pixel structure 10, the luminance of the photoelectric conversion element EL is mainly It depends on the current Id flowing through the second thin film transistor T2, and the current Id mainly depends on the second gate G2 of the second thin film transistor T2 and the first source S1 of the first thin film transistor T1. Pressure difference (Vgs). Therefore, when the capacitance value of the storage capacitor Cst (that is, the capacitance value between the second gate G2 and the first source S1) changes, the voltage between the second gate G2 and the first source S1 will be affected. The difference (Vgs), which in turn affects the current Id flowing through the second thin film transistor T2, thus affects the brightness of the photoelectric conversion element EL. In other words, in order for all of the photoelectric conversion elements EL to provide uniform stable brightness, it is necessary to maintain the capacitance value of the storage capacitor Cst. In this embodiment, the first protruding portion P1 and the second protruding portion P2 of the second semiconductor layer 12 serve as a capacitance compensation structure that protrudes from the first side A1 of the second gate G2 and respectively in the first direction d1. The second side A2, and the first length L1 of the first protrusion P1 and the second length L2 of the second protrusion P2 are both greater than the alignment error of the second semiconductor layer 12. Thereby, even if the second semiconductor layer 12 is shifted in the first direction d1 due to the alignment error of the process, the overlapping area of the second semiconductor layer 12 and the second gate G2 can be maintained constant. In addition, in the second direction d2, the second gate G2 protrudes from opposite sides of the second semiconductor layer 12, and the second gate G2 protrudes from the second semiconductor layer 12 by a length greater than that of the second semiconductor layer 12. Bit error. Thereby, even if the second semiconductor layer 12 is shifted in the second direction d2 due to the alignment error of the process, the overlapping area of the second semiconductor layer 12 and the second gate G2 can be maintained constant. Further, since the opening 204 for connecting the second drain D2 and the second semiconductor layer 12 is located at the position of the second protrusion P2, the second length L2 of the second protrusion P2 should preferably be larger than the size of the opening 204.
請參考第4圖與第5圖。第4圖繪示了本發明之第二實施例之薄膜電晶體的上視示意圖，而第5圖為第4圖之薄膜電晶體沿剖線C-C’所繪示之剖面示意圖。如第4圖與第5圖所示，本實施例之薄膜電晶體40包括一閘極G、一電容補償結構Cp、一半導體層42、一介電層44(第4圖未示)、一汲極D、一源極S與一絕緣層46(第4圖未示)。閘極G設置於一基板4上且電性連接至一閘極線GL。絕緣層46設置於基板4上並覆蓋閘極G與資料線DL。電容補償結構Cp設置於基板4上，且電容補償結構Cp電性連接至閘極 G，其中電容補償結構Cp具有一第一側邊A1面對閘極G以及一第二側邊A2遠離閘極G。半導體層42設置於基板4上且覆蓋部份閘極G，其中半導體層42至少延伸重疊於電容補償結構Cp之第一側邊A1。介電層44設置於基板4上，且介電層44具有一第一開口441及一第二開口442分別暴露出位於閘極G處之部份半導體層42。汲極D設置於基板4上且經由第一開口441接觸半導體層42。源極S設置於基板4上且經由第二開口442接觸半導體層42。介電層44另具有一第三開口443貫穿絕緣層46並暴露出資料線DL，以及一第四開口444(第5圖未示)貫穿絕緣層46並暴露出閘極線GL，其中汲極D經由第三開口443與資料線DL接觸並電性連接，而閘極線GL則經由第四開口444與閘極G接觸並電性連接。在本實施例中，閘極G與資料線DL係由同一層圖案化導電層例如第一金屬層(M1)所構成，而閘極線GL、電容補償結構Cp、源極S與汲極D係由另一層圖案化導電層例如第二金屬層(M2)所構成，但不以此為限。舉例而言，在其它變化實施例中，閘極線GL與閘極G可由同一層圖案化導電層例如第一金屬層(M1)所構成，因此，此時第四開口444就可省略，而與電容補償結構Cp、源極S、汲極D與資料線DL可由另一層圖案化導電層例如第二金屬層(M2)所構成。半導體層42的材料可為例如氧化物半導體、非晶半導體、多晶半導體、微晶半導體、單晶半導體、奈米晶半導體、有機半導體、或其它合適的半導體材料、或上述半導體材料的組合。本發明的半導體層42的材料如上所述，且以氧化物半導體的氧化銦鎵鋅(IGZO)為較佳實施例。絕緣層46與介電層44的材料可為各式無機絕緣材料、有機絕緣材料或有機/無機混合絕緣材料。絕緣層46係作為閘極絕緣層。介電層44會覆蓋半導體層42，用來避免半導體層42在蝕刻源極S與汲極D時受損。 Please refer to Figures 4 and 5. Fig. 4 is a top plan view showing a thin film transistor of a second embodiment of the present invention, and Fig. 5 is a cross-sectional view showing the thin film transistor of Fig. 4 taken along line C-C'. As shown in FIG. 4 and FIG. 5, the thin film transistor 40 of the present embodiment includes a gate G, a capacitor compensation structure Cp, a semiconductor layer 42, and a dielectric layer 44 (not shown in FIG. 4). The drain D, a source S and an insulating layer 46 (not shown in Fig. 4). The gate G is disposed on a substrate 4 and electrically connected to a gate line GL. The insulating layer 46 is disposed on the substrate 4 and covers the gate G and the data line DL. The capacitor compensation structure Cp is disposed on the substrate 4, and the capacitor compensation structure Cp is electrically connected to the gate G, wherein the capacitance compensation structure Cp has a first side A1 facing the gate G and a second side A2 away from the gate G. The semiconductor layer 42 is disposed on the substrate 4 and covers a portion of the gate G, wherein the semiconductor layer 42 extends at least over the first side A1 of the capacitance compensation structure Cp. The dielectric layer 44 is disposed on the substrate 4, and the dielectric layer 44 has a first opening 441 and a second opening 442 respectively exposing a portion of the semiconductor layer 42 at the gate G. The drain D is disposed on the substrate 4 and contacts the semiconductor layer 42 via the first opening 441. The source S is disposed on the substrate 4 and contacts the semiconductor layer 42 via the second opening 442. The dielectric layer 44 further has a third opening 443 extending through the insulating layer 46 and exposing the data line DL, and a fourth opening 444 (not shown in FIG. 5) penetrating the insulating layer 46 and exposing the gate line GL, wherein the drain D is in contact with and electrically connected to the data line DL via the third opening 443, and the gate line GL is in contact with and electrically connected to the gate G via the fourth opening 444. In this embodiment, the gate G and the data line DL are formed by the same patterned conductive layer such as the first metal layer (M1), and the gate line GL, the capacitance compensation structure Cp, the source S and the drain D It is composed of another layer of patterned conductive layer such as the second metal layer (M2), but is not limited thereto. For example, in other variant embodiments, the gate line GL and the gate G may be formed of the same patterned conductive layer, such as the first metal layer (M1), so that the fourth opening 444 may be omitted at this time. The capacitor compensation structure Cp, the source S, the drain D, and the data line DL may be formed of another patterned conductive layer such as a second metal layer (M2). The material of the semiconductor layer 42 may be, for example, an oxide semiconductor, an amorphous semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, a single crystal semiconductor, a nanocrystalline semiconductor, an organic semiconductor, or other suitable semiconductor material, or a combination of the above semiconductor materials. The material of the semiconductor layer 42 of the present invention is as described above, and an indium gallium zinc oxide (IGZO) of an oxide semiconductor is preferred. The material of the insulating layer 46 and the dielectric layer 44 may be various inorganic insulating materials, organic insulating materials or organic/inorganic hybrid insulating materials. The insulating layer 46 serves as a gate insulating layer. The dielectric layer 44 covers the semiconductor layer 42 to prevent the semiconductor layer 42 from being damaged when etching the source S and the drain D.
在本實施例中，半導體層42延伸重疊於電容補償結構Cp之第一側邊A1，且源極S與電容補償結構Cp不重疊，但不以此為限。在其它變化 實施例中，半導體層42可延伸至電容補償結構Cp之第二側邊A2或是突出於第二側邊A2，此時，源極S與電容補償結構Cp仍不重疊。此外，半導體層42重疊於電容補償結構Cp之第一側邊A1具有一重疊區X，其中重疊區X垂直投影於基板4上具有一長度L3與一寬度W3，且長度L3較佳須大於半導體層42的對位誤差。舉例而言，在本實施例中，長度L3實質上介於1微米至5微米之間，但不以此為限。半導體層42具有一通道長度L與一通道寬度W，其中通道長度L是半導體層42在電流(或電子流)的流動方向上的長度，亦即半導體層42在源極S與汲極D之間的長度，而通道寬度W則是半導體層42在實質上垂直於通道長度L的方向上的寬度。重疊區X的長度L3是實質上平行於半導體層42的通道長度L的方向上的長度。由於電容補償結構Cp與閘極線GL電性連接，且半導體層42與源極S電性連接，因此電容補償結構Cp與半導體層42所形成的電容值主要係由半導體層42與電容補償結構Cp的重疊區X的面積所決定。藉由上述配置，當製程的對位誤差而使半導體層42產生偏移時，半導體層42與電容補償結構Cp的重疊區X的面積仍可維持恆定，也就是說，閘極G與源極S之間的電容值(Cgs)可維持恆定，因此可使薄膜電晶體40具有穩定且一致的元件特性。 In this embodiment, the semiconductor layer 42 extends over the first side A1 of the capacitance compensation structure Cp, and the source S does not overlap with the capacitance compensation structure Cp, but is not limited thereto. In other changes In the embodiment, the semiconductor layer 42 may extend to the second side A2 of the capacitance compensation structure Cp or protrude from the second side A2. At this time, the source S and the capacitance compensation structure Cp still do not overlap. In addition, the first side A1 of the semiconductor layer 42 overlying the capacitor compensation structure Cp has an overlap region X, wherein the overlap region X is vertically projected on the substrate 4 and has a length L3 and a width W3, and the length L3 is preferably larger than the semiconductor. The alignment error of layer 42. For example, in the embodiment, the length L3 is substantially between 1 micrometer and 5 micrometers, but not limited thereto. The semiconductor layer 42 has a channel length L and a channel width W, wherein the channel length L is the length of the semiconductor layer 42 in the flow direction of the current (or electron current), that is, the semiconductor layer 42 is at the source S and the drain D. The length of the gap, and the channel width W is the width of the semiconductor layer 42 in a direction substantially perpendicular to the length L of the channel. The length L3 of the overlap region X is a length in a direction substantially parallel to the channel length L of the semiconductor layer 42. Since the capacitance compensation structure Cp is electrically connected to the gate line GL, and the semiconductor layer 42 is electrically connected to the source S, the capacitance values formed by the capacitance compensation structure Cp and the semiconductor layer 42 are mainly composed of the semiconductor layer 42 and the capacitance compensation structure. The area of the overlap region X of Cp is determined. With the above configuration, when the semiconductor layer 42 is shifted by the alignment error of the process, the area of the overlap region X of the semiconductor layer 42 and the capacitance compensation structure Cp can be maintained constant, that is, the gate G and the source are The capacitance value (Cgs) between S can be maintained constant, so that the thin film transistor 40 can have stable and uniform element characteristics.
本實施例之薄膜電晶體並不以上述實施例為限。下文將依序介紹本發明之變化實施例之薄膜電晶體，且為了便於比較各實施例之相異處並簡化說明，在下文之變化實施例中使用相同的符號標注相同的元件，且主要針對各實施例之相異處進行說明，而不再對重覆部分進行贅述。 The thin film transistor of this embodiment is not limited to the above embodiment. Hereinafter, the thin film transistor of the modified embodiment of the present invention will be sequentially described, and in order to facilitate the comparison of the differences of the respective embodiments and simplify the description, the same components are denoted by the same reference numerals in the following modified embodiments, and mainly The differences between the embodiments will be described, and the repeated portions will not be described again.
請參考第6圖與第7圖。第6圖繪示了本發明之第二實施例之變化實施例的薄膜電晶體的上視示意圖，而第7圖為第6圖之薄膜電晶體沿剖線E-E’所繪示之剖面示意圖。如第6圖與第7圖所示，本實施例之薄膜電晶體60包括一閘極G、一電容補償結構Cp、一半導體層42、一介電層44(第6 圖未示)、一汲極D、一源極S與一絕緣層46(第6圖未示)。電容補償結構Cp具有一第一延伸部E1，以及一連接至第一延伸部E1與閘極線GL之第一本體部B1(第7圖未示)，其中第一本體部B1與第一延伸部E1構成形狀約為L形，但不以此為限。其它實施例中，其它形狀亦可，例如：約曲線形、約F形、或其它合適的形狀。另外，源極S1具有一第二延伸部E2，以及一連接至第二延伸部E2之第二本體部B2(第7圖未示)，其中第二本體部B2約為矩形，而第二延伸部E2為L形，但不以此為限。第一延伸部E1實質上平行於第二延伸部E2。第一延伸部E1與第二延伸部E2垂直投影於基板4上具有一間隔(gap)g，其中間隔g係為實質上平行於半導體層42的通道長度L的方向上的長度，且間隔g實質上介於6微米與8微米之間，但不以此為限。在本實施例中，閘極G、閘極線GL與電容補償結構Cp係由同一層圖案化導電層例如第一金屬層(M1)所構成，而資料線DL、源極S與汲極D係由另一層圖案化導電層例如第二金屬層(M2)所構成，但不以此為限。舉例而言，在其它變化實施例中，資料線DL與閘極G可由同一層圖案化導電層例如第一金屬層(M1)所構成，而與電容補償結構Cp、源極S、汲極D與閘極線GL可由另一層圖案化導電層例如第二金屬層(M2)所構成。 Please refer to Figure 6 and Figure 7. 6 is a top view of a thin film transistor of a modified embodiment of the second embodiment of the present invention, and FIG. 7 is a cross-sectional view of the thin film transistor of FIG. 6 taken along line E-E'. schematic diagram. As shown in FIG. 6 and FIG. 7, the thin film transistor 60 of the present embodiment includes a gate G, a capacitor compensation structure Cp, a semiconductor layer 42, and a dielectric layer 44 (6th). The figure is not shown, a drain D, a source S and an insulating layer 46 (not shown in Fig. 6). The capacitor compensation structure Cp has a first extension E1, and a first body portion B1 (not shown in FIG. 7) connected to the first extension E1 and the gate line GL, wherein the first body portion B1 and the first extension The portion E1 is formed in an L shape, but is not limited thereto. In other embodiments, other shapes may also be, for example, about curved, about F-shaped, or other suitable shapes. In addition, the source S1 has a second extension E2, and a second body portion B2 (not shown in FIG. 7) connected to the second extension E2, wherein the second body portion B2 is approximately rectangular and the second extension Part E2 is L-shaped, but not limited to this. The first extension E1 is substantially parallel to the second extension E2. The first extension portion E1 and the second extension portion E2 are perpendicularly projected on the substrate 4 with a gap g, wherein the interval g is a length in a direction substantially parallel to the channel length L of the semiconductor layer 42, and the interval g It is substantially between 6 microns and 8 microns, but not limited to this. In this embodiment, the gate G, the gate line GL and the capacitance compensation structure Cp are composed of the same patterned conductive layer such as the first metal layer (M1), and the data line DL, the source S and the drain D It is composed of another layer of patterned conductive layer such as the second metal layer (M2), but is not limited thereto. For example, in other variant embodiments, the data line DL and the gate G may be formed by the same patterned conductive layer such as the first metal layer (M1), and the capacitance compensation structure Cp, the source S, and the drain D The gate line GL may be composed of another layer of patterned conductive layer such as a second metal layer (M2).
在本實施例中，電容補償結構Cp的第一側邊A1為第一延伸部E1面對閘極G的一側邊與電容補償結構Cp的第二側邊A2為遠離閘極G的另一側邊。半導體層42延伸重疊至於電容補償結構Cp之第一側邊A1，且源極S與電容補償結構Cp不重疊，但不以此為限。在其它變化實施例中，半導體層42可延伸至電容補償結構Cp之第二側邊A2或是突出於第二側邊A2，此時，源極S與電容補償結構Cp仍不重疊。此外，半導體層42重疊於電容補償結構Cp之第一延伸部E1的第一側邊A1具有一重疊區X，其中重疊區X垂直投影於基板4上具有一長度L3與一寬度W3，且長度L3較佳須大於半導體層42的對位誤差。重疊區X的長度L3為平行於半導體層42的 通道長度L的方向上的長度。舉例而言，在本實施例中，長度L3實質上介於1微米至5微米之間，但不以此為限。 In this embodiment, the first side A1 of the capacitance compensation structure Cp is the side of the first extension E1 facing the gate G and the second side A2 of the capacitance compensation structure Cp is the other away from the gate G. Side. The semiconductor layer 42 is extended to overlap the first side A1 of the capacitance compensation structure Cp, and the source S does not overlap with the capacitance compensation structure Cp, but is not limited thereto. In other variant embodiments, the semiconductor layer 42 may extend to the second side A2 of the capacitance compensation structure Cp or protrude from the second side A2. At this time, the source S and the capacitance compensation structure Cp still do not overlap. In addition, the first side A1 of the first extension E1 of the semiconductor layer 42 overlapped with the capacitor compensation structure C1 has an overlap region X, wherein the overlap region X is vertically projected on the substrate 4 and has a length L3 and a width W3, and the length L3 preferably needs to be larger than the alignment error of the semiconductor layer 42. The length L3 of the overlap region X is parallel to the semiconductor layer 42 The length in the direction of the channel length L. For example, in the embodiment, the length L3 is substantially between 1 micrometer and 5 micrometers, but not limited thereto.
本發明之薄膜電晶體可以應用在各類型顯示面板的畫素結構或周邊電路，或其它各種需維持電容值恆定的電子元件中。 The thin film transistor of the present invention can be applied to a pixel structure or a peripheral circuit of each type of display panel, or other various electronic components which are required to maintain a constant capacitance value.
綜上所述，本發明之畫素結構與薄膜電晶體具有電容補償結構的設計，可以避免對位誤差所產生的圖案偏移對於電容值的影響，因此可使得電容值維持恆定而使得薄膜電晶體具有一致的元件特性，並且有效提供畫素結構的顯示品質。 In summary, the pixel structure and the thin film transistor of the present invention have a capacitance compensation structure design, which can avoid the influence of the pattern shift caused by the alignment error on the capacitance value, thereby keeping the capacitance value constant and making the thin film electric The crystal has consistent component characteristics and effectively provides the display quality of the pixel structure.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
40‧‧‧薄膜電晶體 40‧‧‧film transistor
42‧‧‧半導體層 42‧‧‧Semiconductor layer
D‧‧‧汲極 D‧‧‧汲
S‧‧‧源極 S‧‧‧ source
G‧‧‧閘極 G‧‧‧ gate
Cp‧‧‧電容補償結構 Cp‧‧‧Capacitor compensation structure
A1‧‧‧第一側邊 A1‧‧‧ first side
A2‧‧‧第二側邊 A2‧‧‧ second side
L‧‧‧通道長度 L‧‧‧ channel length
W‧‧‧通道寬度 W‧‧‧ channel width
GL‧‧‧閘極線 GL‧‧‧ gate line
DL‧‧‧資料線 DL‧‧‧ data line
441‧‧‧第一開口 441‧‧‧ first opening
442‧‧‧第二開口 442‧‧‧ second opening
443‧‧‧第三開口 443‧‧‧ third opening
444‧‧‧第四開口 444‧‧‧fourth opening
X‧‧‧重疊區 X‧‧‧ overlap zone
L3‧‧‧長度 L3‧‧‧ length
W3‧‧‧寬度 W3‧‧‧Width
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104112727A TWI566024B (en) | 2012-09-20 | 2012-09-20 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104112727A TWI566024B (en) | 2012-09-20 | 2012-09-20 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201530242A TW201530242A (en) | 2015-08-01 |
| TWI566024B true TWI566024B (en) | 2017-01-11 |
Family
ID=54342694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104112727A TWI566024B (en) | 2012-09-20 | 2012-09-20 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI566024B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285302A (en) * | 1992-03-30 | 1994-02-08 | Industrial Technology Research Institute | TFT matrix liquid crystal display with compensation capacitance plus TFT stray capacitance constant irrespective of mask misalignment during patterning |
| TW201100939A (en) * | 2009-01-09 | 2011-01-01 | Century Display Shenzhen Co | Pixel structure |
| TWM397014U (en) * | 2010-07-29 | 2011-01-21 | Chunghwa Picture Tubes Ltd | Thin film transistor array substrate |
-
2012
- 2012-09-20 TW TW104112727A patent/TWI566024B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285302A (en) * | 1992-03-30 | 1994-02-08 | Industrial Technology Research Institute | TFT matrix liquid crystal display with compensation capacitance plus TFT stray capacitance constant irrespective of mask misalignment during patterning |
| TW201100939A (en) * | 2009-01-09 | 2011-01-01 | Century Display Shenzhen Co | Pixel structure |
| TWM397014U (en) * | 2010-07-29 | 2011-01-21 | Chunghwa Picture Tubes Ltd | Thin film transistor array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201530242A (en) | 2015-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI489191B (en) | Pixel structure and thin film transistor | |
| US10269879B2 (en) | Display device having an auxiliary electrode | |
| KR20170124065A (en) | Backplane Substrate and Organic Light Emitting Display Device | |
| US11751442B2 (en) | Display panel and display device | |
| TWI418909B (en) | Flat panel display device and method of manufacturing the same | |
| US11195863B2 (en) | Display panel having a storage capacitor, manufacturing method the same thereof and display module having the same | |
| US8294150B2 (en) | Panel structure including transistor and connecting elements, display device including the same, and methods of manufacturing panel structure and display device | |
| TW201639172A (en) | Pixel structure and display panel | |
| WO2021169571A1 (en) | Display panel and electronic device | |
| KR20100049385A (en) | Array substrate of organic electro-luminescent device | |
| US9269757B2 (en) | Organic light emitting diode display device | |
| KR20140022523A (en) | Thin film transistor substrate and method for manufacturing that same and organic light emitting device using that same | |
| US8390751B2 (en) | Display device and method of manufacturing the same | |
| US9230995B2 (en) | Array substrate, manufacturing method thereof and display device | |
| US9231041B2 (en) | Organic light emitting diode display device and method of manufacturing the same | |
| EP3754637B1 (en) | Pixel unit, array substrate and display device | |
| KR20150087617A (en) | Thin film transistor for a display substrate, display substrate and method of manufacturing a display substrate | |
| US10409126B2 (en) | Thin film transistor unaffected by light and display apparatus having the same | |
| JP6802653B2 (en) | Display device | |
| WO2021081814A1 (en) | Array substrate and display device | |
| KR20170078394A (en) | Array Substrate For Display Device And Method Of Fabricating The Same | |
| KR20160053383A (en) | Thin Film Transistor Array Substrate and Organic Light Emitting Diode Display Device Having The Same | |
| KR20100070729A (en) | Array substrate of organic electro-luminescent device | |
| TWI566024B (en) | Thin film transistor | |
| KR20160003105A (en) | Display device and manufacturing method thereof |