TWI565004B - Dynamic random access memory and method of manufacturing the same - Google Patents

Dynamic random access memory and method of manufacturing the same Download PDF

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TWI565004B
TWI565004B TW103128434A TW103128434A TWI565004B TW I565004 B TWI565004 B TW I565004B TW 103128434 A TW103128434 A TW 103128434A TW 103128434 A TW103128434 A TW 103128434A TW I565004 B TWI565004 B TW I565004B
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bit line
buried
random access
access memory
dynamic random
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TW103128434A
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TW201608674A (en
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田中義典
江明崇
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華邦電子股份有限公司
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Description

動態隨機存取記憶體及其製造方法 Dynamic random access memory and manufacturing method thereof

本發明是有關於一種動態隨機存取記憶體技術，且特別是有關於一種動態隨機存取記憶體及其製造方法。 The present invention relates to a dynamic random access memory technology, and more particularly to a dynamic random access memory and a method of fabricating the same.

動態隨機存取記憶體(DRAM)在隨著元件發展到奈米世代後，面臨到的困難愈來愈多，譬如讀出裕度(sensing margin)變小。目前針對改善讀出裕度的關鍵技術有三個，包括更大的儲存電容、更小的位元線間的電容量(BL capacitance,Cb)以及更小的雜訊(noise)。以目前的DRAM製程來看，因為電容器彼此的距離已經不能再縮小，所以不容易往增加儲存電容方式來改善讀出裕度。 Dynamic random access memory (DRAM) faces more and more difficulties as components develop into the nano generation, such as the sensing margin becomes smaller. There are currently three key technologies for improving read margins, including larger storage capacitors, smaller capacitance (BL capacitance, Cb), and smaller noise. In the current DRAM process, since the distance between the capacitors can no longer be reduced, it is not easy to increase the storage capacitance to improve the read margin.

因此，亟需尋求其他方式來改善奈米世代後的DRAM之讀出裕度。 Therefore, there is an urgent need to find other ways to improve the readout margin of DRAM after the nano generation.

本發明提供一種動態隨機存取記憶體，能改善讀出裕度。 The present invention provides a dynamic random access memory that improves read margin.

本發明另提供一種動態隨機存取記憶體的製造方法，可 製作出具有埋入式字元線與埋入式位元線的記憶體。 The invention further provides a method for manufacturing a dynamic random access memory, which can A memory having a buried word line and a buried bit line is fabricated.

本發明的動態隨機存取記憶體，包括矽基板、第一隔離溝渠結構、第二隔離溝渠結構、由第一與第二隔離溝渠結構定義的主動區域、位在矽基板內的埋入式字元線、位在矽基板內的埋入式位元線與電容器。上述第一隔離溝渠結構沿一第一方向平行排列在矽基板內，而上述第二隔離溝渠結構沿一第二方向平行排列在矽基板內。至於埋入式字元線是沿所述第二方向平行排列在矽基板內，且每個第二隔離溝渠結構之間設置有兩個埋入式字元線，以將每個主動區域分為一個位在所述兩個埋入式字元線之間的位元線接觸窗以及兩個電容器接觸窗。上述埋入式位元線沿一第三方向平行排列在矽基板內，且埋入式位元線位於埋入式字元線上方並與主動區域的位元線接觸窗電性連接。電容器則設置在主動區域上並與電容器接觸窗電性連接。在埋入式位元線與矽基板之間還設有氧化襯層。 The dynamic random access memory of the present invention comprises a germanium substrate, a first isolated trench structure, a second isolated trench structure, an active region defined by the first and second isolated trench structures, and a buried word located in the germanium substrate. A meta-line, a buried bit line and a capacitor located in the germanium substrate. The first isolation trench structures are arranged in parallel in a first direction in the germanium substrate, and the second isolation trench structures are arranged in parallel in a second direction in the germanium substrate. The buried word lines are arranged in parallel along the second direction in the 矽 substrate, and two buried word lines are disposed between each second isolation trench structure to divide each active area into A bit line contact window between the two buried word lines and two capacitor contact windows. The buried bit lines are arranged in parallel in a third direction in the germanium substrate, and the buried bit lines are above the buried word lines and electrically connected to the bit line contact windows of the active area. The capacitor is disposed on the active region and electrically connected to the capacitor contact window. An oxide liner is further disposed between the buried bit line and the germanium substrate.

本發明的動態隨機存取記憶體的製造方法，包括在一矽基板內形成數個第一隔離溝渠結構與數個第二隔離溝渠結構，以定義出數個主動區域。在每個第二隔離溝渠結構之間的矽基板內形成兩個埋入式字元線，以將每個主動區域分為一個位在所述兩個埋入式字元線之間的位元線接觸窗以及兩個電容器接觸窗。在矽基板內形成橫跨埋入式字元線的數個位元線溝渠，並暴露出部分矽基板，再於露出的矽基板的表面形成氧化襯層。然後，移除主動區域的位元線接觸窗上的氧化襯層，再於位元線溝渠內形成 數個埋入式位元線，其中埋入式位元線與主動區域的位元線接觸窗電性連接。在主動區域上形成與電容器接觸窗電性連接的數個電容器。 The method for manufacturing a dynamic random access memory according to the present invention comprises forming a plurality of first isolation trench structures and a plurality of second isolation trench structures in a germanium substrate to define a plurality of active regions. Forming two buried word lines in the germanium substrate between each of the second isolation trench structures to divide each active region into a bit between the two buried word lines Line contact window and two capacitor contact windows. A plurality of bit line trenches are formed in the germanium substrate across the buried word line, and a portion of the germanium substrate is exposed, and an oxide liner is formed on the surface of the exposed germanium substrate. Then, the oxide liner on the bit line contact window of the active region is removed, and then formed in the bit line trench A plurality of buried bit lines, wherein the buried bit lines are electrically connected to the bit line contact windows of the active area. A plurality of capacitors electrically connected to the capacitor contact window are formed on the active region.

基於上述，本發明藉由將字元線上方的位元線也埋入基板內，所以電容器接觸窗不會形成在位元線的側面，所以能降低電容器接觸窗與位元線之間的耦合電容量，且埋入式位元線與矽基板之間有氧化襯層相隔，所以也能藉此降低位元線之間的電容量(Cb)以及降低位元線和矽晶材之間的漏電。因此，本發明能改善DRAM之讀出裕度。 Based on the above, the present invention can also reduce the coupling between the contact window of the capacitor and the bit line by embedding the bit line above the word line in the substrate, so that the contact window of the capacitor is not formed on the side of the bit line. The capacitance, and the buried bit line and the germanium substrate are separated by an oxide liner, so that the capacitance (Cb) between the bit lines can be reduced and the space between the bit line and the germanium crystal can be reduced. Leakage. Therefore, the present invention can improve the read margin of the DRAM.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

100、200‧‧‧矽基板 100,200‧‧‧矽 substrate

102、202‧‧‧第一隔離溝渠結構 102, 202‧‧‧First isolation trench structure

104、204‧‧‧第二隔離溝渠結構 104, 204‧‧‧Second isolation trench structure

106、206‧‧‧主動區域 106, 206‧‧‧ active area

108、208‧‧‧埋入式字元線 108, 208‧‧‧ Buried word line

110、238‧‧‧埋入式位元線 110, 238‧‧‧ Buried bit line

112、252‧‧‧電容器 112, 252‧‧ ‧ capacitor

114、210‧‧‧位元線接觸窗 114, 210‧‧‧ bit line contact window

116、212‧‧‧電容器接觸窗 116, 212‧‧‧ capacitor contact window

118、232‧‧‧磊晶層或多晶矽層 118, 232‧‧‧ epitaxial or polycrystalline layer

120‧‧‧磊晶層 120‧‧‧ epitaxial layer

122、224‧‧‧氧化襯層 122, 224‧‧‧ Oxidation lining

124、230‧‧‧摻雜區 124, 230‧‧‧Doped area

126、127、129、214、223、240、248、300、314、318‧‧‧氮化矽層 126, 127, 129, 214, 223, 240, 248, 300, 314, 318 ‧ ‧ tantalum nitride layer

128、250‧‧‧氧化層 128, 250‧‧‧ oxide layer

130、320‧‧‧絕緣層 130, 320‧‧‧ insulation

132‧‧‧導體層 132‧‧‧Conductor layer

134‧‧‧介電層 134‧‧‧ dielectric layer

200a‧‧‧表面 200a‧‧‧ surface

216、246‧‧‧氧化矽層 216, 246‧‧‧ yttrium oxide layer

218‧‧‧碳層 218‧‧‧ carbon layer

220、228‧‧‧部位 220, 228‧‧‧ parts

222‧‧‧位元線溝渠 222‧‧‧ bit line ditch

226‧‧‧光阻層 226‧‧‧ photoresist layer

234‧‧‧阻障層 234‧‧‧Barrier layer

236‧‧‧金屬 236‧‧‧Metal

242‧‧‧磊晶層 242‧‧‧ epitaxial layer

244、316‧‧‧電容器開口 244, 316‧‧‧ capacitor opening

304‧‧‧開口 304‧‧‧ openings

306‧‧‧摻磷多晶矽層 306‧‧‧phosphorus-doped polysilicon layer

308‧‧‧金屬矽化層 308‧‧‧metal layer

310‧‧‧Ti/TiN層 310‧‧‧Ti/TiN layer

312‧‧‧鎢層 312‧‧‧Tungsten layer

d1、d2‧‧‧距離 D1, d2‧‧‧ distance

圖1A是依照本發明的第一實施例的一種動態隨機存取記憶體的俯視圖。 1A is a top plan view of a dynamic random access memory in accordance with a first embodiment of the present invention.

圖1B是圖1A之I-I’線段的剖面示意圖。 Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A.

圖1C是圖1A之II-II’線段的剖面示意圖。 Fig. 1C is a schematic cross-sectional view taken along line II-II' of Fig. 1A.

圖2A至圖2H是依照本發明的第二實施例的一種動態隨機存取記憶體的製造流程示意圖。 2A through 2H are schematic diagrams showing a manufacturing process of a dynamic random access memory according to a second embodiment of the present invention.

圖3A至圖3C是依照本發明的第三實施例的一種動態隨機存取記憶體的製造流程示意圖。 3A to 3C are schematic diagrams showing a manufacturing process of a dynamic random access memory according to a third embodiment of the present invention.

圖1A是依照本發明的第一實施例的一種動態隨機存取記憶體的俯視圖。圖1B是圖1A之I-I’線段的剖面示意圖。圖1C是圖1A之II-II’線段的剖面示意圖。 1A is a top plan view of a dynamic random access memory in accordance with a first embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along line II-II' of Fig. 1A.

請同時參照圖1A、1B與1C，本實施例之動態隨機存取記憶體包括矽基板100、第一隔離溝渠結構102、第二隔離溝渠結構104、主動區域106、位在矽基板100內的埋入式字元線108、位在矽基板100內的埋入式位元線110以及電容器112。為了清楚說明動態隨機存取記憶體的線路，圖1A中僅顯示以上構件，其他結構可見圖1B和圖1C的剖面圖。 Referring to FIG. 1A, FIG. 1B and FIG. 1C, the dynamic random access memory of the present embodiment includes a germanium substrate 100, a first isolation trench structure 102, a second isolation trench structure 104, an active region 106, and a germanium substrate 100. The buried word line 108, the buried bit line 110 located in the germanium substrate 100, and the capacitor 112. In order to clearly illustrate the line of the DRAM, only the above components are shown in FIG. 1A, and other structures can be seen in the cross-sectional views of FIGS. 1B and 1C.

在第一實施例中，第一隔離溝渠結構102沿第一方向平行排列在矽基板100內、第二隔離溝渠結構104沿第二方向平行排列在矽基板100內，其中第一方向與第二方向在本實施例是夾一銳角θ，但本發明並不限於此。由上述第一與第二隔離溝渠結構102和104所定義的區域即主動區域106。至於埋入式字元線108是沿第二方向平行排列在矽基板100內，且兩兩第二隔離溝渠結構104之間設置有兩個埋入式字元線108，以將每個主動區域106分為一個位在兩埋入式字元線108之間的位元線接觸窗114以及兩個電容器接觸窗(capacitor contact,CC)116。而埋入式位元線110是沿第三方向平行排列在矽基板100內，且埋入式位元線110位於埋入式字元線108上方並與主動區域106的位元線接觸窗114 電性連接，譬如通過設置在埋入式位元線110與位元線接觸窗114之間的磊晶層或多晶矽(poly)層118，使埋入式位元線110與位元線接觸窗114電性相連並降低阻值。至於電容器112是設置在主動區域106上並與電容器接觸窗116電性連接，譬如通過設置在電容器112與電容器接觸窗116之間的磊晶層120，使兩者電性相連並降低阻值。 In the first embodiment, the first isolation trench structures 102 are arranged in parallel in the first direction in the first substrate 100, and the second isolation trench structures 104 are arranged in parallel in the second direction in the second substrate 100, wherein the first direction and the second direction are The direction is an acute angle θ in the present embodiment, but the present invention is not limited thereto. The active area 106 is defined by the first and second isolation trench structures 102 and 104 described above. The buried word lines 108 are arranged in parallel in the second direction in the second substrate 100, and two buried word lines 108 are disposed between the two second isolation trench structures 104 to each active area. 106 is divided into a bit line contact window 114 between the two buried word lines 108 and two capacitor contact (CC) 116. The buried bit line 110 is arranged in parallel along the third direction in the germanium substrate 100, and the buried bit line 110 is located above the buried word line 108 and is in contact with the bit line 114 of the active region 106. Electrically connected, such as by an epitaxial layer or polysilicon layer 118 disposed between the buried bit line 110 and the bit line contact window 114, such that the buried bit line 110 and the bit line contact window 114 is electrically connected and reduces the resistance. As for the capacitor 112, it is disposed on the active region 106 and electrically connected to the capacitor contact window 116. For example, through the epitaxial layer 120 disposed between the capacitor 112 and the capacitor contact window 116, the two are electrically connected and the resistance is lowered.

請繼續參照圖1B和圖1C，在埋入式位元線110與矽基板100之間還設有氧化襯層(oxide liner)122，以隔離埋入式位元線110與矽基板100並藉此降低位元線間的電容量(BL capacitance,Cb)。另外，在主動區域106的位元線接觸窗114內如有摻雜區124，則有利於電性操作。在埋入式位元線110與埋入式字元線108之間則可利用如氮化矽層126之類的膜層來進行隔離。而在埋入式位元線110上方可設置氮化矽層127來隔絕埋入式位元線110和電容器接觸窗116。另外，埋入式字元線108與埋入式位元線110一般是由金屬與阻障層構成，所以圖中的埋入式字元線108與埋入式位元線110跟矽基板100之間都有薄氧化層128來作隔絕。舉例來說，埋入式位元線110可為W/TiN/Ti或W/TiN/Ti/poly的結構。另外，在薄氧化層128上可形成一層氮化矽層129，當作電容器112之圖案定義時的控制層(control layer)，而電容器112通常設置在矽基底100上的絕緣層130內，並且由兩層導體層132夾一層介電層134所構成，其中導體層132如為TiN(或TiN/SiGe)、介電層134如為ZAZ(即ZrO2/Al2O3/ZrO2)之類的介電 材料，則可適用於60nm以下的DRAM。由於位元線110埋入矽基板100內，所以可降低電容器接觸窗116與埋入式位元線110之間的耦合電容量(coupling capacitance)。 Referring to FIG. 1B and FIG. 1C , an oxide liner 122 is further disposed between the buried bit line 110 and the germanium substrate 100 to isolate the buried bit line 110 from the germanium substrate 100. This reduces the capacitance between the bit lines (BL capacitance, Cb). In addition, if there is a doped region 124 within the bit line contact window 114 of the active region 106, electrical operation is facilitated. Between the buried bit line 110 and the buried word line 108, a film layer such as a tantalum nitride layer 126 can be used for isolation. A tantalum nitride layer 127 may be disposed over the buried bit line 110 to insulate the buried bit line 110 and the capacitor contact window 116. In addition, the buried word line 108 and the buried bit line 110 are generally composed of a metal and a barrier layer, so the buried word line 108 and the buried bit line 110 in the figure follow the substrate 100. There is a thin oxide layer 128 between them for isolation. For example, the buried bit line 110 can be a W/TiN/Ti or W/TiN/Ti/poly structure. In addition, a layer of tantalum nitride 129 may be formed on the thin oxide layer 128 as a control layer when the pattern of the capacitor 112 is defined, and the capacitor 112 is usually disposed in the insulating layer 130 on the germanium substrate 100, and The dielectric layer 132 is composed of a dielectric layer 134, wherein the conductive layer 132 is TiN (or TiN/SiGe), and the dielectric layer 134 is ZAZ (ie, ZrO 2 /Al 2 O 3 /ZrO 2 ). Dielectric materials of the type can be applied to DRAMs below 60 nm. Since the bit line 110 is buried in the germanium substrate 100, the coupling capacitance between the capacitor contact window 116 and the buried bit line 110 can be reduced.

圖2A至圖2H是依照本發明的第二實施例的一種動態隨機存取記憶體的製造流程示意圖，其中每一個圖均包括數個剖面以利說明。 2A through 2H are schematic diagrams showing a manufacturing process of a dynamic random access memory according to a second embodiment of the present invention, wherein each of the figures includes a plurality of sections for illustration.

請先參照圖2A的(I)~(III)，其中(II)是(I)之II-II’線段的剖面、(III)是(I)之III-III’線段的剖面。先在矽基板200內形成數個第一隔離溝渠結構202與數個第二隔離溝渠結構204，以定義出數個主動區域206。然後，在每個第二隔離溝渠結構204之間的矽基板200內形成兩個埋入式字元線208，以將每個主動區域206分為一個位在埋入式字元線208之間的位元線接觸窗210以及兩個電容器接觸窗212。由於埋入式字元線208是位在矽基板200之表面200a下一段距離d1的位置，所以可在埋入式字元線208上填入氮化矽層214。而且為了後續要形成埋入式位元線，可在定義出主動區域206之後，於矽基板200全面地形成一層氧化矽層216。 Referring first to (I) to (III) of Fig. 2A, (II) is a cross section of the II-II' line segment of (I), and (III) is a cross section of the III-III' line segment of (I). A plurality of first isolation trench structures 202 and a plurality of second isolation trench structures 204 are formed in the germanium substrate 200 to define a plurality of active regions 206. Then, two buried word lines 208 are formed in the germanium substrate 200 between each of the second isolation trench structures 204 to divide each active region 206 into one bit between the buried word lines 208. The bit line contact window 210 and the two capacitor contact windows 212. Since the buried word line 208 is located at a distance d1 below the surface 200a of the germanium substrate 200, the tantalum nitride layer 214 can be filled in the buried word line 208. Moreover, in order to form a buried bit line later, a layer of ruthenium oxide layer 216 may be formed on the ruthenium substrate 200 after the active region 206 is defined.

然後請參照圖2B的(II)~(III)，其為延續上圖的剖面示意圖。在矽基板200全面地形成碳層218作為蝕刻罩幕，但本發明並不限於此。本圖是用來說明如何製作出要形成埋入式位元線的溝渠，所以凡是能製作出溝渠的技術均可應用於此階段。 Then, refer to (II) to (III) of FIG. 2B, which is a schematic cross-sectional view of the above figure. The carbon layer 218 is entirely formed on the tantalum substrate 200 as an etching mask, but the present invention is not limited thereto. This figure is used to illustrate how to create a trench to form a buried bit line, so any technique that can make a ditch can be applied at this stage.

接著，請參照圖2C的(I)~(V)，其中(II)是(I)之II-II’線 段的剖面、(III)是(I)之III-III’線段的剖面、(IV)是(I)之IV-IV’線段的剖面、(V)是(I)之V-V’線段的剖面。在圖案化氧化矽層216與圖2B之碳層218後，露出預定形成溝渠的部位220，然後進行蝕刻，將部位220底下的矽基板200、第一隔離溝渠結構202、第二隔離溝渠結構204、部分氮化矽層214等移除，並停在埋入式字元線208上方的部分氮化矽層214上，然後再將碳層218完全移除，以形成橫跨埋入式字元線208的數個位元線溝渠222。此時，有部分矽基板200會暴露出來，需於露出的矽基板200的表面形成氧化襯層224，其形成方法例如電漿氧化或高溫熱氧化法。氧化襯層224將作於隔離後續形成之埋入式位元線與矽基板200，以作之間的絕緣。 Next, please refer to (I) to (V) of FIG. 2C, wherein (II) is the II-II' line of (I) The section of the section, (III) is the section of the III-III' line segment of (I), (IV) is the section of the IV-IV' line segment of (I), and (V) is the V-V' line segment of (I) section. After patterning the yttrium oxide layer 216 and the carbon layer 218 of FIG. 2B, the portion 220 where the trench is formed is exposed, and then etching is performed, and the ruthenium substrate 200, the first isolation trench structure 202, and the second isolation trench structure 204 under the portion 220 are etched. A portion of the tantalum nitride layer 214 is removed and stopped on a portion of the tantalum nitride layer 214 above the buried word line 208, and then the carbon layer 218 is completely removed to form a buried character. A plurality of bit line trenches 222 of line 208. At this time, a part of the ruthenium substrate 200 is exposed, and an oxide liner 224 is formed on the surface of the exposed ruthenium substrate 200, such as plasma oxidation or high temperature thermal oxidation. The oxide liner 224 will be used to isolate the subsequently formed buried bit line from the germanium substrate 200 for isolation therebetween.

然後，請參照圖2D的(I)~(V)，其中(II)~(V)是分別為(I)的各線段的剖面。為了移除位元線接觸窗210上的氧化襯層224，可利用光阻層226遮蔽其餘部位，只露出有位元線接觸窗210的部位228，然後利用濕式蝕刻或乾式蝕刻去除位元線接觸窗210上的氧化層。之後可選擇性地在位元線接觸窗210內形成含砷或磷的摻雜區230。 Then, refer to (I) to (V) of FIG. 2D, where (II) to (V) are cross sections of the respective line segments of (I). In order to remove the oxide liner 224 on the bit line contact window 210, the remaining portion can be shielded by the photoresist layer 226, only the portion 228 of the bit line contact window 210 is exposed, and then the bit is removed by wet etching or dry etching. The oxide layer on the line contact window 210. A doped region 230 containing arsenic or phosphorus may then be selectively formed within the bit line contact window 210.

隨後，請參照圖2E的(II)~(V)，在主動區域206的位元線接觸窗210上可選擇性地形成磊晶層或多晶矽層232，來降低阻值。然後，形成阻障層234並形成金屬236填滿位元線溝渠222，其中阻障層234例如Ti/TiN、金屬236例如鎢(W)。 Subsequently, referring to (II) to (V) of FIG. 2E, an epitaxial layer or a polysilicon layer 232 may be selectively formed on the bit line contact window 210 of the active region 206 to reduce the resistance. Then, a barrier layer 234 is formed and a metal 236 is formed to fill the bit line trench 222, wherein the barrier layer 234 is, for example, Ti/TiN, metal 236 such as tungsten (W).

之後，請參照圖2F的(I)~(V)，其中(II)~(V)是分別為(I) 的各線段的剖面。對上一圖中形成的阻障層234與金屬236進行回蝕刻，直到其頂面低於矽基板200之表面200a一段距離d2，以於位元線溝渠222內形成由阻障層234和金屬236構成之埋入式位元線238，其中埋入式位元線238與位元線接觸窗210電性連接。在此階段即完成埋入式位元線238的設置。 After that, please refer to (I)~(V) of Fig. 2F, where (II)~(V) are respectively (I) The section of each line segment. The barrier layer 234 and the metal 236 formed in the previous figure are etched back until the top surface thereof is lower than the surface 200a of the germanium substrate 200 by a distance d2 to form the barrier layer 234 and the metal in the bit line trench 222. 236 constitutes a buried bit line 238 in which the buried bit line 238 is electrically coupled to the bit line contact window 210. The setting of the buried bit line 238 is completed at this stage.

接著，請參照圖2G的(I)~(III)，其中(II)~(III)是分別為(I)的各線段的剖面。為了製作電容器，可先在矽基板200上沉積氮化矽層240並對其進行如化學機械研磨(CMP)或蝕刻的製程，以於埋入式位元線238上形成作為保護用的氮化矽層240，然後進行電容器接觸窗的曝光與自我對準蝕刻，以去除圖2F中的氧化矽層216，而露出電容器接觸窗212。接著，可在電容器接觸窗212表面成長磊晶層242之類的結構來降低阻值。 Next, please refer to (I) to (III) of FIG. 2G, wherein (II) to (III) are cross sections of the respective line segments of (I). In order to fabricate a capacitor, a tantalum nitride layer 240 may be deposited on the tantalum substrate 200 and subjected to a process such as chemical mechanical polishing (CMP) or etching to form a nitride for protection on the buried bit line 238. The layer 240 is then exposed and self-aligned to the capacitor contact window to remove the hafnium oxide layer 216 of FIG. 2F to expose the capacitor contact window 212. Next, a structure such as an epitaxial layer 242 may be grown on the surface of the capacitor contact window 212 to lower the resistance.

然後，請參照圖2H的(I)~(III)，其中(II)~(III)是分別為(I)的各線段的剖面。在矽基板200上先形成氧化矽層246和氮化矽層248，再沉積厚度1μm以上的氧化層250作為後續電容器製作用。之後，利用氮化矽層248作為控制層，定義出電容器開口244，然後在電容器開口244形成與電容器接觸窗212電性連接的數個電容器252，其中電容器252例如由兩層導體層夾一層介電層所構成。譬如用於60nm以下的DRAM的話，與電容器接觸窗212(表面之磊晶層242)接觸的導體層可用TiN、介電層可用選自ZrO2、Al2O3、HfO2所組成之群組的介電材料、最外層的導體層可用TiN再加上一層降低應力的SiGe層，然本發明並不限於此。 Then, refer to (I) to (III) of FIG. 2H, wherein (II) to (III) are cross sections of the respective line segments of (I). A tantalum oxide layer 246 and a tantalum nitride layer 248 are first formed on the tantalum substrate 200, and an oxide layer 250 having a thickness of 1 μm or more is deposited as a subsequent capacitor. Thereafter, a capacitor opening 244 is defined by using a tantalum nitride layer 248 as a control layer, and then a plurality of capacitors 252 are formed in the capacitor opening 244 to be electrically connected to the capacitor contact window 212, wherein the capacitor 252 is sandwiched by, for example, two layers of conductor layers. The electric layer is composed of. For example, for a DRAM of 60 nm or less, the conductor layer in contact with the capacitor contact window 212 (the epitaxial layer 242 of the surface) may be TiN, and the dielectric layer may be a group selected from the group consisting of ZrO 2 , Al 2 O 3 , and HfO 2 . The dielectric material and the outermost conductor layer may be TiN plus a layer of stress-relieving SiGe layer, but the invention is not limited thereto.

圖3A至圖3C是依照本發明的第三實施例的一種動態隨機存取記憶體的製造流程示意圖，且本實施例是接續上圖2F，所以部分構件與第二實施例相同。 3A to 3C are schematic diagrams showing a manufacturing process of a dynamic random access memory according to a third embodiment of the present invention, and the present embodiment is continued from FIG. 2F, so that some of the components are the same as the second embodiment.

請參照圖3A的(I)~(III)，其中(II)~(III)是分別為(I)的各線段的剖面。為了製作電容器，於埋入式位元線238上形成作為保護用的氮化矽層300，然後形成露出電容器接觸窗212的開口304，於電容器接觸窗212上沉積摻雜磷多晶矽層306，之後CMP或回蝕刻。 Please refer to (I) to (III) of FIG. 3A, wherein (II) to (III) are cross sections of the respective line segments of (I). To form a capacitor, a tantalum nitride layer 300 is formed as a protective layer on the buried bit line 238, and then an opening 304 is formed to expose the capacitor contact window 212, and a doped phosphor polysilicon layer 306 is deposited on the capacitor contact window 212, after which CMP or etch back.

然後，請參照圖3B的(II)~(III)，可選擇在摻磷多晶矽層306形成金屬矽化層308(如CoSi或TiSi)，然後沉積如Ti/TiN層310與鎢層312的導體結構，再進行蝕刻，以保留開口304上方的導體結構。 Then, referring to (II) to (III) of FIG. 3B, a metal germanide layer 308 (such as CoSi or TiSi) may be selectively formed in the phosphorus-doped polysilicon layer 306, and then a conductor structure such as a Ti/TiN layer 310 and a tungsten layer 312 may be deposited. Etching is then performed to preserve the conductor structure above the opening 304.

之後，請參照圖3C的(II)~(III)，沉積氮化矽層314並進行平坦化，使其存於鎢層312之兩側。接著，在矽基板200上沉積另一氮化矽層318(作為電容器蝕刻之停止層)，再沉積絕緣層320之後定義出電容器開口316，即可進行如圖2H的電容器製作流程，故不再贅述。 Thereafter, referring to (II) to (III) of FIG. 3C, a tantalum nitride layer 314 is deposited and planarized so as to be deposited on both sides of the tungsten layer 312. Next, another tantalum nitride layer 318 is deposited on the germanium substrate 200 (as a stop layer for capacitor etching), and after the insulating layer 320 is deposited, the capacitor opening 316 is defined, and the capacitor fabrication process as shown in FIG. 2H can be performed. Narration.

綜上所述，在本發明的DRAM中，字元線與位元線均埋設於基板內部，所以電容器接觸窗不會形成在位元線的側面，固可降低電容器接觸窗與位元線之間的耦合電容量，且埋入式位元線與矽基板之間有氧化襯層相隔，所以也能藉此降低位元線和矽晶材之間的漏電，並進而增加DRAM之讀出裕度。 In summary, in the DRAM of the present invention, both the word line and the bit line are buried inside the substrate, so the capacitor contact window is not formed on the side of the bit line, which can reduce the contact window and the bit line of the capacitor. The coupling capacitance between the buried bit line and the germanium substrate is separated by an oxide liner, so that the leakage between the bit line and the germanium crystal can be reduced, thereby increasing the readout margin of the DRAM. degree.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

102‧‧‧第一隔離溝渠結構 102‧‧‧First isolation trench structure

104‧‧‧第二隔離溝渠結構 104‧‧‧Second isolation trench structure

106‧‧‧主動區域 106‧‧‧Active area

108‧‧‧埋入式字元線 108‧‧‧Blinded word line

110‧‧‧埋入式位元線 110‧‧‧Blinded bit line

112‧‧‧電容器 112‧‧‧ capacitor

116‧‧‧電容器接觸窗 116‧‧‧ capacitor contact window

Claims (11)

一種動態隨機存取記憶體，包括：一矽基板；多數個第一隔離溝渠結構，沿一第一方向平行排列在該矽基板內；多數個第二隔離溝渠結構，沿一第二方向平行排列在該矽基板內，且該些第一隔離溝渠結構與該些第二隔離溝渠結構定義出多數個主動區域；多數個埋入式字元線，沿該第二方向平行排列在該矽基板內，且每個第二隔離溝渠結構之間設置有兩個埋入式字元線，以將每個主動區域分為一個位在所述兩個埋入式字元線之間的位元線接觸窗以及兩個電容器接觸窗；多數個埋入式位元線，沿一第三方向平行排列在該矽基板內，且該些埋入式位元線位於該些埋入式字元線上方並與該些主動區域的該位元線接觸窗電性連接；多數個電容器，設置在該些主動區域上並與該些電容器接觸窗電性連接；以及一氧化襯層，設置在該些埋入式位元線與該矽基板之間。 A dynamic random access memory, comprising: a germanium substrate; a plurality of first isolated trench structures arranged in parallel along a first direction in the germanium substrate; and a plurality of second isolated trench structures arranged in parallel along a second direction In the 矽 substrate, the first isolation trench structure and the second isolation trench structures define a plurality of active regions; a plurality of buried word lines are arranged in parallel along the second direction in the 矽 substrate And two buried word lines are disposed between each of the second isolation trench structures to divide each active area into a bit line contact between the two buried word lines a window and two capacitor contact windows; a plurality of buried bit lines are arranged in parallel along a third direction in the germanium substrate, and the buried bit lines are located above the buried word lines Electrically connecting to the bit line contact window of the active regions; a plurality of capacitors disposed on the active regions and electrically connected to the capacitor contact windows; and an oxide liner disposed on the buried holes Type bit line and the germanium substrate . 如申請專利範圍第1項所述的動態隨機存取記憶體，更包括多數個氮化矽層位於該些埋入式字元線上，以與該些埋入式位元線隔離。 The dynamic random access memory according to claim 1, further comprising a plurality of tantalum nitride layers on the buried word lines to be isolated from the buried bit lines. 如申請專利範圍第1項所述的動態隨機存取記憶體，更包 括多數個磊晶層，位於該些埋入式位元線與該些主動區域的該位元線接觸窗之間。 The dynamic random access memory as described in claim 1 of the patent application, A plurality of epitaxial layers are disposed between the buried bit lines and the bit line contact windows of the active regions. 如申請專利範圍第1項所述的動態隨機存取記憶體，更包括多數個多晶矽層，位於該些埋入式位元線與該些主動區域的該位元線接觸窗之間。 The dynamic random access memory according to claim 1, further comprising a plurality of polysilicon layers between the buried bit lines and the bit line contact windows of the active regions. 如申請專利範圍第1項所述的動態隨機存取記憶體，更包括多數個摻雜區，位於該些主動區域的該位元線接觸窗內。 The dynamic random access memory according to claim 1, further comprising a plurality of doped regions located in the bit line contact window of the active regions. 如申請專利範圍第1項所述的動態隨機存取記憶體，其中該第一方向與該第二方向夾一銳角。 The dynamic random access memory according to claim 1, wherein the first direction and the second direction are at an acute angle. 一種動態隨機存取記憶體的製造方法，包括：在一矽基板內形成多數個第一隔離溝渠結構與多數個第二隔離溝渠結構，以定義出多數個主動區域；在每個第二隔離溝渠結構之間的該矽基板內形成兩個埋入式字元線，以將每個主動區域分為一個位在所述兩個埋入式字元線之間的位元線接觸窗以及兩個電容器接觸窗；在該矽基板內形成橫跨該些埋入式字元線的多數個位元線溝渠，並暴露出部分該矽基板；於露出的該矽基板的表面形成氧化襯層；移除該些主動區域的該位元線接觸窗上的該氧化襯層；於該些位元線溝渠內形成多數個埋入式位元線，其中該些埋入式位元線與該些主動區域的該位元線接觸窗電性連接；以及在該些主動區域上形成與該些電容器接觸窗電性連接的多數 個電容器。 A method for manufacturing a dynamic random access memory, comprising: forming a plurality of first isolation trench structures and a plurality of second isolation trench structures in a germanium substrate to define a plurality of active regions; and each second isolation trench Two buried word lines are formed in the germanium substrate between the structures to divide each active region into a bit line contact window between the two buried word lines and two a capacitor contact window; forming a plurality of bit line trenches across the buried word lines in the germanium substrate, and exposing a portion of the germanium substrate; forming an oxide liner on the exposed surface of the germanium substrate; Except for the oxide liner on the bit line contact window of the active regions; forming a plurality of buried bit lines in the bit line trenches, wherein the buried bit lines and the active The bit line contact window of the region is electrically connected; and a plurality of contacts electrically connected to the capacitor contact windows are formed on the active regions Capacitors. 如申請專利範圍第7項所述的動態隨機存取記憶體的製造方法，其中形成該氧化襯層的方法包括電漿氧化或高溫熱氧化法。 The method of manufacturing a dynamic random access memory according to claim 7, wherein the method of forming the oxide liner comprises plasma oxidation or high temperature thermal oxidation. 如申請專利範圍第7項所述的動態隨機存取記憶體的製造方法，其中形成該些位元線溝渠之前更包括：在該些埋入式字元線上填入氮化矽層。 The method for manufacturing a dynamic random access memory according to claim 7, wherein before forming the bit line trenches, the method further comprises: filling the buried word lines with a tantalum nitride layer. 如申請專利範圍第7項所述的動態隨機存取記憶體的製造方法，其中形成該些埋入式位元線之前更包括：在該些主動區域的該位元線接觸窗上形成磊晶層或多晶矽層。 The method for manufacturing a dynamic random access memory according to claim 7, wherein the forming the buried bit lines further comprises: forming an epitaxial layer on the bit line contact window of the active regions; Layer or polysilicon layer. 如申請專利範圍第7項所述的動態隨機存取記憶體的製造方法，其中移除該氧化襯層之後更包括：於該些主動區域的該位元線接觸窗內形成多數個摻雜區。 The method for manufacturing a dynamic random access memory according to claim 7, wherein the removing the oxide liner further comprises: forming a plurality of doped regions in the bit line contact window of the active regions; .
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