TWI562317B - Subtractive self-aligned via and plug patterning for back end of line (beol) interconnects - Google Patents
Subtractive self-aligned via and plug patterning for back end of line (beol) interconnectsInfo
- Publication number
- TWI562317B TWI562317B TW103132260A TW103132260A TWI562317B TW I562317 B TWI562317 B TW I562317B TW 103132260 A TW103132260 A TW 103132260A TW 103132260 A TW103132260 A TW 103132260A TW I562317 B TWI562317 B TW I562317B
- Authority
- TW
- Taiwan
- Prior art keywords
- beol
- interconnects
- line
- back end
- aligned via
- Prior art date
Links
- 238000000059 patterning Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2013/062319 WO2015047318A1 (en) | 2013-09-27 | 2013-09-27 | Subtractive self-aligned via and plug patterning for back end of line (beol) interconnects |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201521173A TW201521173A (zh) | 2015-06-01 |
TWI562317B true TWI562317B (en) | 2016-12-11 |
Family
ID=52744218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103132260A TWI562317B (en) | 2013-09-27 | 2014-09-18 | Subtractive self-aligned via and plug patterning for back end of line (beol) interconnects |
Country Status (6)
Country | Link |
---|---|
US (1) | US9793163B2 (zh) |
EP (1) | EP3050087B1 (zh) |
KR (1) | KR102167351B1 (zh) |
CN (1) | CN105493250B (zh) |
TW (1) | TWI562317B (zh) |
WO (1) | WO2015047318A1 (zh) |
Families Citing this family (38)
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US9236342B2 (en) * | 2013-12-18 | 2016-01-12 | Intel Corporation | Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects |
CN108012562B (zh) | 2015-06-26 | 2022-03-01 | 英特尔公司 | 用于自对准互连件、插塞和过孔的织物式图案化 |
US10490416B2 (en) | 2015-11-16 | 2019-11-26 | Intel Corporation | Structures and methods for improved lithographic processing |
WO2017111924A1 (en) * | 2015-12-21 | 2017-06-29 | Intel Corporation | Grating based plugs and cuts for feature end formation for back end of line (beol) interconnects and structures resulting therefrom |
US10867853B2 (en) * | 2016-05-27 | 2020-12-15 | Intel Corporation | Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects |
WO2018057042A1 (en) * | 2016-09-26 | 2018-03-29 | Intel Corporation | Preformed interlayer connections for integrated circuit devices |
US11527433B2 (en) | 2016-09-30 | 2022-12-13 | Intel Corporation | Via and plug architectures for integrated circuit interconnects and methods of manufacture |
US11171043B2 (en) | 2016-09-30 | 2021-11-09 | Intel Corporation | Plug and trench architectures for integrated circuits and methods of manufacture |
US10879120B2 (en) * | 2016-11-28 | 2020-12-29 | Taiwan Semiconductor Manufacturing | Self aligned via and method for fabricating the same |
CN110337715B (zh) | 2016-12-23 | 2023-08-25 | 英特尔公司 | 高级光刻和自组装装置 |
WO2018125109A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | Subtractive plug etching |
EP3401948B1 (en) | 2017-05-10 | 2019-12-11 | IMEC vzw | A method for patterning a target layer |
US10515896B2 (en) * | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
CN115831969A (zh) * | 2017-11-30 | 2023-03-21 | 英特尔公司 | 用于高级集成电路结构制造的鳍状物图案化 |
JP7348441B2 (ja) | 2018-04-03 | 2023-09-21 | 東京エレクトロン株式会社 | 完全自己整合方式を使用するサブトラクティブ相互接続形成 |
US10192780B1 (en) | 2018-05-29 | 2019-01-29 | Globalfoundries Inc. | Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks |
US10727124B2 (en) | 2018-10-29 | 2020-07-28 | International Business Machines Corporation | Structure and method for forming fully-aligned trench with an up-via integration scheme |
EP3671821A1 (en) * | 2018-12-19 | 2020-06-24 | IMEC vzw | Interconnection system of an integrated circuit |
US11205588B2 (en) | 2019-07-10 | 2021-12-21 | International Business Machines Corporation | Interconnect architecture with enhanced reliability |
US11322402B2 (en) | 2019-08-14 | 2022-05-03 | International Business Machines Corporation | Self-aligned top via scheme |
US10978343B2 (en) | 2019-08-16 | 2021-04-13 | International Business Machines Corporation | Interconnect structure having fully aligned vias |
US11404317B2 (en) * | 2019-09-24 | 2022-08-02 | International Business Machines Corporation | Method for fabricating a semiconductor device including self-aligned top via formation at line ends |
US11094580B2 (en) | 2019-10-01 | 2021-08-17 | International Business Machines Corporation | Structure and method to fabricate fully aligned via with reduced contact resistance |
US11069610B2 (en) * | 2019-10-15 | 2021-07-20 | Micron Technology, Inc. | Methods for forming microelectronic devices with self-aligned interconnects, and related devices and systems |
US11508617B2 (en) | 2019-10-24 | 2022-11-22 | Applied Materials, Inc. | Method of forming interconnect for semiconductor device |
US11257677B2 (en) | 2020-01-24 | 2022-02-22 | Applied Materials, Inc. | Methods and devices for subtractive self-alignment |
US11444029B2 (en) | 2020-02-24 | 2022-09-13 | International Business Machines Corporation | Back-end-of-line interconnect structures with varying aspect ratios |
US11094590B1 (en) | 2020-03-09 | 2021-08-17 | International Business Machines Corporation | Structurally stable self-aligned subtractive vias |
US11328954B2 (en) | 2020-03-13 | 2022-05-10 | International Business Machines Corporation | Bi metal subtractive etch for trench and via formation |
US11410879B2 (en) | 2020-04-07 | 2022-08-09 | International Business Machines Corporation | Subtractive back-end-of-line vias |
US11270913B2 (en) | 2020-04-28 | 2022-03-08 | International Business Machines Corporation | BEOL metallization formation |
US11495538B2 (en) | 2020-07-18 | 2022-11-08 | International Business Machines Corporation | Fully aligned via for interconnect |
US11302637B2 (en) | 2020-08-14 | 2022-04-12 | International Business Machines Corporation | Interconnects including dual-metal vias |
EP3982399A1 (en) | 2020-10-06 | 2022-04-13 | Imec VZW | A method for producing an interconnect via |
US11315872B1 (en) | 2020-12-10 | 2022-04-26 | International Business Machines Corporation | Self-aligned top via |
US11682617B2 (en) | 2020-12-22 | 2023-06-20 | International Business Machines Corporation | High aspect ratio vias for integrated circuits |
US11688636B2 (en) | 2021-06-18 | 2023-06-27 | International Business Machines Corporation | Spin on scaffold film for forming topvia |
US11876047B2 (en) | 2021-09-14 | 2024-01-16 | International Business Machines Corporation | Decoupled interconnect structures |
Citations (2)
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TW483069B (en) * | 2000-09-13 | 2002-04-11 | Chartered Semiconductor Mfg | Laser curing of spin-on dielectric thin films |
TW201250920A (en) * | 2011-06-10 | 2012-12-16 | Toshiba Kk | Interconnect structure with improved alignment for semiconductor devices |
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DE10222609B4 (de) | 2002-04-15 | 2008-07-10 | Schott Ag | Verfahren zur Herstellung strukturierter Schichten auf Substraten und verfahrensgemäß beschichtetes Substrat |
US7268486B2 (en) * | 2002-04-15 | 2007-09-11 | Schott Ag | Hermetic encapsulation of organic, electro-optical elements |
US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8404600B2 (en) | 2008-06-17 | 2013-03-26 | Micron Technology, Inc. | Method for forming fine pitch structures |
US8299622B2 (en) * | 2008-08-05 | 2012-10-30 | International Business Machines Corporation | IC having viabar interconnection and related method |
US8435851B2 (en) | 2011-01-12 | 2013-05-07 | International Business Machines Corporation | Implementing semiconductor SoC with metal via gate node high performance stacked transistors |
CN102709180A (zh) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | 一种铝薄膜的制备工艺 |
US9041217B1 (en) * | 2013-12-18 | 2015-05-26 | Intel Corporation | Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects |
US9236342B2 (en) * | 2013-12-18 | 2016-01-12 | Intel Corporation | Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects |
-
2013
- 2013-09-27 US US14/912,036 patent/US9793163B2/en active Active
- 2013-09-27 KR KR1020167003990A patent/KR102167351B1/ko active IP Right Grant
- 2013-09-27 CN CN201380079168.XA patent/CN105493250B/zh active Active
- 2013-09-27 WO PCT/US2013/062319 patent/WO2015047318A1/en active Application Filing
- 2013-09-27 EP EP13894766.8A patent/EP3050087B1/en active Active
-
2014
- 2014-09-18 TW TW103132260A patent/TWI562317B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW483069B (en) * | 2000-09-13 | 2002-04-11 | Chartered Semiconductor Mfg | Laser curing of spin-on dielectric thin films |
TW201250920A (en) * | 2011-06-10 | 2012-12-16 | Toshiba Kk | Interconnect structure with improved alignment for semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US20160197011A1 (en) | 2016-07-07 |
EP3050087B1 (en) | 2020-04-29 |
KR102167351B1 (ko) | 2020-10-19 |
CN105493250A (zh) | 2016-04-13 |
KR20160064074A (ko) | 2016-06-07 |
US9793163B2 (en) | 2017-10-17 |
CN105493250B (zh) | 2018-12-18 |
TW201521173A (zh) | 2015-06-01 |
EP3050087A1 (en) | 2016-08-03 |
WO2015047318A1 (en) | 2015-04-02 |
EP3050087A4 (en) | 2017-07-26 |
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