TWI557847B - 具有引發應力之源極/汲極形成用間隔件的鰭式場效電晶體及用以製造該鰭式場效電晶體的方法 - Google Patents
具有引發應力之源極/汲極形成用間隔件的鰭式場效電晶體及用以製造該鰭式場效電晶體的方法 Download PDFInfo
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Description
本發明大體上係關於半導體裝置和製造半導體之方法,而尤係關於具有引發應力源極/汲極形成用間隔件之鰭式場效電晶體(FinFET)結構,和製造此FinFET結構之方法。
相對於使用習知的微影術製造方法製造之傳統的平面型金屬氧化物半導體場效電晶體(MOSFET),非平面FET加入各種的垂直電晶體結構。一種此種半導體結構為“FinFET”,其名稱係取自多個薄矽“鰭”,該等鰭用來形成各自的閘極通道,而該等通道寬度典型在數十奈米量級。
詳言之,參照第1圖中所示之先前技術的非平面FET結構範例,FinFET 100通常包含二個或更多個平行矽鰭結構(或簡稱“鰭”)104和106。這些結構典型使用絕緣層上覆矽(SOI)基板(未圖示),具有鰭104和106延伸於共同汲極電極與共同源極電極(未圖示)之間。導電閘極結構102“圍繞”在二個鰭104和106之三側之周圍,並且由標準閘極氧化物層103而與鰭分離。雖然第1圖僅顯示了一個閘極結構102圍繞鰭104和106周圍,但是能夠有二個、三個或更多個平行閘極結構圍繞在該等鰭周圍。如該技術領域中已知者,鰭104和106可經過適當摻雜以產生所希望之FET極性,使得在接近鄰接閘極氧化物103之鰭之表面內形成閘極通道。由雙頭箭號108所表示之閘極之寬度決定裝置之有效的通道長度。
雖然使用引發應力材料為用以增加平面型MOSFET之閘極通道內之載體移動率的已知技術,但是因為FinFET特徵的小尺寸而使得使用此種材料於FinFET結構中更加困難。由於此種裝置的尺寸減小但功能增加,故平行之閘極之間距典型會因為於給定之面積中所需之閘極之數目而減小。當閘極之間距減小時,平行之閘極之間的鰭面積亦會減小。閘極之間之小面積會限制能夠形成在閘極周圍之源極/汲極形成用間隔件(source/drain-forming spacer)之寬度。若源極/汲極形成用間隔件之寬度太小,則後續在這些區域中所形成的源極/汲極區可能會侵入(encroach)至閘極下方之通道中,導致裝置故障。此外,此種小源極/汲極區係造成難以在閘極之間均勻地沉積適當的量之引發應力材料以引發通道中的應力。
因此希望提供用來製造具有受應力源極/汲極區之可微縮(scalable)之FinFET結構之方法。此外,希望提供用來製造具有引發之應力源極/汲極形成用間隔件之FinFET裝置之方法。亦希望提供具有引發應力之源極/汲極形成用間隔件之FinFET結構。再者,由本發明之後續詳細說明和所附之申請專利範圍,結合本發明之伴隨的圖式和此先前技術,本發明之其他希望之特徵和特性將變得很清楚。
本文中提供製造具有引發應力及源極/汲極形成用間隔件的鰭式場效電晶體(FinFET)結構之方法,以及具有此種間隔件之FinFET結構。依照本發明之範例實施例中,一種製造FinFET結構之方法包括製造複數個平行鰭覆蓋於半導體基板上。各該複數個平行鰭具有側壁。製造閘極結構覆蓋於各該複數個平行鰭之一部分。該閘極結構具有側壁並且覆蓋於該複數個平行鰭內之通道上。引發應力側壁間隔件形成在該複數個平行鰭之側壁和該閘極結構之側壁之周圍。該引發應力側壁間隔件引發該通道內之應力。使用該引發應力側壁間隔件和該閘極結構作為植入遮罩植入第一導電率決定用離子於該複數個平行鰭中,以在該複數個平行鰭內形成源極和汲極區域。
依照另一個例示實施例,一種製造FinFET結構之方法,包括製造平行鰭覆蓋於半導體基板上。各該平行鰭具有側壁。製造具有側壁之閘極結構覆蓋於各該平行鰭之第一部分上,而使各該平行鰭之第二部分暴露。第一引發應力側壁間隔件係形成在第一複數個該平行鰭之側壁和該閘極結構之第一部分之側壁之周圍。第二引發應力側壁間隔件形成在第二複數個該平行鰭之側壁和該閘極結構之第二部分之側壁之周圍。該第一引發應力側壁間隔件和該第二引發應力側壁間隔件引發相反的應力。使用該第一引發應力側壁間隔件和該閘極結構之該第一部分作為植入遮罩,將第一導電率決定用離子植入於該第一複數個該平行鰭之該第二部分以形成第一源極和汲極區域。使用該第二引發應力側壁間隔件和該閘極結構之該第二部分作為植入遮罩,將第二導電率決定用離子植入於該第二複數個該平行鰭之該第二部分以形成第二源極和汲極區域。該第一導電率決定用離子係與該第二導電率決定用離子為相反導電率。
於本發明之另一個例示實施例中,一種FinFET結構包括複數個平行鰭覆蓋於半導體基板上。各該複數個平行鰭具有側壁。具有側壁之閘極結構覆蓋於各該複數個平行鰭之第一部分上。源極和汲極區域係配置在各該複數個平行鰭之第二部分內。引發應力側壁間隔件為在各該複數個該平行鰭之該第二部分側壁之周圍和該閘極結構之側壁之周圍。該引發應力側壁間隔件具有寬度而使得該源極和汲極區域不會侵入於該閘極下方各該複數個平行鰭之通道。
本發明之下列實施方式在本質上僅僅為範例,而不欲限制本發明或者本發明之應用和使用。再者,並不欲由任何表現於前述先前技術或下列本發明實施方式中之理論來限定本發明。
第2至26圖係依照本發明之例示實施例顯示平行閘極之間製造具有引發應力之源極/汲極形成用間隔件的FinFET結構之方法。引發應力之源極/汲極形成用間隔件執行至少二個主要的功能。源極/汲極形成用間隔件不但用以間隔源極/汲極區域使得他們不會侵入於閘極下方鰭之通道,而且亦用來引發應力於通道中。因此,能夠達成具有提升裝置性能之可微縮之FinFET裝置。
參照第2圖,依照本發明之例示實施例,製造FinFET結構150之方法包含設置半導體基板200之步驟。如本文中所使用者,用語“半導體基板”將用來包含習知使用於半導體工業中用以製造電子裝置之半導體材料。“半導體材料”包含單晶矽材料,譬如典型使用於半導體工業之相當純的或者稍為摻雜了雜質之單晶矽材料,以及多晶矽材料,和與其他元素譬如鍺、碳等混合之矽。此外,“半導體材料”包含譬如相當純的和摻雜了雜質的鍺、砷化鎵、氧化鋅、玻璃等等之其他的材料。半導體材料較理想為矽基板。矽基板可以是塊體矽晶圓,或者如圖所示,可以包括配置在氧化矽材料204上之含矽材料202,一般已知為絕緣層上覆矽(silicon-on-insulator,SOI)結構,接著,該SOI結構由支撐基板206所支撐。半導體基板200可以進一步包括覆蓋於含矽材料202上之任何其他的材料層,譬如絕緣層、遮罩層等等。芯部形成用材料層(mandrel-forming material layer)210係沉積在半導體基板200上。用於芯部形成用材料層210之適當材料之例子包含但不限於多晶矽、氧化矽、氮化矽等等。
參照第3圖,於沉積芯部形成用材料層210後,譬如一個或多個圖案化光阻之一個或多個圖案化遮罩(未圖示)形成在芯部形成用材料層210上,然後蝕刻該芯部形成用材料層210以形成複數個各具有側壁218之犧牲芯部(sacrificial mandrel)212。此蝕刻可以藉由例如使用根據三氟甲烷/氧(CHF3/O2)以蝕刻氮化矽、CHF3或四氟化碳(CF4)以蝕刻氧氮化矽或氧化矽、或者Cl-或HBr/O2以蝕刻多晶矽之化學反應之電漿或反應性離子蝕刻(RIE)來實施。其次,包含譬如像是氮化矽或氧化矽之介電材料之側壁間隔件214係以共形方式(conformally)覆蓋沉積於該半導體基板200和犧牲芯部212之表面上。可以上述參照芯部形成用材料層210所說明之方式沉積側壁間隔件214。較佳的情況是,選擇側壁間隔件214之組成而使得可以藉由後續的蝕刻製程選擇性地去除犧牲芯部212,而不會讓由側壁間隔件214所形成之側壁間隔件(下文中將討論)受到進一步之腐蝕。舉例而言,若芯部形成用材料層210由氮化矽形成,則側壁間隔件214可以由氧化矽形成,因為犧牲芯部212可以使用加熱的磷酸/水(H3PO4/H2O)溶液而選擇性去除。對於大約25 nm之閘極長度而言,則壁間隔件214具有從大約15 nm至大約40 nm之厚度。實際的厚度將至少部分是根據最終鰭結構之所希望之關鍵尺寸(CD)而定,下文中將討論。
該方法繼續側壁間隔件214之非等向性蝕刻以形成鄰接犧牲芯部212之側壁218之側壁間隔件216,如第4圖中所例示。可以使用上述說明之適當的蝕刻製程實施此蝕刻。然後去除該犧牲芯部212,留下側壁間隔件216實質上完整無缺,如第5圖中所例示。於去除犧牲芯部212後,使用側壁間隔件作為蝕刻遮罩蝕刻含矽材料202(以及硬遮罩,如果其覆蓋了含矽材料202)以形成含矽鰭220,留下由埋置之氧化物層204和矽基板206所形成之半導體基板200,如第6圖中所示。於蝕刻含矽材料202後(和/或於蝕刻任何覆蓋之硬遮罩後),可以使用對間隔件216具選擇性以避免腐蝕鰭220之任何適當的濕或乾蝕刻製程去除側壁間隔件216。雖然第6圖中未圖示,但是因為芯部為方形或矩形之形狀,所以側壁間隔件和鰭以具開口之方形或矩形形成。如此一來,於去除間隔件後,能夠實施鰭220之進一步蝕刻以去除末端部分,也就是,連接二個鄰接之平行鰭220在一起之第6圖之平面以外之鰭部分。蝕刻亦能夠去除任何不需要或者不希望之鰭。雖然第6圖中例示形成8個鰭,但是應該了解到可以製造適合用於特定裝置設備之任何數目之鰭。
參照第7圖,於一個例示實施例中,該方法接著繼續在鰭220之周圍形成閘極絕緣體221。閘極絕緣體221可以是藉由在氧化環境中加熱矽鰭220而形成之熱生長二氧化矽,如所例示,閘極絕緣體221亦可以是沉積之絕緣體,譬如氧化矽、氮化矽、譬如HfSiO等之高介電常數絕緣體。能夠藉由化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、和電漿輔助化學氣相沉積(PECVD)而沉積沉積之絕緣體。於另一個例示實施例中,閘極形成用材料層222接著沉積以覆蓋該閘極絕緣體221和鰭220。閘極形成用材料層包括譬如像是多晶矽、一個或多個金屬、他們的組合等等之導電材料,並且具有適合於所希望之裝置應用之厚度。譬如光阻之遮罩224係沉積覆蓋閘極形成用材料層222並且經由光微影製程而被圖案化,如第8圖中所例示。第8圖為7圖之FinFET結構150沿著8-8軸之剖面圖。
其次,蝕刻閘極形成用材料層222以形成閘極結構226覆蓋鰭220並且去除圖案化之遮罩224,如第9圖中所例示。亦可以使用閘極結構226作為蝕刻遮罩蝕刻閘極絕緣體221。第10圖為第9圖之FinFET結構150之上視圖。如第10圖中所例示,FinFET結構150現在包括四個閘極結構226,其中的二個為一體(integral)並且沿著縱軸形成,由雙頭箭號223所表示,而其中的二個為一體並且沿著平行之縱軸225而形成。雖然第10圖中例示了四個閘極結構,但是將了解到如所安裝之裝置結構需要時,FinFET結構150能夠具有一體和/或平行配置的任何數目之閘極結構。此外,FinFET結構150包括以230表示之複數個平行鰭和以232表示之複數個平行鰭220,該等鰭之每一個具有由雙頭箭號227所表示之縱軸,該縱軸實質上垂直於縱軸223、225。
於形成閘極結構226後,譬如硬遮罩或光阻之遮罩228形成為覆蓋以230表示之複數個鰭220,以232表示之複數個鰭220係保持暴露,如第11和12圖中所例示。第12圖為第11圖之FinFET結構150沿著12-12軸之剖面圖。遮罩228和閘極結構226係用作為離子植入遮罩,以藉由植入決定導電率離子234而形成源極/汲極延伸區236於暴露之以232表示之複數個鰭220中,如第12和13圖中所例示。第13圖為第12圖之FinFET結構150沿著13-13軸之剖面圖。對於n通道FinFET裝置而言,雖然亦能夠使用磷離子,但源極/汲極延伸區236較佳係藉由植入砷離子形成。對於p通道FinFET裝置而言,源極/汲極延伸區236較佳係藉由植入硼離子形成。為了簡潔之目的,暴露之以232表示之複數個鰭220將被視為已經對於n通道FinFET裝置被植入。然後去除遮罩228。
參照第14圖,其係沿著如第12圖之相同的軸,另一個遮罩242(譬如硬遮罩或光阻)係形成覆蓋該以232表示之複數個鰭220,留下以230表示之複數個鰭220被暴露。於形成遮罩242後,遮罩和閘極結構226係用為離子植入遮罩以藉由植入決定導電率離子240形成源極/汲極延伸區238於暴露之以230表示之複數個鰭220中,如第14、15圖中所例示。第15圖為第14圖之FinFET結構150沿著15-15軸之剖面圖。對於p通道FinFET裝置而言,源極/汲極延伸區238較佳係藉由植入硼離子形成。於植入後,去除遮罩242。
接著,覆蓋拉張應力引發層(blanket tensile stress-inducing layer)244係以均勻和共形之方式沉積成覆蓋鰭220、閘極結構226、和半導體基板200,並且後續從以230表示之複數個鰭220去除,如第16圖和17圖中所例示。第16圖為FinFET結構150沿著第14圖之相同軸之剖面圖,而第17圖為第16圖之FinFET結構150沿著17-17軸之剖面圖。該拉張應力引發層244可以是達成下述者之任何材料:能夠形成在鰭上並且產生應力於介面且該應力重新分佈於該鰭中者。拉張應力引發層244引發拉張應力於下方n通道鰭中,該拉張應力提升在n通道內載子(其為電子)之移動率。覆蓋壓縮應力引發層(blanket compressive stress-inducing layer)246係以均勻和共形之方式沉積覆蓋複數個230之鰭220、閘極結構226、拉張應力引發材料244、和埋置之氧化物層204,並且後續至少實質上從拉張應力引發材料244被去除,如第16圖和18圖中所例示。第18圖為第16圖之FinFET結構150沿著18-18軸之剖面圖。壓縮應力引發層246引發壓縮應力於下方p通道鰭中,該壓縮應力提升在p通道內載子(其為電洞)之移動率。於一個例示實施例中,拉張應力引發層244為拉張應力引發用之氮化矽而壓縮應力引發層246為壓縮應力引發用之氮化矽,但亦可以使用譬如鍺化矽和碳化矽之其他材料。沉積拉張應力引發材料和壓縮應力引發材料之方法係該技術領域中廣為人知者,故於本文中不須作進一步之詳細說明。如下面所更詳細討論者,應力引發材料244和246被沉積至分別由箭號245(第17圖)和247(第18圖)所表示之厚度,而使得由該材料形成之間隔件具有下述寬度:其係防止後續形成於鰭中之源極/汲極區域分別侵入於延伸區236和238之間的通道264、266中。
於沉積之後,應力引發材料244和246經過非等向性蝕刻以形成拉張應力引發間隔件248覆蓋該n通道摻雜雜質延伸區236和壓縮應力引發間隔件250覆蓋該p通道摻雜雜質延伸區238,如第19至21圖中所示。第19圖為FinFET結構150沿著如第16圖之相同軸之剖面圖。第20圖為第19圖之FinFET結構150沿著20-20軸之剖面圖,而第21圖為第19圖之FinFET結構150沿著21-21軸之剖面圖。於較佳實施例中,應力引發間隔件248和250實質上同時形成,但間隔件248亦能夠在間隔件250之前或之後形成。
在形成應力引發間隔件248和250之後,該方法接著繼續形成譬如硬遮罩或光阻之遮罩252,其係覆蓋以230表示之該複數個鰭220,如第22圖中所例示,該第22圖為沿著如第19圖之相同軸FinFET結構150之剖面圖。以232表示之複數個鰭220保持暴露。遮罩252、應力引發間隔件248、和閘極結構226被使用為離子植入遮罩,藉由植入決定導電率離子254而形成深源極/汲極區域256於鰭220之暴露部分中,如第22和23圖中所例示。第23圖為第22圖之FinFET結構150沿著23-23軸之剖面圖。對於n通道FinFET裝置而言,源極/汲極區域256較佳係由植入砷離子形成,但亦可以使用磷離子。如第23圖中所例示,能夠將應力引發間隔件248製成具有由箭號249所示之寬度,該寬度足以防止源極/汲極區域256擴散和侵入設置於源極和汲極延伸區236之間的閘極結構226下方之通道264中。因此,避免裝置故障。於形成源極/汲極區域256後,去除遮罩252。
參照第24圖,其為沿著如第22圖相同軸之FinFET結構150之剖面圖,譬如硬遮罩或光阻之另一個遮罩258係形成為覆蓋於以232表示之該複數個鰭220上,留下以230表示之複數個鰭220被暴露。然後使用遮罩258、閘極結構226、和應力引發間隔件250作為離子植入遮罩,並藉由植入決定導電率離子260以形成深源極/汲極區域262於暴露之以230表示之複數個鰭220,如第24和25圖中所例示。第25圖為第24圖之FinFET結構150沿著25-25軸之剖面圖。對於p通道FinFET裝置而言,源極和汲極區域262係較佳藉由植入硼離子形成。如第25圖中所例示,當具有應力引發間隔件248時,能夠將應力引發間隔件250製成具有由箭號251所示之寬度,該寬度足以防止源極/汲極區域262擴散和侵入設置於源極和汲極延伸區238之間的閘極結構226下方之通道266中。於植入完成後,接著去除遮罩258,並且能令FinFET結構150經受退火,譬如快速熱退火(RTA),以活化於源極/汲極延伸區和區域中之雜質。其後,能夠實施任何數目之已知製程步驟,以完成FinFET結構150之製造。舉例而言,如第26圖中所例示,譬如金屬矽化物接觸件之導電接觸件268能夠形成在鰭220和閘極結構226上,如該技術領域中廣為熟知者。雖然上述圖式說明在形成p通道鰭(也就是說,以230表示之複數個鰭220)之前先形成n通道鰭(也就是說,以232表示之複數個鰭220),但是將了解到,本文中亦可以考慮在形成n通道鰭之前先形成p通道鰭。再者,雖然圖式中例示了製造具有n通道鰭和p通道鰭之FinFET結構,但是將了解到亦能夠使用上述方法製造僅具有n通道鰭或僅具有p通道鰭之FinFET結構。
因此,如第22至26圖中所例示,能夠從覆蓋n通道鰭(以232表示之複數個鰭220)之源極/汲極延伸區236之拉張應力引發材料製造應力引發間隔件248,以及從覆蓋p通道鰭(以230表示之複數個鰭220)之源極/汲極延伸區238之壓縮應力引發材料製造應力引發間隔件250。該應力引發間隔件248和250不僅用來間隔源極/汲極延伸區,使得他們不會侵入於鰭之通道中,而且亦用來分別引發應力於通道264、266中。因此,即使閘極之間的區域可能相當小,但是因為應力引發間隔件用於二種目的,因此能有效使用該區域而使得能夠製造出效能最佳而又可微縮之FinFET裝置。此外,因為於形成鰭和閘極二者之後形成間隔件,因此應力引發間隔件的形成會良好整合至FinFET製程中。
雖然已經於本發明之前面實施方式中提出至少一個例示實施例,但是應該了解到存在著大量的變化。亦應該了解到,本文中說明之例示實施例僅為範例,而並不欲以任何方式限制本發明之範圍、可應用性、或組構。相反地,前面的實施方式將提供熟悉此項技術者用來執行所述實施例方便的道引。應該了解到,於例示實施例中所說明之元件之功能和組構可以作各種的改變而不會偏離由所附申請專利範圍所提出之本發明之範圍和他們的法律上的等效物。
100...鰭式場效電晶體(FinFET)
102...導電閘極結構
103...閘極氧化物層
104、106...鰭結構(鰭)
150...FinFET結構
200...半導體基板
202...含矽材料
204...氧化矽材料(氧化物層)
206...矽基板
210...芯部形成用材料層
212...犧牲芯部
214、216...側壁間隔件
218...側壁
220...含矽鰭
221...閘極絕緣體
222...閘極形成用材料層
223、225...縱軸(雙頭箭號)
224、228、242...遮罩
226...閘極結構
227...雙頭箭號
230、232...複數個鰭
234、254、260...決定導電率離子
236、238...源極/汲極延伸區
244...覆蓋拉張應力引發層(材料)
245、247...箭號
246...覆蓋壓縮應力引發層(材料)
248...拉張應力引發間隔件
249‧‧‧箭號
250‧‧‧壓縮應力引發間隔件
251‧‧‧箭號
252、258‧‧‧遮罩
256‧‧‧源極/汲極區域
262‧‧‧深源極/汲極區域
264、266‧‧‧通道
268‧‧‧導電接觸件
上文中結合下列圖式而說明本發明,各圖中相同之元件符號係表示相同的元件,以及其中:
第1圖為可從先前技術得到之FinFET結構之等角圖;
第2至26圖顯示FinFET結構和依照本發明之各種例示實施例之用來製造具有引發應力之源極/汲極形成用間隔件的FinFET結構之方法;
第2至7圖為第2至26圖之FinFET結構沿著相同軸之剖面圖;
第8至9圖為第7圖之FinFET結構沿著8-8軸之剖面圖;
第10圖為第9圖之FinFET結構之上視圖;
第11圖為第10圖之FinFET結構於各種方法步驟後之上視圖;
第12圖為第11圖之FinFET結構沿著12-12軸之剖面圖;
第13圖為第11圖之FinFET結構沿著13-13軸之剖面圖;
第14圖為第12圖之FinFET結構於各種方法步驟後沿著相同軸之剖面圖;
第15圖為第14圖之FinFET結構沿著15-15軸之剖面圖;
第16圖為第14圖之FinFET結構於各種方法步驟後沿著相同軸之剖面圖;
第17圖為第16圖之FinFET結構沿著17-17軸之剖面圖;
第18圖為第16圖之FinFET結構沿著18-18軸之剖面圖;
第19圖為第16圖之FinFET結構於各種方法步驟後沿著相同軸之剖面圖;
第20圖為第19圖之FinFET結構沿著20-20軸之剖面圖;
第21圖為第19圖之FinFET結構沿著21-21軸之剖面圖;
第22圖為第19圖之FinFET結構於各種方法步驟後沿著相同軸之剖面圖;
第23圖為第22圖之FinFET結構沿著23-23軸之剖面圖;
第24圖為第22圖之FinFET結構於各種方法步驟後沿著相同軸之剖面圖;
第25圖為第24圖之FinFET結構沿著25-25軸之剖面圖;
第26圖為第25圖之FinFET結構於各種方法步驟後之等角圖;
150...FinFET結構
200...半導體基板
204...氧化矽材料(氧化物層)
206...矽基板
220...含矽鰭
226...閘極結構
230、232...複數個鰭
248...拉張應力引發間隔件
250...壓縮應力引發間隔件
268...導電接觸件
Claims (9)
- 一種製造FinFET結構(150)之方法,該方法包括下列步驟:製造複數個(230)平行鰭(220)覆蓋於半導體基板(200)上,該複數個平行鰭各者具有側壁;製造閘極結構(226)覆蓋於該複數個(230)平行鰭(220)各者之一部分上,其中該閘極結構具有側壁並且覆蓋於該複數個平行鰭內之通道(266)上;形成毗鄰該複數個(230)平行鰭(220)之側壁和該閘極結構(226)之該側壁的應力引發側壁間隔件(250),其中該應力引發側壁間隔件引發該通道內之應力;以及使用該應力引發側壁間隔件和該閘極結構作為植入遮罩植入第一導電率決定用離子(260)於該複數個平行鰭中,以在該複數個平行鰭內形成源極和汲極區域(262)。
- 如申請專利範圍第1項所述之方法,其中,各該複數個(230)平行鰭(220)具有第一縱軸(227),以及其中,該製造閘極結構(226)之步驟包括形成具有實質上垂直於該第一縱軸的第二縱軸(223,225)的閘極結構。
- 如申請專利範圍第1項所述之方法,進一步包括植入第二導電率決定用離子(240)於該複數個平行鰭中之步驟,該植入第二導電率決定用離子之步驟係於該形成應力引發側壁間隔件之步驟之前和該製造該閘極結構之 步驟之後實施。
- 如申請專利範圍第1項所述之方法,進一步包括形成毗鄰該複數個平行鰭各者之該等側壁的閘極絕緣體(221)之步驟,形成該閘極絕緣體之該步驟係在該製造閘極結構之步驟之前實施。
- 如申請專利範圍第1項所述之方法,其中,該形成應力引發側壁間隔件(250)之步驟包括形成具有足夠大小之寬度(247)的該應力引發側壁間隔件,而使得於該植入步驟後,該源極和汲極區域(262)不會侵入於該複數個平行鰭內之該通道(266)上。
- 如申請專利範圍第1項所述之方法,其中,該形成應力引發側壁間隔件(250)之步驟包括形成拉張應力引發側壁間隔件。
- 如申請專利範圍第1項所述之方法,其中,該形成應力引發側壁間隔件(250)之步驟包括形成壓縮應力引發側壁間隔件。
- 如申請專利範圍第1項所述之方法,其中,該半導體基板(200)包括半導體材料(202),以及其中該製造複數個平行鰭(220)之步驟包括下列步驟:形成犧牲芯部(212)覆蓋該半導體材料上;形成側壁間隔件形成用材料(214)覆蓋於該犧牲芯部上;非等向性蝕刻該側壁間隔件形成用材料(214)以形成側壁間隔件(216); 去除該犧牲芯部(212),留下該側壁間隔件(216)實質上完整無缺;以及使用該側壁間隔件作為蝕刻遮罩蝕刻該半導體材料(202)。
- 如申請專利範圍第1項所述之方法,其中,該製造閘極結構(226)之步驟包括下列步驟:形成導電材料之覆蓋層(222)覆蓋該複數個平行鰭(220);形成圖案化之遮罩(224)覆蓋該導電材料之該覆蓋層;以及蝕刻該導電材料之覆蓋層。
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