TWI556409B - Five transistor static random access memory - Google Patents

Five transistor static random access memory Download PDF

Info

Publication number
TWI556409B
TWI556409B TW104133101A TW104133101A TWI556409B TW I556409 B TWI556409 B TW I556409B TW 104133101 A TW104133101 A TW 104133101A TW 104133101 A TW104133101 A TW 104133101A TW I556409 B TWI556409 B TW I556409B
Authority
TW
Taiwan
Prior art keywords
nmos transistor
voltage
read
control signal
word line
Prior art date
Application number
TW104133101A
Other languages
Chinese (zh)
Other versions
TW201714281A (en
Inventor
蕭明椿
鄭瑜
Original Assignee
修平學校財團法人修平科技大學
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 修平學校財團法人修平科技大學 filed Critical 修平學校財團法人修平科技大學
Priority to TW104133101A priority Critical patent/TWI556409B/en
Application granted granted Critical
Publication of TWI556409B publication Critical patent/TWI556409B/en
Publication of TW201714281A publication Critical patent/TW201714281A/en

Links

Landscapes

  • Static Random-Access Memory (AREA)

Description

5T靜態隨機存取記憶體 5T static random access memory

本發明係有關於一種單埠(single port)靜態隨機存取記憶體(Static Random Access Memory，簡稱SRAM)，尤指一種有效提高單埠SRAM之待機效能，並能有效提高讀取速度與有效降低漏電流(leakage current)且能解決習知具單一位元線之單埠SRAM寫入邏輯1困難之單埠SRAM。 The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示，其主要包括一記憶體陣列(memory array)，該記憶體陣列係由複數個記憶體區塊(memory block，MB1、MB2等)所組成，每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞；複數條字元線(word line，WL1、WL2等)，每一字元線對應至複數列記憶體晶胞中之一列；以及複數位元線對(bit line pairs，BL1、BLB1...BLm、BLBm等)，每一位元線對係對應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB 1). , MB 2 , etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL 1 , WL 2 , etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL 1 , BLB 1 ... BL m , BLB m , etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL 1 ... BL m ) and one complementary bit line (BLB 1 ... BLB m ).

第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞 之電路示意圖，其中，PMOS電晶體(P11)和(P12)稱為負載電晶體(load transistor)，NMOS電晶體(N11)和(N12)稱為驅動電晶體(driving transistor)，NMOS電晶體(N13)和(N14)稱為存取電晶體(access transistor)，WL為字元線(word line)，而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line)，由於該單埠SRAM晶胞需要6個電晶體，且於讀取邏輯0時，為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通，節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(1)：VAR=VDD×(RN11)/(RN11+RN13)<VTN12 (1)以防止讀取時之半選定晶胞干擾(half-selected cell disturbance)，其中，VAR表示節點A之讀取初始瞬間電壓，RN11與RN13分別表示該NMOS電晶體(N11)與該NMOS電晶體(N13)之導通電阻，而VDD與VTN12分別表示電源供應電壓與該NMOS電晶體(N12)之臨界電壓，此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率，cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US76060B2號專利說明書第2欄第8-10行)。 Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P11) and (P12) are called load transistors, NMOS transistors. (N11) and (N12) are called driving transistors, NMOS transistors (N13) and (N14) are called access transistors, WL is word line, and BL And BLB are a bit line and a complementary bit line, respectively, since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V AR ) of the node A must satisfy the equation (1): V AR = V DD × (R N11 ) / (R N11 + R N13 ) < V TN12 (1) to prevent half-selected cell disturbance when reading, wherein V AR represents the initial instantaneous voltage of the reading of node A, and R N11 and R N13 respectively represent the NMOS transistor (N11) ) oN resistance of the NMOS transistor (N13), and V DD and V TN12 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (N12) of this The current drive capability ratio (ie, cell ratio) between the drive transistor and the access transistor is typically set between 2.2 and 3.5 (refer to US Pat. No. 2,760,060, filed on October 20, 1998. Lines 8-10).

第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬。 The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖，與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體 晶胞少一個電晶體及少一條位元線，惟該5T單埠靜態隨機存取記憶體晶胞在不變更PMOS電晶體(P11)和(P12)以及NMOS電晶體(N11)、(N12)和(N13)的通道寬長比(亦即保持與6T SRAM晶胞相同之電晶體通道寬長比)的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(VAW)等於方程式(2)：VAW=VDD×(RN11)/(RN11+RN13) (2)其中，VAW表示節點A之寫入初始瞬間電壓，RN11與RN13分別表示NMOS電晶體(N11)與NMOS電晶體(N13)之導通電阻，比較方程式(1)與方程式(2)可知，寫入初始瞬間電壓(VAW)小於NMOS電晶體(N12)之臨界電壓(VTN12)，因而無法完成寫入邏輯1之操作。第3圖所示5T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第4圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistor (P11). Write logic 1 with (P12) and channel width-to-length ratio of NMOS transistors (N11), (N12), and (N13) (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell) Quite difficult problem. Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. initial transient voltage (V AW) is equal to equation (2): V AW = V DD × (R N11) / (R N11 + R N13) (2) where, V AW indicates the node A writes the initial transient voltage, R N11 And R N13 respectively indicate the on-resistances of the NMOS transistor (N11) and the NMOS transistor (N13). Comparing equations (1) and (2), the initial transient voltage (V AW ) is smaller than the NMOS transistor (N12). The threshold voltage (V TN12 ) makes it impossible to complete the operation of writing logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that it is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line.

解決上述5T靜態隨機存取記憶體晶胞寫入邏輯1困難之方法有如下幾種，第一種方法為寫入時將供應至記憶體晶胞之電壓位準拉低至低於電源供應電壓(VDD)，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體(N11)之導通電阻以於寫入操作期間能使驅動電晶體NMOS電晶體(N12)導通，而完成寫入邏輯1之操作，例如專利文獻1(99年4月27日第US7706203 B2號)所 提出之「Memory System」、專利文獻2(103年2月11日第TWI426515 B號)所提出之「寫入操作時降低電源電壓之單埠SRAM」、專利文獻3(103年2月11日第TWI426514 B號)所提出之「寫入操作時降低電源電壓之單埠靜態隨機存取記憶體」、專利文獻4(102年12月11日第TWI419162 B號)所提出之「具放電路徑之單埠靜態隨機存取記憶體」及專利文獻5(103年1月30日第US2014/0029333 A1號)所提出之「Five Transistor SRAM Cell」等等均屬之，該等專利雖可有效解決寫入邏輯1困難之問題，惟由於該等專利需設置雙電源及/或放電路徑，且該等專利寫入時須將供應至記憶體晶胞之電壓位準拉低至低於電源供應電壓(VDD)並於寫入完成後將供應至記憶體晶胞之電壓位準回復為電源供應電壓(VDD)，因此均會造成無謂的功率耗損，再者該等專利均未考慮到降低待機功率及45奈米操作電壓將降為1.1±30%時所造成讀取速度降低等問題，因此仍有改進空間。 The method for solving the above-mentioned 5T static random access memory cell writing logic 1 is as follows. The first method is to pull the voltage level supplied to the memory cell lower than the power supply voltage when writing. (VDD), so that when writing logic 1 (assuming node A originally stores logic 0, and now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor (N11) during the write operation The driving transistor NMOS transistor (N12) can be turned on to complete the operation of writing the logic 1, for example, Patent Document 1 (US Pat. No. 7,706,202 B2, April 27, 1999) "Memory System" proposed in the "Memory System", Patent Document 2 (TWI426515 B, February 11, 103), "SRAM with reduced power supply voltage during write operation", Patent Document 3 (February 11, 103, pp. TWI426514 B) "Standard Static Random Access Memory with Reduced Power Supply Voltage During Write Operation", Patent Document 4 (TWI419162 B, December 11, 102) "Five Transistor SRAM Cell", etc., as disclosed in Patent Document 5 (US2014/0029333 A1, January 30, 103), which can effectively solve the writing. Logic 1 is difficult, but because these patents require dual power and/or discharge paths, the voltages supplied to the memory cell must be pulled low below the power supply voltage (VDD). And returning the voltage level supplied to the memory cell to the power supply voltage (VDD) after writing is completed, thus causing unnecessary power consumption, and none of these patents considers reducing standby power and 45 The reading speed caused by the nano operating voltage will drop to 1.1±30% Reduce the problem, so there is still room for improvement.

第二種方法為重新設計PMOS電晶體(P11)和(P12)以及NMOS電晶體(N11)、(N12)和(N13)的通道寬長比，例如非專利文獻6(Satyanand Nalam et al.,”5T SRAM with asymmetric sizing for improved read stability”,IEEE Journal of Solid-State Circuits.,Vol.46.No.10,pp 2431-2442,Oct.2011.)，惟由於PMOS電晶體(P11)和(P12)的通道寬長比不再相同且NMOS電晶體(N11)和(N12)的通道寬長比不再相同，因此會使靜態雜訊邊際(SNM)降低，且亦未考慮到降低待機功率及45奈米操作電壓將降為1.1±30%時所造成讀取速度降低等問題，因此仍有改進空間。 The second method is to redesign the channel width to length ratio of the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 6 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability", IEEE Journal of Solid-State Circuits ., Vol. 46. No. 10, pp 2431-2442, Oct. 2011.), due to PMOS transistors (P11) and ( The channel width to length ratio of P12) is no longer the same and the channel width to length ratio of NMOS transistors (N11) and (N12) are no longer the same, thus reducing the static noise margin (SNM) and not reducing the standby power. And when the operating voltage of 45 nm is reduced to 1.1±30%, the reading speed is reduced, so there is still room for improvement.

第三種方法為寫入時將供應至記憶體晶胞之存取電晶體(N13)閘極之字元線(WL)電壓位準拉高至高於電源供應電壓(VDD)，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)， 藉由降低存取電晶體(N13)之導通電阻以於寫入初始瞬間(write initial instant)能使驅動電晶體NMOS電晶體(N12)導通，而完成寫入邏輯1之操作，例如專利文獻7(102年8月1日第TWI404065號)所提出之「寫入操作時提高字元線電壓位準之單埠靜態隨機存取記憶體」，惟由於寫入時將供應至記憶體晶胞之存取電晶體(N13)閘極之字元線(WL)電壓位準拉高至高於電源供應電壓(VDD)會增加寫入時之半選定晶胞干擾(half-selected cell disturbance)，且亦未考慮到45奈米操作電壓降為1.1±30%時所造成讀取速度降低之問題，因此仍有改進空間。 The third method is to increase the word line (WL) voltage level of the access transistor (N13) gate supplied to the memory cell to a voltage higher than the power supply voltage (VDD) for writing. Logic 1 (assuming node A originally stores a logic 0, but now wants to write a logic 1), The operation of writing the logic 1 can be completed by lowering the on-resistance of the access transistor (N13) to enable the driving transistor NMOS transistor (N12) to be turned on at the initial write instant, for example, Patent Document 7 (No. TWI404065, August 1, 102) "Serial random access memory that raises the word line voltage level during write operation", but is supplied to the memory cell due to writing. Accessing the transistor (N13) gate word line (WL) voltage level higher than the power supply voltage (VDD) increases the half-selected cell disturbance during writing, and also The problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30% is not taken into account, so there is still room for improvement.

第四種方法為寫入時將驅動電晶體NMOS電晶體(N11)之源極電壓位準拉高至高於接地電壓，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體(N11)之汲極電壓位準，以於寫入初始瞬間能使驅動電晶體NMOS電晶體(N12)導通，而完成寫入邏輯1之操作，例如專利文獻8(103年9月1日第TWI451414號)所提出之「具高效能之靜態隨機存取記憶體」、專利文獻9(103年5月1日第TWI436359號)所提出之「5T單埠SRAM」、專利文獻10(103年4月1日第TWI433151號)所提出之「5T靜態隨機存取記憶體」及專利文獻11(103年2月1日第TWI425510號)所提出之「具低待機電流之單埠靜態隨機存取記憶體」，惟該等專利均未考慮到45奈米操作電壓降為1.1±30%時所造成讀取速度降低之問題，另專利文獻12(104年3月21日第TWI478165號)所提出之「具高效能之單埠靜態隨機存取記憶體」，雖考慮到45奈米以下SRAM操作電壓降為1.1±30%時所造成讀取速度降低之問題，惟由於係藉由讀取操作期間將驅動電晶體NMOS電晶體(N11)之源極電壓由原本之接地電壓下拉至低於接地電壓以提高讀取速度，但缺乏於該讀取操作期間將該驅動電晶體NMOS電晶體(N11)之源極電壓由低於接地電壓回復至接地電壓之機制，因 此存在無謂的功率耗損之缺失，故仍有改進空間。 The fourth method is to raise the source voltage level of the driving transistor NMOS transistor (N11) above the ground voltage during writing so as to write logic 1 (assuming that node A originally stores logic 0, and now wants Write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), so that the driving transistor NMOS transistor (N12) can be turned on at the initial writing speed, and the writing logic 1 is completed. The operation is as follows, for example, "High-performance static random access memory" proposed in Patent Document 8 (TWI451414, September 1, 103), and Patent Document 9 (TWI 436359, May 1, 103) "5T 單埠SRAM", "5T static random access memory" proposed in Patent Document 10 (TWI433151, April 1, 103), and Patent Document 11 (TWI425510, February 1, 103) Proposed "Static Static Random Access Memory with Low Standby Current", but these patents do not take into account the problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30%. 12 (TWI478165, March 21, 104) "High-performance static random access memory Although the read speed is reduced due to the SRAM operating voltage drop of 1.1±30% below 45 nm, the source of the transistor NMOS transistor (N11) will be driven by the read operation. The voltage is pulled down from the original ground voltage to below the ground voltage to increase the reading speed, but the source voltage of the driving transistor NMOS transistor (N11) is reduced from the ground voltage to the ground voltage during the read operation. Mechanism There is a lack of unnecessary power consumption, so there is still room for improvement.

第五種方法為寫入時藉由背閘極偏壓(back gate bias)技術以提高驅動電晶體NMOS電晶體(N11)之臨界電壓並同時降低存取電晶體(N13)之臨界電壓，以便於寫入邏輯1時(假設節點A原本儲存邏輯0，而現在欲寫入邏輯1)，藉由提高驅動電晶體NMOS電晶體(N11)之汲極電壓位準，以於寫入初始瞬間能使驅動電晶體NMOS電晶體(N12)導通，而完成寫入邏輯1之操作，惟該方法須使用分離井(split well)會增加製程複雜度，因此較少使用。 The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor (N11) while reducing the threshold voltage of the access transistor (N13) by writing back gate bias technology. When writing logic 1 (assuming node A originally stores logic 0, but now wants to write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), the initial instant energy can be written. The drive transistor NMOS transistor (N12) is turned on to complete the operation of writing logic 1, but the method requires the use of a split well to increase process complexity and is therefore less used.

第六種方法為重新設計PMOS電晶體(P11)和(P12)以及NMOS電晶體(N11)、(N12)和(N13)之間的連接關係，例如非專利文獻13(Chua-Chin Wang et al.,”A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process”,2014 International Symposium on Circuits and Systems,pp 1126-1129,June 2014.)及非專利文獻14(Shyam Akashe et al.,”High density and low leakage current based 5T SRAM cell using 45nm technology”,2011 International Conference on Nanoscience,Engineering and Technology(ICONSET),pp 346-350,Nov,2011.)，惟由於該等非專利文獻並未考慮到45奈米操作電壓降為1.1±30%時所造成讀取速度降低之問題，因此仍有改進空間。 The sixth method is to redesign the connection relationship between the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 13 (Chua-Chin Wang et al) "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and non-patent document 14 (Shyam Akashe) Et al., "High density and low leakage current based 5T SRAM cell using 45nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov, 2011.), due to these non-patents The literature does not consider the problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30%, so there is still room for improvement.

接著，探討藉由將所有記憶體晶胞中之NMOS電晶體(N11)和(N12)之源極電壓由原本之接地電壓提高至較接地電壓為高之一預定電壓，以謀求降低待機操作之功率消耗的之技術，例如專利文獻15(97年6月3日第US7382674 B2號)所提出之「Static random access memory(SRAM)with clamped source potential in standby mode」、專利文獻16(96年8月7日第US7254085 B2號)所提出之「Static random access memory device and method of reducing standby current」、非專利文獻17(Tae-Hyoung Kim et al.,”A Voltage Scalable 0.26V,64kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode”,IEEE Journal of Solid-State Circuits.,Vol.64,pp 1785-1795,2009.)所提出之8T SRAM以及非專利文獻18(Ding-Ming Kwai,”Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution”,Design,and Testing,2009.MTDT '09.IEEE International Workshop on Memory Technology,pp 77-82,Aug.31 2009-Sept.2009.)等等均屬之，該等專利文獻或非專利文獻於待機操作時，均是藉由將所有記憶體晶胞中之驅動電晶體(亦即第1b圖之NMOS電晶體N11和N12)之源極電壓由原本之接地電壓提高至較該接地電壓為高之一預定電壓，以謀求降低待機操作之功率消耗，惟由於該等專利文獻或非專利文獻之較接地電壓為高的該預定電壓僅係藉由電晶體之漏電流對寄生電容的充電而產生，而造成靜態隨機存取記憶體進入待機模式之速度極為緩慢，並因而導致降低待機效能之缺失：亦即該等專利文獻或非專利文獻均缺乏待機啟動電路以促使靜態隨機存取記憶體快速進入待機模式，因此仍有改進空間。 Next, it is proposed to reduce the standby voltage by increasing the source voltage of the NMOS transistors (N11) and (N12) in all the memory cells from the original ground voltage to a predetermined voltage higher than the ground voltage. A technique of power consumption, for example, "Static random access memory (SRAM) with clamped source potential in standby mode" proposed in Patent Document 15 (No. US Pat. No. 7,382,674 B2, June 3, 1997), Patent Document 16 (August 96) "Static random access memory device and method of reducing standby current", No. 77254085 B2, No. 7 (Tae-Hyoung Kim et al., "A Voltage Scalable 0.26V, 64 kb 8T SRAM With Vmin Lowering" Techniques and Deep Sleep Mode ", IEEE Journal of Solid-State Circuits., Vol.64, pp 1785-1795,2009.) proposed the 8T SRAM, and Non-Patent Document 18 (Ding-Ming Kwai," Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution ", Design, and Testing, 2009.MTDT '09 .IEEE International Workshop on Memory Technology, pp 77-82, Aug.31 2009-Sept.2009.) , etc. are the property of, those special In the standby operation, the literature or non-patent literature improves the source voltage of the driving transistor (ie, the NMOS transistors N11 and N12 of FIG. 1b) from the original ground voltage to all the memory cells. The predetermined voltage is higher than the ground voltage to reduce the power consumption of the standby operation. However, since the ground voltage of the patent documents or the non-patent literature is higher than the ground voltage, the predetermined voltage is only caused by the leakage current of the transistor. The charging of parasitic capacitance occurs, and the rate at which the SRAM enters the standby mode is extremely slow, and thus the lack of standby performance is reduced: that is, the patent documents or the non-patent literature lack a standby start circuit to promote static The random access memory quickly enters standby mode, so there is still room for improvement.

有鑑於此，本發明之主要目的係提出一種5T靜態隨機存取記憶體，其能藉由控制電路以於讀取初始瞬間將靠近位元線之驅動電晶體的源極電壓從原本的接地電壓改為比接地電壓還低，此時可配置較小通道寬長比之驅動電晶體即可完成讀取動作，且於讀取邏輯0時也不會造成遠離位元線之驅動電晶體的瞬間導通而阻礙讀取操作，同時寫入時亦可有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題。 In view of the above, the main object of the present invention is to provide a 5T static random access memory capable of controlling the source voltage of the driving transistor close to the bit line from the original ground voltage by the control circuit. It is changed to be lower than the grounding voltage. At this time, the driving transistor with a smaller channel width-to-length ratio can be configured to complete the reading operation, and when the logic 0 is read, the moment of driving the transistor away from the bit line is not caused. Turning on hinders the read operation, and at the same time, it is also effective to avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line.

本發明之次要目的係提出一種5T靜態隨機存取記憶體，其能藉由字元線電壓位準轉變電路，以於讀取操作期間將施加至選定晶胞之 存取電晶體的字元線電壓下拉至低於電源供應電壓，以有效降低讀取時之半選定晶胞干擾。 A secondary object of the present invention is to provide a 5T static random access memory that can be applied to a selected cell by a word line voltage level transition circuit during a read operation. The word line voltage of the access transistor is pulled down below the power supply voltage to effectively reduce half-selected cell interference during reading.

本發明之再一目的係提出一種5T靜態隨機存取記憶體，其能藉由控制電路以有效提高讀取速度，且能藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損。 A further object of the present invention is to provide a 5T static random access memory capable of effectively improving the reading speed by the control circuit, and capable of improving the reading speed by the two-stage read control. Avoid unnecessary power consumption.

本發明之又一目的係提出一種5T靜態隨機存取記憶體，其能藉由控制電路以有效降低待機模式之漏電流。 Another object of the present invention is to provide a 5T static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

本發明提出一種5T靜態隨機存取記憶體，其主要包括一記憶體陣列、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)以及複數個字元線電壓位準轉變電路(5)，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞設置一個控制電路及一個字元線電壓位準轉變電路(5)，且每一記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體N11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體N12所組成)及一存取電晶體(由一第三NMOS電晶體N13所組成)。每一控制單元(2)係連接至對應列記憶體晶胞中之每一記憶體晶胞的該第一NMOS電晶體(N11)的源極以及該第二NMOS電晶體(N12)的源極，以便因應不同操作模式而控制該第一NMOS電晶體(N11)的源極電壓以及該第二NMOS電晶體(N12)的源極電壓。於讀取模式之第一階段時，將靠近位元線(BL)之該第一NMOS電晶體(N11)的源極從原本的接地電壓改為比接地電壓還低，此時可配置較小通道寬長比之該第一NMOS電晶體(N11)與該 第二NMOS電晶體(N12)即可完成讀取動作，且於讀取邏輯0時也不會造成遠離位元線(BL)之該第二NMOS電晶體(N12)由於瞬間導通而阻礙讀取操作，而於讀取模式之第二階段時則藉由將該第一NMOS電晶體(N11)的源極從比接地電壓還低設定回接地電壓，以便減少無謂的功率消耗；於寫入模式時，將靠近位元線(BL)之該第一NMOS電晶體(N11)的源極維持原本的接地電壓，因配置有較小通道寬長比之該第一NMOS電晶體(N11)與該第二NMOS電晶體(N12)，因此可有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題；於待機模式時，可有效降低漏電流，而於保持模式時則可維持原有的電氣特性。再者，藉由該待機啟動電路(4)的設計，以有效促使具單埠SRAM快速進入待機模式，並因而有效提高單埠SRAM之待機效能。此外，藉由該複數個字元線電壓位準轉變電路(5)的設計，以增加該第三NMOS電晶體(N13)於讀取模式下之導通電阻，並因而有效降低讀取時之半選定晶胞干擾。 The invention provides a 5T static random access memory, which mainly comprises a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4) and a plurality of word lines. a voltage level conversion circuit (5), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit and a word line voltage level transition a circuit (5), and each of the memory cells (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor N11) and a second inverter (consisting of a second PMOS transistor P12 and a second NMOS transistor N12) and an access transistor (composed of a third NMOS transistor N13). Each control unit (2) is connected to a source of the first NMOS transistor (N11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (N12) In order to control the source voltage of the first NMOS transistor (N11) and the source voltage of the second NMOS transistor (N12) in response to different operation modes. In the first stage of the read mode, the source of the first NMOS transistor (N11) close to the bit line (BL) is changed from the original ground voltage to be lower than the ground voltage, and the configuration is smaller. Channel width to length ratio of the first NMOS transistor (N11) and the The second NMOS transistor (N12) can complete the reading operation, and when the logic 0 is read, the second NMOS transistor (N12) far from the bit line (BL) is prevented from being read due to the instantaneous conduction. Operating, and in the second phase of the read mode, the source of the first NMOS transistor (N11) is set back to ground voltage from a lower ground voltage to reduce unnecessary power consumption; When the source of the first NMOS transistor (N11) close to the bit line (BL) maintains the original ground voltage, the first NMOS transistor (N11) is configured with a smaller channel width to length ratio. The second NMOS transistor (N12) can effectively avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line; in the standby mode, the leakage current can be effectively reduced, while in the hold mode It can maintain the original electrical characteristics. Moreover, the design of the standby start circuit (4) is effective to prompt the 單埠SRAM to quickly enter the standby mode, and thus effectively improve the standby performance of the 單埠SRAM. In addition, the design of the plurality of word line voltage level transition circuits (5) increases the on-resistance of the third NMOS transistor (N13) in the read mode, thereby effectively reducing the half of the read period. Selected cell interference.

BLB1 …BLBm‧‧‧互補位元線 BLB 1 ... BLB m ‧‧‧complementary bit line

BLB‧‧‧互補位元線 BLB‧‧‧complementary bit line

MB1 …MBk‧‧‧記憶體區塊 MB 1 ... MB k ‧‧‧ memory block

WL1 …WLn‧‧‧字元線 WL 1 ... WL n ‧‧‧ character line

BL1 …BLm‧‧‧位元線 BL 1 ... BL m ‧‧‧ bit line

I1、I2、I3‧‧‧漏電流 I 1 , I 2 , I 3 ‧‧‧ leakage current

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Precharge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

5‧‧‧字元線電壓位準轉變 電路 5‧‧‧Word line voltage level shift Circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor

N11‧‧‧第一NMOS電晶體 N11‧‧‧First NMOS transistor

N12‧‧‧第二NMOS電晶體 N12‧‧‧Second NMOS transistor

N13‧‧‧第三NMOS電晶體 N13‧‧‧ Third NMOS transistor

A‧‧‧儲存節點 A‧‧‧ storage node

B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node

BL‧‧‧位元線 BL‧‧‧ bit line

WLC‧‧‧字元線控制信號 WLC‧‧‧ word line control signal

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node

N21‧‧‧第四NMOS電晶體 N21‧‧‧4th NMOS transistor

N22‧‧‧第五NMOS電晶體 N22‧‧‧ fifth NMOS transistor

N23‧‧‧第六NMOS電晶體 N23‧‧‧ sixth NMOS transistor

N24‧‧‧第七NMOS電晶體 N24‧‧‧ seventh NMOS transistor

N25‧‧‧第八NMOS電晶體 N25‧‧‧ eighth NMOS transistor

N26‧‧‧第九NMOS電晶體 N26‧‧‧Ninth NMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧ read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

INV‧‧‧第三反相器 INV‧‧‧ third inverter

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

P31‧‧‧第三PMOS電晶體 P31‧‧‧ Third PMOS transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

N41‧‧‧第十NMOS電晶體 N41‧‧‧ tenth NMOS transistor

P41‧‧‧第四PMOS電晶體 P41‧‧‧4th PMOS transistor

D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

WL‧‧‧字元線 WL‧‧‧ character line

R‧‧‧讀取信號 R‧‧‧Read signal

/W‧‧‧反相寫入信號 /W‧‧‧Inverted write signal

/RW‧‧‧反相讀寫控制信號 /RW‧‧‧Inverted read/write control signal

P51‧‧‧第五PMOS電晶體 P51‧‧‧ Fifth PMOS transistor

N51‧‧‧第十一NMOS電晶體 N51‧‧11 eleventh NMOS transistor

N52‧‧‧第十二NMOS電晶體 N52‧‧‧12th NMOS transistor

第1a圖 係顯示習知之靜態隨機存取記憶體；第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖；第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖；第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖；第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖；第5圖 係顯示本發明較佳實施例所提出之電路示意圖；第6圖 係顯示第5圖之本發明較佳實施例於寫入期間之簡化電路圖； 第7圖 係顯示第5圖之本發明較佳實施例之寫入動作時序圖；第8圖 係顯示第5圖之本發明較佳實施例於讀取期間之簡化電路圖；第9圖 係顯示第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a schematic circuit diagram showing a preferred embodiment of the present invention; and FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; Figure 7 is a timing chart showing the writing operation of the preferred embodiment of the present invention in Figure 5; and Figure 8 is a simplified circuit diagram showing the preferred embodiment of the present invention in the fifth drawing during reading; Figure 5 is a simplified circuit diagram of a preferred embodiment of the present invention during standby.

根據上述之主要目的，本發明提出一種5T靜態隨機存取記憶體，其主要包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1)；複數個控制電路(2)，每一列記憶晶胞設置一個控制電路(2)；複數個預充電電路(3)，每一行記憶晶胞設置一個預充電電路(3)；一待機啟動電路(4)；以及複數個字元線電壓位準轉變電路(5)。 According to the above main object, the present invention provides a 5T static random access memory, which mainly comprises a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column. The memory cell and each row of memory cells comprise a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3) Each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4); and a plurality of word line voltage level transition circuits (5).

為了便於說明起見，第5圖所示之靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條字元線(WL)、一條位元線(BL)、一控制電路(2)、一預充電電路(3)、一待機啟動電路(4)以及一字元線電壓位準轉變電路(5)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體N11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體N12所組成)、一第三NMOS電晶體(N13)，其中，該第一反相器及該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入，而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。在此值得注意 的是，該第一NMOS電晶體(N11)與該第二NMOS電晶體(N12)具有相同之通道寬長比，該第一PMOS電晶體(P11)與該第二PMOS電晶體(P12)亦具有相同之通道寬長比，且該第一NMOS電晶體(N11)對該第三NMOS電晶體(N13)之通道寬長比的比值係設計為小於第1b圖之傳統6T SRAM晶胞之2.2，例如將該第一NMOS電晶體(N11)對該第三NMOS電晶體(N13)之通道寬長比的比值設計為1.2至1.8之間，最好為1.2至1.5之間。 For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3), a standby start circuit (4), and a word line voltage level transition circuit (5) are described as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor N11) and a second inverter (by a second PMOS) a first NMOS transistor (N13), wherein the first NMOS transistor and the second NMOS transistor are in an inter-coupled connection, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It is worth noting here The first NMOS transistor (N11) and the second NMOS transistor (N12) have the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) are also Having the same channel aspect ratio, and the ratio of the channel width to length ratio of the first NMOS transistor (N11) to the third NMOS transistor (N13) is designed to be smaller than 2.2 of the conventional 6T SRAM cell of FIG. For example, the ratio of the channel width to length ratio of the first NMOS transistor (N11) to the third NMOS transistor (N13) is designed to be between 1.2 and 1.8, preferably between 1.2 and 1.5.

請再參考第5圖，該控制電路(2)係由一第四NMOS電晶體(N21)、一第五NMOS電晶體(N22)、一第六NMOS電晶體(N23)、一第七NMOS電晶體(N24)、一第八NMOS電晶體(N25)、一第九NMOS電晶體(N26)、一讀取控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(N21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與一第二低電壓節點(VL2)；該第五NMOS電晶體(N22)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該待機模式控制信號(S)與一第一低電壓節點(VL1)；該第六NMOS電晶體(N23)之源極係連接至接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)；該第七NMOS電晶體(N24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(N25)之汲極、該讀取控制信號(RC)與該第一低電壓節點(VL1)；該第八NMOS電晶體(N25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(N24)之源極；該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與 該第八NMOS電晶體(N25)之閘極之間；該第三反相器(INV)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入；該第九NMOS電晶體(N26)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第一低電壓節點(VL1)。在此值得注意的是，該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Referring to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (N21), a fifth NMOS transistor (N22), a sixth NMOS transistor (N23), and a seventh NMOS device. a crystal (N24), an eighth NMOS transistor (N25), a ninth NMOS transistor (N26), a read control signal (RC), a third inverter (INV), and a first delay circuit ( D1), an accelerated read voltage (RGND), a standby mode control signal (S), and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (N21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (N22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (N23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (N24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (N25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (N25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (N24); the first The delay circuit (D1) is connected to the output of the third inverter (INV) Between the gates of the eighth NMOS transistor (N25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the first delay circuit (D1) The input, the gate, the gate and the drain of the ninth NMOS transistor (N26) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the first low voltage node (VL1) . It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.

該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準，於寫入模式時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體N11)的源極電壓(即該第一低電壓節點VL1)設定成接地電壓，且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體N12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓。 The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) (ie, the first low voltage node VL1) is set to a ground voltage, and another cell in the selected cell will be selected The source voltage of the driving transistor (ie, the second NMOS transistor N12) (ie, the second low voltage node VL2) is set to a ground voltage.

於讀取模式之一第一階段時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體N11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度，而於讀取模式之一第二階段時，將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體N11)的源極電壓設定回接地電壓，以便減少無謂的功率消耗，其中該讀取模式之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(N25)之閘極電壓足以關閉該第八NMOS電晶體(N25)為止之時間，其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路 (D1)所提供之延遲時間來調整。 In the first phase of one of the read modes, the source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node) VL1) is set to the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed, and is one of the read modes. In the phase, the source voltage of the driving transistor (ie, the first NMOS transistor N11) of the selected cell closer to the bit line (BL) is set back to the ground voltage to reduce unnecessary power consumption, wherein the reading The second phase of the mode is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the gate of the eighth NMOS transistor (N25) a voltage is sufficient to turn off the eighth NMOS transistor (N25), the value of which may be caused by the falling delay time of the third inverter (INV) and the first delay circuit (D1) The delay time provided is adjusted.

於待機模式時，將所有記憶晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓，以便降低漏電流；而於保持模式時則將記憶晶胞中之驅動電晶體的源極電壓設定成接地電壓，以便維持原來之保持特性，其詳細工作電壓位準如表1所示。 In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

表1中之該讀取控制信號(RC)為一讀取信號(R)與該字元線(WL)信號的及閘運算結果。在此值得注意的是，對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(N24)之漏電流。 The read control signal (RC) in Table 1 is the result of the AND operation of a read signal (R) and the word line (WL) signal. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (N24). Current.

請參考第5圖，該預充電電路(3)係由一第三PMOS電晶體(P31)以及一預充電信號(P)所組成，該第三PMOS電晶體(P31)之源極、閘極與汲極係分別連接至一電源供應電壓(VDD)、該預充電信號(P)與該位元線(BL)，以便於預充電期間，藉由邏輯低位準之該預充電信號(P)，以將該位元線(BL)預充電至該電源供應電壓(VDD)之位準。 Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). And the drain system are respectively connected to a power supply voltage (V DD ), the precharge signal (P) and the bit line (BL), so as to be pre-charged by a logic low level during pre-charging (P) ) to precharge the bit line (BL) to the level of the power supply voltage (V DD ).

請再參考第5圖，該待機啟動電路(4)係由一第四PMOS電晶體(P41)、一第十NMOS電晶體(N41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第四PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十NMOS電晶體(N41)之汲極；該第十NMOS電晶體(N41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第四PMOS電晶體(P41)之汲極；該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該延遲電路(D2)之輸出則連接至該第十NMOS電晶體(N41)之閘極。 Referring to FIG. 5 again, the standby starting circuit (4) is a fourth PMOS transistor (P41), a tenth NMOS transistor (N41), a second delay circuit (D2), and the reverse standby mode. The control signal (/S) is composed of. a source, a gate and a drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V DD ), the reverse standby mode control signal (/S), and the tenth NMOS transistor ( a drain of N41); a source, a gate and a drain of the tenth NMOS transistor (N41) are respectively connected to the output of the first low voltage node (VL1), the second delay circuit (D2), and a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D2) is coupled to the The gate of a ten NMOS transistor (N41).

請再參考第5圖，該字元線電壓位準轉變電路(5)係由一第五PMOS電晶體(P51)、一第十一NMOS電晶體(N51)、一第十二NMOS電晶體(N52)、該讀取信號(R)、一反相寫入信號(/W)、一反相讀寫控制信號(/RW)以及一字元線控制信號(WLC)所組成，其中該讀取信號(R)與該反相寫入信號(/W)可來自SRAM之讀寫控制接腳，當該讀寫控制接腳為邏輯高位準時指示讀取操作(即該讀取信號R為邏輯高位準)，而該讀寫控制接腳為邏輯低位準時指示寫入操作(即該反相寫入信號/W為邏輯低位準)，至於該讀寫控制接腳之反相信號則等同該反相讀寫控制信號(/RW)。該第五PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該字元線(WL)、該反相寫入信號(/W)與該字元線控制信號(WLC)；該第十一NMOS電晶體(N51)之源極、閘極與汲極係分別連接至該字元線控制信號(WLC)、該讀取信號(R)與該字元線(WL)；而該第十二NMOS電晶體(N52)之源極、閘極與汲極係分別連接至該字元線控制信號 (WLC)、該反相讀寫控制信號(/RW)與該字元線(WL)。 Referring to FIG. 5 again, the word line voltage level shifting circuit (5) is composed of a fifth PMOS transistor (P51), an eleventh NMOS transistor (N51), and a twelfth NMOS transistor ( N52), the read signal (R), an inverting write signal (/W), an inverting read/write control signal (/RW), and a word line control signal (WLC), wherein the reading The signal (R) and the inverted write signal (/W) may be from a read/write control pin of the SRAM, and the read operation is indicated when the read/write control pin is at a logic high level (ie, the read signal R is a logic high bit) The read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level), and the inverted signal of the read/write control pin is equivalent to the reverse phase Read and write control signals (/RW). a source, a gate and a drain of the fifth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write signal (/W) and the word line control signal (WLC) The source, gate and drain of the eleventh NMOS transistor (N51) are respectively connected to the word line control signal (WLC), the read signal (R) and the word line (WL); The source, gate and drain of the twelfth NMOS transistor (N52) are respectively connected to the word line control signal (WLC), the inverted read/write control signal (/RW) and the word line (WL).

該字元線電壓位準轉變電路(5)之詳細工作電壓位準如表2所示。 The detailed operating voltage level of the word line voltage level shifting circuit (5) is shown in Table 2.

其中VTN51表示該第十一NMOS電晶體(N51)之臨界電壓。在此值得注意的是，本發明一方面藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，另一方面藉由該字元線電壓位準轉變電路(5)，以於讀取操作期間將施加至選定晶胞之存取電晶體的字元線電壓下拉至低於該電源供應電壓(即VDD-VTN51)，以有效降低讀取時之半選定晶胞干擾。 Where V TN51 represents the threshold voltage of the eleventh NMOS transistor (N51). It should be noted here that the present invention uses two-stage read control to improve the read speed while avoiding unnecessary power consumption, and on the other hand, the word line voltage level transition circuit ( 5), in order to effectively lower the word line voltage applied to the access transistor of the selected cell during the read operation to be lower than the power supply voltage (ie, V DD -V TN51 ) Selected cell interference.

茲依單埠SRAM之工作模式說明第5圖之本發明較佳實施例的工作原理如下： The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I)寫入模式(write mode) (I) write mode

於寫入操作開始前，該待機控制信號(S)為邏輯低位準、該反相待機控制信號(/S)為邏輯高位準，使得該第九NMOS電晶體(N26)導通(ON)，並使得該第一低電壓節點(VL1)呈接地電壓。 Before the start of the write operation, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, such that the ninth NMOS transistor (N26) is turned "ON", and The first low voltage node (VL1) is brought to a ground voltage.

而於寫入操作期間內，該待機控制信號(S)為邏輯低位準、該反相待機控制信號(/S)為邏輯高位準，使得該第九NMOS電晶體(N26)導通(ON)，並使得該第一低電壓節點(VL1)仍呈接地電壓，由於該第一NMOS電晶體(N11)之通道寬長比係設計成比第1b圖之傳統6T SRAM的驅動電晶體(N11)之通道寬長比還來得小，亦即，節點A原本儲存邏輯0而現在欲寫入邏輯1之寫入初始瞬間電壓(VAW)滿足方程式(3)：VAW=VDD×(RN11)/(RN11+RN13)>VTN12 (3)其中，VAW表示節點A之寫入初始瞬間電壓，RN11與RN13分別表示該第一NMOS電晶體(N11)與該第三NMOS電晶體(N13)之導通電阻，而VDD與VTN12分別表示該電源供應電壓與該第二NMOS電晶體(N12)之臨界電壓，因此可有效避免寫入邏輯1困難之問題。第6圖所示為第5圖之本發明較佳實施例於寫入期間之簡化電路圖。 During the write operation period, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, so that the ninth NMOS transistor (N26) is turned on (ON). And the first low voltage node (VL1) is still grounded, because the channel width to length ratio of the first NMOS transistor (N11) is designed to be larger than the driving transistor (N11) of the conventional 6T SRAM of FIG. The channel width-to-length ratio is also small, that is, node A originally stores logic 0 and now writes logic 1 to write the initial instantaneous voltage (V AW ) to satisfy equation (3): V AW = V DD × (R N11 ) /(R N11 +R N13 )>V TN12 (3) wherein V AW represents the initial transient voltage of the node A, and R N11 and R N13 represent the first NMOS transistor (N11) and the third NMOS, respectively. The on-resistance of the crystal (N13), and V DD and V TN12 respectively represent the threshold voltage of the power supply voltage and the second NMOS transistor (N12), so that the problem of difficulty in writing the logic 1 can be effectively avoided. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

接下來依單埠SRAM之4種寫入狀態來說明第6圖之本發明較佳實施例如何完成寫入動作。 Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(一)節點A原本儲存邏輯0，而現在欲寫入邏輯0：在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一NMOS電晶體(N11)為導通(ON)。因為該第一NMOS電晶體(N11)為ON，所以當寫入動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)。當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(N13)(即存取電晶體)的臨界電壓時，該第三NMOS電晶體(N13)由截止(OFF)轉變為導通(ON)，此時因為位元線 (BL)是接地電壓，所以該節點A會保持原本之接地電壓，直到寫入週期結束。 (1) Node A originally stores a logic 0, but now wants to write a logic 0: before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (N11) is turned on (ON) ). Since the first NMOS transistor (N11) is ON, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V DD ) when the write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13) (ie, the access transistor), the third NMOS transistor (N13) is turned from OFF (OFF) to Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(二)節點A原本儲存邏輯0，而現在欲寫入邏輯1：在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一NMOS電晶體(N11)為導通(ON)。因為該第一NMOS電晶體(N11)為ON，所以當寫入動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)，該節點A的電壓會跟隨該字元線控制信號(WLC)的電壓而上升。 (2) Node A originally stores a logic 0, and now wants to write a logic 1: before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (N11) is turned on (ON) ). Since the first NMOS transistor (N11) is ON, when the write operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V DD ), the node A The voltage will rise following the voltage of the word line control signal (WLC).

當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(N13)的臨界電壓時，該第三NMOS電晶體(N13)由截止(OFF)轉變為導通(ON)，此時因為該位元線(BL)是High(該電源供應電壓VDD)，並且因為該第一NMOS電晶體(N11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態，所以該第一PMOS電晶體(P11)仍為截止(OFF)，而該節點A則會滿足方程式(3)，因此能使該第二NMOS電晶體(N12)導通，於是使得節點B放電至一較低電壓位準，該節點B之較低電壓位準會使得該第一NMOS電晶體(N11)之導通等效電阻(RN11)呈現較高的電阻值，該第一NMOS電晶體(N11)之該較高的電阻值會於該節點A獲得較高電壓位準，該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體N12所組成)，而使得該節點B呈現更低電壓位準，該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體N11所組成)，而使得該節點A獲 得更高電壓位準，依此循環，即可將該節點A充電至該電源供應電壓(VDD)，而完成邏輯1的寫入動作。 When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13), the third NMOS transistor (N13) is turned from OFF to ON. Because the bit line (BL) is High (the power supply voltage V DD ), and because the first NMOS transistor (N11) is still ON and the node B is still at a voltage level close to the power supply voltage ( The initial state of the voltage level of V DD ), so the first PMOS transistor (P11) is still turned off (OFF), and the node A satisfies the equation (3), thereby enabling the second NMOS transistor ( N12) is turned on, so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B causes the conduction equivalent resistance (R N11 ) of the first NMOS transistor (N11) to be higher. The resistance value, the higher resistance value of the first NMOS transistor (N11) will obtain a higher voltage level at the node A, and the higher voltage level of the node A will pass through the second inverter ( The second PMOS transistor P12 and the second NMOS transistor N12 are formed, so that the node B exhibits a lower voltage level, and the lower voltage level of the node B passes through The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor N11) causes the node A to obtain a higher voltage level, and according to the cycle, the node A can be charged to the node The power supply voltage (V DD ) completes the write operation of logic 1.

(三)節點A原本儲存邏輯1，而現在欲寫入邏輯1：在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)，且該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(N13)的臨界電壓時，該第三NMOS電晶體(N13)由截止(OFF)轉變為導通(ON)；此時因為該位元線(BL)是High(該電源供應電壓VDD)，並且因為該第一PMOS電晶體(P11)仍為ON，所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準，直到寫入週期結束。 (3) Node A originally stores logic 1, and now wants to write logic 1: Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on (ON) ). When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (N13) At the threshold voltage, the third NMOS transistor (N13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V DD ), and because of the A PMOS transistor (P11) is still ON, so the voltage at node A is maintained at the voltage level of the power supply voltage (V DD ) until the end of the write cycle.

(四)節點A原本儲存邏輯1，而現在欲寫入邏輯0：在寫入動作發生前(該字元線控制信號WLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓VDD)，且該該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(N13)的臨界電壓時，該第三NMOS電晶體(N13)由截止(OFF)轉變為導通(ON)，此時因為該位元線(BL)是Low(接地電壓)，所以會將該節點A以及該第一低電壓節點(VL1)放電而完成邏輯0的寫入動作，直到寫入週期結束。 (4) Node A originally stores logic 1, and now wants to write logic 0: before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on (ON) ). When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the word line control signal (WLC) is greater than the third NMOS transistor (N13) At the threshold voltage, the third NMOS transistor (N13) is turned from OFF to ON. At this time, since the bit line (BL) is Low (ground voltage), the node A and The first low voltage node (VL1) is discharged to complete the write operation of logic 0 until the end of the write cycle.

第6圖所示之本發明較佳實施例簡化電路圖，於寫入操作時 之HSPICE暫態分析模擬結果，如第7圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，本發明所提出之5T靜態隨機存取記憶體，能藉由配置較小通道寬長比的該第一NMOS電晶體(N11)提高寫入期間節點A之電壓位準，以有效避免習知具單一位元線之單埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 A simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 6 during a write operation The HSPICE transient analysis simulation results, as shown in Fig. 7, are simulated using TSMC 90 nm CMOS process parameters. From the simulation results, it can be confirmed that the 5T static random access memory proposed by the present invention can borrow The first NMOS transistor (N11) configured with a smaller channel aspect ratio increases the voltage level of the node A during writing to effectively avoid the conventional static random access memory cell with a single bit line. There is a problem that writing logic 1 is quite difficult.

(II)讀取模式(read mode) (II) Read mode (read mode)

於讀取操作開始前，該讀取控制信號(RC)及該待機模式控制信號(S)均為邏輯低位準，使得該第九NMOS電晶體(N26)導通(ON)，並使得該第一低電壓節點(VL1)呈接地電壓。另一方面，由於該讀取控制信號(RC)為邏輯低位準，使得該第七NMOS電晶體(N24)截止(OFF)，並使得該第八NMOS電晶體(N25)導通(ON)。 Before the reading operation starts, the read control signal (RC) and the standby mode control signal (S) are both logic low levels, so that the ninth NMOS transistor (N26) is turned on (ON), and the first The low voltage node (VL1) is at ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (N24) is turned off (OFF), and the eighth NMOS transistor (N25) is turned "ON".

第8圖所示為第5圖之本發明較佳實施例於讀取期間之簡化電路圖，其係藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，於讀取操作之一第一階段，該讀取控制信號(RC)為邏輯高位準，使得該第七NMOS電晶體(N24)導通，由於此時該第八NMOS電晶體(N25)仍導通，於是該第一低電壓節點(VL1)呈較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention during the reading period of Figure 5, which is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In a first stage of the read operation, the read control signal (RC) is at a logic high level, such that the seventh NMOS transistor (N24) is turned on, since the eighth NMOS transistor (N25) is still turned on at this time, Then, the first low voltage node (VL1) is at the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed.

而於讀取操作之一第二階段，雖然該讀取控制信號(RC)仍為邏輯高位準，使得該第七NMOS電晶體(N24)仍為導通，惟由於此時該第八NMOS電晶體(N25)截止，於是該第一低電壓節點(VL1)會經由導通的該 第九NMOS電晶體(N26)而呈接地電壓，藉此可有效減少無謂的功率消耗。在此值得注意的是，該讀取操作之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(N25)之閘極電壓足以關閉該第八NMOS電晶體(N25)為止之時間，其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者，無論於讀取操作之該第一階段抑是該第二階段，該第九NMOS電晶體(N26)均呈導通狀態(由於該第九NMOS電晶體(N26)之閘極為電源供應電壓VDD之位準)。 In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (N24) is still turned on, but since the eighth NMOS transistor is at this time (N25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (N26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, regardless of the first phase of the read operation or the second phase, the ninth NMOS transistor (N26) is in an on state (since the gate of the ninth NMOS transistor (N26) is at a power supply voltage The level of V DD ).

接下來依單埠SRAM之2種讀取狀態來說明第8圖之本發明較佳實施例如何設定該加速讀取電壓(RGND)與如何降低讀取時之半選定晶胞干擾。 Next, how to set the accelerated read voltage (RGND) and how to reduce the half-selected cell interference during reading according to the preferred embodiment of the present invention in FIG. 8 is illustrated by the two read states of the SRAM.

(一)讀取邏輯1(節點A儲存邏輯1)：在讀取動作發生前，該第一NMOS電晶體(N11)為截止(OFF)且該第二NMOS電晶體(N12)為導通(ON)，該節點A與該節點B分別為該電源供應電壓(VDD)與接地電壓，而該位元線(BL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間，由於該字元線控制信號(WLC)為該電源供應電壓扣抵該第十一NMOS電晶體(N51)之臨界電壓(即VDD-VTN51)，因此該第三NMOS電晶體(N13)截止(OFF)，藉此可有效保持該位元線(BL)為該電源供應電壓直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是，由於此時該第一低電壓節點(VL1)為該加速讀取電壓(RGND)，為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流，必須將該加速讀取電壓(RGND)設定為低於該第一NMOS電晶體(N11) 之臨界電壓(VTN11)，亦即| RGND |<VTN11 (4)其中，| RGND |與VTN11分別表示該加速讀取電壓之絕對值與該第一NMOS電晶體(N11)之臨界電壓。 (1) Read logic 1 (node A storage logic 1): before the read operation occurs, the first NMOS transistor (N11) is off (OFF) and the second NMOS transistor (N12) is on (ON) The node A and the node B are respectively the power supply voltage (V DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V DD ) due to the precharge circuit (3) . During the reading, since the word line control signal (WLC) is that the power supply voltage is biased against the threshold voltage of the eleventh NMOS transistor (N51) (ie, V DD -V TN51 ), the third NMOS is The crystal (N13) is turned off (OFF), whereby the bit line (BL) can be effectively maintained for the power supply voltage until the read cycle ends and the operation of reading the logic 1 is successfully completed. It is worth noting here that since the first low voltage node (VL1) is the accelerated read voltage (RGND) at this time, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, it is necessary to The accelerated read voltage (RGND) is set lower than the threshold voltage (V TN11 ) of the first NMOS transistor (N11), that is, | RGND | < V TN11 (4), where | RGND | and V TN11 respectively indicate Accelerating the absolute value of the read voltage and the threshold voltage of the first NMOS transistor (N11).

(二)讀取邏輯0(節點A儲存邏輯0)：在讀取動作發生前，該第一NMOS電晶體(N11)為導通(ON)且該第二NMOS電晶體(N12)為截止(OFF)，該節點A與該節點B分別為接地電壓與該電源供應電壓(VDD)，而該位元線(BL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。因為該第一NMOS電晶體(N11)為ON，所以當讀取動作開始時，該字元線控制信號(WLC)由Low(接地電壓)轉High(該電源供應電壓扣抵該第十一NMOS電晶體(N51)之臨界電壓VDD-VTN51)。當該字元線控制信號(WLC)的電壓大於該第三NMOS電晶體(N13)的臨界電壓時，該第三NMOS電晶體(N13)由截止(OFF)轉變為導通(ON)，此時該節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(5)：VAR=VDD×(RN11+RN23)/(RN13+RN11+RN23)+RGND×(RN13)/(RN13+RN11+RN23)<VTN12 (5) (2) Reading logic 0 (node A stores logic 0): before the read operation occurs, the first NMOS transistor (N11) is turned on (ON) and the second NMOS transistor (N12) is turned off (OFF) ), the node A and the node B are the ground voltage and the power supply voltage (V DD), and the bit line (BL) due to the precharge circuit (3) is equal to the power supply voltage (V DD) . Since the first NMOS transistor (N11) is ON, when the reading operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage is applied to the eleventh NMOS). The threshold voltage of the transistor (N51) is V DD -V TN51 ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13), the third NMOS transistor (N13) is turned from OFF to ON. The initial instantaneous voltage (V AR ) of the reading of node A must satisfy equation (5): V AR = V DD × (R N11 + R N23 ) / (R N13 + R N11 + R N23 ) + RGND × (R N13 )/(R N13 +R N11 +R N23 )<V TN12 (5)

其中，VAR表示節點A讀取邏輯0時之初始瞬間電壓，RN11、RN13與RN23分別表示該第一NMOS電晶體(N11)、該第三NMOS電晶體(N13)與該第六NMOS電晶體(N23)之導通電阻，而VDD、RGND與VTN12分別表示該電源供應電壓(VDD)、該加速讀取電壓(RGND)與該NMOS電晶體(N12)之臨界電壓。在此值得注意的是，該加速讀取電壓(RGND)係設計成低於接 地電壓且該加速讀取電壓之絕對值設計成小於該第一NMOS電晶體(N11)之臨界電壓。再者，為了有效降低讀取時之半選定晶胞干擾與容易滿足方程式(5)，本發明將讀取期間之該字元線控制信號(WLC)設定為該電源供應電壓扣抵該第十一NMOS電晶體(N51)之臨界電壓(VDD-VTN51)。 Wherein, V AR represents an initial instantaneous voltage when node A reads logic 0, and R N11 , R N13 and R N23 respectively represent the first NMOS transistor (N11), the third NMOS transistor (N13), and the sixth The on-resistance of the NMOS transistor (N23), and V DD , RGND and V TN12 represent the power supply voltage (V DD ), the accelerated read voltage (RGND), and the threshold voltage of the NMOS transistor (N12), respectively. It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (N11). Furthermore, in order to effectively reduce the half-selected cell interference during reading and to easily satisfy equation (5), the present invention sets the word line control signal (WLC) during reading to the power supply voltage to the tenth The threshold voltage (V DD -V TN51 ) of an NMOS transistor (N51).

(III)待機模式(standby mode) (III) Standby mode

首先，說明第5圖之待機啟動電路(4)如何促使單埠SRAM快速進入待機模式，以有效提高SRAM之待機效能：(1)於進入待機模式之前，該反相待機模式控制信號(/S)為邏輯High，該邏輯High之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)截止(OFF)，並使得該第十NMOS電晶體(N41)導通(ON)；(2)而於進入待機模式後，該反相待機模式控制信號(/S)為邏輯Low，該邏輯Low之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)導通(ON)，惟於待機模式之初始期間內(該初始期間係等於該反相待機模式控制信號(/S)由邏輯High轉變為邏輯Low起算，至該第十NMOS電晶體(N41)之閘極電壓足以關閉該第十NMOS電晶體(N41)為止之時間，其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整)，該第十NMOS電晶體(N41)仍導通(ON)，於是可對該第一低電壓節點(VL1)快速充電到達該第六NMOS電晶體(N23)之臨界電壓(VTN23)的電壓位準，亦即單埠SRAM可快速進入待機模式。在此值得注意的是，於待機模式之該初始期間後，該第十NMOS電晶體(N41)關閉並停止供應電流。 First, how the standby start circuit (4) of Fig. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and the tenth NMOS transistor (N41) is turned on (ON); (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) to be turned on. (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the gate of the tenth NMOS transistor (N41) The period of the pole voltage is sufficient to turn off the tenth NMOS transistor (N41), which can be adjusted by a delay time provided by the second delay circuit (D2), and the tenth NMOS transistor (N41) is still turned on. (ON), then the first low voltage node (VL1) can be quickly charged to reach the critical point of the sixth NMOS transistor (N23) Voltage (V TN23) voltage level, i.e., single-port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the tenth NMOS transistor (N41) is turned off and the supply current is stopped.

請參考第5圖，於待機模式時，該待機模式控制信號(S)為邏輯高位準，而該反相待機模式控制信號(/S)為邏輯低位準，該邏輯低位準之該反相待機模式控制信號(/S)可使得該控制電路(2)中之該第四 NMOS電晶體(N21)截止(OFF)，而該邏輯高位準之該待機模式控制信號(S)則使得該第五NMOS電晶體(N22)導通(ON)，此時該第五NMOS電晶體(N22)係作為等化器(equalizer)使用，因此可藉由呈導通狀態之該第五NMOS電晶體(N22)，以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準，且該等電壓位準均會等於該第六NMOS電晶體(N23)之臨界電壓(VTN23)的電壓位準。第9圖所示為第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (N21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (N22) is turned on (ON), and the fifth NMOS transistor (N22) is used as an equalizer, so that the fifth NMOS transistor (N22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (N23) The voltage level of the threshold voltage (V TN23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

接下來說明本發明於待機模式(standby mode)時如何減少漏電流，請參考第9圖，第9圖描述有本發明實施例處於待機模式時所產生之各漏電流(subthreshold leakage current)I1、I2、I3，其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(在此值得注意的是，由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該第六NMOS電晶體(N23)之臨界電壓(VTN23)的電壓位準，因此節點A為邏輯Low之電壓位準亦維持在該VTN23的電壓位準)，而該第二反相器之輸出(即節點B)為邏輯High(電源供應電壓VDD)。請參考第1b圖之先前技藝與第9圖之本發明實施例，來說明本發明所提出之靜態隨機存取記憶體與第1b圖之6T SRAM於漏電流方面之比較，首先關於流經該第三NMOS電晶體(N13)之漏電流I1，由於本發明於待機模式時節點A之電壓位準係維持在該VTN23的電壓位準，且假設字元線(WL)於待機模式時係設定成接地電壓，而位元線(BL)於待機模式時則設定為該電源供應電壓(VDD)，因此本發明之第三NMOS電晶體(N13)的閘源極電壓(VGS)為負值，反觀於待機模式時第1b圖先前技藝之NMOS電晶體(N13)的閘源極電壓(VGS)等於0，根 據閘極引發汲極洩漏(Gate Induced Drain Leakage，簡稱GIDL)效應或2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果可知，對於NMOS電晶體而言，閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%，因此導因於GIDL效應所引發之流經本發明之該第三NMOS電晶體(N13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(N13)者；再者，本發明該第三NMOS電晶體(N13)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTN23的電壓位準，反觀於待機模式時傳統第1b圖6T靜態隨機存取記憶體之NMOS電晶體(N13)之汲源極電壓(VDS)係等於該電源供應電壓(VDD)，根據汲極引發能障下跌(Drain-Induced Barrier Lowering，簡稱DIBL)效應，由於DIBL效應所引發之流經本發明之該第三NMOS電晶體(N13)之漏電流I1亦小於第1b圖先前技藝之NMOS電晶體(N13)者；結果，流經本發明之該第三NMOS電晶體(N13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(N13)者。 Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I 1 generated when the embodiment of the present invention is in the standby mode. I 2 , I 3 , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V TN23 ) of the sixth NMOS transistor (N23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V TN23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. The leakage current I 1 of the third NMOS transistor (N13) is maintained at the voltage level of the V TN 23 due to the voltage level of the node A in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V DD ) in the standby mode, so the gate-source voltage (V GS ) of the third NMOS transistor (N13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V GS ) of the prior art NMOS transistor (N13) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, thus resulting in the flow of the invention due to the GIDL effect The third NMOS transistor (N13) of the drain current I 1 is much smaller than the prior art of FIG. 1b of the NMOS transistor (N13) are; Furthermore, the present invention is the third NMOS transistor (N13) of the drain-source voltage ( V DS ) deducts the voltage level of the V TN 23 for the power supply voltage (V DD ), and the source voltage of the NMOS transistor (N13) of the conventional 1b to 6T static random access memory in the standby mode. (V DS ) is equal to the power supply voltage (V DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect (N13) of the drain current I 1 is also smaller than the prior art of FIG. 1b NMOS transistor (N13) are; As a result, the third NMOS transistor (N13) of the present invention to flow through the drain current I 1 is much smaller than the previous section in FIG. 1b The NMOS transistor (N13) of the art.

接著關於流經該第一PMOS電晶體(P11)之漏電流I2，由於待機模式時該第一PMOS電晶體(P11)之源極係為該電源供應電壓(VDD)，而該第一PMOS電晶體(P11)之汲極係維持在該該VTN23的電壓位準，因此本發明之該第一PMOS電晶體(P11)之源汲極電壓(VSD)為該電源供應電壓(VDD)扣減該VTN23的電壓位準，反觀於待機模式時第1b圖先前技藝之PMOS電晶體(P11)之源汲極電壓(VSD)係等於該電源供應電壓(VDD)，根據DIBL效應，因此流經本發明之該第一PMOS電晶體(P11)之漏電流I2會小於第1b圖先前技藝之PMOS電晶體(P11)者。 Next, regarding the leakage current I 2 flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V TN23 , so the source drain voltage (V SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V). DD ) deducting the voltage level of the V TN23 , and in the standby mode, the source drain voltage (V SD ) of the prior art PMOS transistor (P11) of FIG. 1b is equal to the power supply voltage (V DD ), according to The DIBL effect, therefore, the leakage current I 2 flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P11) of Figure 1b.

最後，關於流經該第二NMOS電晶體(N12)之漏電流I3， 由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該VTN23的電壓位準，節點A之電壓位準亦維持在該VTN23的電壓位準，而節點B之電壓位準係等於該電源供應電壓(VDD)且該第二NMOS電晶體(N12)之基底為接地電壓，因此本發明之該第二NMOS電晶體(N12)的基源極電壓(VBS)為負值，且該第二NMOS電晶體(N12)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTN23的電壓位準，反觀於待機模式時第1b圖先前技藝之NMOS電晶體(N12)的基源極電壓(VBS)等於0，且NMOS電晶體(N12)之汲源極電壓(VDS)等於該電源供應電壓(VDD)，根據本體效應(body effect)及DIBL效應可知，流經本發明之該第二NMOS電晶體(N12)之漏電流I3遠小於第1b圖先前技藝之NMOS電晶體(N12)者。由上述分析可知，本發明所提出之單埠靜態隨機存取記憶體與第1b圖先前技藝相較具有較低之漏電流。 Finally, regarding the leakage current I 3 flowing through the second NMOS transistor (N12), the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V TN23 due to the standby mode, node A The voltage level is also maintained at the voltage level of the V TN23 , and the voltage level of the node B is equal to the power supply voltage (V DD ) and the base of the second NMOS transistor (N12) is the ground voltage, so The base-source voltage (V BS ) of the second NMOS transistor (N12) is negative, and the 汲 source voltage (V DS ) of the second NMOS transistor (N12) is the power supply voltage (V) DD ) deducting the voltage level of the V TN23 , in contrast to the standby mode, the base-source voltage (V BS ) of the prior art NMOS transistor (N12) of FIG. 1b is equal to 0, and the NMOS transistor (N12) The source voltage (V DS ) is equal to the power supply voltage (V DD ). According to the body effect and the DIBL effect, the leakage current I 3 flowing through the second NMOS transistor (N12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (N12). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV)保持模式(hold mode) (IV) hold mode

保持模式時，由於該第一低電壓節點(VL1)與該第二低電壓節點(VL2)均設定成接地電壓，其工作原理相同於第3圖傳統具單一位元線之5T SRAM晶胞，於此不再累述。 In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【發明功效】 【Effects of invention】

本發明所提出之5T靜態隨機存取記憶體，具有如下功效： (1)有效降低讀取時之半選定晶胞干擾：本發明可藉由字元線電壓位準轉變電路(5)，以於讀取操作期間將施加至選定晶胞之存取電晶體(即第三NMOS電晶體N13)的字元線電壓下拉至低於該電源供應電壓(即VDD-VTN51)，其一方面可降低半選定晶胞中之第三NMOS電晶體(N13) 的讀取干擾，另一方面可藉由減輕滿足方程式(5)所需之加速讀取電壓(RGND)，以降低半選定晶胞中之第一NMOS電晶體(N11)的讀取干擾；(2)較小之晶胞尺寸：由於本發明係將該第一NMOS電晶體(N11)對該第三NMOS電晶體(N13)之通道寬長比的比值設計為1.2至1.5之間，因此具有較小之晶胞尺寸；(3)高讀取速度並避免無謂的功率消耗：本發明係採用二階段讀取操作，於讀取操作之第一階段藉由將第一低電壓節點(VL1)設定成較接地電壓為低之加速讀取電壓(RGND)以有效提高讀取速度，而於讀取操作之第二階段則藉由將第一低電壓節點(VL1)設定回接地電壓，以便減少無謂的功率消耗；(4)避免寫入邏輯1困難之問題：本發明於寫入操作時，可藉由配置較小通道寬長比的第一NMOS電晶體(N11)以於不阻礙讀取操作的情況下，藉由滿足方程式(3)以有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題；(5)快速進入待機模式：由於本發明設置有待機啟動電路(4)以促使SRAM快速進入待機模式，並藉此以謀求提高單埠SRAM之待機效能；(6)低待機電流：由於本發明於待機模式時，可藉由呈導通狀態之第五NMOS電晶體(N22)，以使得該第一低電壓節點(VL1)之電壓位準相等於第二低電壓節點(VL2)之電壓位準，並使得該等電壓位準均等於第六NMOS電晶體(N23)之臨界電壓的位準，因此本發明所提出之單埠靜態隨機存取記憶體亦具備低待機電流之功效；(7)低電晶體數：對於具有1024列1024行之SRAM陣列而言，傳統第1b圖6T靜態隨機存取記憶體陣列共需1024×1024×6=6,291,456顆電晶體，而本發明所提出之靜態隨機存取記憶體僅至少需1024×1024×5+1024×18+6=5,261,318顆電晶體，其減少16.4%之電晶體數。 The 5T static random access memory proposed by the invention has the following effects: (1) effectively reducing half-selected cell interference during reading: the present invention can be implemented by a word line voltage level conversion circuit (5) Pulling the word line voltage applied to the access transistor of the selected cell (ie, the third NMOS transistor N13) below the power supply voltage (ie, V DD -V TN51 ) during the read operation, on the one hand The read disturb of the third NMOS transistor (N13) in the half selected cell can be reduced, and the half selected cell can be reduced by reducing the accelerated read voltage (RGND) required to satisfy equation (5). Read interference of the first NMOS transistor (N11); (2) smaller cell size: since the present invention is the first NMOS transistor (N11) to the third NMOS transistor (N13) The ratio of the channel width to length ratio is designed to be between 1.2 and 1.5, thus having a smaller cell size; (3) high read speed and avoiding unnecessary power consumption: the present invention uses a two-stage read operation for reading The first phase of operation is performed by setting the first low voltage node (VL1) to an accelerated read voltage (RGND) that is lower than the ground voltage. Effectively increase the reading speed, and in the second stage of the read operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption; (4) avoiding the difficulty of writing logic 1 The present invention can effectively avoid the equation (3) by configuring the first NMOS transistor (N11) with a smaller channel aspect ratio in the write operation without satisfying the read operation. Knowing that a single bit line 單埠SRAM has a problem of writing logic 1 is quite difficult; (5) quickly entering standby mode: since the present invention is provided with a standby start circuit (4) to cause the SRAM to quickly enter the standby mode, and thereby In order to improve the standby performance of the 單埠SRAM; (6) low standby current: since the present invention is in the standby mode, the fifth NMOS transistor (N22) in an on state can be used to make the first low voltage node ( The voltage level of VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (N23), and thus the present invention proposes After that, the static random access memory also has low waiting. The effect of the machine current; (7) the number of low-voltage crystals: for a SRAM array with 1024 columns and 1024 rows, the conventional 1b Figure 6T static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors. However, the static random access memory proposed by the present invention only needs at least 1024 × 1024 × 5 + 1024 × 18 + 6 = 5,261,318 transistors, which reduces the number of transistors by 16.4%.

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Precharge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

5‧‧‧字元線電壓位準轉變電路 5‧‧‧Word line voltage level shift circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor

N11‧‧‧第一NMOS電晶體 N11‧‧‧First NMOS transistor

N12‧‧‧第二NMOS電晶體 N12‧‧‧Second NMOS transistor

N13‧‧‧第三NMOS電晶體 N13‧‧‧ Third NMOS transistor

A‧‧‧儲存節點 A‧‧‧ storage node

B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node

BL‧‧‧位元線 BL‧‧‧ bit line

WLC‧‧‧字元線控制信號 WLC‧‧‧ word line control signal

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node

N21‧‧‧第四NMOS電晶體 N21‧‧‧4th NMOS transistor

N22‧‧‧第五NMOS電晶體 N22‧‧‧ fifth NMOS transistor

N23‧‧‧第六NMOS電晶體 N23‧‧‧ sixth NMOS transistor

N24‧‧‧第七NMOS電晶體 N24‧‧‧ seventh NMOS transistor

N25‧‧‧第八NMOS電晶體 N25‧‧‧ eighth NMOS transistor

N26‧‧‧第九NMOS電晶體 N26‧‧‧Ninth NMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧ read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

INV‧‧‧第三反相器 INV‧‧‧ third inverter

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

P31‧‧‧第三PMOS電晶體 P31‧‧‧ Third PMOS transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

N41‧‧‧第十NMOS電晶體 N41‧‧‧ tenth NMOS transistor

P41‧‧‧第四PMOS電晶體 P41‧‧‧4th PMOS transistor

D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

WL‧‧‧字元線 WL‧‧‧ character line

R‧‧‧讀取信號 R‧‧‧Read signal

/W‧‧‧反相寫入信號 /W‧‧‧Inverted write signal

/RW‧‧‧反相讀寫控制信號 /RW‧‧‧Inverted read/write control signal

P51‧‧‧第五PMOS電晶體 P51‧‧‧ Fifth PMOS transistor

N51‧‧‧第十一NMOS電晶體 N51‧‧11 eleventh NMOS transistor

N52‧‧‧第十二NMOS電晶體 N52‧‧‧12th NMOS transistor

Claims (10)

一種5T靜態隨機存取記憶體，包括：一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包含有複數個記憶體晶胞(1)；複數個控制電路(2)，每一列記憶體晶胞設置一個控制電路(2)；複數個預充電電路(3)，每一行記憶晶胞設置一個預充電電路(3)；一待機啟動電路(4)，該待機啟動電路(4)係促使該5T靜態隨機存取記憶體快速進入待機模式，以有效提高該5T靜態隨機存取記憶體之待機效能；以及複數個字元線電壓位準轉變電路(5)，每一列記憶體晶胞設置一個字元線電壓位準轉變電路(5)；其中，每一記憶體晶胞(1)更包含：一第一反相器，係由一第一PMOS電晶體(P11)與一第一NMOS電晶體(N11)所組成，該第一反相器係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間；一第二反相器，係由一第二PMOS電晶體(P12)與一第二NMOS電晶體(N12)所組成，該第二反相器係連接在該電源供應電壓(VDD)與一第二低電壓節點(VL2)之間；一儲存節點(A)，係由該第一反相器之輸出端所形成；一反相儲存節點(B)，係由該第二反相器之輸出端所形成；一第三NMOS電晶體(N13)，係連接在該儲存節點(A)與一位元線(BL)之間，且閘極連接至一字元線控制信號(WLC)；其中，該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出端(即該儲存節點A)係連接至該第二反相器之輸入端，而該第二反相器之輸出端(即該反相儲存節點B)則連接至該第一反相器之輸入端；而每一控制電路(2)更包含：一第四NMOS電晶體(N21)、一第五NMOS電晶體(N22)、一第六NMOS電晶體(N23)、一第七NMOS電晶體(N24)、一第八NMOS電晶體(N25)、一第九NMOS電晶體(N26)、一讀取控 制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)；其中，該第四NMOS電晶體(N21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2)；該第五NMOS電晶體(N22)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該待機模式控制信號(S)與該第一低電壓節點(VL1)；該第六NMOS電晶體(N23)之源極係連接至接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)；該第七NMOS電晶體(N24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(N25)之汲極、該讀取控制信號(RC)與該第一低電壓節點(VL1)；該第八NMOS電晶體(N25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(N24)之源極；該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(N25)之閘極之間；該第三反相器(INV)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入；該第九NMOS電晶體(N26)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第一低電壓節點(VL1)；其中，對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(N24)於非讀取模式期間之漏電流；再者，該待機啟動電路(4)係設計成於進入待機模式之一初始期間內，對該第一低電壓節點(VL1)處之寄生電容快速充電至該第六NMOS電晶體(N23)之臨界電壓(VTN23)的電壓位準；此外，每一字元線電壓位準轉變電路(5)更包含：一第五PMOS電晶體(P51)、一第十一NMOS電晶體(N51)、一第十二NMOS電晶體(N52)、 一讀取信號(R)、一反相寫入信號(/W)、一反相讀寫控制信號(/RW)以及該字元線控制信號(WLC)；其中，該第五PMOS電晶體(P51)之源極、閘極與汲極係分別連接至一字元線(WL)、該反相寫入信號(/W)與該字元線控制信號(WLC)；該第十一NMOS電晶體(N51)之源極、閘極與汲極係分別連接至該字元線控制信號(WLC)、該讀取信號(R)與該字元線(WL)；而該第十二NMOS電晶體(N52)之源極、閘極與汲極係分別連接至該字元線控制信號(WLC)、該反相讀寫控制信號(/RW)與該字元線(WL)；在此值得注意的是，每一字元線電壓位準轉變電路(5)於讀取操作時，將選定晶胞之該字元線(WL)由該電源供應電壓(VDD)轉變為該電源供應電壓(VDD)扣抵該第十一NMOS電晶體(N51)之臨界電壓(VTN51)(即VDD-VTN51)後提供給與該字元線控制信號(WLC)；而於寫入操作時，則將選定晶胞之該字元線(WL)的該電源供應電壓(VDD)提供給與該字元線控制信號(WLC)。 A 5T static random access memory comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells The cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells Providing a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompting the 5T static random access memory to quickly enter a standby mode to effectively improve the 5T static random access memory Standby performance; and a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5); wherein each memory cell (1) The method further includes: a first inverter comprising a first PMOS transistor (P11) and a first NMOS transistor (N11) connected to a power supply voltage (V DD ) ) between a first low voltage node (VL1) and a second inverter PMOS transistor (P12) and a second NMOS transistor (N12) being composed of lines of the second inverter is connected between the power supply voltage (V DD) and a second low voltage node (VL2); a a storage node (A) formed by an output of the first inverter; an inverting storage node (B) formed by an output of the second inverter; and a third NMOS transistor ( N13) is connected between the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); wherein the first inverter and the second The inverter is connected in an alternating manner, that is, the output end of the first inverter (ie, the storage node A) is connected to the input end of the second inverter, and the output end of the second inverter (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (N21), a fifth NMOS transistor ( N22), a sixth NMOS transistor (N23), a seventh NMOS transistor (N24), an eighth NMOS transistor (N25), a ninth NMOS transistor (N26), and a read control signal (RC) ), a third inverter (INV), a a delay circuit (D1), an accelerated read voltage (RGND), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the source of the fourth NMOS transistor (N21) a pole, a gate and a drain are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); a source and a gate of the fifth NMOS transistor (N22) The pole and the drain are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); and the source of the sixth NMOS transistor (N23) Connected to a ground voltage, the gate is connected to the drain and connected to the first low voltage node (VL1); the source, the gate and the drain of the seventh NMOS transistor (N24) are respectively connected to the a drain of the eighth NMOS transistor (N25), the read control signal (RC) and the first low voltage node (VL1); a source, a gate and a drain of the eighth NMOS transistor (N25) Connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (N24); the first delay circuit (D1) is connected to the first The output of the inverter (INV) is between the gate of the eighth NMOS transistor (N25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is Connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (N26) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and The first low voltage node (VL1); wherein the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (N24) leakage current during the non-read mode; further, the standby start circuit (4) is designed to be parasitic capacitance at the first low voltage node (VL1) during an initial period of entering the standby mode The voltage level of the threshold voltage (V TN23 ) of the sixth NMOS transistor (N23) is rapidly charged; in addition, each word line voltage level conversion circuit (5) further includes: a fifth PMOS transistor (P51) ), an eleventh NMOS transistor (N51), a twelfth NMOS transistor (N52), a read signal (R), an inverted write signal (/W), an inversion read and write a signal (/RW) and the word line control signal (WLC); wherein the source, the gate and the drain of the fifth PMOS transistor (P51) are respectively connected to a word line (WL), An inverted write signal (/W) and the word line control signal (WLC); a source, a gate and a drain of the eleventh NMOS transistor (N51) are respectively connected to the word line control signal ( WLC), the read signal (R) and the word line (WL); and the source, gate and drain of the twelfth NMOS transistor (N52) are respectively connected to the word line control signal ( WLC), the inverted read/write control signal (/RW) and the word line (WL); it is worth noting here that each word line voltage level transition circuit (5) is used during a read operation The word line (WL) of the selected unit cell is converted from the power supply voltage (V DD ) to the power supply voltage (V DD ) to the threshold voltage (V TN51 ) of the eleventh NMOS transistor (N51) ( That is, V DD -V TN51 ) is supplied to the word line control signal (WLC); and in the write operation, the power supply voltage (V DD ) of the word line (WL) of the selected unit cell is selected. The word line control signal (WLC) is provided. 如申請專利範圍第1項所述之5T靜態隨機存取記憶體，其中，該每一記憶體晶胞(1)中之該第一NMOS電晶體(N11)對該第三NMOS電晶體(N13)之通道寬長比的比值設計為1.2至1.5之間。 The 5T static random access memory according to claim 1, wherein the first NMOS transistor (N11) in the memory cell (1) is the third NMOS transistor (N13) The ratio of the channel width to length ratio is designed to be between 1.2 and 1.5. 如申請專利範圍第2項所述之5T靜態隨機存取記憶體，其中，該每一記憶體晶胞(1)中之該第一NMOS電晶體(N11)與該第二NMOS電晶體(N12)具有相同之通道寬長比，且該第一PMOS電晶體(P11)與該第二PMOS電晶體(P12)亦具有相同之通道寬長比。 The 5T static random access memory according to claim 2, wherein the first NMOS transistor (N11) and the second NMOS transistor (N12) in each memory cell (1) Having the same channel aspect ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width to length ratio. 如申請專利範圍第3項所述之5T靜態隨機存取記憶體，其中，該每一控制電路(2)中之該加速讀取電壓(RGND)係設定為低於該每一記憶體晶胞(1)中之該第一NMOS電晶體(N11)之臨界電壓(VTN11)。 The 5T static random access memory according to claim 3, wherein the accelerated read voltage (RGND) in each control circuit (2) is set lower than each memory cell. The threshold voltage (V TN11 ) of the first NMOS transistor (N11) in ( 1 ). 如申請專利範圍第4項所述之5T靜態隨機存取記憶體，其中，該每一字元線電壓位準轉變電路(5)中之該讀取信號(R)與該反相寫入信號(/W)係來自該5T靜態隨機存取記憶體之一讀寫控制接腳，當該讀寫控制接腳為邏輯高位準時指示讀取操作(即該讀取信號R為邏輯高位準)，而該讀寫控制接腳為邏輯低位準時指示寫入操作(即該反相寫入信號/W為邏輯低位準)，至於該反相讀寫控制信號(/RW)則為該讀寫控制接腳 之反相信號。 5. The 5T static random access memory according to claim 4, wherein the read signal (R) and the inverted write signal in the each word line voltage level transition circuit (5) (/W) is a read/write control pin from the 5T static random access memory. When the read/write control pin is logic high, the read operation is indicated (ie, the read signal R is a logic high level). The read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level), and the inverted read/write control signal (/RW) is the read/write control connection. foot Inverted signal. 如申請專利範圍第5項所述之5T靜態隨機存取記憶體，其中，該每一控制電路(2)中之該讀取控制信號(RC)為該讀取信號(R)與該字元線(WL)信號的及閘(AND gate)運算結果，亦即僅於該讀取信號(R)與該字元線(WL)信號均為邏輯高位準時，該讀取控制信號(RC)方為邏輯高位準。 5. The 5T static random access memory according to claim 5, wherein the read control signal (RC) in each control circuit (2) is the read signal (R) and the character. The result of the AND gate operation of the line (WL) signal, that is, the read control signal (RC) side only when the read signal (R) and the word line (WL) signal are both at a logic high level. It is logically high. 如申請專利範圍第6項所述之5T靜態隨機存取記憶體，其中，該每一預充電電路(3)係由一第三PMOS電晶體(P31)以及一預充電信號(P)所組成；其中，該第三PMOS電晶體(P31)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該預充電信號(P)與該位元線(BL)，以便於一預充電期間，藉由邏輯低位準之該預充電信號(P)，以將該位元線(BL)預充電至該電源供應電壓(VDD)之位準。 The 5T static random access memory according to claim 6, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). Wherein the source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to a power supply voltage (V DD ), the precharge signal (P) and the bit line (BL), so that During a precharge period, the precharge signal (P) is logic low to precharge the bit line (BL) to the level of the power supply voltage (V DD ). 如申請專利範圍第7項所述之5T靜態隨機存取記憶體，其中，該待機啟動電路(4)係由一第四PMOS電晶體(P41)、一第十NMOS電晶體(N41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成；其中，該第四PMOS電晶體(P41)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十NMOS電晶體(N41)之汲極；該第十NMOS電晶體(N41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第四PMOS電晶體(P41)之汲極；該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十NMOS電晶體(N41)之閘極。 The 5T static random access memory according to claim 7, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41), a tenth NMOS transistor (N41), and a a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage ( V DD ), the inverted standby mode control signal (/S) and the drain of the tenth NMOS transistor (N41); the source, the gate and the drain of the tenth NMOS transistor (N41) are respectively connected Up to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inversion The standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the tenth NMOS transistor (N41). 如申請專利範圍第8項所述之5T靜態隨機存取記憶體，其中，該待機啟動電路(4)進入待機模式之該初始期間係等於該反相待機模式控制信號(/S)由邏輯高位準轉變為邏輯低位準起算，至該第十NMOS電晶體(N41)之閘極電壓足以關閉該第十NMOS電晶體(N41)為止之時間，其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整。 The 5T static random access memory according to claim 8, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) being logic high The quasi-transition is a logic low level, until the gate voltage of the tenth NMOS transistor (N41) is sufficient to turn off the tenth NMOS transistor (N41), which can be performed by the second delay circuit (D2) Provide one of the delay times to adjust. 如申請專利範圍第9項所述之5T靜態隨機存取記憶體，其中，該每一記憶體晶胞(1)之讀取操作係可再細分成二個階段，於該讀取操作之一第一階段係藉由將該第一低電壓節點(VL1)設定成較接地電壓為低之該加速讀取電壓(RGND)以有效提高讀取速度，而於該讀取操作之一第二階段則藉由將該第一低電壓節點(VL1)設定回接地電壓，以便減少無謂的功率消耗，該讀取操作之該第二階段與該第一階段間隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，至該第八NMOS電晶體(N25)之閘極電壓足以關閉該第八NMOS電晶體(N25)為止之時間，其可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之另一延遲時間來調整。 The 5T static random access memory according to claim 9, wherein the read operation of each memory cell (1) can be subdivided into two stages, one of the reading operations. The first stage is to increase the read speed by setting the first low voltage node (VL1) to the accelerated read voltage (RGND) lower than the ground voltage, and in the second stage of the read operation Then, by setting the first low voltage node (VL1) back to the ground voltage, so as to reduce unnecessary power consumption, the time between the second phase of the read operation and the first phase is equal to the read control signal. (RC) from the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), which can be performed by the third The falling delay time of the inverter (INV) is adjusted with another delay time provided by the first delay circuit (D1).
TW104133101A 2015-10-07 2015-10-07 Five transistor static random access memory TWI556409B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW104133101A TWI556409B (en) 2015-10-07 2015-10-07 Five transistor static random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104133101A TWI556409B (en) 2015-10-07 2015-10-07 Five transistor static random access memory

Publications (2)

Publication Number Publication Date
TWI556409B true TWI556409B (en) 2016-11-01
TW201714281A TW201714281A (en) 2017-04-16

Family

ID=57851459

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104133101A TWI556409B (en) 2015-10-07 2015-10-07 Five transistor static random access memory

Country Status (1)

Country Link
TW (1) TWI556409B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273030A (en) * 2017-07-18 2019-01-25 延世大学校产学协力团 Static random access memory including auxiliary circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090161410A1 (en) * 2007-12-21 2009-06-25 Texas Instruments Inc. Seven transistor sram cell
US20100002496A1 (en) * 2008-07-02 2010-01-07 Kabushi Kaisha Toshiba Semiconductor memory device
US20130100731A1 (en) * 2011-10-21 2013-04-25 Ching-Te Chuang Independenty-controlled-gate sram
US20130141962A1 (en) * 2011-12-06 2013-06-06 Taiwan Semicondcutor Manufacturing Company, Ltd. Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits
TWI433152B (en) * 2010-06-28 2014-04-01 Univ Hsiuping Sci & Tech 7t dual port sram

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090161410A1 (en) * 2007-12-21 2009-06-25 Texas Instruments Inc. Seven transistor sram cell
US20100002496A1 (en) * 2008-07-02 2010-01-07 Kabushi Kaisha Toshiba Semiconductor memory device
TWI433152B (en) * 2010-06-28 2014-04-01 Univ Hsiuping Sci & Tech 7t dual port sram
US20130100731A1 (en) * 2011-10-21 2013-04-25 Ching-Te Chuang Independenty-controlled-gate sram
US20130141962A1 (en) * 2011-12-06 2013-06-06 Taiwan Semicondcutor Manufacturing Company, Ltd. Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273030A (en) * 2017-07-18 2019-01-25 延世大学校产学协力团 Static random access memory including auxiliary circuit
CN109273030B (en) * 2017-07-18 2022-07-15 延世大学校产学协力团 Static random access memory including auxiliary circuit

Also Published As

Publication number Publication date
TW201714281A (en) 2017-04-16

Similar Documents

Publication Publication Date Title
TWI556242B (en) Single port static random access memory (8)
TWI582769B (en) Static random access memory
TWI529711B (en) Single port static random access memory (2)
TWI638365B (en) Five-transistor static random access memory with fast write speed
TWI529712B (en) Single port static random access memory (6)
TWI529713B (en) Single port static random access memory (5)
TWI634564B (en) Five transistor single port static random access memory
TWI529715B (en) Single port static random access memory (3)
TWI582770B (en) Five transistor static random access memory
TWI618082B (en) Five transistor static random access memory
TWI591638B (en) Five transistor static random access memory
TWI611424B (en) Five transistor static random access memory with fast read speed
TWI556409B (en) Five transistor static random access memory
TWI579846B (en) 7t dual port static random access memory
TWI559453B (en) Single port static random access memory (4)
TWI660349B (en) Five-transistor single port static random access memory with fast read/write speed
TWI618085B (en) Static random access memory
TWI609372B (en) Single port static random access memory
TWI591634B (en) Five transistor static random access memory
TWI521510B (en) Single port static random access memory (1)
TWI570717B (en) Five transistor static random access memory
TWI566255B (en) Five transistor static random access memory
TWI660366B (en) Five-transistor static random access memory with fast read/write speed
TWI573139B (en) Single port static random access memory
TWI622062B (en) Static random access memory with fast read speed

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees