TWI556223B - Liquid crystal display device and operating method thereof - Google Patents

Liquid crystal display device and operating method thereof Download PDF

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Publication number
TWI556223B
TWI556223B TW104137918A TW104137918A TWI556223B TW I556223 B TWI556223 B TW I556223B TW 104137918 A TW104137918 A TW 104137918A TW 104137918 A TW104137918 A TW 104137918A TW I556223 B TWI556223 B TW I556223B
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signal
gate
chamfered
gate driving
clock signal
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TW104137918A
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Chinese (zh)
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TW201719617A (en
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朱育緯
蕭開元
李建鋒
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友達光電股份有限公司
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Priority to TW104137918A priority Critical patent/TWI556223B/en
Priority to CN201511002576.2A priority patent/CN105374337A/en
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Publication of TW201719617A publication Critical patent/TW201719617A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G09G2300/0491—Use of a bi-refringent liquid crystal, optically controlled bi-refringence [OCB] with bend and splay states, or electrically controlled bi-refringence [ECB] for controlling the color
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Description

液晶顯示裝置及其操作方法 Liquid crystal display device and operating method thereof

本發明是有關於一種顯示裝置，尤其是有關於一種液晶顯示裝置的結構及其操作方法。 The present invention relates to a display device, and more particularly to a structure of a liquid crystal display device and a method of operating the same.

當前之液晶顯示器包括多列畫素，每一列畫素接收一個閘極驅動訊號，當同一列的畫素因為閘極驅動訊號而開啟時，被開啟的畫素會根據所接收的顯示資料來顯示。而為了減少畫素因寄生電容所導致的畫面閃爍，習知常利用削角電路使液晶顯示器具有削角的閘極驅動訊號來驅動上述之畫素。又，為了避免畫素在錯誤的時間被閘極驅動訊號開啟而顯示錯誤的顯示資料，也就是畫素被錯充，需要額外的設計，因而會大幅增加液晶顯示器之內部走線區域以及使用元件數量，進而增加整體能量以及成本的消耗。 The current liquid crystal display includes a plurality of columns of pixels, and each column of pixels receives a gate driving signal. When the pixels of the same column are turned on due to the gate driving signal, the turned-on pixels are displayed according to the received display data. . In order to reduce the flicker caused by the parasitic capacitance of the pixel, it is conventional to use a chamfer circuit to make the liquid crystal display have a chamfered gate driving signal to drive the above pixel. Moreover, in order to prevent the pixel from being turned on by the gate driving signal at the wrong time and displaying the wrong display material, that is, the pixel is mischarged, an additional design is required, thereby greatly increasing the internal wiring area of the liquid crystal display and using the component. Quantity, which in turn increases overall energy and cost.

為了解決上述之缺憾，本發明提出一種液晶顯示裝置，其包括顯示單元、時脈控制單元以及閘極驅動模組，其中，顯示單元具有多個畫素單元，時脈控制單元是用以產生時脈訊號，閘級驅動模組與時脈控制單元電性耦接，閘級驅動模組是用以根據時脈訊號產生削角閘極驅動訊號並傳送 至對應的多個畫素單元，且削角閘極驅動訊號是根據時脈訊號進行削角。 In order to solve the above drawbacks, the present invention provides a liquid crystal display device including a display unit, a clock control unit, and a gate driving module, wherein the display unit has a plurality of pixel units, and the clock control unit is used to generate the time. The pulse signal, the gate drive module is electrically coupled to the clock control unit, and the gate drive module is configured to generate a chamfer gate drive signal according to the clock signal and transmit To the corresponding multiple pixel units, and the chamfered gate drive signal is chamfered according to the clock signal.

在本發明的較佳實施例中，上述之閘級驅動模組更包括閘極驅動單元以及削角電路，閘極驅動單元與時脈控制單元電性耦接以根據時脈訊號輸出閘極驅動訊號，削角電路與多個畫素單元、閘極驅動單元以及時脈控制單元電性耦接，削角電路是用以接收閘極驅動訊號以及時脈訊號並根據時脈訊號對閘極驅動訊號進行削角以產生削角閘極驅動訊號，削角電路並將削角閘極驅動訊號傳送至對應的多個畫素單元。 In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit, and the gate driving unit is electrically coupled to the clock control unit to output the gate driving according to the clock signal. The signal, the chamfering circuit is electrically coupled to the plurality of pixel units, the gate driving unit and the clock control unit, and the chamfering circuit is configured to receive the gate driving signal and the clock signal and drive the gate according to the clock signal The signal is chamfered to generate a chamfered gate drive signal, and the chamfering circuit transmits the chamfered gate drive signal to the corresponding plurality of pixel units.

在本發明的較佳實施例中，上述之閘級驅動模組更包括閘極驅動單元以及削角電路，削角電路與時脈控制單元電性耦接，是用以接收時脈訊號以及高電壓準位，並根據時脈訊號對高電壓準位進行削角以產生削角高電壓準位，閘極驅動單元與削角電路、時脈控制單元以及多個畫素單元電性耦接，閘極驅動單元是用以接收削角高電壓準位以及時脈訊號，並根據削角高電壓準位以及時脈訊號產生削角閘極驅動訊號，並將削角閘極驅動訊號傳送至對應的多個畫素單元。 In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit, and the chamfering circuit is electrically coupled to the clock control unit to receive the clock signal and the high Voltage level, and chamfering the high voltage level according to the clock signal to generate a chamfer high voltage level, the gate driving unit is electrically coupled with the chamfering circuit, the clock control unit and the plurality of pixel units, The gate driving unit is configured to receive the chamfer high voltage level and the clock signal, and generate the chamfering gate driving signal according to the chamfering high voltage level and the clock signal, and transmit the chamfering gate driving signal to the corresponding Multiple pixel units.

在本發明的較佳實施例中，上述之時脈訊號、削角閘極驅動訊號以及資料驅動訊號皆具有一第一型態觸發緣以及一第二型態觸發緣，資料驅動訊號之第二型態觸發緣晚於時脈訊號以及削角閘極驅動訊號之第一型態觸發緣，資料驅動訊號之第二型態觸發緣早於時脈訊號以及削角閘極驅動訊號之第二型態觸發緣。 In a preferred embodiment of the present invention, the clock signal, the chamfered gate driving signal and the data driving signal have a first type trigger edge and a second type trigger edge, and the second data driving signal The type trigger edge is later than the first pulse trigger edge of the clock signal and the chamfered gate drive signal, and the second type trigger edge of the data drive signal is earlier than the clock signal and the second type of the chamfered gate drive signal State trigger edge.

本發明更提出一種液晶顯示裝置之操作方法，液晶顯示裝置包括多個畫素單元、時脈控制單元以及閘極驅動模組，時脈控制單元用以輸出時脈訊號以及資料驅動訊號，液晶顯示裝置之操作方法包括以下步驟：使閘極驅動模組接 收時脈訊號並據以產生削角閘極驅動訊號；以及使多個畫素單元接收削角閘極驅動訊號，其中，削角閘極驅動訊號是根據時脈訊號進行削角。 The invention further provides a method for operating a liquid crystal display device. The liquid crystal display device comprises a plurality of pixel units, a clock control unit and a gate driving module. The clock control unit is configured to output a clock signal and a data driving signal, and the liquid crystal display The operation method of the device includes the following steps: connecting the gate driving module Receiving a clock signal and generating a chamfered gate driving signal; and causing the plurality of pixel units to receive the chamfering gate driving signal, wherein the chamfering gate driving signal is chamfered according to the clock signal.

在本發明的較佳實施例中，上述之閘極驅動模組更包括閘極驅動單元以及削角電路，液晶顯示裝置之操作方法更包括：使閘極驅動單元接收時脈訊號並據以輸出一閘極驅動訊號；使削角電路接收時脈訊號以及閘極驅動訊號並以時脈訊號對閘極驅動訊號進行削角以輸出一削角閘極驅動訊號。 In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit. The operating method of the liquid crystal display device further includes: causing the gate driving unit to receive the clock signal and output the signal according to the output. a gate driving signal; the chamfering circuit receives the clock signal and the gate driving signal and chamfers the gate driving signal by the clock signal to output a chamfering gate driving signal.

在本發明的較佳實施例中，上述之閘極驅動模組更包括閘極驅動單元以及削角電路，液晶顯示裝置之操作方法更包括：使削角電路接收時脈訊號以及高電壓準位，並根據時脈訊號對高電壓準位進行削角以產生一削角高電壓準位；使閘極驅動單元接收時脈訊號以及削角高電壓準位，並根據時脈訊號以及削角高電壓準位產生削角閘極驅動訊號。 In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit. The operating method of the liquid crystal display device further includes: receiving the clock signal and the high voltage level by the chamfering circuit And chamfering the high voltage level according to the clock signal to generate a chamfered high voltage level; enabling the gate driving unit to receive the clock signal and the chamfering high voltage level, and according to the clock signal and the chamfer angle The voltage level produces a chamfered gate drive signal.

在本發明的較佳實施例中，上述之時脈訊號、削角閘極驅動訊號以及資料驅動訊號皆具有一第一型態觸發緣以及一第二型態觸發緣，資料驅動訊號之第二型態觸發緣晚於時脈訊號以及削角閘極驅動訊號之第一型態觸發緣，資料驅動訊號之第二型態觸發緣早於時脈訊號以及削角閘極驅動訊號之第二型態觸發緣。 In a preferred embodiment of the present invention, the clock signal, the chamfered gate driving signal and the data driving signal have a first type trigger edge and a second type trigger edge, and the second data driving signal The type trigger edge is later than the first pulse trigger edge of the clock signal and the chamfered gate drive signal, and the second type trigger edge of the data drive signal is earlier than the clock signal and the second type of the chamfered gate drive signal State trigger edge.

本發明可有效避免錯充的情況發生，因此本發明明顯可有效降低元件走線區域以及元件數量，大幅減少整體能量以及成本的消耗。 The invention can effectively avoid the occurrence of mischarge, and therefore the invention can obviously reduce the component routing area and the number of components, and greatly reduce the overall energy and cost consumption.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明如下。 The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

10‧‧‧液晶顯示裝置 10‧‧‧Liquid crystal display device

11‧‧‧時脈控制單元 11‧‧‧clock control unit

12‧‧‧閘極驅動模組 12‧‧‧Gate drive module

121‧‧‧閘極驅動單元 121‧‧‧Gate drive unit

122‧‧‧削角電路 122‧‧‧Chamfering circuit

13‧‧‧資料驅動單元 13‧‧‧Data Drive Unit

14‧‧‧顯示單元 14‧‧‧Display unit

141‧‧‧畫素單元 141‧‧‧ pixel unit

CLK‧‧‧時脈訊號 CLK‧‧‧ clock signal

STB、STB1、STB2‧‧‧資料驅動訊號 STB, STB1, STB2‧‧‧ data drive signals

GOUT、GOUT1…GOUTn‧‧‧削角閘極驅動訊號 G OUT , G OUT1 ... G OUTn ‧‧‧Chamfering gate drive signal

G1、G2…Gn‧‧‧閘極驅動訊號 G 1 , G 2 ... Gn‧‧‧ gate drive signal

VGH‧‧‧高電壓準位 V GH ‧‧‧high voltage level

VGHM‧‧‧削角高電壓準位 V GHM ‧‧‧Chamfering high voltage level

T、T1、T2‧‧‧時段 T, T 1 , T 2 ‧ ‧ hours

圖1A為本發明之液晶顯示裝置實施例一示意圖。 1A is a schematic view showing a first embodiment of a liquid crystal display device of the present invention.

圖1B為本發明之液晶顯示裝置實施例一之時序示意圖。 FIG. 1B is a timing diagram of Embodiment 1 of a liquid crystal display device of the present invention.

圖2A為本發明之液晶顯示裝置實施例二示意圖。 2A is a schematic view showing a second embodiment of a liquid crystal display device of the present invention.

圖2B為本發明之液晶顯示裝置實施例二之時序示意圖。 2B is a timing diagram of a second embodiment of a liquid crystal display device of the present invention.

圖3A為本發明之液晶顯示裝置實施例一操作方法步驟示意圖。 3A is a schematic view showing the steps of an operation method of the liquid crystal display device of the present invention.

圖3B為本發明之液晶顯示裝置實施例二操作方法步驟示意圖。 FIG. 3B is a schematic diagram showing the steps of the second embodiment of the liquid crystal display device of the present invention.

請參閱圖1A，圖1A為本發明之液晶顯示裝置10實施例1，液晶顯示裝置10包括時脈控制單元11、閘極驅動模組12、資料驅動單元13以及顯示單元14。時脈控制單元11與閘極驅動模組12以及資料驅動單元13電性耦接，時脈控制單元11是用以產生時脈訊號CLK以及資料驅動訊號STB。資料驅動單元13與時脈控制單元11電性耦接，是用以接收資料驅動訊號STB並根據資料驅動訊號STB輸出顯示資料至電性耦接的顯示單元14。顯示單元14包括多個畫素單元141，每個畫素單元141皆與資料驅動單元13以及閘極驅動模組12電性耦接，每個畫素單元141是用以根據閘極驅動模組12輸出之削角閘極驅動訊號GOUT決定是否顯示由資料驅動單元13所接收的顯示資料。閘極驅動模組12包括閘極驅動單元121以及削角電路122，閘極驅動單元121與時脈控制單元11以及削角電路122電性耦接，閘極驅動單元121是用以接收上述之時脈訊號CLK，並根據時脈訊號CLK產生對應 於每列畫素單元141的閘極驅動訊號，如圖1A所示之G1、G1…Gn，削角電路122與時脈控制單元11以及閘極驅動單元121電性耦接，削角電路122接收上述之時脈訊號CLK以及閘極驅動訊號G1…Gn，並根據時脈訊號CLK對接收的閘極驅動訊號G1…Gn進行削角而產生對應的削角閘極驅動訊號GOUT1…GOUTn，如圖1A所示，削角電路122並將削角後的削角閘極驅動訊號GOUT1…GOUTn傳送至對應列的畫素單元141，使接收到對應的削角閘極驅動訊號GOUT1…GOUTn的畫素單元141可據以開啟並顯示所接收的顯示資料。 Referring to FIG. 1A, FIG. 1A shows a first embodiment of a liquid crystal display device 10 of the present invention. The liquid crystal display device 10 includes a clock control unit 11, a gate driving module 12, a data driving unit 13, and a display unit 14. The clock control unit 11 is electrically coupled to the gate driving module 12 and the data driving unit 13. The clock control unit 11 is configured to generate the clock signal CLK and the data driving signal STB. The data driving unit 13 is electrically coupled to the clock control unit 11 for receiving the data driving signal STB and outputting the display data according to the data driving signal STB to the display unit 14 electrically coupled. The display unit 14 includes a plurality of pixel units 141. Each of the pixel units 141 is electrically coupled to the data driving unit 13 and the gate driving module 12, and each of the pixel units 141 is configured according to the gate driving module. The 12-output chamfered gate drive signal G OUT determines whether or not the display material received by the data driving unit 13 is displayed. The gate driving unit 12 includes a gate driving unit 121 and a chamfering circuit 122. The gate driving unit 121 is electrically coupled to the clock control unit 11 and the chamfering circuit 122. The gate driving unit 121 is configured to receive the above. The clock signal CLK generates a gate driving signal corresponding to each column of pixels 141 according to the clock signal CLK, as shown in FIG. 1A, G 1 , G 1 ... Gn, the chamfering circuit 122 and the clock control unit 11 and a driving unit 121 is electrically gate coupled chamfered circuit 122 receives the above-described of the clock signal CLK and the gate drive signals G 1 ... Gn, and for the gate drive signal G received 1 ... Gn according to the clock signal CLK The chamfered corners generate corresponding chamfered gate drive signals G OUT1 ... G OUTn , as shown in FIG. 1A, the chamfering circuit 122 transmits the chamfered gate drive signals G OUT1 ... G OUTn to the corresponding columns. The pixel unit 141 enables the pixel unit 141 that receives the corresponding chamfered gate drive signals G OUT1 ... G OUTn to turn on and display the received display material.

接著請參考圖1B，圖1B為上述之時脈訊號CLK、資料驅動訊號STB、閘極驅動訊號G1…Gn以及削角閘極驅動訊號GOUT1…GOUTn之時序示意圖，在此實施例中閘極驅動訊號G1…Gn以閘極驅動訊號G1以及閘極驅動訊號G2為例，削角閘極驅動訊號GOUT1…GOUTn以削角閘極驅動訊號GOUT1以及削角閘極驅動訊號GOUT2為例。以下先以閘極驅動訊號G1以及削角閘極驅動訊號GOUT1為例說明各訊號間之時序關係。時脈訊號CLK、資料驅動訊號STB、閘極驅動訊號G1、以及削角閘極驅動訊號GOUT皆具有一第一型態觸發緣以及一第二型態觸發緣，第一型態觸發緣可以為上升緣或下降緣其中之一，第二型態觸發緣可以為上升緣或下降緣其中之另一，閘極驅動訊號G1以及削角閘極驅動訊號GOUT1的第一型態觸發緣以及第二型態觸發緣具有大致相同的致能時間，時脈訊號CLK之第一型態觸發緣與閘極驅動訊號G1以及削角閘極驅動訊號GOUT1的第一型態觸發緣具有大致相同的致能時間，時脈訊號CLK之第二型態觸發緣則早於閘極驅動訊號G1以及削角閘極驅動訊號GOUT1，資料驅動訊號STB的第一型態觸發緣與時脈訊號CLK、閘極驅動訊號G1以及削角閘極驅動訊號GOUT1的第一型態觸發緣具有相同的致能時間，資 料驅動訊號STB的第二型態觸發緣之致能時間則早於時脈訊號CLK、閘極驅動訊號G1以及削角閘極驅動訊號GOUT1的第二型態觸發緣。 Referring to FIG. 1B, FIG. 1B is a timing diagram of the clock signal CLK, the data driving signal STB, the gate driving signals G 1 ... Gn, and the chamfered gate driving signals G OUT1 ... G OUTn . In this embodiment, The gate drive signals G 1 ... Gn take the gate drive signal G 1 and the gate drive signal G 2 as an example. The chamfered gate drive signals G OUT1 ... G OUTn are used as the chamfered gate drive signal G OUT1 and the chamfered gate The drive signal G OUT2 is taken as an example. Hereinafter, the timing relationship between the signals will be described by taking the gate driving signal G 1 and the chamfering gate driving signal G OUT1 as an example. The clock signal CLK, the data driving signal STB, the gate driving signal G 1 , and the chamfered gate driving signal G OUT both have a first type trigger edge and a second type trigger edge, and the first type trigger edge It may be one of a rising edge or a falling edge, and the second type triggering edge may be the other of the rising edge or the falling edge, and the first type trigger of the gate driving signal G 1 and the chamfering gate driving signal G OUT1 The edge and the second type trigger edge have substantially the same enable time, the first type trigger edge of the clock signal CLK and the gate drive signal G 1 and the first type trigger edge of the chamfer gate drive signal G OUT1 Having substantially the same enable time, the second type trigger edge of the clock signal CLK is earlier than the gate drive signal G 1 and the chamfered gate drive signal G OUT1 , and the first type trigger edge of the data drive signal STB The first type triggering edge of the clock signal CLK, the gate driving signal G 1 and the chamfering gate driving signal G OUT1 have the same enabling time, and the enabling time of the second type triggering edge of the data driving signal STB is Earlier than the clock signal CLK, gate drive signal G 1 And a second type of trigger edge of the chamfered gate drive signal G OUT1 .

接著以下將配合圖1A以及圖1B來說明本發明之液晶顯示裝置10實施例1之運作方法。首先在時段T，閘極驅動單元121接收時脈訊號CLK並開始據以輸出閘極驅動訊號G1，而與閘極驅動訊號G1對應之資料驅動訊號STB1之第二型態觸發緣則晚於閘極驅動訊號G1第一型態觸發緣的時間被致能，資料驅動單元13再根據資料驅動訊號STB1之第二型態觸發緣輸出顯示資料至畫素單元141中。此外，削角電路122接收時脈訊號CLK以及閘極驅動訊號G1。由圖1B中可以看出，於時段T1中，削角電路122在時脈訊號CLK為一低電壓準位(例如為邏輯低電位)時，利用時脈訊號CLK的低電壓準位將閘極驅動訊號G1進行削角以產生削角閘極驅動訊號GOUT1，並將削角閘極驅動訊號GOUT1傳送至對應之畫素單元141。其中，以削角閘極驅動訊號GOUT2為例，當削角閘極驅動訊號GOUT2之第一型態觸發緣被致能時，對應削角閘極驅動訊號GOUT2之資料驅動訊號STB2之第一型態觸發緣也同時被致能，但資料驅動訊號STB2之第二型態觸發緣尚未被致能，然資料驅動單元13是根據資料驅動訊號STB之第二型態觸發緣致動以將顯示資料傳送至電性耦接之畫素單元141，也就是說，在資料驅動訊號STB2之第一型態觸發緣被致能但第二型態觸發緣尚未被致能的區間，也就是圖1B的時段T2時，被削角閘極驅動訊號GOUT2致能之畫素單元141是接收被削角閘極驅動訊號GOUT1致能之畫素單元141所接收之顯示資料，也就是上一列畫素單元141所接收的顯示資料，雖在此區間內被削角閘極驅動訊號GOUT2致能之畫素單元141接收了上一列畫素單元141的顯示資料，然在資料驅動訊號STB2之第二 型態觸發緣被致能時，正確的顯示資料可立即覆蓋畫素單元141先前所接收之顯示資料，因此被削角閘極驅動訊號GOUT2致能之畫素單元141仍可快速的正常顯示應顯示的資料。 Next, a method of operating the first embodiment of the liquid crystal display device 10 of the present invention will be described below with reference to FIGS. 1A and 1B. First, in the time period T, the gate driving unit 121 receives the clock signal CLK and starts to output the gate driving signal G 1 , and the second type triggering edge of the data driving signal STB1 corresponding to the gate driving signal G 1 is late. The time of the first type trigger edge of the gate driving signal G 1 is enabled, and the data driving unit 13 outputs the display data to the pixel unit 141 according to the second type trigger edge of the data driving signal STB1. In addition, the chamfering circuit 122 receives the clock signal CLK and the gate driving signal G 1 . As can be seen in FIG. 1B, in the period T 1, the chamfered circuit 122 when the clock signal CLK (e.g., logic low) is a low voltage level, when using low voltage level of the gate clock signal CLK The pole drive signal G 1 is chamfered to generate a chamfered gate drive signal G OUT1 , and the chamfered gate drive signal G OUT1 is transmitted to the corresponding pixel unit 141. Wherein chamfered to gate drive signal G OUT2 as an example, when the chamfering patterns for a first gate drive signal G OUT2 of the edge trigger is enabled, the corresponding chamfered gate drive signal G OUT2 of the data driving signal STB2 The first type trigger edge is also enabled at the same time, but the second type trigger edge of the data driving signal STB2 has not been enabled, and the data driving unit 13 is activated according to the second type trigger edge of the data driving signal STB. The display data is transmitted to the electrically coupled pixel unit 141, that is, the interval in which the first type trigger edge of the data driving signal STB2 is enabled but the second type trigger edge is not enabled, that is, During the time period T 2 of FIG. 1B, the pixel unit 141 enabled by the chamfered gate drive signal G OUT2 receives the display data received by the pixel unit 141 enabled by the chamfered gate drive signal G OUT1 , that is, The display data received by the previous column of pixel units 141, although the pixel unit 141 enabled by the chamfered gate drive signal G OUT2 in this interval receives the display data of the previous column of pixel units 141, but the data drive signal When the second type of trigger edge of STB2 is enabled, Immediately correct the display data of pixel units cover the display data 141 previously received, the thus chamfered gate drive enable signal G OUT2 of the unit pixel 141 may still display the normal fast data to be displayed.

請參閱圖2A，圖2A為本發明之液晶顯示裝置10實施例2，圖2A與圖1A之差別在於，圖2A之削角電路122是用以接收時脈訊號CLK以及高電壓準位VGH(例如為邏輯高電位)，削角電路122並根據時脈訊號CLK對高電壓準位進行削角以產生削角高電壓準位VGHM，削角電路122再將削角高電壓準位VGHM傳送至閘極驅動單元121。圖2A之閘極驅動單元121是用以接收時脈訊號CLK以及削角高電壓準位VGHM，並根據時脈訊號CLK以及削角高電壓準位VGHM產生削角閘極驅動訊號GOUT1…GOUTn，閘極驅動單元121再將削角閘極驅動訊號GOUT1…GOUTn傳送至對應之畫素單元141，如圖2A所示。 2A, FIG. 2A is a second embodiment of the liquid crystal display device 10 of the present invention. The difference between FIG. 2A and FIG. 1A is that the chamfering circuit 122 of FIG. 2A is configured to receive the clock signal CLK and the high voltage level V GH . (for example, logic high), the chamfering circuit 122 chamfers the high voltage level according to the clock signal CLK to generate a chamfered high voltage level V GHM , and the chamfering circuit 122 further chamfers the high voltage level V The GHM is transmitted to the gate driving unit 121. The gate driving unit 121 of FIG. 2A is configured to receive the clock signal CLK and the chamfer high voltage level V GHM , and generate the chamfered gate driving signal G OUT1 according to the clock signal CLK and the chamfer high voltage level V GHM . ...G OUTn , the gate driving unit 121 transmits the chamfered gate driving signals G OUT1 ... G OUTn to the corresponding pixel units 141 as shown in FIG. 2A.

請參閱圖2B，圖2B為上述之時脈訊號CLK、資料驅動訊號STB、高電壓準位VGH、削角高電壓準位VGHM以及削角閘極驅動訊號GOUT1…GOUTn之時序示意圖，在此實施例中削角閘極驅動訊號GOUT1…GOUTn以削角閘極驅動訊號GOUT1以及削角閘極驅動訊號GOUT2為例。以下先以削角閘極驅動訊號GOUT1為例說明各訊號間之時序關係。時脈訊號CLK、資料驅動訊號STB以及削角閘極驅動訊號GOUT皆具有一第一型態觸發緣以及一第二型態觸發緣，時脈訊號CLK之第一型態觸發緣與削角閘極驅動訊號GOUT1的第一型態觸發緣具有相同的致能時間，時脈訊號CLK之第二型態觸發緣則早於削角閘極驅動訊號GOUT1之第二型態觸發緣，資料驅動訊號STB的第一型態觸發緣與時脈訊號CLK以及削角閘極驅動訊號GOUT1的第一型態觸發緣具有相同的致能時間，資料驅動訊號STB的第二型態觸發緣之致能時間則早於時脈訊號CLK 以及削角閘極驅動訊號GOUT1的第二型態觸發緣。 Please refer to FIG. 2B. FIG. 2B is a timing diagram of the clock signal CLK, the data driving signal STB, the high voltage level V GH , the chamfer high voltage level V GHM , and the chamfered gate driving signals G OUT1 ... G OUTn . In this embodiment, the chamfered gate drive signals G OUT1 ... G OUTn are exemplified by the chamfered gate drive signal G OUT1 and the chamfered gate drive signal G OUT2 . The following uses the chamfered gate drive signal G OUT1 as an example to illustrate the timing relationship between the signals. The clock signal CLK, the data driving signal STB, and the chamfered gate driving signal G OUT both have a first type trigger edge and a second type trigger edge, and the first type trigger edge and chamfer of the clock signal CLK The first type trigger edge of the gate drive signal G OUT1 has the same enable time, and the second type trigger edge of the clock signal CLK is earlier than the second type trigger edge of the chamfered gate drive signal G OUT1 . The first type triggering edge of the data driving signal STB has the same enabling time as the first type triggering edge of the clock signal CLK and the chamfering gate driving signal G OUT1 , and the second type triggering edge of the data driving signal STB The enable time is earlier than the second type trigger edge of the clock signal CLK and the chamfered gate drive signal G OUT1 .

接著以下將配合圖2A以及圖2B來說明本發明之液晶顯示裝置10實施例2之運作方法。首先在時段T，削角電路122接收時脈訊號CLK以及高電壓準位VGH，削角電路122並根據時脈訊號CLK對高電壓準位VGH進行削角，即圖2B時段T1，以時脈訊號CLK之低電壓準位對高電壓準位VGH進行削角以產生削角高電壓準位VGHM，閘極驅動單元121接收時脈訊號CLK以及削角高電壓準位VGHM並據以輸出削角閘極驅動訊號GOUT1，而與閘極驅動訊號G1對應之資料驅動訊號STB1之第二型態觸發緣晚於閘極驅動訊號G1第一型態觸發緣的時間被致能，資料驅動單元13根據資料驅動訊號STB1之第二型態觸發緣輸出顯示資料至畫素單元141中。其中，以削角閘極驅動訊號GOUT2為例，當削角閘極驅動訊號GOUT2之第一型態觸發緣被致能時，對應削角閘極驅動訊號GOUT2之資料驅動訊號STB2之第一型態觸發緣也同時被致能，但資料驅動訊號STB2之第二型態觸發緣尚未被致能，然資料驅動單元13是根據資料驅動訊號STB之第二型態觸發緣致動以將顯示資料傳送至電性耦接之畫素單元141，也就是說，在資料驅動訊號STB2之第一型態觸發緣被致能但第二型態觸發緣尚未被致能的區間，也就是圖2B的時段T2時，被削角閘極驅動訊號GOUT2致能之畫素單元141是接收被削角閘極驅動訊號GOUT1致能之畫素單元141所接收之顯示資料，雖在此時間內被削角閘極驅動訊號GOUT2致能之畫素單元141接收了上一列畫素單元141的顯示資料，然在資料驅動訊號STB2之第二型態觸發緣被致能時，正確的顯示資料可立即覆蓋畫素單元141先前所接收之顯示資料，因此被削角閘極驅動訊號GOUT2致能之畫素單元141仍可快速的正常顯示應顯示的資料。 Next, a method of operating the second embodiment of the liquid crystal display device 10 of the present invention will be described below with reference to FIGS. 2A and 2B. First, in the period T, chamfering the circuit 122 receives the clock signal CLK and a high voltage level V GH, chamfered circuit 122 and the clock signal CLK to a high voltage level V GH for chamfering according to that in FIG. 2B period T 1, The high voltage level V GH is chamfered by the low voltage level of the clock signal CLK to generate a chamfered high voltage level V GHM , and the gate driving unit 121 receives the clock signal CLK and the chamfer high voltage level V GHM time and outputting gate drive signals chamfered G OUT1, with the gate drive signals G 1 corresponding to the second data driving signals STB1 patterns of trigger edge triggered late in a first edge of the gate drive signals G type When enabled, the data driving unit 13 outputs the display data to the pixel unit 141 according to the second type trigger edge of the data driving signal STB1. Wherein chamfered to gate drive signal G OUT2 as an example, when the chamfering patterns for a first gate drive signal G OUT2 of the edge trigger is enabled, the corresponding chamfered gate drive signal G OUT2 of the data driving signal STB2 The first type trigger edge is also enabled at the same time, but the second type trigger edge of the data driving signal STB2 has not been enabled, and the data driving unit 13 is activated according to the second type trigger edge of the data driving signal STB. The display data is transmitted to the electrically coupled pixel unit 141, that is, the interval in which the first type trigger edge of the data driving signal STB2 is enabled but the second type trigger edge is not enabled, that is, In the period T 2 of FIG. 2B, the pixel unit 141 enabled by the chamfered gate driving signal G OUT2 is the display data received by the pixel unit 141 enabled by the chamfered gate driving signal G OUT1 , although The pixel unit 141 enabled by the chamfered gate drive signal G OUT2 receives the display data of the previous column of pixel units 141 during this time, and is correct when the second type trigger edge of the data drive signal STB2 is enabled. The display data can immediately cover the previous element of the pixel unit 141 The received display information is thus chamfered gate drive enable signal G OUT2 of the unit pixel 141 may still display the normal fast data to be displayed.

根據上述之內容，本發明更可匯整出液晶顯示裝置10之操作方法。請參閱圖3A以及圖1A，圖3A為液晶顯示裝置10實施例一之操作方法實施例，以下並以閘極驅動訊號G1以及削角閘極驅動訊號GOUT1為例來說明，其步驟包括：使閘極驅動單元121接收時脈訊號CLK並根據時脈訊號CLK輸出閘極驅動訊號G1(步驟301)；接著使削角電路122接收時脈訊號CLK以及閘極驅動訊號G1，並以時脈訊號CLK對閘極驅動訊號G1進行削角以輸出削角閘極驅動訊號GOUT1(步驟302)；使資料驅動單元13根據資料驅動訊號STB之第二型態觸發緣輸出多個顯示資料至多個畫素單元141(步驟303)；使畫素單元141接收顯示資料以及削角閘極驅動訊號GOUT1，畫素單元141因為削角閘極驅動訊號GOUT1而開啟，並顯示所接收的顯示資料(步驟304)。請參閱圖3B以及圖1B，圖3B為液晶顯示裝置10實施例二之操作方法實施例，其步驟包括：使削角電路122接收時脈訊號CLK以及高電壓準位VGH，並根據時脈訊號CLK對高電壓準位VGH進行削角以產生削角高電壓準位VGHM(步驟311)；使閘極驅動單元121接收時脈訊號CLK以及削角高電壓準位VGHM，並根據時脈訊號CLK以及削角高電壓準位VGHM產生削角閘極驅動訊號GOUT1(步驟312)；使資料驅動單元13根據資料驅動訊號STB之第二型態觸發緣輸出多個顯示資料至多個畫素單元141(步驟313)；使畫素單元141接收顯示資料以及削角閘極驅動訊號GOUT1，畫素單元141因為削角閘極驅動訊號GOUT1而開啟，並顯示所接收的顯示資料(步驟304)。 According to the above, the present invention can further integrate the operation method of the liquid crystal display device 10. Referring to FIG. 3A and FIG. 1A , FIG. 3A is an embodiment of an operation method of the first embodiment of the liquid crystal display device 10 . The following is an example of the gate driving signal G 1 and the chamfered gate driving signal G OUT1 . The steps include: The gate driving unit 121 receives the clock signal CLK and outputs the gate driving signal G 1 according to the clock signal CLK (step 301); then, the chamfering circuit 122 receives the clock signal CLK and the gate driving signal G 1 , and The gate driving signal G 1 is chamfered by the clock signal CLK to output the chamfered gate driving signal G OUT1 (step 302); and the data driving unit 13 outputs multiple signals according to the second type triggering edge of the data driving signal STB. The data is displayed to the plurality of pixel units 141 (step 303); the pixel unit 141 receives the display data and the chamfered gate driving signal G OUT1 , and the pixel unit 141 is turned on because of the chamfered gate driving signal G OUT1 , and displays The received display material (step 304). Referring to FIG. 3B and FIG. 1B, FIG. 3B is an embodiment of the operation method of the second embodiment of the liquid crystal display device 10. The step of the method includes: the chamfering circuit 122 receives the clock signal CLK and the high voltage level V GH according to the clock. The signal CLK chamfers the high voltage level V GH to generate the chamfered high voltage level V GHM (step 311); the gate driving unit 121 receives the clock signal CLK and the chamfer high voltage level V GHM , and according to The clock signal CLK and the chamfered high voltage level V GHM generate a chamfered gate driving signal G OUT1 (step 312); the data driving unit 13 outputs a plurality of display data according to the second type trigger edge of the data driving signal STB. The pixel unit 141 (step 313); the pixel unit 141 receives the display data and the chamfered gate driving signal G OUT1 , the pixel unit 141 is turned on by the chamfering gate driving signal G OUT1 , and displays the received display. Information (step 304).

綜以上所述，本發明因以時脈訊號CLK替代額外的外部削角訊號來進行削角，仍可有效避免錯充的情況發生，因此本發明明顯可有效降低元件走線區域以及元件數量，進而大幅減少整體能量以及成本的消耗。 In view of the above, the present invention can effectively avoid the occurrence of mis-charging by replacing the external chamfer signal with the clock signal CLK, so that the present invention can effectively reduce the component routing area and the number of components. In turn, the overall energy and cost consumption are greatly reduced.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可做些許之更動與潤飾，因此本發明之保護範圍當視後付之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

CLK‧‧‧時脈訊號 CLK‧‧‧ clock signal

STB、STB1、STB2‧‧‧資料驅動訊號 STB, STB1, STB2‧‧‧ data drive signals

GOUT、GOUT1‧‧‧削角閘極驅動訊號 G OUT , G OUT1 ‧‧‧ chamfered gate drive signal

G1、G2‧‧‧閘極驅動訊號 G 1 , G 2 ‧‧ ‧ gate drive signal

T、T1、T2‧‧‧時段 T, T 1 , T 2 ‧ ‧ hours

Claims (6)

一種液晶顯示裝置，其包括：一顯示單元，其具有多個畫素單元；一時脈控制單元，是用以產生一時脈訊號；以及一閘極驅動模組，與該時脈控制單元電性耦接，該閘極驅動模組用以根據該時脈訊號產生一削角閘極驅動訊號並傳送至對應的該些畫素單元，其中，該削角閘極驅動訊號是根據該時脈訊號進行削角；其中，該閘極驅動模組更包括：一閘極驅動單元，與該時脈控制單元電性耦接，該閘極驅動單元係用以根據該時脈訊號輸出一閘極驅動訊號；以及一削角電路，與該些畫素單元、該閘極驅動單元以及該時脈控制單元電性耦接，該削角電路係用以接收該閘極驅動訊號以及該時脈訊號並根據該時脈訊號對該閘極驅動訊號進行削角以產生該削角閘極驅動訊號，該削角電路並將該削角閘極驅動訊號傳送至對應的該些畫素單元。 A liquid crystal display device includes: a display unit having a plurality of pixel units; a clock control unit for generating a clock signal; and a gate driving module electrically coupled to the clock control unit The gate driving module generates a chamfered gate driving signal according to the clock signal and transmits the signal to the corresponding pixel unit, wherein the chamfering gate driving signal is performed according to the clock signal The gate driving module further includes: a gate driving unit electrically coupled to the clock control unit, wherein the gate driving unit is configured to output a gate driving signal according to the clock signal And a chamfering circuit electrically coupled to the pixel unit, the gate driving unit, and the clock control unit, the chamfering circuit is configured to receive the gate driving signal and the clock signal according to The clock signal chamfers the gate drive signal to generate the chamfered gate drive signal, and the chamfer circuit transmits the chamfered gate drive signal to the corresponding pixel units. 如請求項1所述之液晶顯示裝置，其中，該液晶顯示裝置更包括一資料驅動單元，該資料驅動單元是用以接收該時脈控制單元所產生的一資料驅動訊號(STB)，並根據該資料驅動訊號輸出一顯示資料至電性耦接之該些畫素單元。 The liquid crystal display device of claim 1, wherein the liquid crystal display device further comprises a data driving unit, wherein the data driving unit is configured to receive a data driving signal (STB) generated by the clock control unit, and according to The data driving signal outputs a display data to the pixel units electrically coupled. 如請求項2所述之液晶顯示裝置，其中，該時脈訊號、該削角閘極驅動訊號以及該資料驅動訊號皆具有 一第一型態觸發緣以及一第二型態觸發緣，該資料驅動訊號之該第二型態觸發緣晚於該時脈訊號以及該削角閘極驅動訊號之該第一型態觸發緣，該資料驅動訊號之該第二型態觸發緣早於該時脈訊號以及該削角閘極驅動訊號之該第二型態觸發緣。 The liquid crystal display device of claim 2, wherein the clock signal, the chamfered gate driving signal, and the data driving signal have a first type trigger edge and a second type trigger edge, the second type trigger edge of the data driving signal is later than the clock signal and the first type trigger edge of the chamfered gate driving signal The second type triggering edge of the data driving signal is earlier than the clock signal and the second type triggering edge of the chamfering gate driving signal. 一種液晶顯示裝置之操作方法，該液晶顯示裝置包括多個畫素單元、一時脈控制單元以及一閘極驅動模組，該時脈控制單元用以輸出一時脈訊號以及一資料驅動訊號，該閘極驅動模組更包括一閘極驅動單元以及一削角電路，使該閘極驅動模組接收該時脈訊號並據以產生一削角閘極驅動訊號，該液晶顯示裝置之操作方法包括以下步驟：使該閘極驅動單元接收該時脈訊號並據以輸出一閘極驅動訊號；使該削角電路接收該時脈訊號以及該閘極驅動訊號並以該時脈訊號對該閘極驅動訊號進行削角以輸出該削角閘極驅動訊號；以及使該些畫素單元接收該削角閘極驅動訊號；其中，該削角閘極驅動訊號是根據該時脈訊號進行削角。 A method of operating a liquid crystal display device includes a plurality of pixel units, a clock control unit, and a gate driving module, wherein the clock control unit outputs a clock signal and a data driving signal, the gate The pole drive module further includes a gate drive unit and a chamfering circuit, wherein the gate drive module receives the clock signal and generates a chamfered gate drive signal, and the operation method of the liquid crystal display device includes the following Step: the gate driving unit receives the clock signal and outputs a gate driving signal; the cornering circuit receives the clock signal and the gate driving signal, and drives the gate with the clock signal The signal is chamfered to output the chamfered gate drive signal; and the pixel unit receives the chamfered gate drive signal; wherein the chamfered gate drive signal is chamfered according to the clock signal. 如請求項4所述之液晶顯示裝置之操作方法，該液晶顯示裝置更包括了一資料驅動單元，該顯示面板之操作方法更包括以下步驟：使該資料驅動單元根據該資料驅動訊號輸出多個顯示資料至該些畫素單元。 The operating method of the liquid crystal display device of claim 4, further comprising a data driving unit, the operating method of the display panel further comprising the steps of: causing the data driving unit to output a plurality of signals according to the data driving signal Display data to the pixel units. 如請求項4所述之液晶顯示裝置之操作方法，其中， 該時脈訊號、該削角閘極驅動訊號以及該資料驅動訊號皆具有一第一型態觸發緣以及一第二型態觸發緣，該資料驅動訊號之該第二型態觸發緣晚於該時脈訊號以及該削角閘極驅動訊號之該第一型態觸發緣，該資料驅動訊號之該第二型態觸發緣早於該時脈訊號以及該削角閘極驅動訊號之該第二型態觸發緣。 The method of operating a liquid crystal display device according to claim 4, wherein The clock signal, the chamfered gate driving signal and the data driving signal both have a first type triggering edge and a second type triggering edge, and the second type triggering edge of the data driving signal is later than the The first signal triggering edge of the clock signal and the chamfered gate driving signal, the second type triggering edge of the data driving signal is earlier than the clock signal and the second of the chamfering gate driving signal Type trigger edge.
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