TWI555177B - One time programming memory and associated memory cell structure - Google Patents
One time programming memory and associated memory cell structure Download PDFInfo
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本發明是有關於一種記憶體，且特別是有關於一次編程記憶體及其相關記憶胞結構。 The present invention relates to a memory, and more particularly to a one-time programming memory and its associated memory cell structure.
眾所周知，非揮發性記憶體在斷電之後仍舊可以保存其資料內容。一般來說，當非揮發性記憶體製造完成並出廠後，使用者即可以編程(program)非揮發性記憶體，進而將資料記錄在非揮發性記憶體中。而根據編程的次數，非揮發性記憶體可進一步區分為多次編程記憶體(multi-time programming memory，簡稱MTP記憶體)，或者一次編程記憶體(one time programming memory，簡稱OTP記憶體)。 It is well known that non-volatile memory can still retain its data content after power failure. Generally, when the non-volatile memory is manufactured and shipped out, the user can program the non-volatile memory to record the data in the non-volatile memory. According to the number of programming, the non-volatile memory can be further divided into a multi-time programming memory (MTP memory) or a one-time programming memory (OTP memory).
基本上，使用者可以對MTP記憶體進行多次的儲存資料修改。相反地，使用者僅可以編程一次OTP記憶體。一旦OTP記憶體編程完成之後，其儲存資料將無法修改。 Basically, the user can perform multiple data modification on the MTP memory. Conversely, the user can only program the OTP memory once. Once the OTP memory is programmed, its stored data cannot be modified.
請參照第1A圖與第1B圖，其所繪示為OTP記憶體的記憶胞及其等效電路示意圖。第1A圖與第1B圖中包括二個記憶胞110、120，每個記憶胞110、120中具有二個電晶體，可稱為2T記憶胞。 Please refer to FIG. 1A and FIG. 1B , which are diagrams showing the memory cells of the OTP memory and their equivalent circuits. The first and second panels include two memory cells 110 and 120. Each of the memory cells 110 and 120 has two transistors, which may be referred to as 2T memory cells.
如圖第1A圖所示，利用淺溝渠隔離結構(STI)130將P型基板(P-sub)100區分為二個部分以定義出二個記憶胞110、120的區域。於第一記憶胞110中，二個N摻雜區域111、 112之間的P型基板100表面上具有第一閘極結構113，其包括一閘極氧化層(gate oxide)、多晶矽閘極(poly gate)以及間隙壁(spacer)。再者，N摻雜區域112與淺溝渠隔離結構(STI)130之間的P型基板100表面上具有第二閘極結構114。再者，N摻雜區域111連接至位元線BL0、第一閘極結構113連接至字元線WL0、第二閘極結構114連接至控制線CL0。 As shown in FIG. 1A, the P-substrate 100 (P-sub) 100 is divided into two portions by a shallow trench isolation structure (STI) 130 to define regions of the two memory cells 110, 120. In the first memory cell 110, two N-doped regions 111, The surface of the P-type substrate 100 between 112 has a first gate structure 113 including a gate oxide, a poly gate, and a spacer. Furthermore, a second gate structure 114 is formed on the surface of the P-type substrate 100 between the N-doped region 112 and the shallow trench isolation structure (STI) 130. Furthermore, the N-doped region 111 is connected to the bit line BL0, the first gate structure 113 is connected to the word line WL0, and the second gate structure 114 is connected to the control line CL0.
同理，於第二記憶胞120中，二個N摻雜區域121、122之間的P型基板100表面上具有第一閘極結構123。再者，N摻雜區域122與淺溝渠隔離結構(STI)130之間的P型基板100表面上具有第二閘極結構124。再者，N摻雜區域121連接至位元線BL1、第一閘極結構123連接至字元線WL1、第二閘極結構124連接至控制線CL1。 Similarly, in the second memory cell 120, the P-type substrate 100 between the two N-doped regions 121, 122 has a first gate structure 123 on its surface. Furthermore, a second gate structure 124 is formed on the surface of the P-type substrate 100 between the N-doped region 122 and the shallow trench isolation structure (STI) 130. Furthermore, the N-doped region 121 is connected to the bit line BL1, the first gate structure 123 is connected to the word line WL1, and the second gate structure 124 is connected to the control line CL1.
如第1B圖所示，第一記憶胞110中包括一開關電晶體T01以及一儲存電晶體T00，開關電晶體T01閘極連接至字元線WL0，其第一汲/源端(drain/source terminal)連接至位元線BL0；儲存電晶體T00閘極連接至控制線CL0，其第一汲/源端連接至開關電晶體T01的第二汲/源端，其第二汲/源端為浮接(floating)。 As shown in FIG. 1B, the first memory cell 110 includes a switching transistor T01 and a storage transistor T00. The gate of the switching transistor T01 is connected to the word line WL0, and the first port/source terminal (drain/source) Terminal) is connected to the bit line BL0; the storage transistor T00 gate is connected to the control line CL0, the first 源/source end is connected to the second 汲/source end of the switching transistor T01, and the second 汲/source end is Floating.
同理，第二記憶胞120中包括一開關電晶體T11以及一儲存電晶體T10，開關電晶體T11閘極連接至字元線WL1，其第一汲/源端連接至位元線BL1；儲存電晶體T10閘極連接至控制線CL1，其第一汲/源端連接至開關電晶體T11的第二汲/源端，其第二汲/源端為浮接。 Similarly, the second memory cell 120 includes a switching transistor T11 and a storage transistor T10. The gate of the switching transistor T11 is connected to the word line WL1, and the first 源/source terminal is connected to the bit line BL1; The gate of the transistor T10 is connected to the control line CL1, the first 源/source terminal of which is connected to the second 汲/source terminal of the switching transistor T11, and the second 汲/source terminal thereof is floating.
舉例來說，於編程第一記憶胞110時，提供0V至位元線BL0、3.3V至字元線WL0、6.5V至控制線CL0。則開關電晶體T01導通(turn on)，並造成儲存電晶體T00的閘極氧化層被破壞，使得儲存電晶體T00的閘極與第一汲/源端之間呈現短路的低電阻的特性。因此，第一記憶胞110可視為一第一儲存狀態。 For example, when programming the first memory cell 110, 0V to bit line BL0, 3.3V to word line WL0, 6.5V are supplied to the control line CL0. Then, the switching transistor T01 turns on, and causes the gate oxide layer of the storage transistor T00 to be destroyed, so that the gate of the storage transistor T00 and the first 汲/source terminal exhibit a short-circuit low resistance characteristic. Therefore, the first memory cell 110 can be regarded as a first storage state.
另外，於編程第二記憶胞120時，提供0V至位元 線BL1、3.3V至字元線WL1、0V至控制線CL1。則開關電晶體T11導通(turn on)，而儲存電晶體T10的閘極氧化層不會被破壞，使得儲存電晶體T10的閘極與第一汲/源端之間呈現開路的高電阻的特性。因此，第二記憶胞120可視為一第二儲存狀態。 In addition, when programming the second memory cell 120, 0V to bit is provided. Lines BL1, 3.3V to word lines WL1, 0V to control line CL1. Then, the switching transistor T11 is turned on, and the gate oxide layer of the storage transistor T10 is not destroyed, so that the gate of the storage transistor T10 and the first 汲/source end exhibit an open circuit with high resistance. . Therefore, the second memory cell 120 can be regarded as a second storage state.
請參照第1C圖，其所繪示為習知OTP記憶體編程後的記憶胞等效電路示意圖。經由上述的方式編程後，第一記憶胞110中的儲存電晶體T00可等效為一電阻，其具有低電阻的特性，可視為第一儲存狀態。而第二記憶胞120中的儲存電晶體T10可等效為一電容，其具有高電阻的特性，可視為第二儲存狀態。 Please refer to FIG. 1C, which is a schematic diagram of a memory cell equivalent circuit after programming the conventional OTP memory. After being programmed in the above manner, the storage transistor T00 in the first memory cell 110 can be equivalent to a resistor having a low resistance characteristic, which can be regarded as the first storage state. The storage transistor T10 in the second memory cell 120 can be equivalent to a capacitor having a high resistance characteristic and can be regarded as a second storage state.
請參照第2A圖與第2B圖，其所繪示為另一OTP記憶體的記憶胞及其等效電路示意圖。第2A圖與第2B圖中包括二個記憶胞210、220，每個記憶胞210、220中具有一個電晶體，可稱為1T記憶胞。 Please refer to FIG. 2A and FIG. 2B , which are diagrams showing the memory cells of another OTP memory and their equivalent circuits. 2A and 2B include two memory cells 210, 220, each having a transistor in the memory cells 210, 220, which may be referred to as a 1T memory cell.
如第2A圖所示，利用淺溝渠隔離結構(STI)230將P型基板(P-sub)200區分為二個部分以定義出二個記憶胞210、220的區域。於第一記憶胞210中，N摻雜區域212與淺溝渠隔離結構230之間的P型基板200表面上形成第一閘極結構214。再者，N摻雜區域212連接至位元線BL0、第一閘極結構214連接至字元線WL0。 As shown in FIG. 2A, the P-substrate 200 (P-sub) 200 is divided into two portions by a shallow trench isolation structure (STI) 230 to define regions of the two memory cells 210, 220. In the first memory cell 210, a first gate structure 214 is formed on the surface of the P-type substrate 200 between the N-doped region 212 and the shallow trench isolation structure 230. Furthermore, the N-doped region 212 is connected to the bit line BL0, and the first gate structure 214 is connected to the word line WL0.
同理，於第二記憶胞220中，N摻雜區域222與淺溝渠隔離結構230之間的P型基板200表面上形成第二閘極結構224。再者，N摻雜區域222連接至位元線BL1、第二閘極結構224連接至字元線WL1。 Similarly, in the second memory cell 220, a second gate structure 224 is formed on the surface of the P-type substrate 200 between the N-doped region 222 and the shallow trench isolation structure 230. Furthermore, the N-doped region 222 is connected to the bit line BL1 and the second gate structure 224 is connected to the word line WL1.
由第2A圖可知，第一閘極結構214與第二閘極結構224皆包括一閘極氧化層、多晶矽閘極以及間隙壁。其中，閘極氧化層被區分為二個部分，靠近N摻雜區域222的第一部分閘極氧化層的厚度較厚，靠近淺溝渠隔離結構230的第二部分閘極氧化層的厚度較薄。 As can be seen from FIG. 2A, the first gate structure 214 and the second gate structure 224 each include a gate oxide layer, a polysilicon gate, and a spacer. Wherein, the gate oxide layer is divided into two parts, the first portion of the gate oxide layer near the N-doped region 222 has a thicker thickness, and the second portion of the gate oxide layer near the shallow trench isolation structure 230 has a thinner thickness.
如第2B圖所示，第一記憶胞210中的電晶體可等 效為一子開關電晶體T01與一子儲存電晶體T00，子開關電晶體T01的閘極連接至字元線WL0，其第一汲/源端連接至位元線BL0；子儲存電晶體T00閘極連接至字元線WL0，其第一汲/源端連接至子開關電晶體T01的第二汲/源端，其第二汲/源端為浮接。 As shown in FIG. 2B, the transistors in the first memory cell 210 can wait for The effect is a sub-switching transistor T01 and a sub-storage transistor T00, the gate of the sub-switching transistor T01 is connected to the word line WL0, the first 源/source end is connected to the bit line BL0; the sub-storage transistor T00 The gate is connected to the word line WL0, and the first 源/source terminal is connected to the second 汲/source terminal of the sub-switch transistor T01, and the second 汲/source terminal is floating.
同理，第二記憶胞220中的電晶體可效為一子開關電晶體T11與一子儲存電晶體T10，子開關電晶體T11的閘極連接至字元線WL1，其第一汲/源端連接至位元線BL1；子儲存電晶體T10閘極連接至字元線WL1，其第一汲/源端連接至子開關電晶體T11的第二汲/源端，其第二汲/源端為浮接。 Similarly, the transistor in the second memory cell 220 can be implemented as a sub-switching transistor T11 and a sub-storage transistor T10, and the gate of the sub-switching transistor T11 is connected to the word line WL1, the first source/source thereof. The terminal is connected to the bit line BL1; the gate of the sub-storage transistor T10 is connected to the word line WL1, and the first 源/source terminal is connected to the second 汲/source terminal of the sub-switch transistor T11, and the second 汲/source thereof The end is floating.
舉例來說，於編程第一記憶胞210時，提供0V至位元線BL0、5V至字元線WL0。則子開關電晶體T01導通(turn on)，並造成子儲存電晶體T00中較薄的閘極氧化層被破壞，使得子儲存電晶體T00的閘極與第一汲/源端之間呈現短路的低電阻的特性。因此，第一記憶胞210可視為一第一儲存狀態。 For example, when programming the first memory cell 210, 0V to bit lines BL0, 5V are supplied to the word line WL0. Then, the sub-switch transistor T01 turns on, and causes the thin gate oxide layer in the sub-storage transistor T00 to be destroyed, so that the gate of the sub-storage transistor T00 and the first 汲/source terminal are short-circuited. Low resistance characteristics. Therefore, the first memory cell 210 can be regarded as a first storage state.
另外，於編程第二記憶胞220時，提供0V至位元線BL1、3.3V至字元線WL1。則子開關電晶體T11導通(turn on)，而子儲存電晶體T10中較薄的閘極氧化層亦不會被破壞，使得子儲存電晶體T10的閘極與第一汲/源端之間呈現開路的高電阻的特性。因此，第二記憶胞220可視為一第二儲存狀態。 In addition, when the second memory cell 220 is programmed, 0V to bit lines BL1, 3.3V are supplied to the word line WL1. Then, the sub-switching transistor T11 is turned on, and the thin gate oxide layer in the sub-storage transistor T10 is not destroyed, so that the gate of the sub-storage transistor T10 is present between the gate and the first source/source. The high resistance of the open circuit. Therefore, the second memory cell 220 can be regarded as a second storage state.
請參照第2C圖，其所繪示為習知OTP記憶體編程後的記憶胞等效電路示意圖。經由上述的方式編程後，第一記憶胞210中的子儲存電晶體T00可等效為一電阻，其具有低電阻的特性，可視為第一儲存狀態。而第二記憶胞220中的子儲存電晶體T10可等效為一電容，其具有高電阻的特性，可視為第二儲存狀態。 Please refer to FIG. 2C, which is a schematic diagram of a memory cell equivalent circuit after programming the conventional OTP memory. After being programmed in the above manner, the sub-storage transistor T00 in the first memory cell 210 can be equivalent to a resistor having a low resistance characteristic, which can be regarded as the first storage state. The sub-storage transistor T10 in the second memory cell 220 can be equivalent to a capacitor having a high resistance characteristic and can be regarded as a second storage state.
眾所周知，淺溝渠隔離結構(STI)是用來隔絕二個電晶體，使得二個電晶體之間不會形成通道(channel)而產生漏電並互相影響。 It is well known that a shallow trench isolation structure (STI) is used to isolate two transistors so that no channels are formed between the two transistors to cause leakage and mutual influence.
換句話說，將淺溝渠隔離結構運用在OTP記憶體係 用來防止二記憶胞之間形成N型摻雜區，避免於記憶胞編程時產生漏電至相鄰的記憶胞而造成編程失敗。 In other words, the shallow trench isolation structure is applied to the OTP memory system. It is used to prevent the formation of N-type doping regions between the two memory cells, thereby avoiding leakage of electricity to adjacent memory cells during memory cell programming and causing programming failure.
再者，在記憶胞中，儲存電晶體的閘極結構需要覆蓋在淺溝渠隔離結構上。而為了防止對準偏差(misalignment)，在記憶胞的製作過程，需要提供一些保留區域(margin)。所以記憶胞的尺寸會較大。 Furthermore, in the memory cell, the gate structure of the storage transistor needs to be covered on the shallow trench isolation structure. In order to prevent misalignment, it is necessary to provide some margins in the process of making the memory cells. Therefore, the size of the memory cell will be larger.
另一方面，由於淺溝渠隔離結構的尺寸非常大，也會使得記憶胞之間的距離變大。因此，習知OTP記憶體的尺寸無法進一步的縮小。 On the other hand, since the size of the shallow trench isolation structure is very large, the distance between the memory cells is also increased. Therefore, the size of the conventional OTP memory cannot be further reduced.
本發明的目的係提出一種一次編程記憶體，其記憶胞之間並無淺溝渠隔離結構。用以縮小記憶胞之間的距離，並且有效地縮小OTP記憶體的尺寸。 The object of the present invention is to provide a one-time programming memory in which there is no shallow trench isolation structure between the memory cells. It is used to reduce the distance between memory cells and effectively reduce the size of OTP memory.
本發明係為一種一次編程記憶體，包括：一第一型區域，該第一型區域的一表面有一第一第二型摻雜區域、一第二第二型摻雜區域、一第三第二型摻雜區域與一第四第二型摻雜區域；一第一閘極結構，形成於該第一第二型摻雜區域與該第二第二型摻雜區域之間的該表面上方；一第二閘極結構；一第三閘極結構，形成於該第三第二型摻雜區域與該第四第二型摻雜區域之間的該表面上方；一第四閘極結構；其中該第二閘極結構與該第四閘極結構形成於該第二第二型摻雜區域與該第四第二型摻雜區域之間的該表面上方；其中，該第一型區域、該第一第二型摻雜區域、該第二第二型摻雜區域與該第一閘極結構形成一第一記憶胞中的一第一開關電晶體；該第一型區域、該第二第二型摻雜區域與該第二閘極結構形成該第一記憶胞中的一第一儲存電晶體；該第一型區域、該第三第二型摻雜區域、該第四第二型摻雜區域與該第三閘極結構形成一第二記憶胞中的一第二開關電晶體；該第一型區域、該第四第二型摻雜區域與該第四閘極結構形 成該第二記憶胞中的一第二儲存電晶體；以及其中，該第二第二型摻雜區域與該第四第二型摻雜區域之間的該表面下方為一第一型半導體。 The present invention is a one-time programming memory comprising: a first type region, a surface of the first type region having a first second type doped region, a second second type doped region, and a third portion a doped region and a fourth doped region; a first gate structure formed over the surface between the first doped region and the second doped region a second gate structure; a third gate structure formed over the surface between the third second type doped region and the fourth second type doped region; a fourth gate structure; The second gate structure and the fourth gate structure are formed over the surface between the second second type doped region and the fourth second type doped region; wherein the first type region, The first second type doping region, the second second type doping region and the first gate structure form a first switching transistor in a first memory cell; the first type region, the second portion The second type doping region and the second gate structure form a first storage transistor in the first memory cell; the first The region, the third second type doped region, the fourth second type doped region and the third gate structure form a second switching transistor in the second memory cell; the first type region, the first type region a fourth second type doped region and the fourth gate structure Forming a second storage transistor in the second memory cell; and wherein the surface between the second second type doped region and the fourth second type doped region is a first type semiconductor.
本發明係為一種一次編程記憶體，包括：一第一型區域，該第一型區域的一表面有一第一第二型摻雜區域與一第二第二型摻雜區域；一第一閘極結構，包括一第一閘極氧化層覆蓋於該表面上、一第一閘極覆蓋於該第一閘極氧化層上、與一第一間隙壁包圍該第一閘極氧化層與該第一閘極，其中該第一閘極氧化層包括一第一部分第一閘極氧化層與一第二部分第一閘極氧化層，且該第二部分第一閘極氧化層薄於該第一部分第一閘極氧化層；一第二閘極結構，包括一第二閘極氧化層覆蓋於該表面上、一第二閘極覆蓋於該第二閘極氧化層上、與一第二間隙壁包圍該第二閘極氧化層與該第二閘極，其中該第二閘極氧化層包括一第一部分第二閘極氧化層與一第二部分第二閘極氧化層，且該第二部分第二閘極氧化層薄於該第一部分第二閘極氧化層；其中該第一閘極結構與該第二閘極結構形成於該第一第二型摻雜區域與該第二第二型摻雜區域之間的該表面上方；其中，該第一型區域、該第一第二型摻雜區域、該第一部分第一閘極氧化層與該第一閘極形成一第一記憶胞中的一第一子開關電晶體；該第一型區域、該第二部分第一閘極氧化層與該第一閘極形成該第一記憶胞中的一第一子儲存電晶體；該第一型區域、該第二第二型摻雜區域、該第一部分第二閘極氧化層與該第二閘極形成一第二記憶胞中的一第二子開關電晶體；該第一型區域、該第二部分第二閘極氧化層與該第二閘極形成該第二記憶胞中的一第二子儲存電晶體；以及其中，該第一第二型摻雜區域與該第二第二型摻雜區域之間的該表面下方為一第一型半導體。 The present invention is a one-time programming memory comprising: a first type region, a surface of the first type region having a first second type doped region and a second second type doped region; a first gate The pole structure includes a first gate oxide layer covering the surface, a first gate covering the first gate oxide layer, and a first spacer surrounding the first gate oxide layer and the first gate a gate, wherein the first gate oxide layer comprises a first portion of the first gate oxide layer and a second portion of the first gate oxide layer, and the second portion of the first gate oxide layer is thinner than the first portion a first gate oxide layer; a second gate structure comprising a second gate oxide layer overlying the surface, a second gate overlying the second gate oxide layer, and a second spacer Surrounding the second gate oxide layer and the second gate, wherein the second gate oxide layer comprises a first portion of the second gate oxide layer and a second portion of the second gate oxide layer, and the second portion The second gate oxide layer is thinner than the first portion of the second gate oxide layer; wherein the first gate Forming the second gate structure over the surface between the first second type doping region and the second second type doping region; wherein the first type region, the first second type The doped region, the first portion of the first gate oxide layer and the first gate form a first sub-switch transistor in the first memory cell; the first type region, the second portion of the first gate is oxidized Forming a first sub-storage transistor in the first memory cell with the first gate; the first type region, the second second type doping region, the first portion of the second gate oxide layer and the The second gate forms a second sub-switch transistor in the second memory cell; the first type region, the second portion of the second gate oxide layer and the second gate form the second memory cell a second sub-storage transistor; and wherein the surface between the first second-type doped region and the second second-type doped region is a first type semiconductor.
本發明係為一種為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： The present invention is intended to provide a better understanding of the above and other aspects of the present invention.
100、200‧‧‧P型基板 100, 200‧‧‧P type substrate
110、120、210、220‧‧‧記憶胞 110, 120, 210, 220‧‧‧ memory cells
111、112、121、122、212、222‧‧‧N型摻雜區域 111, 112, 121, 122, 212, 222‧‧‧N-doped regions
113、114、123、124、214、224‧‧‧閘極結構 113, 114, 123, 124, 214, 224‧‧ ‧ gate structure
130、230‧‧‧淺溝渠隔離結構 130, 230‧‧‧ shallow trench isolation structure
300、400‧‧‧P型基板 300, 400‧‧‧P type substrate
310、320、392、390、410、420、460、480‧‧‧記憶胞 310, 320, 392, 390, 410, 420, 460, 480‧‧‧ memory cells
311、312、321、322、412、422‧‧‧N型摻雜區域 311, 312, 321, 322, 412, 422‧‧‧N-doped regions
365、366、375、376、462、482‧‧‧N型摻雜區域 365, 366, 375, 376, 462, 482‧‧‧N-doped regions
330、340、350、360、430、440‧‧‧閘極結構 330, 340, 350, 360, 430, 440‧‧ ‧ gate structure
367、371、377、381、470、490‧‧‧閘極結構 367, 371, 377, 381, 470, 490‧‧ ‧ gate structure
331、341、351、361、431、441‧‧‧閘極氧化層 331, 341, 351, 361, 431, 441‧‧ ‧ gate oxide layer
368、372、378、382、471、491‧‧‧閘極氧化層 368, 372, 378, 382, 471, 491‧‧ ‧ gate oxide layer
332、342、352、362、432、442‧‧‧多晶矽閘極 332, 342, 352, 362, 432, 442‧‧‧ polysilicon gates
369、373、379、383、472、492‧‧‧多晶矽閘極 369, 373, 379, 383, 472, 492‧‧‧ polycrystalline germanium gate
333、343、353、363、433、443‧‧‧間隙壁 333, 343, 353, 363, 433, 443‧‧ ‧ spacers
370、374、377、384、473、493‧‧‧間隙壁 370, 374, 377, 384, 473, 493 ‧ ‧ spacers
399、499‧‧‧P型重摻雜區域499 399, 499‧‧‧P type heavily doped area 499
431a、441a、471a、491a‧‧‧第一部分閘極氧化層 431a, 441a, 471a, 491a‧‧‧ the first part of the gate oxide layer
431b、441b、471b、491b‧‧‧第二部分閘極氧化層 431b, 441b, 471b, 491b‧‧‧ the second part of the gate oxide layer
第1A圖與第1B圖所繪示為OTP記憶體的記憶胞及其等效電路示意圖。 FIG. 1A and FIG. 1B are diagrams showing a memory cell of an OTP memory and an equivalent circuit thereof.
第1C圖所繪示為習知OTP記憶體編程後的記憶胞等效電路示意圖。 FIG. 1C is a schematic diagram of a memory cell equivalent circuit after programming the conventional OTP memory.
第2A圖與第2B圖所繪示為另一OTP記憶體的記憶胞及其等效電路示意圖。 2A and 2B are diagrams showing a memory cell of another OTP memory and an equivalent circuit thereof.
第2C圖所繪示為習知OTP記憶體編程後的記憶胞等效電路示意圖。 FIG. 2C is a schematic diagram of a memory cell equivalent circuit after programming the conventional OTP memory.
第3A圖所繪示為本發明OTP記憶體的記憶胞之第一實施例。 FIG. 3A illustrates a first embodiment of a memory cell of the OTP memory of the present invention.
第3B圖所繪示為第一實施例OTP記憶體編程後的記憶胞示意圖。 FIG. 3B is a schematic diagram of a memory cell after programming the OTP memory of the first embodiment.
第3C圖所繪示為本發明OTP記憶體的記憶胞第二實施例示意圖。 FIG. 3C is a schematic diagram showing a second embodiment of a memory cell of the OTP memory of the present invention.
第4A圖所繪示為本發明OTP記憶體的記憶胞之第三實施例。 Fig. 4A is a diagram showing a third embodiment of the memory cell of the OTP memory of the present invention.
第4B圖所繪示為第二實施例OTP記憶體編程後的記憶胞示意圖。 FIG. 4B is a schematic diagram of a memory cell after programming the OTP memory of the second embodiment.
第4C圖所繪示為本發明OTP記憶體的記憶胞第四實施例示意圖。 FIG. 4C is a schematic view showing a fourth embodiment of the memory cell of the OTP memory of the present invention.
請參照第3A圖，其所繪示為本發明OTP記憶體的記憶胞第一實施例示意圖。第3A圖中包括二個記憶胞310、320，每個記憶胞310、320中具有二個電晶體，可稱為2T記憶胞。 Please refer to FIG. 3A, which is a schematic diagram of a first embodiment of a memory cell of the OTP memory of the present invention. FIG. 3A includes two memory cells 310 and 320. Each of the memory cells 310 and 320 has two transistors, which may be referred to as 2T memory cells.
於第一記憶胞310中，二個N摻雜區域311、312 之間的P型基板300表面上具有第一閘極結構330，其包括閘極氧化層331、多晶矽閘極332以及間隙壁333。再者，於N摻雜區域312另一側的P型基板300表面上具有第二閘極結構340，其包括閘極氧化層341、多晶矽閘極342以及間隙壁343。再者，N摻雜區域311連接至位元線BL0、第一閘極結構330的多晶矽閘極332連接至字元線WL0、第二閘極結構340的多晶矽閘極342連接至控制線CL0。 In the first memory cell 310, two N-doped regions 311, 312 The surface of the P-type substrate 300 has a first gate structure 330 including a gate oxide layer 331, a polysilicon gate 332, and a spacer 333. Furthermore, a second gate structure 340 is formed on the surface of the P-type substrate 300 on the other side of the N-doped region 312, and includes a gate oxide layer 341, a polysilicon gate 342, and a spacer 343. Furthermore, the N-doped region 311 is connected to the bit line BL0, the polysilicon gate 332 of the first gate structure 330 is connected to the word line WL0, and the polysilicon gate 342 of the second gate structure 340 is connected to the control line CL0.
同理，於第二記憶胞320中，二個N摻雜區域321、322之間的P型基板300表面上具有第一閘極結構350，其包括閘極氧化層351、多晶矽閘極352以及間隙壁353。再者，於N摻雜區域322另一側的P型基板300表面上具有第二閘極結構360，其包括閘極氧化層361、多晶矽閘極362以及間隙壁363。再者，N摻雜區域321連接至位元線BL1、第一閘極結構350的多晶矽閘極352連接至字元線WL1、第二閘極結構360的多晶矽閘極362連接至控制線CL1。 Similarly, in the second memory cell 320, the surface of the P-type substrate 300 between the two N-doped regions 321, 322 has a first gate structure 350 including a gate oxide layer 351, a polysilicon gate 352, and Clearance wall 353. Furthermore, on the surface of the P-type substrate 300 on the other side of the N-doped region 322, there is a second gate structure 360 including a gate oxide layer 361, a polysilicon gate 362, and a spacer 363. Furthermore, the N-doped region 321 is connected to the bit line BL1, and the polysilicon gate 352 of the first gate structure 350 is connected to the word line WL1, and the polysilicon gate 362 of the second gate structure 360 is connected to the control line CL1.
第一記憶胞310中的P型基板300、二個N摻雜區域311、312以及第一閘極結構330形成一開關電晶體；P型基板300、N摻雜區域312以及第二閘極結構340形成一儲存電晶體。同理，第二記憶胞320中的P型基板300、二個N摻雜區域321、322以及第一閘極結構350形成一開關電晶體；P型基板300、N摻雜區域322以及第二閘極結構360係形成一儲存電晶體。 The P-type substrate 300, the two N-doped regions 311, 312, and the first gate structure 330 in the first memory cell 310 form a switching transistor; the P-type substrate 300, the N-doped region 312, and the second gate structure 340 forms a storage transistor. Similarly, the P-type substrate 300, the two N-doped regions 321, 322, and the first gate structure 350 in the second memory cell 320 form a switching transistor; the P-type substrate 300, the N-doped region 322, and the second The gate structure 360 forms a storage transistor.
再者，本發明OTP記憶體的記憶胞第一實施例之等效電路以及其動作原理相同於第1B圖與第1C圖，此處不再贅述。 Furthermore, the equivalent circuit of the first embodiment of the memory cell of the OTP memory of the present invention and the operation principle thereof are the same as those of FIG. 1B and FIG. 1C, and details are not described herein again.
根據本發明的第一實施例，本發明的二個記憶胞310、320之間並未形成其他的隔離結構用來隔離二記憶胞310、320。本發明的二個記憶胞之間310、320僅利用原來P型基板的P型半導體即可有效地隔離二個記憶胞310、320。因此，可以將儲存電晶體之閘極結構340、360製作的非常靠近，而二個記憶胞310、320之間也不會受到影響。 According to the first embodiment of the present invention, no other isolation structure is formed between the two memory cells 310, 320 of the present invention for isolating the two memory cells 310, 320. The two memory cells 310, 320 of the present invention can effectively isolate the two memory cells 310, 320 by using only the P-type semiconductor of the original P-type substrate. Therefore, the gate structures 340, 360 of the storage transistor can be made very close, and the two memory cells 310, 320 are not affected.
如第3A圖所示，於二個記憶胞310、320內，儲存電晶體中的閘極結構340、360製做的非常靠近，使得間隙壁343、363彼此重疊。根據本發明的第一實施例，只要儲存電晶體中的多晶矽閘極342、362未互相接觸，二個記憶胞310、320之間並不會受到影響。亦即，二個記憶胞310、320皆可順利的進行編程。 As shown in Fig. 3A, in the two memory cells 310, 320, the gate structures 340, 360 in the storage transistor are made very close together such that the spacers 343, 363 overlap each other. According to the first embodiment of the present invention, as long as the polysilicon gates 342, 362 in the storage transistor are not in contact with each other, the two memory cells 310, 320 are not affected. That is, both memory cells 310, 320 can be successfully programmed.
舉例來說，於編程第一記憶胞310時，提供0V至位元線BL0、3.3V至字元線WL0、6.5V至控制線CL0。則開關電晶體導通，並造成儲存電晶體的閘極氧化層341被破壞，使得儲存電晶體的多晶矽閘極342與N型參雜區312之間呈現短路的低電阻的特性。因此，第一記憶胞310可視為一第一儲存狀態。 For example, when programming the first memory cell 310, 0V to bit line BL0, 3.3V to word line WL0, 6.5V are supplied to the control line CL0. Then, the switching transistor is turned on, and the gate oxide layer 341 of the storage transistor is destroyed, so that the low-resistance characteristic of short-circuiting between the polysilicon gate 342 and the N-type doping region 312 of the storage transistor is exhibited. Therefore, the first memory cell 310 can be regarded as a first storage state.
由第3B圖可知，當開關電晶體導通時，N摻雜區域312的電壓約為0V且多晶矽閘極362的電壓約為6.5V。因此，最接近N摻雜區域312處的閘極氧化層341會被破壞，而呈現短路的低電阻的特性。因此，第一記憶胞310可視為第一儲存狀態。 As can be seen from FIG. 3B, when the switching transistor is turned on, the voltage of the N-doped region 312 is about 0 V and the voltage of the polysilicon gate 362 is about 6.5V. Therefore, the gate oxide layer 341 closest to the N-doped region 312 is destroyed, exhibiting a short-circuited low-resistance characteristic. Therefore, the first memory cell 310 can be regarded as the first storage state.
另外，於編程第二記憶胞320時，提供0V至位元線BL1、3.3V至字元線WL1、0V至控制線CL1。則開關電晶體導通，而儲存電晶體的閘極氧化層不會被破壞，使得儲存電晶體的閘極與第一汲/源端之間呈現開路的高電阻的特性。因此，第二記憶胞320可視為一第二儲存狀態。 In addition, when the second memory cell 320 is programmed, 0V to bit lines BL1, 3.3V are supplied to the word lines WL1, 0V to the control line CL1. Then, the switching transistor is turned on, and the gate oxide layer of the storage transistor is not destroyed, so that the gate of the storage transistor and the first 汲/source end exhibit an open circuit with high resistance. Therefore, the second memory cell 320 can be regarded as a second storage state.
由第3B圖可知，當開關電晶體導通時，N摻雜區域322的電壓約為0V且多晶矽閘極362的電壓約為0V。因此，閘極氧化層361將不會被破壞，而呈現短路的低電阻的特性。因此，第二記憶胞320可視為第二儲存狀態。 As can be seen from FIG. 3B, when the switching transistor is turned on, the voltage of the N-doped region 322 is about 0V and the voltage of the polysilicon gate 362 is about 0V. Therefore, the gate oxide layer 361 will not be destroyed, but exhibits a low resistance characteristic of a short circuit. Therefore, the second memory cell 320 can be regarded as the second storage state.
由以上的說明可知，本發明可以讓記憶胞310、320彼此非常的靠近，其距離可以小於二倍的間隙壁寬度。 As can be seen from the above description, the present invention allows the memory cells 310, 320 to be very close to each other with a distance less than twice the width of the spacer.
一般來說，間隙壁的寬度相關於閘極結構的寬度。假設閘極結構的寬度為100nm，則間隙壁的寬度大約為閘極結構寬度的0.25~1.5倍，亦即間隙壁的寬度在25nm~150nm之間。因 此，兩個間隙壁最大的寬度為300nm。換句話說，當第二閘極結構340與第二閘極結構360的寬度皆為100nm時，記憶胞310、320之間的距離會小於兩個間隙壁最大寬度(300nm)，或者小於三個閘極結構之寬度(300nm)。 In general, the width of the spacer is related to the width of the gate structure. Assuming that the width of the gate structure is 100 nm, the width of the spacer is approximately 0.25 to 1.5 times the width of the gate structure, that is, the width of the spacer is between 25 nm and 150 nm. because Thus, the maximum width of the two spacers is 300 nm. In other words, when the widths of the second gate structure 340 and the second gate structure 360 are both 100 nm, the distance between the memory cells 310, 320 may be less than the maximum width of the two spacers (300 nm), or less than three. The width of the gate structure (300 nm).
根據本發明的第一實施例，只要二個記憶胞310、320之間的材料係相同於P型基板300的P型半導體，即可有效地防止二個記憶胞310、320之間互相影響。因此，在不考量OTP記憶體的尺寸下，在二個記憶胞310、320之間距離大於二個間隙壁的寬度時，當然也可以有效地防止二個儲存電晶體之間形成通道(channel)而產生漏電並互相影響。 According to the first embodiment of the present invention, as long as the material between the two memory cells 310, 320 is the same as the P-type semiconductor of the P-type substrate 300, the mutual influence of the two memory cells 310, 320 can be effectively prevented. Therefore, when the distance between the two memory cells 310, 320 is greater than the width of the two spacers without considering the size of the OTP memory, it is of course possible to effectively prevent the formation of channels between the two storage transistors. The leakage occurs and affects each other.
請參照第請參照第3C圖，其所繪示為本發明OTP記憶體的記憶胞第二實施例示意圖。其中，每個記憶胞392、390中具有二個電晶體。 Please refer to FIG. 3C for a second embodiment, which is a schematic diagram of a second embodiment of a memory cell of the OTP memory of the present invention. There are two transistors in each of the memory cells 392 and 390.
於第一記憶胞392中，二個N摻雜區域365、366之間的P型基板395表面上具有第一閘極結構367，其包括閘極氧化層368、多晶矽閘極369以及間隙壁370。再者，於N摻雜區域366另一側的P型基板395表面上具有第二閘極結構371，其包括閘極氧化層372、多晶矽閘極373以及間隙壁374。再者，N摻雜區域365連接至位元線BL0、第一閘極結構367的多晶矽閘極369連接至字元線WL0、第二閘極結構371的多晶矽閘極373連接至控制線CL0。 In the first memory cell 392, the surface of the P-type substrate 395 between the two N-doped regions 365, 366 has a first gate structure 367 including a gate oxide layer 368, a polysilicon gate 369, and a spacer 370. . Furthermore, a second gate structure 371 is provided on the surface of the P-type substrate 395 on the other side of the N-doped region 366, which includes a gate oxide layer 372, a polysilicon gate 373, and a spacer 374. Furthermore, the N-doped region 365 is connected to the bit line BL0, the polysilicon gate 369 of the first gate structure 367 is connected to the word line WL0, and the polysilicon gate 373 of the second gate structure 371 is connected to the control line CL0.
同理，於第二記憶胞390中，二個N摻雜區域375、376之間的P型基板395表面上具有第一閘極結構377，其包括閘極氧化層378、多晶矽閘極379以及間隙壁380。再者，於N摻雜區域376另一側的P型基板395表面上具有第二閘極結構381，其包括閘極氧化層382、多晶矽閘極383以及間隙壁384。再者，N摻雜區域375連接至位元線BL1、第一閘極結構377的多晶矽閘極379連接至字元線WL1、第二閘極結構381的多晶矽閘極383連接至控制線CL1。 Similarly, in the second memory cell 390, the surface of the P-type substrate 395 between the two N-doped regions 375, 376 has a first gate structure 377 including a gate oxide layer 378, a polysilicon gate 379, and Clearance wall 380. Furthermore, a second gate structure 381 is formed on the surface of the P-type substrate 395 on the other side of the N-doped region 376, which includes a gate oxide layer 382, a polysilicon gate 383, and a spacer 384. Furthermore, the N-doped region 375 is connected to the bit line BL1, and the polysilicon gate 379 of the first gate structure 377 is connected to the word line WL1, and the polysilicon gate 383 of the second gate structure 381 is connected to the control line CL1.
第一記憶胞392中的P型基板395、二個N摻雜區域365、366以及第一閘極結構367形成一開關電晶體；P型基板395、N摻雜區域366以及第二閘極結構371形成一儲存電晶體。同理，第二記憶胞390中的P型基板395、二個N摻雜區域375、376以及第一閘極結構377形成一開關電晶體；P型基板395、N摻雜區域376以及第二閘極結構381係形成一儲存電晶體。 The P-type substrate 395, the two N-doped regions 365, 366 and the first gate structure 367 in the first memory cell 392 form a switching transistor; the P-type substrate 395, the N-doped region 366, and the second gate structure 371 forms a storage transistor. Similarly, the P-type substrate 395, the two N-doped regions 375, 376 and the first gate structure 377 in the second memory cell 390 form a switching transistor; the P-type substrate 395, the N-doped region 376, and the second The gate structure 381 forms a storage transistor.
根據本發明的第二實施例，二個記憶胞392、390中的第二閘極結構371、381之間的表面下方為一P型重摻雜(P+)區域399。其可更有效地防止二個記憶胞392、390之間互相影響。 In accordance with a second embodiment of the present invention, below the surface between the second gate structures 371, 381 of the two memory cells 392, 390 is a P-type heavily doped (P+) region 399. It can more effectively prevent the interaction between the two memory cells 392, 390.
請參照第4A圖，其所繪示為本發明OTP記憶體的記憶胞第三實施例示意圖。第4A圖中包括二個記憶胞410、420，每個記憶胞410、420中具有一個電晶體，可稱為1T記憶胞。 Please refer to FIG. 4A, which is a schematic diagram of a third embodiment of a memory cell of the OTP memory of the present invention. Figure 4A includes two memory cells 410, 420, each having a transistor in the memory cells 410, 420, which may be referred to as a 1T memory cell.
於二個N摻雜區域412、422之間的P型基板400表面上具有第一閘極結構430以及第二閘極結構440，分別屬於第一記憶胞410與第二記憶胞420。第一閘極結構430包括閘極氧化層431、多晶矽閘極432以及間隙壁433；第二閘極結構440包括閘極氧化層441、多晶矽閘極442以及間隙壁443。 The first gate structure 430 and the second gate structure 440 are disposed on the surface of the P-type substrate 400 between the two N-doped regions 412 and 422, and belong to the first memory cell 410 and the second memory cell 420, respectively. The first gate structure 430 includes a gate oxide layer 431, a polysilicon gate 432, and a spacer 433. The second gate structure 440 includes a gate oxide layer 441, a polysilicon gate 442, and a spacer 443.
再者，第一記憶胞410中，N摻雜區域412連接至位元線BL0、第一閘極結構430的多晶矽閘極432連接至字元線WL0；第二記憶胞420中，N摻雜區域422連接至位元線BL1、第二閘極結構440的多晶矽閘極442連接至字元線WL1。 Furthermore, in the first memory cell 410, the N-doped region 412 is connected to the bit line BL0, the polysilicon gate 432 of the first gate structure 430 is connected to the word line WL0, and the second memory cell 420 is N-doped. The region 422 is connected to the bit line BL1, and the polysilicon gate 442 of the second gate structure 440 is connected to the word line WL1.
根據本發明的第三實施例，第一閘極結構430的閘極氧化層431根據其厚度可區分為二個部分，第一部分的閘極氧化層431a較厚，第二部分的閘極氧化層431b較薄。再者，第二閘極結構440的閘極氧化層441根據其厚度可區分為二個部分，第一部分的閘極氧化層441a較厚，第二部分的閘極氧化層441b較薄。 According to the third embodiment of the present invention, the gate oxide layer 431 of the first gate structure 430 can be divided into two portions according to the thickness thereof, the gate oxide layer 431a of the first portion is thick, and the gate oxide layer of the second portion is The 431b is thinner. Furthermore, the gate oxide layer 441 of the second gate structure 440 can be divided into two portions according to the thickness thereof, the gate oxide layer 441a of the first portion is thicker, and the gate oxide layer 441b of the second portion is thinner.
因此，第一記憶胞410中的電晶體可區分為子開關電晶體以及子儲存電晶體。其中，P型基板400、N摻雜區域412、 第一部分閘極氧化層431a與多晶矽閘極432係形成子開關電晶體；P型基板400、第二部分閘極氧化層431b與多晶矽閘極432係形成子儲存電晶體。同理，第二記憶胞420中的電晶體區分為子開關電晶體以及子儲存電晶體。其中，P型基板400、N摻雜區域422、第一部分閘極氧化層441a與多晶矽閘極442係形成子開關電晶體；P型基板400、第二部分閘極氧化層441b與多晶矽閘極442係形成子儲存電晶體。 Therefore, the transistors in the first memory cell 410 can be distinguished as sub-switch transistors and sub-storage transistors. Wherein, the P-type substrate 400, the N-doped region 412, The first portion of the gate oxide layer 431a and the polysilicon gate 432 form a sub-switch transistor; the P-type substrate 400, the second portion of the gate oxide layer 431b and the polysilicon gate 432 form a sub-storage transistor. Similarly, the transistors in the second memory cell 420 are divided into sub-switch transistors and sub-storage transistors. The P-type substrate 400, the N-doped region 422, the first partial gate oxide layer 441a and the polysilicon gate 442 form a sub-switching transistor; the P-type substrate 400, the second partial gate oxide layer 441b and the polysilicon gate 442 The sub-storage transistor is formed.
再者，本發明OTP記憶體的記憶胞之等效電路以及其動作原理相同於第2B圖與第2C圖，此處不再贅述。 Furthermore, the equivalent circuit of the memory cell of the OTP memory of the present invention and the operation principle thereof are the same as those of the 2B and 2C drawings, and are not described herein again.
根據本發明的第三實施例，本發明的二個記憶胞410、420之間並未形成其他的隔離結構用來隔離二記憶胞410、420。本發明的二個記憶胞之間410、420僅利用原來P型基板的P型半導體即可有效地隔離二個記憶胞410、420。因此，可以二個記憶胞410、420內之閘極結構430、440製作的非常靠近，而二個記憶胞410、420之間也不會受到影響。 According to the third embodiment of the present invention, no other isolation structure is formed between the two memory cells 410, 420 of the present invention for isolating the two memory cells 410, 420. The two memory cells 410, 420 of the present invention can effectively isolate the two memory cells 410, 420 by using only the P-type semiconductor of the original P-type substrate. Therefore, the gate structures 430 and 440 in the two memory cells 410 and 420 can be made very close, and the two memory cells 410 and 420 are not affected.
如第4A圖所示，於二個記憶胞410、420內，閘極結構430、440製做的非常靠近，使得間隙壁433、443彼此重疊。根據本發明的第三實施例，只要儲存電晶體中的多晶矽閘極432、442未互相接觸，二個記憶胞410、420之間並不會受到影響。亦即，二個記憶胞440、460皆可順利的進行編程。 As shown in FIG. 4A, in the two memory cells 410, 420, the gate structures 430, 440 are made very close together such that the spacers 433, 443 overlap each other. According to the third embodiment of the present invention, as long as the polysilicon gates 432, 442 in the storage transistor are not in contact with each other, the two memory cells 410, 420 are not affected. That is, both memory cells 440, 460 can be successfully programmed.
舉例來說，於編程第一記憶胞410時，提供0V至位元線BL0、5V至字元線WL0。則子開關電晶體導通，並造成子儲存電晶體的第二部分閘極氧化層431b被破壞，使得子儲存電晶體的多晶矽閘極432與P型基板400之間呈現短路的低電阻的特性。因此，第一記憶胞410可視為第一儲存狀態。 For example, when programming the first memory cell 410, 0V to bit line BL0, 5V is supplied to the word line WL0. Then, the sub-switch transistor is turned on, and the second portion of the gate oxide layer 431b of the sub-storage transistor is destroyed, so that the low-resistance characteristic of the short-circuit between the polysilicon gate 432 of the sub-storage transistor and the P-type substrate 400 is exhibited. Therefore, the first memory cell 410 can be regarded as the first storage state.
由第4B圖可知，當子開關電晶體導通時，第一部分閘極氧化層431a下方的通道(channel)的電壓約為0V且多晶矽閘極432的電壓約為5V。因此，最接通道處的第二部分閘極氧化層431b會被破壞，而呈現短路的低電阻的特性。因此，第一記 憶胞410可視為第一儲存狀態。 As can be seen from FIG. 4B, when the sub-switch transistor is turned on, the voltage of the channel under the first portion of the gate oxide layer 431a is about 0V and the voltage of the polysilicon gate 432 is about 5V. Therefore, the second portion of the gate oxide layer 431b at the most connected channel is destroyed, exhibiting a short-circuited low resistance characteristic. Therefore, the first record The memory cell 410 can be regarded as the first storage state.
另外，於編程第二記憶胞420時，提供0V至位元線BL1、3.3V至字元線WL1。則子開關電晶體導通，而子儲存電晶體的第二部分閘極氧化層441b不會被破壞，使得子儲存電晶體的多晶矽閘極442與P型基板400之間呈現開路的高電阻的特性。因此，第二記憶胞420可視為一第二儲存狀態。 In addition, when the second memory cell 420 is programmed, 0V to bit lines BL1, 3.3V are supplied to the word line WL1. Then, the sub-switch transistor is turned on, and the second portion of the gate oxide layer 441b of the sub-storage transistor is not destroyed, so that the polysilicon gate 442 of the sub-storage transistor and the P-type substrate 400 exhibit an open-circuit high resistance characteristic. Therefore, the second memory cell 420 can be regarded as a second storage state.
由第4B圖可知，當子開關電晶體導通時，第一部分閘極氧化層441a下方的通道(channel)的電壓約為0V且多晶矽閘極442的電壓約為3.3V，尚在耐壓的範圍內。因此，第二部分閘極氧化層441b不會被破壞，而呈現開路的高電阻的特性。因此，第二記憶胞420可視為第二儲存狀態。 As can be seen from FIG. 4B, when the sub-switch transistor is turned on, the voltage of the channel under the first portion of the gate oxide layer 441a is about 0 V and the voltage of the polysilicon gate 442 is about 3.3 V, which is still in the range of withstand voltage. Inside. Therefore, the second portion of the gate oxide layer 441b is not broken, but exhibits an open-circuit high resistance characteristic. Therefore, the second memory cell 420 can be regarded as the second storage state.
由以上的說明可知，本發明可以讓記憶胞410、420彼此非常的靠近，其距離可以小於二倍的間隙壁寬度。 As can be seen from the above description, the present invention allows the memory cells 410, 420 to be very close to each other with a distance less than twice the spacer width.
一般來說，間隙壁的寬度相關於閘極結構的寬度。假設閘極結構的寬度為200nm，則間隙壁的寬度大約為閘極結構寬度的0.25~1.5倍，亦即間隙壁的寬度在50nm~300nm之間。因此，兩個間隙壁最大的寬度為600nm。換句話說，當第一閘極結構430與第二閘極結構440的寬度皆為200nm時，記憶胞410、420之間的距離會小於兩個間隙壁最大寬度(600nm)，或者小於三個閘極結構之寬度(300nm)。 In general, the width of the spacer is related to the width of the gate structure. Assuming that the width of the gate structure is 200 nm, the width of the spacer is approximately 0.25 to 1.5 times the width of the gate structure, that is, the width of the spacer is between 50 nm and 300 nm. Therefore, the maximum width of the two spacers is 600 nm. In other words, when the widths of the first gate structure 430 and the second gate structure 440 are both 200 nm, the distance between the memory cells 410, 420 is less than the maximum width of the two spacers (600 nm), or less than three. The width of the gate structure (300 nm).
根據本發明的第三實施例，只要二個記憶胞410、420之間的材料係相同於P型基板400的P型半導體，即可有效地防止二個記憶胞410、420之間互相影響。因此，在不考量OTP記憶體的尺寸下，在二個記憶胞410、420之間距離大於二個間隙壁的寬度時，當然也可以有效地防止二個儲存電晶體之間形成通道(channel)而產生漏電並互相影響。 According to the third embodiment of the present invention, as long as the material between the two memory cells 410, 420 is the same as the P-type semiconductor of the P-type substrate 400, the mutual influence of the two memory cells 410, 420 can be effectively prevented. Therefore, when the distance between the two memory cells 410 and 420 is greater than the width of the two spacers without considering the size of the OTP memory, it is of course possible to effectively prevent the formation of channels between the two storage transistors. The leakage occurs and affects each other.
請參照第4C圖，其所繪示為本發明OTP記憶體的記憶胞第四實施例示意圖。其中，每個記憶胞460、480中具有一個電晶體。 Please refer to FIG. 4C, which is a schematic diagram of a fourth embodiment of a memory cell of the OTP memory of the present invention. There is one transistor in each of the memory cells 460, 480.
於二個N摻雜區域462、482之間的P型基板495表面上具有第一閘極結構470以及第二閘極結構490，分別屬於第一記憶胞460與第二記憶胞480。第一閘極結構470包括閘極氧化層471、多晶矽閘極472以及間隙壁473；第二閘極結構490包括閘極氧化層491、多晶矽閘極492以及間隙壁493。 A first gate structure 470 and a second gate structure 490 are disposed on the surface of the P-type substrate 495 between the two N-doped regions 462, 482, respectively belonging to the first memory cell 460 and the second memory cell 480. The first gate structure 470 includes a gate oxide layer 471, a polysilicon gate 472, and a spacer 473. The second gate structure 490 includes a gate oxide layer 491, a polysilicon gate 492, and a spacer 493.
再者，第一記憶胞460中，N摻雜區域462連接至位元線BL0、第一閘極結構470的多晶矽閘極472連接至字元線WL0；第二記憶胞480中，N摻雜區域482連接至位元線BL1、第二閘極結構490的多晶矽閘極492連接至字元線WL1。 Furthermore, in the first memory cell 460, the N-doped region 462 is connected to the bit line BL0, the polysilicon gate 472 of the first gate structure 470 is connected to the word line WL0, and the second memory cell 480 is N-doped. The region 482 is connected to the bit line BL1, and the polysilicon gate 492 of the second gate structure 490 is connected to the word line WL1.
根據本發明的第四實施例，第一閘極結構470的閘極氧化層471根據其厚度可區分為二個部分，第一部分的閘極氧化層471a較厚，第二部分的閘極氧化層471b較薄。再者，第二閘極結構490的閘極氧化層491根據其厚度可區分為二個部分，第一部分的閘極氧化層491a較厚，第二部分的閘極氧化層491b較薄。 According to the fourth embodiment of the present invention, the gate oxide layer 471 of the first gate structure 470 can be divided into two portions according to the thickness thereof, the gate oxide layer 471a of the first portion is thick, and the gate oxide layer of the second portion is 471b is thinner. Furthermore, the gate oxide layer 491 of the second gate structure 490 can be divided into two portions according to the thickness thereof, the gate oxide layer 491a of the first portion is thicker, and the gate oxide layer 491b of the second portion is thinner.
因此，第一記憶胞460中的電晶體可區分為子開關電晶體以及子儲存電晶體。其中，P型基板495、N摻雜區域462、第一部分閘極氧化層471a與多晶矽閘極472係形成子開關電晶體；P型基板495、第二部分閘極氧化層471b與多晶矽閘極472係形成子儲存電晶體。同理，第二記憶胞480中的電晶體區分為子開關電晶體以及子儲存電晶體。其中，P型基板495、N摻雜區域482、第一部分閘極氧化層491a與多晶矽閘極492係形成子開關電晶體；P型基板495、第二部分閘極氧化層491b與多晶矽閘極492係形成子儲存電晶體。 Thus, the transistors in the first memory cell 460 can be distinguished as sub-switch transistors and sub-storage transistors. The P-type substrate 495, the N-doped region 462, the first portion of the gate oxide layer 471a and the polysilicon gate 472 form a sub-switch transistor; the P-type substrate 495, the second portion of the gate oxide layer 471b and the polysilicon gate 472 The sub-storage transistor is formed. Similarly, the transistors in the second memory cell 480 are divided into sub-switch transistors and sub-storage transistors. The P-type substrate 495, the N-doped region 482, the first portion of the gate oxide layer 491a and the polysilicon gate 492 form a sub-switch transistor; the P-type substrate 495, the second portion of the gate oxide layer 491b and the polysilicon gate 492 The sub-storage transistor is formed.
根據本發明的第四實施例，第一閘極結構470與第二閘極結構490之間的表面下方為一P型重摻雜(P+)區域499。其可更有效地防止二個記憶胞460、480之間互相影響。 In accordance with a fourth embodiment of the present invention, a P-type heavily doped (P+) region 499 is below the surface between the first gate structure 470 and the second gate structure 490. It can more effectively prevent the interaction between the two memory cells 460, 480.
由以上的說明可知，本發明細提出OTP記憶體及其相關記憶胞結構。在完全沒有淺溝渠隔離結構之下，將二記憶胞 製作的非常靠近，並且仍舊可以正常操作記憶胞。 As apparent from the above description, the present invention proposes an OTP memory and its associated memory cell structure. Two memory cells under no shallow trench isolation structure at all The production is very close, and the memory cells can still be operated normally.
再者，由於本發明OTP記憶體的記憶胞之間距離非常的短，可以有效的提高記憶胞的密度，增加OTP記憶體的容量。 Furthermore, since the distance between the memory cells of the OTP memory of the present invention is very short, the density of the memory cells can be effectively increased, and the capacity of the OTP memory can be increased.
再者，上述實施例中皆以P型基板以及N型摻雜區域所組成的N型電晶體來進行說明，在此領域的技術人員當然也可以利用N型基板以及P型摻雜區所形成的P型電晶體來實現本發明。再者，於實際的運用上，P型基板可以由P型井區域(P-well region)來取代，同樣也可以達到發明的成效。 Furthermore, in the above embodiments, the N-type transistor composed of the P-type substrate and the N-type doped region is described, and those skilled in the art can of course also form the N-type substrate and the P-type doped region. A P-type transistor is used to implement the invention. Furthermore, in practical applications, the P-type substrate can be replaced by a P-well region, and the effect of the invention can also be achieved.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
300‧‧‧P型基板 300‧‧‧P type substrate
310、320‧‧‧記憶胞 310, 320‧‧‧ memory cells
311、312、321、322‧‧‧N型摻雜區域 311, 312, 321, 322‧‧‧N-doped regions
330、340、350、360‧‧‧閘極結構 330, 340, 350, 360‧‧‧ gate structure
331、341、351、361‧‧‧閘極氧化層 331, 341, 351, 361‧‧ ‧ gate oxide layer
332、342、352、362‧‧‧多晶矽閘極 332, 342, 352, 362‧‧‧ polysilicon gate
333、343、353、363‧‧‧間隙壁 333, 343, 353, 363‧ ‧ spacers
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050062062A1 (en) * | 2003-06-09 | 2005-03-24 | Nantero, Inc. | One-time programmable, non-volatile field effect devices and methods of making same |
| US20060054952A1 (en) * | 2004-06-04 | 2006-03-16 | Stmicroelectronics Sa | One-time programmable memory device |
| TW200807694A (en) * | 2006-07-18 | 2008-02-01 | Ememory Technology Inc | Semiconductor capacitor, one time programmable memory cell and fabricating method and operating method thereof |
| TW200814305A (en) * | 2006-09-07 | 2008-03-16 | Alpha & Omega Semiconductor | New configuration and method of manufacturing the one-time programmable (OTP) memory cells |
| TW201310579A (en) * | 2011-08-16 | 2013-03-01 | Maxchip Electronics Corp | Semiconductor structure and method of forming the same |
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| KR100517560B1 (en) * | 2003-07-14 | 2005-09-28 | 삼성전자주식회사 | Eeprom device having selection transistors and method of fabricating the same |
| KR100784870B1 (en) * | 2006-07-14 | 2007-12-14 | 삼성전자주식회사 | Eeprom device and method of fabricating the same |
| US8502348B2 (en) * | 2011-07-08 | 2013-08-06 | United Microelectronics Corp. | Differential varactor device |
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| US20050062062A1 (en) * | 2003-06-09 | 2005-03-24 | Nantero, Inc. | One-time programmable, non-volatile field effect devices and methods of making same |
| US20060054952A1 (en) * | 2004-06-04 | 2006-03-16 | Stmicroelectronics Sa | One-time programmable memory device |
| TW200807694A (en) * | 2006-07-18 | 2008-02-01 | Ememory Technology Inc | Semiconductor capacitor, one time programmable memory cell and fabricating method and operating method thereof |
| TW200814305A (en) * | 2006-09-07 | 2008-03-16 | Alpha & Omega Semiconductor | New configuration and method of manufacturing the one-time programmable (OTP) memory cells |
| TW201310579A (en) * | 2011-08-16 | 2013-03-01 | Maxchip Electronics Corp | Semiconductor structure and method of forming the same |
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