TWI553925B - Self-rectifying resistive random access memory cell structure - Google Patents
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- 239000002184 metal Substances 0.000 claims description 81
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- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
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- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
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- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910002451 CoOx Inorganic materials 0.000 claims 1
- 229910015189 FeOx Inorganic materials 0.000 claims 1
- 229910005855 NiOx Inorganic materials 0.000 claims 1
- 229910003070 TaOx Inorganic materials 0.000 claims 1
- 229910003087 TiOx Inorganic materials 0.000 claims 1
- -1 VOx Inorganic materials 0.000 claims 1
- MIQCYQOWOLNWJX-UHFFFAOYSA-N [O--].[O--].[Mn++].[Sr++] Chemical compound [O--].[O--].[Mn++].[Sr++] MIQCYQOWOLNWJX-UHFFFAOYSA-N 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 1
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- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims 1
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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Description
本發明係關於一種記憶體裝置，特別係關於一種電阻式隨機存取記憶體。 The present invention relates to a memory device, and more particularly to a resistive random access memory.
設計者正在尋找下一代的非揮發性記憶體，例如磁阻式隨機存取記憶體、相變化隨機存取記憶體、導電橋接式隨機存取記憶體及電阻式隨機存取記憶體(以下簡稱為RRAM)，以增加寫入速度及減少功耗。在上述種類的非揮發性記憶體中，RRAM之結構簡單、且具有簡單的交錯陣列及可於低溫製造、功率消耗低、操作電壓低、寫入抹除時間短、耐久度長、記憶時間長、非破壞性讀取、多狀態記憶、元件製程簡單及可微縮性，，所以成為新興非揮發性記憶體的主流。習知的電阻式非揮發性記憶體的基本結構為底電極、電阻轉態層及頂電極構成的一金屬-絕緣體-金屬(metal-insulator-metal,MIM)疊層結構，且電阻式非揮發性記憶體的電阻轉換(resistive switching，RS)阻值特性為元件的重要特性。 Designers are looking for next-generation non-volatile memory, such as magnetoresistive random access memory, phase-change random access memory, conductive bridged random access memory, and resistive random access memory (hereafter referred to as RRAM) to increase write speed and reduce power consumption. Among the above types of non-volatile memory, the RRAM has a simple structure and a simple staggered array and can be manufactured at low temperature, low power consumption, low operating voltage, short write erasing time, long durability, and long memory time. Non-destructive read, multi-state memory, simple component process and scalability, so it has become the mainstream of emerging non-volatile memory. The basic structure of the conventional resistive non-volatile memory is a metal-insulator-metal (MIM) laminated structure composed of a bottom electrode, a resistance transition layer and a top electrode, and a resistive non-volatile structure. Resistive switching (RS) resistance characteristics of the memory are important characteristics of the component.
雖然RRAM交錯陣列之結構簡單，但在製造上仍有許多問題待解決，特別是其3D交錯陣列。如無法形成3D交錯陣列，就高容量的資料儲存裝置來說，RRAM的每位元成本有可能無法與3D NAND記憶體競爭。 Although the structure of the RRAM interleaved array is simple, there are still many problems to be solved in manufacturing, especially its 3D interleaved array. If a 3D interleaved array cannot be formed, the high cost of the data storage device may not compete with the 3D NAND memory per bit cost of the RRAM.
RRAM交錯陣列理論上可容許4F2之最小單元晶胞尺寸(其中F為最小元件尺寸)，且低溫製程可容許記憶體陣列之堆疊達到前所未有的積體密度。然而，在1R結構中(僅具有一電阻元件)，會有潛電流通過相鄰未被選擇之記憶胞，而嚴重地影響讀取裕量，且限制交錯陣列之最大尺寸低於64位元。此問題可藉由增加非線性選擇裝置與這些電阻轉換元件串聯予以解決。例如，已發展出一二極體搭配一電阻(1D1R)、一選擇器搭配一電阻(1S1R)、一雙極性接面電晶體搭配一電阻(1BJT1R)、一MOSFET電晶體搭配一電阻(1T1R)等記憶胞結構。在上述記憶胞結構中，1BJT1R結構及1T1R結構過於複雜且需高溫製程而較不適用，且互補式電阻轉換元件(CRS)記憶胞結構亦有破壞性讀出的問題。因此，1D1R結構及1S1R結構較適合3D交錯陣列之運用。 The RRAM interleaved array theoretically allows a minimum cell unit size of 4F 2 (where F is the smallest element size), and the low temperature process allows the stack of memory arrays to achieve an unprecedented bulk density. However, in the 1R structure (having only one resistive element), there is a potential current passing through adjacent unselected memory cells, which seriously affects the read margin, and limits the maximum size of the staggered array to less than 64 bits. This problem can be solved by adding a nonlinear selection device in series with these resistance conversion elements. For example, a diode has been developed with a resistor (1D1R), a selector with a resistor (1S1R), a bipolar junction transistor with a resistor (1BJT1R), a MOSFET transistor with a resistor (1T1R). And other memory cell structure. In the above memory cell structure, the 1BJT1R structure and the 1T1R structure are too complicated and require a high temperature process, and are not suitable, and the complementary resistance conversion element (CRS) memory cell structure also has a problem of destructive readout. Therefore, the 1D1R structure and the 1S1R structure are more suitable for the application of the 3D interleaved array.
本發明提供一種電阻式非揮發性記憶體裝置及其製造方法，以提升電阻式非揮發性記憶體裝置的可靠度。 The present invention provides a resistive non-volatile memory device and a method of fabricating the same to improve the reliability of a resistive non-volatile memory device.
本發明之一實施例係提供一種自整流電阻式隨機存取記憶體記憶胞結構。上述RRAM記憶胞結構包括一第一電極；一絕緣體-金屬轉變材料層，設置於上述第一電極上；一阻障層，設置於上述絕緣體-金屬轉變材料層上；一第二電極，設置於上述阻障層上，其中上述絕緣體-金屬轉變材料層藉由上述阻障層與上述第二電極隔開。 One embodiment of the present invention provides a self-rectifying resistive random access memory memory cell structure. The RRAM memory cell structure includes a first electrode; an insulator-metal transition material layer disposed on the first electrode; a barrier layer disposed on the insulator-metal transition material layer; and a second electrode disposed on In the above barrier layer, the insulator-metal transition material layer is separated from the second electrode by the barrier layer.
500a、500b‧‧‧電阻式隨機存取記憶體記憶胞結構 500a, 500b‧‧‧Resistive random access memory cell structure
200、300、400‧‧‧第一電極 200, 300, 400‧‧‧ first electrode
202、208、214、220‧‧‧底面 202, 208, 214, 220‧‧‧ bottom
204、210、216、222‧‧‧頂面 204, 210, 216, 222‧‧‧ top
206、306、406‧‧‧絕緣體-金屬轉變材料層 206, 306, 406‧‧‧Insulator-metal transition material layer
212、312、412‧‧‧阻障層 212, 312, 412‧‧ ‧ barrier layer
218、318、418‧‧‧第二電極 218, 318, 418‧‧‧ second electrode
302、304、308、310、314、316、320、322‧‧‧側面 302, 304, 308, 310, 314, 316, 320, 322‧‧‧ side
第1圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構之剖面示意圖。 1 is a cross-sectional view showing a memory cell structure of a resistive random access memory according to an embodiment of the present invention.
第2圖顯示本發明之另一實施例之電阻式隨機存取記憶體記憶胞結構之剖面示意圖。 2 is a cross-sectional view showing a memory cell structure of a resistive random access memory according to another embodiment of the present invention.
第3A、3B圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構之操作機制示意圖。 3A and 3B are views showing the operation mechanism of the memory cell structure of the resistive random access memory according to an embodiment of the present invention.
第4圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構的電流對電壓(I-V)關係示意圖。 Fig. 4 is a view showing a current-to-voltage (I-V) relationship of a resistive random access memory cell structure according to an embodiment of the present invention.
為了讓本發明之目的、特徵、及優點能更明顯易懂，下文特舉實施例，並配合所附圖示，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。且實施例中圖式標號之部分重複，係為了簡化說明，並非意指不同實施例之間的關聯性。 In order to make the objects, features, and advantages of the present invention more comprehensible, the detailed description of the embodiments and the accompanying drawings. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. The overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description and are not intended to be related to the different embodiments.
本發明實施例係提供一種電阻式隨機存取記憶體記憶胞結構，例如為具有自限流及自整流之特性一電阻式非揮發性記憶體記憶胞結構，上述RRAM記憶胞結構的電阻轉態層由一絕緣體-金屬轉變材料(insulator-metal-transition material，IMT material)形成，因而可稱為一絕緣體-金屬轉變材料層。並且，上述絕緣體-金屬轉變材料層與耦接操作偏壓(不為零的正或負電壓)的電極係藉由一阻障層隔開。上述RRAM記憶胞結構為一金屬層-絕緣層-絕緣層-金屬層(metal-insulator-insulator-metal，MIIM)疊層結構，因而具有自 限流及自整流之特性，其亦可解決傳統RRAM 3D交錯陣列之1R記憶胞之潛電流的問題。 Embodiments of the present invention provide a resistive random access memory memory cell structure, for example, a self-limiting current and self-rectifying characteristic, a resistive non-volatile memory memory cell structure, and a resistance transition state of the RRAM memory cell structure. The layer is formed of an insulator-metal-transition material (IMT material) and thus may be referred to as an insulator-metal transition material layer. Moreover, the insulator-metal transition material layer and the electrode coupled to the operating bias (positive or negative voltage that is not zero) are separated by a barrier layer. The above RRAM memory cell structure is a metal-insulator-insulator-metal (MIIM) laminated structure, and thus has a self- The current limiting and self-rectifying characteristics can also solve the problem of the latent current of the 1R memory cell of the conventional RRAM 3D interleaved array.
第1圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構500a之剖面示意圖。本發明一實施例之RRAM記憶胞結構500a包括一第一電極200、一絕緣體-金屬轉變材料層206、一阻障層212以及一第二電極218。如第1圖所示，上述RRAM記憶胞結構500a為一水平堆疊之MIIM疊層結構，結構，意即RRAM記憶胞結構500a中任兩相鄰層的界面大體上平行一基板(圖未顯示)表面。 1 is a cross-sectional view showing a resistive random access memory cell structure 500a according to an embodiment of the present invention. The RRAM memory cell structure 500a according to an embodiment of the invention includes a first electrode 200, an insulator-metal transition material layer 206, a barrier layer 212, and a second electrode 218. As shown in FIG. 1, the RRAM memory cell structure 500a is a horizontally stacked MIIM stacked structure, that is, the interface of any two adjacent layers in the RRAM memory cell structure 500a is substantially parallel to a substrate (not shown). surface.
第一電極200具有一底面202和一頂面204，第二電極218具有一底面220和一頂面222。如第1圖所示，第二電極218係設置於第一電極200的頂面204上方。上述第一電極200可視為一底電極200，而上述第二電極218可視為一頂電極200。在本發明一些實施例中，第一電極200和第二電極218的材質可擇自下列組成之族群：Ti、Ta、Ni、Cu、W、Hf、Zr、Nb、Y、Zn、Co、Al、Si、Ge及前述之合金。舉例來說，第一電極層200可為Ti層，且第二電極層218可為Ta層。可利用電子束真空蒸鍍或濺鍍法形成上述第一電極200和第二電極218。 The first electrode 200 has a bottom surface 202 and a top surface 204. The second electrode 218 has a bottom surface 220 and a top surface 222. As shown in FIG. 1 , the second electrode 218 is disposed above the top surface 204 of the first electrode 200 . The first electrode 200 can be regarded as a bottom electrode 200, and the second electrode 218 can be regarded as a top electrode 200. In some embodiments of the present invention, the materials of the first electrode 200 and the second electrode 218 may be selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al. , Si, Ge and the aforementioned alloys. For example, the first electrode layer 200 can be a Ti layer, and the second electrode layer 218 can be a Ta layer. The first electrode 200 and the second electrode 218 described above may be formed by electron beam vacuum evaporation or sputtering.
如第1圖所示，絕緣體-金屬轉變材料層206設置於第一電極200的頂面204上。在本發明一些實施例中，絕緣體-金屬轉變材料層206具有一底面208和一頂面210，絕緣體-金屬轉變材料層206的底面208可與第一電極200的頂面204直接接觸。並且，絕緣體-金屬轉變材料層206可與第一電極200形成歐姆接觸。在本發明一些實施例中，絕緣體-金屬轉變材料層 206可因為不同的外加電壓而呈現絕緣體態或金屬態兩種不同的電阻狀態。因而絕緣體-金屬轉變材料層206可以做為RRAM記憶胞結構的電阻轉態層，用來儲存資料。也因此，絕緣體-金屬轉變材料層206在不同的外加電壓下不會存在導電絲。絕緣體-金屬轉變材料層206的材質可包括NiOx、TiOx、VOx、FeOx、CoOx、NbOx、鐠鈣錳氧化物(Praseodymium Calcium Manganese Oxide，PCMO)或上述組合。在本發明一些實施例中，可利用沉積方式形成絕緣體-金屬轉變材料層206例如原子層沉積、化學氣相沉積、電漿增強式化學氣相沉積、有機金屬化學氣相沉積、物理氣相沉積或其他適當。或者，在本發明一些其他實施例中，絕緣體-金屬轉變材料層206可由直接氧化第一電極200之表面部分形成。例如，可利用熱氧化法或雷射氧化法等氧化方式，直接氧化第一電極200之表面部分以形成絕緣體-金屬轉變材料層206。 As shown in FIG. 1, an insulator-metal transition material layer 206 is disposed on the top surface 204 of the first electrode 200. In some embodiments of the invention, the insulator-metal transition material layer 206 has a bottom surface 208 and a top surface 210, and the bottom surface 208 of the insulator-metal transition material layer 206 may be in direct contact with the top surface 204 of the first electrode 200. Also, the insulator-metal transition material layer 206 can form an ohmic contact with the first electrode 200. In some embodiments of the invention, the insulator-metal transition material layer 206 may exhibit two different resistance states, either in an insulator state or a metal state, due to different applied voltages. Thus, the insulator-metal transition material layer 206 can be used as a resistive transition layer of the RRAM memory cell structure for storing data. As a result, the insulator-metal transition material layer 206 does not have conductive filaments at different applied voltages. The material of the insulator-metal transition material layer 206 may include NiO x , TiO x , VO x , FeO x , CoO x , NbO x , Praseodymium Calcium Manganese Oxide (PCMO), or a combination thereof. In some embodiments of the present invention, an insulator-metal transition material layer 206 such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, organometallic chemical vapor deposition, physical vapor deposition may be formed by deposition. Or other appropriate. Alternatively, in some other embodiments of the invention, the insulator-metal transition material layer 206 may be formed by directly oxidizing a surface portion of the first electrode 200. For example, the surface portion of the first electrode 200 may be directly oxidized by an oxidation method such as thermal oxidation or laser oxidation to form the insulator-metal transition material layer 206.
如第1圖所示，阻障層212設置於絕緣體-金屬轉變材料層206的頂面210上。阻障層212具有一底面214和一頂面216，阻障層212的底面214可與絕緣體-金屬轉變材料層206的頂面210直接接觸，且阻障層212的頂面216與第二電極218的底面220直接接觸。因此，阻障層212可藉由絕緣體-金屬轉變材料層206與第一電極200隔開。在本發明一些實施例中，阻障層212可由具有一能隙的絕緣材料形成，上述能隙約大於2eV。並且，可選擇阻障層212的材質，使其能隙大於第一電極200、絕緣體-金屬轉變材料層206與第二電極218的能隙。因此，當對RRAM記憶胞結構500a外加電壓使電子從第一電極200注射進 入絕緣體-金屬轉變材料層206使其轉變為低電阻態(金屬態)時，上述電子會被阻障層212阻擋而不會進入第二電極218而再度改變絕緣體-金屬轉變材料層206的電阻狀態。或者，當對RRAM記憶胞結構500a外加電壓使存在於絕緣體-金屬轉變材料層206中的電子(e)逃出至第一電極200使其轉變為高電阻態(絕緣體態)時，從第二電極218朝絕緣體-金屬轉變材料層206注入的電子，會被阻障層212阻擋而不會進入絕緣體-金屬轉變材料層206而再度改變絕緣體-金屬轉變材料層206的電阻狀態。並且，當對RRAM記憶胞結構500a外加電壓操作時，設置於第二電極218和絕緣體-金屬轉變材料層206之間的阻障層212會使RRAM記憶胞結構500a具有非線性的電流對電壓(I-V)關係。阻障層212的材質可包括例如TaOx、HfO2、SiO2或上述組合。 As shown in FIG. 1, the barrier layer 212 is disposed on the top surface 210 of the insulator-metal transition material layer 206. The barrier layer 212 has a bottom surface 214 and a top surface 216. The bottom surface 214 of the barrier layer 212 can be in direct contact with the top surface 210 of the insulator-metal transition material layer 206, and the top surface 216 and the second electrode of the barrier layer 212. The bottom surface 220 of the 218 is in direct contact. Therefore, the barrier layer 212 may be separated from the first electrode 200 by the insulator-metal transition material layer 206. In some embodiments of the invention, the barrier layer 212 may be formed of an insulating material having an energy gap of greater than about 2 eV. Moreover, the material of the barrier layer 212 may be selected such that the energy gap is larger than the energy gap of the first electrode 200, the insulator-metal transition material layer 206, and the second electrode 218. Therefore, when a voltage is applied to the RRAM memory cell structure 500a to inject electrons from the first electrode 200 into the insulator-metal transition material layer 206 to be converted into a low resistance state (metal state), the electrons are blocked by the barrier layer 212. The resistance state of the insulator-metal transition material layer 206 is again changed without entering the second electrode 218. Alternatively, when a voltage is applied to the RRAM memory cell structure 500a such that electrons (e) present in the insulator-metal transition material layer 206 escape to the first electrode 200 to be converted into a high resistance state (insulator state), from the second The electrons injected by the electrode 218 toward the insulator-metal transition material layer 206 are blocked by the barrier layer 212 without entering the insulator-metal transition material layer 206 to change the resistance state of the insulator-metal transition material layer 206 again. Moreover, when a voltage operation is applied to the RRAM memory cell structure 500a, the barrier layer 212 disposed between the second electrode 218 and the insulator-metal transition material layer 206 causes the RRAM memory cell structure 500a to have a non-linear current-to-voltage ( IV) Relationship. The material of the barrier layer 212 may include, for example, TaO x , HfO 2 , SiO 2 , or a combination thereof.
在本發明一些實施例中，阻障層212的材質可為SiO2。並且，阻障層212與絕緣體-金屬轉變材料層206可分別由不同的材料形成。在本發明一些實施例中，絕緣體-金屬轉變材料層206可由第一電極200之金屬元素的氧化物形成，阻障層212可由第二電極218之金屬元素的氧化物形成，且第一電極200之金屬元素不同於第二電極218之金屬元素。舉例來說，當第一電極200由Ti形成時，絕緣體-金屬轉變材料層206係由TiO2形成，且當第二電極218由Ta形成時，阻障層212係由Ta2Ox形成。 In some embodiments of the present invention, the material of the barrier layer 212 may be SiO 2 . Also, the barrier layer 212 and the insulator-metal transition material layer 206 may be formed of different materials, respectively. In some embodiments of the present invention, the insulator-metal transition material layer 206 may be formed of an oxide of a metal element of the first electrode 200, and the barrier layer 212 may be formed of an oxide of a metal element of the second electrode 218, and the first electrode 200 The metal element is different from the metal element of the second electrode 218. For example, when the first electrode 200 is formed of Ti, the insulator-metal transition material layer 206 is formed of TiO 2 , and when the second electrode 218 is formed of Ta, the barrier layer 212 is formed of Ta 2 O x .
第2圖顯示本發明之另一實施例之電阻式隨機存取記憶體記憶胞結構500b之剖面示意圖。上述圖式中的各元件 如有與第1圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。 2 is a cross-sectional view showing a resistive random access memory cell structure 500b according to another embodiment of the present invention. Elements in the above figures If there is a part that is the same as or similar to that shown in Fig. 1, reference may be made to the related description above, and no repeated explanation is given here.
本發明一實施例之RRAM記憶胞結構500b包括一第一電極300、一絕緣體-金屬轉變材料層306、一阻障層312以及一第二電極318。如第2圖所示，上述RRAM記憶胞結構500b為一垂直堆疊之MIIM疊層結構，意即RRAM記憶胞結構500b中任兩相鄰層的界面大體上垂直一基板(圖未顯示)表面。 The RRAM memory cell structure 500b according to an embodiment of the invention includes a first electrode 300, an insulator-metal transition material layer 306, a barrier layer 312, and a second electrode 318. As shown in FIG. 2, the RRAM memory cell structure 500b is a vertically stacked MIIM stack structure, that is, the interface of any two adjacent layers in the RRAM memory cell structure 500b is substantially perpendicular to a substrate (not shown) surface.
如第2圖所示，上述RRAM記憶胞結構500b的第一電極300具有彼此相對的一側壁302和一側壁304，絕緣體-金屬轉變材料層306具有彼此相對的一側面308和一側面310，阻障層312具有彼此相對的一側面314和一側面316，第二電極318具有彼此相對的一側面320和一側面322。第一電極300的側面304與絕緣體-金屬轉變材料層306的側面308直接接觸，絕緣體-金屬轉變材料層306的側面310與阻障層312的側面314直接接觸，阻障層312的側面316與第二電極318的側面320直接接觸。 As shown in FIG. 2, the first electrode 300 of the RRAM memory cell structure 500b has a sidewall 302 and a sidewall 304 opposite to each other. The insulator-metal transition material layer 306 has a side surface 308 and a side surface 310 opposite to each other. The barrier layer 312 has a side 314 and a side 316 opposite to each other, and the second electrode 318 has a side 320 and a side 322 opposite to each other. The side surface 304 of the first electrode 300 is in direct contact with the side 308 of the insulator-metal transition material layer 306, and the side surface 310 of the insulator-metal transition material layer 306 is in direct contact with the side surface 314 of the barrier layer 312, and the side surface 316 of the barrier layer 312 is The side 320 of the second electrode 318 is in direct contact.
如第2圖所示，在本發明一些實施例中，上述RRAM記憶胞結構500b的第一電極300與第二電極318的材質和形成方式可類似或相同於如第1圖所示之上述RRAM記憶胞結構500a的第一電極200與第二電極218的材質和形成方式。上述RRAM記憶胞結構500b的絕緣體-金屬轉變材料層306的材質和形成方式可類似或相同於上述RRAM記憶胞結構500a的絕緣體-金屬轉變材料層206的材質和形成方式。並且，阻障層312的材質和形成方式可類似或相同於上述RRAM記憶胞結構500a的阻障層312的材質和形成方式。 As shown in FIG. 2, in some embodiments of the present invention, the material and formation manner of the first electrode 300 and the second electrode 318 of the RRAM memory cell structure 500b may be similar or identical to the above-described RRAM as shown in FIG. The material and formation of the first electrode 200 and the second electrode 218 of the memory cell structure 500a. The material and formation of the insulator-metal transition material layer 306 of the RRAM memory cell structure 500b may be similar or identical to the material and formation of the insulator-metal transition material layer 206 of the RRAM memory cell structure 500a. Moreover, the material and formation of the barrier layer 312 can be similar or identical to the material and formation of the barrier layer 312 of the RRAM memory cell structure 500a.
第3A、3B圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構之操作機制示意圖。第3A圖顯示RRAM記憶胞結構轉變為低電阻態(金屬態)的操作方式及能帶的變化示意圖。第3B圖顯示RRAM記憶胞結構轉變為高電阻態(絕緣體態)的操作方式及能帶的變化示意圖。第3A、3B圖中的元件400為RRAM記憶胞結構的第一電極，元件406為RRAM記憶胞結構的絕緣體-金屬轉變材料層，元件412為RRAM記憶胞結構的阻障層，且元件418為RRAM記憶胞結構的第二電極。另外如第3A圖箭頭左側的能帶圖所示，當對RRAM記憶胞結構的第一電極400電性接地(GND)，且對第二電極418電性耦接至一不為零的正電壓(+V)時，電子(e)會從第一電極400注入進入絕緣體-金屬轉變材料層406中(如單線箭頭所示)。值得注意的是，由於RRAM記憶胞結構的絕緣體-金屬轉變材料層406與被施加正電壓的第二電極418藉由阻障層212隔開。所以，當以第3A圖箭頭左側的方式操作RRAM記憶胞結構時，從第一電極400注入的上述電子會被阻障層212阻擋而不會進入第二電極218而再度改變絕緣體-金屬轉變材料層206的電阻狀態。上述過程可稱為電子摻雜。如第3A圖箭頭右側的能帶圖所示，絕緣體-金屬轉變材料層406經過電子摻雜之後，其能帶會轉變為與第二電極418相同，意即絕緣體-金屬轉變材料層406轉變為穩定的低電阻態(金屬態)，具有金屬的性質。並且，絕緣體-金屬轉變材料層406可與第一電極400形成歐姆接觸，以增加電子摻雜的效率。 3A and 3B are views showing the operation mechanism of the memory cell structure of the resistive random access memory according to an embodiment of the present invention. Figure 3A shows a schematic diagram of the operation of the RRAM memory cell structure into a low resistance state (metal state) and the change of the energy band. Figure 3B shows a schematic diagram of the operation of the RRAM memory cell structure into a high-resistance state (insulator state) and the change of the energy band. The component 400 in FIGS. 3A and 3B is the first electrode of the RRAM memory cell structure, the component 406 is the insulator-metal transition material layer of the RRAM memory cell structure, the component 412 is the barrier layer of the RRAM memory cell structure, and the component 418 is The second electrode of the RRAM memory cell structure. In addition, as shown in the energy band diagram on the left side of the arrow of FIG. 3A, when the first electrode 400 of the RRAM memory cell structure is electrically grounded (GND), and the second electrode 418 is electrically coupled to a non-zero positive voltage. At (+V), electrons (e) are injected from the first electrode 400 into the insulator-metal transition material layer 406 (as indicated by the single-line arrow). It is noted that the insulator-metal transition material layer 406 of the RRAM memory cell structure is separated from the second electrode 418 to which a positive voltage is applied by the barrier layer 212. Therefore, when the RRAM memory cell structure is operated in the manner of the left side of the arrow of FIG. 3A, the electrons injected from the first electrode 400 are blocked by the barrier layer 212 without entering the second electrode 218 to change the insulator-metal transition material again. The resistance state of layer 206. The above process can be referred to as electron doping. As shown in the energy band diagram on the right side of the arrow in FIG. 3A, after the insulator-metal transition material layer 406 is electronically doped, its energy band is converted to be the same as the second electrode 418, meaning that the insulator-metal transition material layer 406 is converted into Stable low resistance state (metal state) with metallic properties. Also, the insulator-metal transition material layer 406 can form an ohmic contact with the first electrode 400 to increase the efficiency of electron doping.
如第3B圖箭頭左側的能帶圖所示，當對RRAM記憶 胞結構的第一電極400電性接地(GND)，且對第二電極418電性耦接至一不為零的負電壓(-V)時，存在於絕緣體-金屬轉變材料層406中的電子(e)會逃出至第一電極400(如單線箭頭所示)。如第3B圖圖箭頭右側的能帶圖所示，電子逃出絕緣體-金屬轉變材料層406之後，其能帶會回復未摻雜電子的狀態，意即絕緣體-金屬轉變材料層406轉變為穩定的高電阻態(絕緣體)，具有絕緣體的性質。值得注意的是，由於RRAM記憶胞結構的絕緣體-金屬轉變材料層406與被施加負電壓的第二電極418藉由阻障層212隔開。所以，當以第3B圖箭頭左側的方式操作RRAM記憶胞結構時，從第二電極418朝絕緣體-金屬轉變材料層206注入的電子，會被阻障層212阻擋而不會進入絕緣體-金屬轉變材料層206而再度改變絕緣體-金屬轉變材料層206的電阻狀態。 As shown in the band diagram on the left side of the arrow in Figure 3B, when remembering the RRAM The first electrode 400 of the cell structure is electrically grounded (GND), and when the second electrode 418 is electrically coupled to a non-zero negative voltage (-V), the electrons present in the insulator-metal transition material layer 406 (e) will escape to the first electrode 400 (as indicated by the single-line arrow). As shown in the energy band diagram on the right side of the arrow in Fig. 3B, after the electrons escape the insulator-metal transition material layer 406, the energy band returns to the state of undoped electrons, meaning that the insulator-metal transition material layer 406 is stabilized. High resistance state (insulator) with insulator properties. It is noted that the insulator-metal transition material layer 406 of the RRAM memory cell structure is separated from the second electrode 418 to which a negative voltage is applied by the barrier layer 212. Therefore, when the RRAM memory cell structure is operated in the manner of the left side of the arrow of FIG. 3B, electrons injected from the second electrode 418 toward the insulator-metal transition material layer 206 are blocked by the barrier layer 212 without entering the insulator-metal transition. The material layer 206 changes the resistance state of the insulator-metal transition material layer 206 again.
第4圖顯示本發明之一實施例之電阻式隨機存取記憶體記憶胞結構的電流對電壓(I-V)關係示意圖。在第4圖所示之實施例中，RRAM記憶胞結構係由一Ti第一電極、一TiO2絕緣體-金屬轉變材料層、一SiO2阻障層及一Ta第二電極依續堆疊形成，其中TiO2絕緣體-金屬轉變材料層之厚度約為30nm，且SiO2阻障層之厚度為10nm。 Fig. 4 is a view showing a current-to-voltage (IV) relationship of a resistive random access memory cell structure according to an embodiment of the present invention. In the embodiment shown in FIG. 4, the RRAM memory cell structure is formed by successively stacking a Ti first electrode, a TiO 2 insulator-metal transition material layer, a SiO 2 barrier layer, and a Ta second electrode. The thickness of the TiO 2 insulator-metal transition material layer is about 30 nm, and the thickness of the SiO 2 barrier layer is 10 nm.
如第4圖所示，本發明實施例之RRAM記憶胞結構為一雙極型的RRAM，其可藉由施予一正電壓而轉換至設定狀態。並且，本發明實施例之RRAM記憶胞結構具有自限流(self-compliance)及自整流(self-rectifying)之特性。如第4圖所示，本發明實施例之RRAM記憶胞結構可被約+5V之最小電壓 轉換至設定狀態及被約-4V之最小電壓轉換至重設狀態。可利用+/-2V之電壓進行讀取本發明實施例之RRAM記憶胞結構。由第4圖可知，由於本發明實施例之RRAM記憶胞結構的阻障層的能隙選擇大於絕緣體-金屬轉變材料層的能隙。所以，流向第二電極之電流在流經阻障層時，會被阻障層重整。並且，流向第一電極的電流則可輕易通過絕緣體-金屬轉變材料層。所以，當對RRAM記憶胞結構施加正偏壓(外加電壓)增加時(從0V增加至+4V)，上述RRAM記憶胞結構的電流會被重整，具有自整流(self-rectifying)特性，因而有效抑制潛電流。如第4圖所示，當對RRAM記憶胞結構施加負偏壓(外加電壓)增加時(從0V增加至-4V)，RRAM記憶胞結構會呈現兩個電阻態。並且，當負偏壓增加至-4V時，本發明實施例之RRAM記憶胞結構可具有約小於10-5之電流限制極限(current compliance limit level)，具有自限流(self-compliance)特性。另外，在偏壓(外加電壓)約±2V時，上述RRAM記憶胞結構的整流比值(current rectification ratio)(例如限流水平對整流水平之比例)約大於10。另外，如第4圖所示之不同樣式的線段係表示本發明實施例之RRAM記憶胞結構經多次重複操作仍具有電阻轉換特性。 As shown in FIG. 4, the RRAM memory cell structure of the embodiment of the present invention is a bipolar RRAM that can be switched to a set state by applying a positive voltage. Moreover, the RRAM memory cell structure of the embodiment of the invention has self-compliance and self-rectifying characteristics. As shown in FIG. 4, the RRAM memory cell structure of the embodiment of the present invention can be switched to a set state by a minimum voltage of about +5 V and converted to a reset state by a minimum voltage of about -4 V. The RRAM memory cell structure of the embodiment of the present invention can be read using a voltage of +/- 2V. As can be seen from FIG. 4, the energy gap of the barrier layer of the RRAM memory cell structure of the embodiment of the present invention is greater than that of the insulator-metal transition material layer. Therefore, the current flowing to the second electrode is reformed by the barrier layer as it flows through the barrier layer. Also, the current flowing to the first electrode can easily pass through the insulator-metal transition material layer. Therefore, when a positive bias (applied voltage) is applied to the RRAM memory cell structure (from 0V to +4V), the current of the RRAM memory cell structure is reformed and has self-rectifying characteristics. Effectively suppress latent currents. As shown in Figure 4, when a negative bias (applied voltage) is applied to the RRAM memory cell structure (from 0V to -4V), the RRAM memory cell structure exhibits two resistance states. Moreover, when the negative bias voltage is increased to -4 V, the RRAM memory cell structure of the embodiment of the present invention may have a current compliance limit level of less than about 10 -5 with self-compliance characteristics. In addition, when the bias voltage (applied voltage) is about ±2 V, the current rectification ratio of the RRAM memory cell structure (for example, the ratio of the current limiting level to the rectification level) is greater than about 10. In addition, the different styles of line segments as shown in FIG. 4 indicate that the RRAM memory cell structure of the embodiment of the present invention has resistance conversion characteristics after repeated operations.
本發明實施例之RRAM記憶胞結構可僅為1R記憶胞結構，且具有類於似傳統與非線性選擇器連接之電阻器(例如1T1R、1D1R、1S1R、1BJT1R)之非線性電流對電壓(I-V)關係的性質。此外，本發明實施例之RRAM記憶胞結構可免去初始形成步驟，意即可不需初始形成電壓來活化上述RRAM記憶胞結構。本發明實施例之RRAM記憶胞結構可以避免因具較大 電壓之初始形成步驟而傷害本身結構，因而可具有較佳的可靠度。並且，本發明實施例之RRAM記憶胞結構係具有自限流及自整流之特性，其亦可解決傳統RRAM 3D交錯陣列之1R記憶胞之潛電流的問題。 The RRAM memory cell structure of the embodiment of the present invention may be only a 1R memory cell structure, and has a nonlinear current-to-voltage (IV) similar to a resistor (such as 1T1R, 1D1R, 1S1R, 1BJT1R) connected to a conventional nonlinear selector. The nature of the relationship. In addition, the RRAM memory cell structure of the embodiment of the present invention can eliminate the initial formation step, which means that the initial RRAM memory cell structure can be activated without initial voltage formation. The RRAM memory cell structure of the embodiment of the invention can be avoided The initial formation step of the voltage damages the structure itself and thus has better reliability. Moreover, the RRAM memory cell structure of the embodiment of the invention has the characteristics of self-limiting current and self-rectification, and can also solve the problem of the latent current of the 1R memory cell of the conventional RRAM 3D interlaced array.
雖然本發明已以實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described by way of example only, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
500a‧‧‧電阻式隨機存取記憶體記憶胞結構 500a‧‧‧Resistive random access memory cell structure
200‧‧‧第一電極 200‧‧‧first electrode
202、208、214、220‧‧‧底面 202, 208, 214, 220‧‧‧ bottom
204、210、216、222‧‧‧頂面 204, 210, 216, 222‧‧‧ top
206‧‧‧絕緣體-金屬轉變材料層 206‧‧‧Insulator-metal transition material layer
212‧‧‧阻障層 212‧‧‧Barrier layer
218‧‧‧第二電極 218‧‧‧second electrode
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