TWI550800B - Through silicon via structure with rugged bump on chip backside - Google Patents
Through silicon via structure with rugged bump on chip backside Download PDFInfo
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- TWI550800B TWI550800B TW102140939A TW102140939A TWI550800B TW I550800 B TWI550800 B TW I550800B TW 102140939 A TW102140939 A TW 102140939A TW 102140939 A TW102140939 A TW 102140939A TW I550800 B TWI550800 B TW I550800B
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Description
本發明係有關於半導體晶片之矽穿孔結構，特別係有關於一種具強固型晶背凸塊之矽穿孔結構。 The present invention relates to a tantalum perforated structure for a semiconductor wafer, and more particularly to a tantalum perforated structure having a strong crystalline back bump.
矽穿孔(Through Silicon Via)係應用於先進的半導體晶片接合結構，達到晶片之縱向雙面導通，可進行高堆疊數與小尺寸的立體(3D)晶片對晶片堆疊組合。利用矽穿孔之立體(3D)晶片堆疊技術可維持摩爾定律(Moore's Law)的持續發展，能實現在更小尺寸內具有高速傳輸與低消耗功率的積體電路。目前矽穿孔製程依矽穿孔形成之時機之不同主要可區分為三大方案，即前段鑽孔(via-first)、中段鑽孔(via-middle)與後段鑽孔(via-last)，其中前段鑽孔製程為矽穿孔形成在積體電路製作之前，中段鑽孔為矽穿孔形成在積體電路製作之後與後通道(back end of line，BEOL)製作之前，後段鑽孔為矽穿孔形成在前通道(FEOL)製程與後通道(BEOL)製程之後。 Through Silicon Via is applied to advanced semiconductor wafer bonding structures to achieve vertical double-sided conduction of the wafer, enabling high stack count and small size stereo (3D) wafer-to-wafer stacking. The continuous development of Moore's Law can be achieved by using a three-dimensional (3D) wafer stacking technique of 矽 perforation, which enables an integrated circuit with high-speed transmission and low power consumption in a smaller size. At present, the timing of the perforation process depends on the timing of the formation of the perforation, which can be divided into three major schemes, namely, the via-first, the via-middle and the via-last. The drilling process is formed by the boring of the boring hole before the formation of the integrated circuit, and the drilling of the middle section is formed by the boring of the boring. After the formation of the integrated circuit and the back end of the line (BEOL), the hole in the back section is formed by the boring. After the channel (FEOL) process and the back channel (BEOL) process.
此外，已知技術為除了矽穿孔之外亦將微型凸塊製作於晶片之表面，以供立體晶片堆疊之接合。第1圖係為習知具晶背凸塊之矽穿孔結構之局部截面示意圖。第2圖係為該習知矽穿孔結構在凸塊形成與孔電鍍之前之局部截面示意圖。習知具有晶背凸塊之矽穿孔結構200係包 含一半導體基板210、一銲墊220、一貫穿孔230、一介電內襯240以及一填孔導體250。在矽穿孔製程中，該半導體基板210之主動面211係貼附於一晶圓承載系統20。該貫穿孔230係貫穿該半導體基板210之主動面211與背面212而連通至該銲墊220，該介電內襯240包覆該貫穿孔230之孔壁，該填孔導體250係埋設於該貫穿孔230中以電性導通至該銲墊220並突出於該背面213以形成一晶背凸塊251，該晶背凸塊251之頂面可設置有銲料260。即使在矽穿孔製程中，該貫穿孔230具有標準的垂直孔壁，然而該介電內襯240在沉積時會在該貫穿孔230之外孔緣形成一懸突孔緣243，此一頸口缺陷將導致該填孔導體250在該貫穿孔230內產生未填滿的電鍍空隙252(void)、一電鍍種子層270在該貫穿孔230內之連續性形成困難、該晶背凸塊251的易於斷裂。特別是該電鍍空隙252的存在，當該晶背凸塊251承受熱應力時，該電鍍空隙252會加速該填孔導體250之結構破壞，進而引起傳輸不佳甚至於故障的電性表現。 In addition, the known technique is to fabricate microbumps on the surface of the wafer in addition to the ruthenium perforations for the bonding of the stacked wafers. Figure 1 is a partial cross-sectional view showing a conventional perforated structure having a crystal back bump. Figure 2 is a partial cross-sectional view of the conventional crucible structure prior to bump formation and hole plating. Conventional perforated structure 200 with a back bump A semiconductor substrate 210, a pad 220, a uniform via 230, a dielectric liner 240, and a via conductor 250 are included. In the 矽 矽 process, the active surface 211 of the semiconductor substrate 210 is attached to a wafer carrier system 20 . The through hole 230 is connected to the bonding pad 220 through the active surface 211 and the back surface 212 of the semiconductor substrate 210. The dielectric liner 240 covers the hole wall of the through hole 230. The hole-filling conductor 250 is embedded in the hole. The through hole 230 is electrically connected to the bonding pad 220 and protrudes from the back surface 213 to form a crystal back bump 251. The top surface of the crystal back bump 251 may be provided with solder 260. Even in the boring and perforating process, the through hole 230 has a standard vertical hole wall, but the dielectric lining 240 forms a cantilevered hole 243 at the outer edge of the through hole 230 during deposition, the neck opening The defect will cause the hole-filling conductor 250 to generate an unfilled plating void 252 in the through-hole 230, and the continuity of a plating seed layer 270 in the through-hole 230 is difficult to form, and the crystal back bump 251 is formed. Easy to break. In particular, the presence of the plating void 252, when the crystal back bump 251 is subjected to thermal stress, the plating void 252 accelerates structural damage of the via-hole conductor 250, thereby causing poor electrical transmission or even electrical failure.
為了解決上述之問題，本發明之主要目的係在於提供一種具強固型晶背凸塊之矽穿孔結構，具備強固型晶背凸塊並解決了習知矽穿孔內電鍍空隙之缺陷，用以改善晶背凸塊下矽穿孔導體不耐用易於斷裂之問題。 In order to solve the above problems, the main object of the present invention is to provide a crucible perforated structure with a strong crystal back bump, which has a strong crystal back bump and solves the defects of the electroplated void in the conventional crucible for improvement. The back of the crystal back bump is not durable and is prone to breakage.
本發明之次一目的係在於提供一種具強固型晶背凸塊之矽穿孔結構，用以改善矽穿孔填充之製程窗(process window)，而達到較佳的矽穿孔製程良率。 A second object of the present invention is to provide a crucible perforation structure having a strong crystal back bump for improving the process window of the perforated filling to achieve a better crucible perforation process yield.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種具強固型晶背凸塊之矽穿孔結構，其係包含一半導體基板、至少一銲墊、一貫 穿孔、一介電內襯以及一填孔導體。該半導體基板係具有一主動面與一背面。該銲墊係設置於該主動面。該貫穿孔係由該背面貫穿該半導體基板，以連通至該銲墊。該介電內襯係包覆該貫穿孔之內孔壁，該介電內襯係具有一位於該銲墊上之內開口與一位於該背面之外開口。該填孔導體係填滿該貫穿孔並具有一突出於該背面之晶背凸塊。其中，該貫穿孔在往該背面處係形成有複數個孔徑增大之缺口環，該些缺口環之總深度係不小於該半導體基板之該主動面至該背面之厚度之二十分之一且不大於該厚度之三分之二，並且該介電內襯係填入該些缺口環之凹陷部，該外開口係不小於該內開口。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a crucible perforation structure with a strong crystal back bump, which comprises a semiconductor substrate, at least one pad, and consistently A perforation, a dielectric liner, and a hole-filling conductor. The semiconductor substrate has an active surface and a back surface. The pad is disposed on the active surface. The through hole penetrates the semiconductor substrate from the back surface to communicate with the pad. The dielectric liner covers the inner wall of the through hole, and the dielectric liner has an inner opening on the pad and an opening outside the back. The hole filling guide system fills the through hole and has a crystal back bump protruding from the back surface. The through hole is formed with a plurality of notch rings having an increased aperture diameter at the back surface, and the total depth of the notch rings is not less than one-twentieth of the thickness of the active surface of the semiconductor substrate to the back surface. And not more than two-thirds of the thickness, and the dielectric liner is filled into the recesses of the notch rings, and the outer opening is not less than the inner opening.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之矽穿孔結構之一較佳實施例中，該些缺口環之凹陷部倒角係可不小於90度且不大於180度，可減少對該晶背凸塊之銳角應力作用，並有利於一電鍍種子層在該貫穿孔之連續形成。 In a preferred embodiment of the foregoing perforated structure, the chamfering of the notch of the notch ring may be not less than 90 degrees and not more than 180 degrees, which may reduce the acute angular stress on the crystal back bump, and is beneficial to A plating seed layer is continuously formed in the through hole.
在前述之矽穿孔結構之一較佳實施例中，該主動面上係可形成有一內絕緣層，該半導體基板由該貫穿孔之內孔壁至該內絕緣層之截面夾角係不小於70度且不大於90度，即該貫穿孔之內孔壁本身即為往該背面孔徑逐漸擴大之型態。 In a preferred embodiment of the foregoing through-hole structure, the active surface may be formed with an inner insulating layer, and the semiconductor substrate has an angle of not less than 70 degrees from the inner wall of the through hole to the inner insulating layer. And not more than 90 degrees, that is, the inner wall of the through hole itself is a shape in which the aperture is gradually enlarged toward the back surface.
在前述之矽穿孔結構之一較佳實施例中，該背面上係可形成有一晶背保護層，該介電內襯係延伸並覆蓋該晶背保護層。 In a preferred embodiment of the foregoing ruthenium perforation structure, a backside protection layer may be formed on the back surface, and the dielectric liner extends and covers the crystal back protection layer.
在前述之矽穿孔結構之一較佳實施例中，該填孔導體以及包含該晶背凸塊之一體部份係為銅(Cu)或鎢(W)材質，並在該晶背凸塊上設置有銲料，故施加於焊接後該 晶背凸塊之應力可分散到該貫穿孔內。 In a preferred embodiment of the foregoing puncturing structure, the hole-filling conductor and the body portion including the crystal-back bump are made of copper (Cu) or tungsten (W), and are on the crystal back bump. Solder is set, so it is applied after soldering The stress of the crystal back bump can be dispersed into the through hole.
在前述之矽穿孔結構之一較佳實施例中，該些缺口環之覆蓋區域係可為不重疊地圍繞在該介電內襯之該內開口之孔徑向面積之外。 In a preferred embodiment of the foregoing perforated structure, the coverage areas of the notch rings may be non-overlapping around the radial area of the aperture of the inner opening of the dielectric liner.
在前述之矽穿孔結構之一較佳實施例中，該些缺口環之數量係可為三個或三個以上。 In a preferred embodiment of the foregoing perforated structure, the number of the notched rings may be three or more.
在前述之矽穿孔結構之一較佳實施例中，該介電內襯係可完全填滿該些缺口環之凹陷部，以提供一重塑形孔，以使該填孔導體填滿於該貫穿孔之部位成為一具有連續壁面之細柱體。 In a preferred embodiment of the foregoing puncturing structure, the dielectric lining can completely fill the recesses of the notched rings to provide a reshaped hole to fill the hole-filling conductor. The portion of the through hole becomes a thin cylinder having a continuous wall surface.
10‧‧‧晶圓承載系統 10‧‧‧ Wafer Carrying System
20‧‧‧晶圓承載系統 20‧‧‧ Wafer Carrying System
100‧‧‧矽穿孔結構 100‧‧‧矽 perforated structure
110‧‧‧半導體基板 110‧‧‧Semiconductor substrate
111‧‧‧主動面 111‧‧‧Active surface
112‧‧‧背面 112‧‧‧Back
113‧‧‧晶背保護層 113‧‧‧ Crystal back protective layer
114‧‧‧內絕緣層 114‧‧‧Insulation
120‧‧‧銲墊 120‧‧‧ solder pads
130‧‧‧貫穿孔 130‧‧‧through holes
131‧‧‧第一缺口環 131‧‧‧First gap ring
132‧‧‧第二缺口環 132‧‧‧second notched ring
133‧‧‧第三缺口環 133‧‧‧ third notched ring
140‧‧‧介電內襯 140‧‧‧Dielectric lining
141‧‧‧內開口 Opening within 141‧‧
142‧‧‧外開口 142‧‧‧Outside opening
143‧‧‧重塑形孔 143‧‧‧Reshaped holes
150‧‧‧填孔導體 150‧‧‧filling conductor
151‧‧‧晶背凸塊 151‧‧‧ crystal back bump
160‧‧‧銲料 160‧‧‧ solder
170‧‧‧電鍍種子層 170‧‧‧Electroplating seed layer
200‧‧‧矽穿孔結構 200‧‧‧矽 perforated structure
210‧‧‧半導體基板 210‧‧‧Semiconductor substrate
211‧‧‧主動面 211‧‧‧ active face
212‧‧‧背面 212‧‧‧Back
220‧‧‧銲墊 220‧‧‧ solder pads
230‧‧‧貫穿孔 230‧‧‧through holes
240‧‧‧介電內襯 240‧‧‧ dielectric lining
243‧‧‧懸突孔緣 243‧‧‧Overhanging edge
250‧‧‧填孔導體 250‧‧‧ hole-filling conductor
251‧‧‧晶背凸塊 251‧‧‧ crystal back bump
252‧‧‧電鍍空隙 252‧‧‧Electroplating voids
260‧‧‧銲料 260‧‧‧ solder
270‧‧‧電鍍種子層 270‧‧‧Electroplating seed layer
h0‧‧‧半導體基板之厚度 H0‧‧‧Thickness of semiconductor substrate
h1‧‧‧第一缺口環之深度 h1‧‧‧Deep of the first notched ring
h2‧‧‧第二缺口環之深度 h2‧‧‧Deep of the second notched ring
h3‧‧‧第三缺口環之深度 h3‧‧‧Deep of the third notched ring
T0‧‧‧外開口之孔徑向面積 T0‧‧‧ Radial area of the outer opening
W0‧‧‧內開口之孔徑向面積 Radial area of the opening in W0‧‧
W1‧‧‧第一缺口環之覆蓋區域 W1‧‧‧ coverage area of the first notched ring
W2‧‧‧第二缺口環之覆蓋區域 W2‧‧‧ coverage area of the second notched ring
W3‧‧‧第三缺口環之覆蓋區域 W3‧‧‧ coverage area of the third notched ring
α‧‧‧第一缺口環之凹陷部倒角 α‧‧‧The first notched ring chamfer
β‧‧‧第二缺口環之凹陷部倒角 β‧‧‧The second notch ring is chamfered
γ‧‧‧第三缺口環之凹陷部倒角 γ‧‧‧The third notched ring is chamfered
θ‧‧‧半導體基板之孔壁截面夾角 θ‧‧‧The angle of the hole wall section of the semiconductor substrate
第1圖：習知具晶背凸塊之矽穿孔結構之局部截面示意圖。 Fig. 1 is a partial cross-sectional view showing a conventional perforated structure with a crystal back bump.
第2圖：習知矽穿孔結構在凸塊形成與孔電鍍之前之局部截面示意圖。 Fig. 2 is a partial cross-sectional view showing the conventional perforated structure before bump formation and hole plating.
第3圖：依據本發明之一具體實施例，一種具強固型晶背凸塊之矽穿孔結構之局部截面示意圖。 Figure 3 is a partial cross-sectional view showing a crucible perforated structure having a strong crystalline back bump according to an embodiment of the present invention.
第4圖：依據本發明之一具體實施例，該矽穿孔結構在凸塊形成與孔電鍍之前之局部截面示意圖。 Figure 4 is a partial cross-sectional view of the ruthenium perforated structure prior to bump formation and hole plating, in accordance with an embodiment of the present invention.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置 性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual implementation of the number, shape and size ratio is an option The design of the features, the detailed component layout may be more complicated.
依據本發明之一具體實施例，一種具強固型晶背凸塊之矽穿孔結構舉例說明於第3圖之局部截面示意圖以及第4圖之在凸塊形成與孔電鍍之前之局部截面示意圖。該矽穿孔結構100係包含一半導體基板110、至少一銲墊120、一貫穿孔130、一介電內襯140(dielectric liner)以及一填孔導體150。 In accordance with an embodiment of the present invention, a crucible perforated structure having a strong crystalline back bump is illustrated in a partial cross-sectional view of FIG. 3 and a partial cross-sectional view of the fourth embodiment prior to bump formation and hole plating. The crucible structure 100 includes a semiconductor substrate 110, at least one pad 120, a uniform via 130, a dielectric liner 140, and a via conductor 150.
該半導體基板110係具有一主動面111與一背面112。該銲墊120係設置於該主動面111。該主動面111設置有積體電路元件以及適當的互連導線115(conducting interconnect)。該主動面111上係可形成有一內絕緣層114，其係介設於該半導體基板110與用以包覆該些互連導線115與該銲墊120之介電材料層之間。通常在晶圓製程中，該半導體基板110係以該主動面111面向一晶圓承載系統10(wafer support system,WSS)的方式貼附於該晶圓承載系統10，該晶圓承載系統10之材質係可為玻璃或矽等硬質且熱膨脹係數與半導體晶圓匹配之材料。故該半導體基板110在晶圓階段時可有效薄化到8密爾以下，故該貫穿孔130之深度相對縮小，在可執行穿孔製程能力的合理孔深寬比下，以利該貫穿孔130之孔微小化之製作。另，該背面112係為該主動面111之相對表面，通常該背面112係未佈設積體電路元件。 The semiconductor substrate 110 has an active surface 111 and a back surface 112. The pad 120 is disposed on the active surface 111. The active surface 111 is provided with integrated circuit components and a suitable conducting interconnect 115. The active surface 111 is formed with an inner insulating layer 114 disposed between the semiconductor substrate 110 and a layer of dielectric material for covering the interconnecting wires 115 and the pad 120. Generally, in the wafer process, the semiconductor substrate 110 is attached to the wafer carrier system 10 with the active surface 111 facing a wafer support system (WSS). The wafer carrier system 10 The material can be a material such as glass or tantalum that has a hard thermal expansion coefficient matching the semiconductor wafer. Therefore, the semiconductor substrate 110 can be effectively thinned to less than 8 mils in the wafer stage, so that the depth of the through hole 130 is relatively reduced, and the through hole 130 can be formed under a reasonable hole aspect ratio capable of performing the punching process capability. The production of the hole is miniaturized. In addition, the back surface 112 is an opposite surface of the active surface 111. Usually, the back surface 112 is not provided with integrated circuit elements.
該貫穿孔130係由該背面112貫穿該半導體基板110，以連通至該銲墊120，故該貫穿孔130的外孔徑即便擴大亦不影響積體電路元件之設置。在本實施例中，該貫穿孔130係對準但不貫穿該銲墊120。 The through hole 130 penetrates the semiconductor substrate 110 from the back surface 112 to communicate with the pad 120. Therefore, even if the outer aperture of the through hole 130 is enlarged, the arrangement of the integrated circuit components is not affected. In the present embodiment, the through hole 130 is aligned but does not penetrate the pad 120.
該介電內襯140係包覆該貫穿孔130之內孔壁，該介電內襯140係具有一位於該銲墊120上之內開口 141與一位於該背面112之外開口142。該介電內襯140之材質係可為電絕緣之氧化物、氮化物、或有機聚合物，例如二氧化矽(SiO2)、氮化矽(SiN)或氮氧化矽(SiON)，可為單層膜或是多層膜之組合。更具體地，該背面112上係可形成有一晶背保護層113，該介電內襯140係延伸並覆蓋該晶背保護層113。並且，該填孔導體150係填滿該貫穿孔130並具有一突出於該背面112之晶背凸塊151。此外，在該介電內襯140與該填孔導體150之間係可形成一電鍍種子層170，以利該填孔導體150及其晶背凸塊151之電鍍形成，該電鍍種子層170係可利用物理氣相沉積(PVD)方法形成，較佳地，該電鍍種子層170之材質係為鈦/氮化鈦(Ti/TiN)或鉭/氮化鉭(Ta/TaN)，而同時具備阻障層(barrier)之功能。在一較佳實施例中，該填孔導體150以及包含該晶背凸塊151之一體部份係為銅(Cu)或鎢(W)材質，並在該晶背凸塊151上設置有銲料160，故施加於焊接後該晶背凸塊151之應力可分散到該貫穿孔130內。 The dielectric liner 140 covers the inner wall of the through hole 130. The dielectric liner 140 has an inner opening 141 on the pad 120 and an opening 142 outside the back surface 112. The material of the dielectric liner 140 may be an electrically insulating oxide, a nitride, or an organic polymer, such as cerium oxide (SiO 2 ), cerium nitride (SiN) or cerium oxynitride (SiON), which may be A single layer film or a combination of multilayer films. More specifically, a back protective layer 113 may be formed on the back surface 112, and the dielectric liner 140 extends and covers the crystal back protective layer 113. Moreover, the hole-filling conductor 150 fills the through hole 130 and has a crystal back bump 151 protruding from the back surface 112. In addition, a plating seed layer 170 may be formed between the dielectric liner 140 and the hole-filling conductor 150 to facilitate plating of the hole-filling conductor 150 and the crystal back bump 151 thereof. It can be formed by a physical vapor deposition (PVD) method. Preferably, the plating seed layer 170 is made of titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN). The function of the barrier. In a preferred embodiment, the hole-filling conductor 150 and a body portion including the crystal back bump 151 are made of copper (Cu) or tungsten (W), and solder is disposed on the crystal back bump 151. 160, the stress applied to the crystal back bump 151 after soldering can be dispersed into the through hole 130.
其中，該貫穿孔130在往該背面112處係形成有複數個孔徑增大之缺口環131、132、133，可利用不同圖案的微影成像與深反應式離子蝕刻(DRIE)技術形成該些缺口環。並且，該些缺口環之總深度係不小於該半導體基板110之該主動面111至該背面112之厚度之二十分之一，亦不大於上述厚度之三分之二。該些缺口環之數量較佳為三個或三個以上，在相同的缺口環之總深度下，越多的缺口環之數量可降低每一缺口環之單位深度，使得該貫穿孔130之孔外徑益加的平滑，在本實施例中，該些缺口環由該背面112往內係包含第一缺口環131、第二缺口環132與第三缺口環133。可對照第4圖，該半導體基板110之厚度係標示為h0，其係相當於該貫穿孔130之深度，而該 第一缺口環131之深度係標示為h1，該第二缺口環132之深度係標示為h2，該第三缺口環133之深度係標示為h3，其算式為：0.05×h0≦h1+h2+h3≦0.666×h0，換言之，該些缺口環131、132、133係不靠近該主動面111並且佔據該半導體基板110之厚度比不超過三分之二，故該半導體基板110可維持足夠之結構強度並且不影響該主動面111之積體電路配置。並且，該介電內襯140係填入該些缺口環131、132、133之凹陷部，該外開口142係不小於該內開口141，如第4圖所示，該外開口142之孔徑向面積係標示為T0，該內開口141之孔徑向面積係標示為W0，其算式為：T0≧W0，藉此有效減輕該半導體基板110之懸突孔緣(overhang hole edge)施加於該晶背凸塊151之應力。 The through hole 130 is formed with a plurality of notched rings 131, 132, and 133 having an increased aperture at the back surface 112. The lithographic imaging and deep reactive ion etching (DRIE) techniques of different patterns can be used to form the notches. Notched ring. Moreover, the total depth of the notch rings is not less than one-twentieth of the thickness of the active surface 111 to the back surface 112 of the semiconductor substrate 110, and is not more than two-thirds of the thickness. The number of the notched rings is preferably three or more. Under the total depth of the same notched ring, the more the number of notched rings can reduce the unit depth of each notched ring, so that the through hole 130 has a hole. In the present embodiment, the notch rings include the first notch ring 131, the second notch ring 132, and the third notch ring 133 from the back surface 112. According to FIG. 4, the thickness of the semiconductor substrate 110 is denoted by h0, which corresponds to the depth of the through hole 130, and the The depth of the first notch ring 131 is denoted by h1, the depth of the second notch ring 132 is denoted by h2, and the depth of the third notch ring 133 is denoted by h3, and the formula is: 0.05×h0≦h1+h2+ H3 ≦ 0.666 × h0, in other words, the notched rings 131, 132, 133 are not close to the active surface 111 and occupy less than two-thirds of the thickness of the semiconductor substrate 110, so the semiconductor substrate 110 can maintain a sufficient structure The strength does not affect the integrated circuit configuration of the active surface 111. Moreover, the dielectric liner 140 is filled into the recessed portions of the notched rings 131, 132, and 133. The outer opening 142 is not smaller than the inner opening 141. As shown in FIG. 4, the outer opening 142 has a radial hole. The area is denoted as T0, and the radial area of the hole of the inner opening 141 is denoted as W0, and the formula is: T0 ≧ W0, thereby effectively reducing the overhang hole edge of the semiconductor substrate 110 applied to the crystal back The stress of the bump 151.
在一較佳實施例中，該些缺口環131、132、133之凹陷部倒角係可不小於90度且不大於180度，可進一步減少對該晶背凸塊151之銳角應力作用，並有利於該電鍍種子層在該貫穿孔130之連續形成。並如第4圖所示，具體表現為，該第一缺口環131之覆蓋區域W1、該第二缺口環132之覆蓋區域W2、該第三缺口環133之覆蓋區域W3係皆可為不重疊地圍繞在該介電內襯140之該內開口141之孔徑向面積W0之外，該第一缺口環131之覆蓋區域W1係應不小於該第二缺口環132之覆蓋區域W2(W1≧W2)。此外，該第一缺口環131之凹陷部倒角係標示為α，該第二缺口環132之凹陷部倒角係標示為β，該第三缺口環133之凹陷部倒角係標示為γ，其算式為：90°≦α,β,γ≦180°。較佳地，該半導體基板110由該貫穿孔130之內孔壁至該內絕緣層114之截面夾角係不小於70度且不大於90度，如第4圖所示，該半導體基板110之孔壁 截面夾角θ係不小於70度且不大於90度(70°≦θ≦90°)，即該貫穿孔130之內孔壁本身即為往該背面112孔徑逐漸擴大之型態。 In a preferred embodiment, the notch chamfers of the notched rings 131, 132, and 133 may be not less than 90 degrees and not more than 180 degrees, which may further reduce the acute angle stress on the crystal back bumps 151, and is advantageous. The plating seed layer is continuously formed in the through hole 130. As shown in FIG. 4, the coverage area W1 of the first notch ring 131, the coverage area W2 of the second notch ring 132, and the coverage area W3 of the third notch ring 133 may not overlap. The coverage area W1 of the first notch ring 131 should be not less than the coverage area W2 of the second notch ring 132 (W1≧W2), except for the radial area W0 of the hole of the inner opening 141 of the dielectric liner 140. ). In addition, the chamfering of the recessed portion of the first notch ring 131 is denoted by α, the chamfer of the recessed portion of the second notched ring 132 is denoted by β, and the chamfer of the recessed portion of the third notched ring 133 is denoted by γ. Its formula is: 90 ° ≦ α, β, γ ≦ 180 °. Preferably, the semiconductor substrate 110 has an angle of not less than 70 degrees and no more than 90 degrees from the inner wall of the through hole 130 to the inner insulating layer 114. As shown in FIG. 4, the hole of the semiconductor substrate 110 wall The section angle θ is not less than 70 degrees and not more than 90 degrees (70° ≦ θ ≦ 90°), that is, the inner wall of the through hole 130 itself is a shape in which the aperture of the back surface 112 is gradually enlarged.
較佳地，再如第3圖所示，該介電內襯140係可完全填滿該些缺口環131、132、133之凹陷部，以提供一重塑形孔143，以使該填孔導體150填滿於該貫穿孔130之部位成為一具有連續壁面之細柱體，即該填孔導體150之壁面無彎折之凸緣或缺口，以利該電鍍種子層170在該貫穿孔130內之連續覆蓋面之形成，同時能減輕該填孔導體150之凹凸壁面對該半導體基板110之應力傷害。 Preferably, as shown in FIG. 3, the dielectric liner 140 can completely fill the recesses of the notch rings 131, 132, 133 to provide a reshaped hole 143 for the hole filling. The conductor 150 fills the portion of the through hole 130 to form a thin cylinder having a continuous wall surface, that is, a flange or a notch of the wall surface of the hole-filling conductor 150, so that the plating seed layer 170 is in the through hole 130. The formation of the continuous covering surface therein can reduce the stress damage of the concave-convex wall of the hole-filling conductor 150 facing the semiconductor substrate 110.
因此，本發明提供之一種具強固型晶背凸塊之矽穿孔結構，具備強固型晶背凸塊並解決了習知矽穿孔內電鍍空隙之缺陷，用以改善晶背凸塊下矽穿孔導體不耐用易於斷裂之問題。並且，本矽穿孔結構係能用以改善矽穿孔填充之製程窗(process window)，例如有較為彈性的電鍍時間達到貫穿孔之無空隙電鍍填滿，而達到較佳的矽穿孔製程良率。 Therefore, the present invention provides a crucible perforated structure with a strong crystal back bump, which has a strong crystal back bump and solves the defects of the plating void in the conventional crucible for improving the underlying conductor of the crystal back bump. It is not durable and easy to break. Moreover, the present perforated structure can be used to improve the process window of the perforated filling, for example, the more flexible plating time reaches the void-free plating filling of the through-hole, and the better the perforation process yield is achieved.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。 The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
10‧‧‧晶圓承載系統 10‧‧‧ Wafer Carrying System
100‧‧‧矽穿孔結構 100‧‧‧矽 perforated structure
110‧‧‧半導體基板 110‧‧‧Semiconductor substrate
111‧‧‧主動面 111‧‧‧Active surface
112‧‧‧背面 112‧‧‧Back
113‧‧‧晶背保護層 113‧‧‧ Crystal back protective layer
114‧‧‧內絕緣層 114‧‧‧Insulation
120‧‧‧銲墊 120‧‧‧ solder pads
130‧‧‧貫穿孔 130‧‧‧through holes
131‧‧‧第一缺口環 131‧‧‧First gap ring
132‧‧‧第二缺口環 132‧‧‧second notched ring
133‧‧‧第三缺口環 133‧‧‧ third notched ring
140‧‧‧介電內襯 140‧‧‧Dielectric lining
141‧‧‧內開口 Opening within 141‧‧
142‧‧‧外開口 142‧‧‧Outside opening
143‧‧‧重塑形孔 143‧‧‧Reshaped holes
150‧‧‧填孔導體 150‧‧‧filling conductor
151‧‧‧晶背凸塊 151‧‧‧ crystal back bump
160‧‧‧銲料 160‧‧‧ solder
170‧‧‧電鍍種子層 170‧‧‧Electroplating seed layer
Claims (9)
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Citations (5)
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|---|---|---|---|---|
| TW445552B (en) * | 1998-11-25 | 2001-07-11 | Applied Materials Inc | Structure and method for improving low temperature copper reflow in semiconductor features |
| TW201025544A (en) * | 2008-12-16 | 2010-07-01 | Powertech Technology Inc | Chip having TSV's, its forming method and a chip stack utilizing the chip |
| CN101965636A (en) * | 2008-03-07 | 2011-02-02 | 东京毅力科创株式会社 | Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer |
| TW201306213A (en) * | 2011-07-19 | 2013-02-01 | 矽品精密工業股份有限公司 | Through silicon via structure for impedance matching and electrical interconnection |
| WO2013142863A1 (en) * | 2012-03-23 | 2013-09-26 | Texas Instruments Incorporated | Through-silicon via filling |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW445552B (en) * | 1998-11-25 | 2001-07-11 | Applied Materials Inc | Structure and method for improving low temperature copper reflow in semiconductor features |
| CN101965636A (en) * | 2008-03-07 | 2011-02-02 | 东京毅力科创株式会社 | Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer |
| TW201025544A (en) * | 2008-12-16 | 2010-07-01 | Powertech Technology Inc | Chip having TSV's, its forming method and a chip stack utilizing the chip |
| TW201306213A (en) * | 2011-07-19 | 2013-02-01 | 矽品精密工業股份有限公司 | Through silicon via structure for impedance matching and electrical interconnection |
| WO2013142863A1 (en) * | 2012-03-23 | 2013-09-26 | Texas Instruments Incorporated | Through-silicon via filling |
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