TWI550520B - Memory card connector for electronic devices - Google Patents
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Description
本說明書之主題一般而言係有關於電子裝置之領域，更特定言之係有關於一種記憶卡及其之用於電子裝置的連接器。 The subject matter of this specification relates generally to the field of electronic devices, and more particularly to a memory card and connector therefor for electronic devices.
諸如膝上型電腦、平板計算裝置、電子式閱讀器、行動電話及相似裝置的電子裝置可包括用於可取出記憶卡，例如，安全數位(SD)記憶卡的連接器。SD卡具有若干操作上的限制。此外，SD卡的發展對於供應商而言為昂貴的。因此，使電子裝置接受SD卡之外的記憶卡的技術具實用性。 Electronic devices such as laptops, tablet computing devices, electronic readers, mobile phones, and the like may include connectors for removable memory cards, such as secure digital (SD) memory cards. The SD card has several operational limitations. In addition, the development of SD cards is expensive for suppliers. Therefore, the technique of causing an electronic device to accept a memory card other than the SD card has practicality.
依據本發明之一具體實施例，係特地提出一種電子裝置，其包含：一主體；一位在該主體中包含一開口用以接受一記憶卡的插座，其中該插座包含：一第一組之連接器，其經組配以與位在根據一第一標準組配的一記憶卡上的接腳連接；以及一第二組之連接器，其經組配以與位在根據一第二標準組配的一記憶卡上的接腳連接。 According to an embodiment of the present invention, an electronic device is specifically provided, comprising: a main body; a socket including an opening in the main body for accepting a memory card, wherein the socket comprises: a first group a connector that is configured to be coupled to a pin on a memory card that is assembled in accordance with a first standard; and a second set of connectors that are assembled to be in accordance with a second standard A pin connection on a memory card that is assembled.
100‧‧‧電子裝置 100‧‧‧Electronic devices
102‧‧‧處理器 102‧‧‧Processor
106‧‧‧核心 106‧‧‧ core
108‧‧‧快取記憶體 108‧‧‧Cache memory
112‧‧‧互連 112‧‧‧Interconnection
120‧‧‧系統硬體/記憶體控制器 120‧‧‧System hardware/memory controller
122‧‧‧處理器/記憶體控制器 122‧‧‧Processor/Memory Controller
124‧‧‧圖形處理器 124‧‧‧graphic processor
125‧‧‧邏輯 125‧‧‧Logic
126‧‧‧網路介面 126‧‧‧Internet interface
128‧‧‧匯流排結構 128‧‧‧ bus bar structure
130‧‧‧RF收發器 130‧‧‧RF Transceiver
132‧‧‧信號處理模組 132‧‧‧Signal Processing Module
134‧‧‧近場通訊無線電裝置 134‧‧‧ Near Field Communication Radio
136‧‧‧感應器/鍵板 136‧‧‧Sensor/Keyboard
138‧‧‧顯示器 138‧‧‧ display
140‧‧‧記憶體 140‧‧‧ memory
142‧‧‧作業系統 142‧‧‧ operating system
144‧‧‧系統呼叫介面模組 144‧‧‧System Call Interface Module
146‧‧‧通訊介面 146‧‧‧Communication interface
150‧‧‧檔案系統 150‧‧‧File System
152‧‧‧處理控制子系統 152‧‧‧Processing Control Subsystem
154‧‧‧硬體介面模組 154‧‧‧hard interface module
170‧‧‧控制器 170‧‧‧ Controller
172‧‧‧處理器 172‧‧‧ processor
174‧‧‧記憶體模組 174‧‧‧ memory module
178‧‧‧I/O介面 178‧‧‧I/O interface
210‧‧‧主體 210‧‧‧ Subject
220‧‧‧插座/連接器 220‧‧‧Socket/connector
230‧‧‧記憶卡/插座 230‧‧‧ Memory Card/Socket
240‧‧‧第一組連接器 240‧‧‧First set of connectors
250‧‧‧第二組連接器 250‧‧‧Second set of connectors
320‧‧‧單晶片系統 320‧‧‧Single wafer system
332‧‧‧安全數位介面 332‧‧‧Safe Digital Interface
334‧‧‧超高速二代介面 334‧‧‧Super high speed second generation interface
336‧‧‧通用快閃儲存介面 336‧‧‧Universal flash storage interface
340‧‧‧耦合感應器 340‧‧‧coupled sensor
510,515,520,525‧‧‧作業 510, 515, 520, 525 ‧ ‧ homework
600‧‧‧計算系統 600‧‧‧ Computing System
602‧‧‧中央處理單元 602‧‧‧Central Processing Unit
603‧‧‧電腦網路 603‧‧‧ computer network
604‧‧‧互連網路(或匯流排) 604‧‧‧Internet (or bus)
606‧‧‧晶片組 606‧‧‧ Chipset
608‧‧‧記憶體控制集線器 608‧‧‧Memory Control Hub
610‧‧‧記憶體控制器 610‧‧‧ memory controller
612‧‧‧記憶體 612‧‧‧ memory
614‧‧‧圖形介面 614‧‧‧ graphical interface
616‧‧‧顯示器裝置 616‧‧‧Display device
618‧‧‧集線器介面 618‧‧‧ Hub Interface
620‧‧‧輸入/輸出控制集線器 620‧‧‧Input/Output Control Hub
622‧‧‧匯流排 622‧‧‧ busbar
624‧‧‧周邊橋接器 624‧‧‧ perimeter bridge
626‧‧‧聲音裝置 626‧‧‧Sound device
628‧‧‧磁碟機 628‧‧‧Disk machine
630‧‧‧網路介面裝置 630‧‧‧Network interface device
700‧‧‧計算系統 700‧‧‧ Computing System
702,702-1~701-N‧‧‧處理器 702, 702-1~701-N‧‧‧ processor
704‧‧‧互連網路或匯流排 704‧‧‧Internet or bus
706,706-1~706-N‧‧‧處理器核心 706,706-1~706-N‧‧‧ processor core
708‧‧‧快取記憶體 708‧‧‧Cache memory
710‧‧‧路由器 710‧‧‧ router
712‧‧‧互連網路/匯流排 712‧‧‧Internet/bus
714‧‧‧記憶體 714‧‧‧ memory
716,716‧‧‧1級快取記憶體 716,716‧‧‧1 level cache memory
720‧‧‧處理器控制邏輯或單元 720‧‧‧Processor Control Logic or Unit
802‧‧‧提取單元 802‧‧‧ extraction unit
804‧‧‧解碼單元/匯流排 804‧‧‧Decoding unit/bus
806‧‧‧排程單元 806‧‧‧scheduling unit
808‧‧‧執行單元 808‧‧‧ execution unit
810‧‧‧回退單元 810‧‧‧Return unit
812‧‧‧匯流排 812‧‧‧ busbar
814‧‧‧匯流排單元 814‧‧‧ Busbar unit
816‧‧‧暫存器 816‧‧‧ register
902‧‧‧單晶片系統(SOC) 902‧‧‧Single Chip System (SOC)
920‧‧‧處理器核心 920‧‧‧ processor core
930‧‧‧圖形處理器核心 930‧‧‧Graphic Processor Core
940‧‧‧輸入/輸出介面 940‧‧‧Input/Output Interface
942‧‧‧記憶體控制器 942‧‧‧ memory controller
960‧‧‧記憶體 960‧‧‧ memory
970‧‧‧I/O裝置 970‧‧‧I/O device
1000‧‧‧計算系統 1000‧‧‧Computation System
1002,1004‧‧‧處理器 1002,1004‧‧‧ processor
1003‧‧‧電腦網路 1003‧‧‧ computer network
1006,1008‧‧‧局部記憶體控制器集線器 1006,1008‧‧‧Local Memory Controller Hub
1010,1012‧‧‧記憶體 1010, 1012‧‧‧ memory
1014,1022,1024‧‧‧點對點介面 1014, 1022, 1024‧‧‧ peer-to-peer interface
1016,1018‧‧‧PtP介面電路 1016,1018‧‧‧PtP interface circuit
1020‧‧‧晶片組 1020‧‧‧ chipsets
1026,1028,1030,1032‧‧‧點對點介面電路 1026, 1028, 1030, 1032‧‧‧ point-to-point interface circuits
1034‧‧‧高性能圖形電路 1034‧‧‧High performance graphics circuit
1036‧‧‧高性能圖形介面 1036‧‧‧High-performance graphical interface
1037,1041‧‧‧PtP介面電路 1037,1041‧‧‧PtP interface circuit
1040,1044‧‧‧匯流排 1040, 1044‧‧ ‧ busbar
1042‧‧‧匯流排橋接器 1042‧‧‧ Bus Bars
1043‧‧‧I/O裝置 1043‧‧‧I/O device
1045‧‧‧鍵盤/滑鼠 1045‧‧‧Keyboard/mouse
1046‧‧‧通訊裝置 1046‧‧‧Communication device
1048‧‧‧數據儲存裝置 1048‧‧‧Data storage device
1049‧‧‧編碼 1049‧‧‧ Code
參考該等伴隨的圖式說明較佳實施例詳細說 明。 Referring to the accompanying drawings, the preferred embodiment will be described in detail. Bright.
圖1係為根據一些實例適合於包括一記憶卡連接器的電子裝置之概略圖解。 1 is a diagrammatic illustration of an electronic device suitable for including a memory card connector in accordance with some examples.
圖2A-2D係為根據一些實例適合於包括一記憶卡連接器的電子裝置之一架構的概略圖解。 2A-2D are diagrammatic illustrations of one of the architectures of an electronic device suitable for including a memory card connector, according to some examples.
圖3-4係為根據一些實例適合於包括一記憶卡連接器的電子裝置之一架構的概略圖解。 3-4 is a diagrammatic illustration of an architecture suitable for one of the electronic devices including a memory card connector, according to some examples.
圖5係為根據一些實例的一流程圖，圖示應用電子裝置中的一記憶卡連接器之一方法的操作。 5 is an illustration of the operation of one of the methods of a memory card connector in an application electronic device, in accordance with a flow chart of some examples.
圖6-10係為根據一些實例適合於應用一記憶卡連接器之電子裝置的概略圖解。 6-10 are schematic illustrations of an electronic device suitable for applying a memory card connector in accordance with some examples.
本文所說明者係為於電子裝置中應用記憶卡連接器的示範系統及方法。於以下的說明中，提出複數的具體細節以提供不同實例的一徹底瞭解。然而，熟知此技藝之人士應瞭解的是能夠在無該等具體細節的狀況下實踐不同的實例。於其他的例子中，並未詳細地圖示或說明廣為熟知的方法、程序、組件及電路，俾以不致使該等特別的實例難理解。 The person illustrated herein is an exemplary system and method for applying a memory card connector in an electronic device. In the following description, specific details are set forth to provide a thorough understanding of the various examples. However, those skilled in the art should understand that various embodiments can be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits are not shown or described in detail so as not to obscure such particular examples.
圖1係為根據一些實例適合於包括一記憶卡連接器的電子裝置之概略圖解。首先參考圖1，於不同的實例中，電子裝置100可包括或是耦合至一或更多的伴隨輸入/輸出裝置，包括顯示器、一或更多的揚聲器、鍵盤、一或更多其他的I/O裝置、滑鼠、相機、或是相似裝置。其他的示範 I/O裝置可包括觸控式螢幕、聲音啟動輸入裝置、軌跡球、地理位置判定裝置、加速度計/陀螺儀、生物特徵輸入裝置、以及任何其他容許該電子裝置100接收來自於使用者的輸入。 1 is a diagrammatic illustration of an electronic device suitable for including a memory card connector in accordance with some examples. Referring first to FIG. 1, in various examples, electronic device 100 can include or be coupled to one or more accompanying input/output devices, including a display, one or more speakers, a keyboard, one or more other I /O device, mouse, camera, or similar device. Other demonstrations The I/O device can include a touch screen, a sound activated input device, a trackball, a geographic location determining device, an accelerometer/gyroscope, a biometric input device, and any other input that allows the electronic device 100 to receive input from a user. .
該電子裝置100包括系統硬體120及記憶體140，其可應用作為揮發性或是非揮發性隨機存取記憶體及/或非揮發性唯讀記憶體。檔案儲存可於通訊上耦合至電子裝置100。該檔案儲存可位於電子裝置100內部，諸如，例如，內嵌式多媒體卡(eMMC)、固態硬碟(SSD)、一或更多的硬碟，或是其他型式的儲存裝置。可交替地，該檔案儲存亦可位於電子裝置100外部，諸如，例如，一或更多的外部硬碟，網路附裝儲存、或是一個別的儲存網路。 The electronic device 100 includes a system hardware 120 and a memory 140 that can be applied as a volatile or non-volatile random access memory and/or a non-volatile read-only memory. The file storage can be communicatively coupled to the electronic device 100. The file storage can be internal to the electronic device 100, such as, for example, an embedded multimedia card (eMMC), a solid state drive (SSD), one or more hard disks, or other types of storage devices. Alternatively, the file storage may also be external to the electronic device 100, such as, for example, one or more external hard drives, network attached storage, or another storage network.
系統硬體120可包括一或更多的處理器122、圖形處理器124、網路介面126、以及匯流排結構128。於一具體實施例中，處理器122可具體化為由位於美國加州聖塔克拉拉(Santa Clara)的Intel公司販售的Intel® AtomTM基單晶片系統(SOC)或Intel® Core2 Duo®或i3/i5/i7系列處理器。如於本文中使用，該用語“處理器”意指任何類型的計算元件，諸如但未限制在，微處理器、微控制器、複雜指令集計算(CISC)微處理器、精簡指令集(RISC)微處理器、極長指令字組(VLIW)微處理器、或是任何其他類型的處理器或處理電路。 System hardware 120 can include one or more processors 122, graphics processor 124, network interface 126, and bus structure 128. In one particular embodiment, the processor 122 may be embodied in Santa Clara, California (Santa Clara) of Intel Corporation sold Intel® Atom TM yl single wafer system (SOC) or Intel® Core2 Duo® or I3/i5/i7 series processor. As used herein, the term "processor" means any type of computing element such as, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC). A microprocessor, very long instruction set (VLIW) microprocessor, or any other type of processor or processing circuit.
圖形處理器124可使用作為管理圖形及/或視訊作業的輔助處理器。圖形處理器124可整合在電子裝置100 之母板上或可經由一位在母板上的擴充插槽耦合，或可位設在相同晶粒或相同封裝上作為該處理單元。 Graphics processor 124 can be used as an auxiliary processor for managing graphics and/or video jobs. The graphics processor 124 can be integrated in the electronic device 100 The motherboard may be coupled via one of the expansion slots on the motherboard, or may be located on the same die or the same package as the processing unit.
於一具體實施例中，網路介面126可為一有線的介面，諸如乙太網路介面(見，例如，電氣及電子工程師學會/IEEE 802.3-2002)或是一無線介面，諸如一IEEE 802.11a，b或g相容介面(見，例如，用於系統LAN/MAN之間資訊科技(IT)-電信及資訊交換的IEEE標準-Part II：無線LAN介質存取控制(MAC)及實體層(PHY)規格修訂4：2.4GHz頻帶內進一步更高數據率擴展，802.11G-2003)。無線介面的另一個實例可為一般封包式無線電服務(GPRS)介面(見，例如，GPRS手機要求指南，行動通訊全球系統/GSM協會，Ver.3.0.1，2002年12月)。 In one embodiment, the network interface 126 can be a wired interface, such as an Ethernet interface (see, for example, the Institute of Electrical and Electronics Engineers/IEEE 802.3-2002) or a wireless interface, such as an IEEE 802.11. a, b or g compatible interface (see, for example, information technology (IT) for system LAN/MAN - IEEE standard for telecommunications and information exchange - Part II: Wireless LAN Media Access Control (MAC) and physical layer (PHY) Specification Revision 4: Further higher data rate expansion in the 2.4 GHz band, 802.11G-2003). Another example of a wireless interface may be the General Packet Radio Service (GPRS) interface (see, for example, GPRS Handset Requirements Guide, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).
匯流排結構128連接系統硬體128的不同組件。於一具體實施例中，匯流排結構128可為一或更多之複數種類的匯流排結構，包括記憶體匯流排、周邊匯流排或外部匯流排、及/或使用任意可用匯流排架構的局部匯流排，包括但未限制在，11位元匯流排、工業標準架構(ISA)、微通道架構(MSA)、擴展ISA(EISA)、智能驅動電子裝置(IDE)、VESA局部匯流排(VLB)、周邊組件互連(PCI)、通用序列匯流排(USB)、先進圖形埠(AGP)、個人電腦記憶卡國際協會匯流排(PCMCIA)、及小型電腦系統界面(SCSI)，高速同步序列介面(HSI)、序列低功耗晶片間媒體匯流排(SLIMbus®)，或相似者。 The busbar structure 128 connects the different components of the system hardware 128. In one embodiment, the bus bar structure 128 can be one or more of a plurality of types of bus bar structures, including a memory bus bar, a peripheral bus bar or an external bus bar, and/or a portion using any available bus bar architecture. Bus, including but not limited to, 11-bit bus, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB) Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Advanced Graphics (AGP), Personal Computer Memory Card International Association Bus (PCMCIA), and Small Computer System Interface (SCSI), High Speed Synchronous Sequence Interface ( HSI), sequential low-power inter-wafer media bus (SLIMbus®), or similar.
電子裝置100可包括一RF收發器130發送RF信號、 近場通訊(NFC)無線電裝置134、以及一信號處理模組132處理由RF收發器130接收的信號。RF收發器可經由一協定施作一局部無線連接，諸如，例如，藍芽或802.11X、IEEE 802.11a，b或g相容介面(見，例如，用於系統LAN/MAN之間資訊科技(IT)-電信及資訊交換的IEEE標準-Part II：無線LAN介質存取控制(MAC)及實體層(PHY)規格修訂4：2.4GHz頻帶內進一步更高數據率擴展，802.11G-2003)。無線介面的另一個實例可為寬頻多重分碼存取(WCDMA)、長期演進行動通信系統(LTE)、一般封包式無線電服務(GPRS)介面(見，例如，GPRS手機要求指南，行動通訊全球系統/GSM協會，Ver.3.0.1，2002年12月)。 The electronic device 100 can include an RF transceiver 130 to transmit an RF signal, A near field communication (NFC) radio 134, and a signal processing module 132 process the signals received by the RF transceiver 130. The RF transceiver can be implemented as a partial wireless connection via a protocol such as, for example, Bluetooth or 802.11X, IEEE 802.11a, b or g compatible interface (see, for example, for information technology between system LAN/MAN ( IT) - IEEE Standard for Telecommunications and Information Exchange - Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification Revision 4: Further higher data rate extensions in the 2.4 GHz band, 802.11G-2003). Another example of a wireless interface may be wideband multiple code access (WCDMA), long term evolution mobile communication system (LTE), general packet radio service (GPRS) interface (see, for example, GPRS handset requirements guide, mobile communications global system) /GSM Association, Ver.3.0.1, December 2002).
電子裝置100可進一步包括一或更多的感應器136，諸如熱感應器、耦合感應器、或是相似者。電子裝置100可進一步包括一或更多的輸入/輸出介面諸如，例如，鍵板(keypad)136及顯示器138。於一些實例中，電子裝置100可不具鍵板以及使用觸控板輸入。 The electronic device 100 can further include one or more sensors 136, such as a thermal sensor, a coupled inductor, or the like. The electronic device 100 may further include one or more input/output interfaces such as, for example, a keypad 136 and a display 138. In some examples, the electronic device 100 may have no keypad and input using a touchpad.
記憶體140可包括一作業系統142用於管理電子裝置100之作業。於一具體實施例中，作業系統142包括一硬體介面模組154，對系統硬體120提供一介面。此外，作業系統140可包括一管理在電子裝置100之作業中所使用之檔案的檔案系統150，以及一管理在電子裝置100上執行的處理之處理控制子系統152。 The memory 140 can include an operating system 142 for managing the operations of the electronic device 100. In one embodiment, the operating system 142 includes a hardware interface module 154 that provides an interface to the system hardware 120. In addition, operating system 140 can include a file system 150 that manages files used in the operation of electronic device 100, and a process control subsystem 152 that manages the processes performed on electronic device 100.
作業系統142可包括(或管理)一或更多個通訊介面146，其可與系統硬體120結合以收發來自於一遠端來源 的數據封包及/或數據流。作業系統142可進一步包括一系統呼叫介面模組144，提供介於該作業系統142與常駐在記憶體130中的一或更多個應用模組之間的一介面。作業系統142可具體化為一UNIX作業系統或其之任一衍生系統(例如，Linux，Android等)或是Window®品牌作業系統，或是其他的作業系統。 Operating system 142 can include (or manage) one or more communication interfaces 146 that can be coupled with system hardware 120 for transceiving from a remote source Data packets and/or data streams. The operating system 142 can further include a system call interface module 144 that provides an interface between the operating system 142 and one or more application modules resident in the memory 130. The operating system 142 can be embodied as a UNIX operating system or any of its derivatives (eg, Linux, Android, etc.) or a Window® brand operating system, or other operating system.
於一些實例中，一電子裝置可包括一控制器170，其可包含一或更多的與該主要執行環境分開的控制器。該分開可為物理性的，其意義上該控制器可在與該等主要處理器實體上分開的控制器中施用。可交替地，該可信任的執行環境可為邏輯性的，其意義上該控制器可寄存在寄存該等主要處理器的相同晶片或是晶片組上。 In some examples, an electronic device can include a controller 170 that can include one or more controllers separate from the primary execution environment. The separation may be physical in the sense that the controller may be applied in a separate controller from the primary processor entities. Alternatively, the trusted execution environment can be logical in the sense that the controller can be hosted on the same wafer or chipset hosting the primary processors.
經由實例，於一些實例中，該控制器170可施用作為位設在該電子裝置100之該母板上的一獨立積體電路，例如，作為一位在該相同的SOC晶粒上之專用的處理器塊。於其他的實例中，該信任的執行引擎可使用硬體增強機構在與該(等)處理器之其他者分離的該(等)處理器122的一部分上施用。 By way of example, in some examples, the controller 170 can be applied as a separate integrated circuit disposed on the motherboard of the electronic device 100, for example, as a bit dedicated to the same SOC die. Processor block. In other examples, the trusted execution engine can be applied on a portion of the processor 122 that is separate from the other of the processor(s) using a hardware enhancement mechanism.
於圖1中圖示的該具體實施例中，該控制器170包含一處理器172、一記憶體模組174、以及一I/O介面178。於一些實例中，該記憶體模組174可包含一持續性快閃記憶體模組，並且不同的功能性模組可施用作為於該持續性記憶體模組中編碼的邏輯指令，例如，韌體或軟體。該I/O模組178可包含一序列I/O模組或是一平行I/O模組。由於該控 制器170係與該(等)主要處理器122及作業系統142分開，該控制器170可構成為具安全性，亦即，對於典型地由該主機處理器122安裝軟體攻擊之駭客為不可接取的。 In the specific embodiment illustrated in FIG. 1, the controller 170 includes a processor 172, a memory module 174, and an I/O interface 178. In some examples, the memory module 174 can include a persistent flash memory module, and different functional modules can be applied as logic instructions encoded in the persistent memory module, for example, tough Body or software. The I/O module 178 can include a sequence of I/O modules or a parallel I/O module. Due to the control The controller 170 is separate from the main processor 122 and the operating system 142. The controller 170 can be constructed to be secure, that is, for a hacker who typically attacks the software installed by the host processor 122. Pick up.
圖2A-2D係為根據一些實例適合於包括一記憶卡連接器的電子裝置之一架構的概略圖解。圖2A係為根據一些實例適合於包括一記憶卡連接器的一電子裝置之一側視圖的一概略圖解。參考圖2A，於一些實例中，一電子裝置100包含一主體210，其可為一單一部分外殼210或是一多部分外殼210。主體210可由一適合的剛性材料構成，例如，一聚合物、金屬或是相同材料。主體210可包含一或更多的插座220用以接受一記憶卡230。例如，該記憶卡230可施作為一安全數位(SD)記憶卡或是作為一通用快閃儲存(UFS)記憶卡。在以下的網址處可在網際網路找到針對SD記憶卡的標準：https：//www.sdcard.org/home/，https：//www.sdcard.org/developers/overview/family/。可在網址https：//jedec.org/standards-documents/focus/flash/universal-flash-storage-ufs找到針對UFS記憶卡的標準。 2A-2D are diagrammatic illustrations of one of the architectures of an electronic device suitable for including a memory card connector, according to some examples. 2A is a diagrammatic illustration of a side view of one of an electronic device suitable for including a memory card connector, according to some examples. Referring to FIG. 2A, in some examples, an electronic device 100 includes a body 210 that can be a single portion of the housing 210 or a multi-part housing 210. Body 210 can be constructed of a suitable rigid material, such as a polymer, metal, or the like. The body 210 can include one or more receptacles 220 for accepting a memory card 230. For example, the memory card 230 can be implemented as a secure digital (SD) memory card or as a universal flash memory (UFS) memory card. The standard for SD memory cards can be found on the Internet at https://www.sdcard.org/home/, https://www.sdcard.org/developers/overview/family/. The standard for UFS memory cards can be found at https://jedec.org/standards-documents/focus/flash/universal-flash-storage-ufs.
圖2B係為圖2A中所圖示的該插座220的一展開圖。於圖4B中所圖示的該實例中，圖解針對第一組之連接器240及第二組連接器250的一佈置。於圖2B中所圖示的該實例中，位在該插座220之該第一側邊上的該第一組連接器240可經組配與位在一安全數位(SD)記憶卡上的接腳連接，同時該第二組連接器250可經組配與位在通用快閃儲存(UFS)記憶卡上的接腳連接。 2B is an expanded view of the socket 220 illustrated in FIG. 2A. In the example illustrated in FIG. 4B, an arrangement for the first set of connectors 240 and the second set of connectors 250 is illustrated. In the example illustrated in FIG. 2B, the first set of connectors 240 located on the first side of the socket 220 can be assembled and interfaced on a secure digital (SD) memory card. The feet are connected while the second set of connectors 250 can be assembled to be connected to pins located on a Universal Flash Storage (UFS) memory card.
熟知此技藝之人士將確認的是該第一組連接器 140與該第二組連接器多少係為任意的並且能夠為相反的，以致位在該插座220之該第一側邊上的該等連接器240可經組配以與位在一通用快閃儲存(UFS)記憶卡上的接腳連接，同時該第二組連接器可經組配以與位在一安全數位(SD)記憶卡上的接腳連接。 Those skilled in the art will recognize the first set of connectors 140 and the second set of connectors are somewhat arbitrary and can be reversed such that the connectors 240 positioned on the first side of the receptacle 220 can be assembled to be in a universal flash A pin connection on the storage (UFS) memory card, and the second set of connectors can be assembled to connect to a pin on a secure digital (SD) memory card.
圖2C係為於圖2B中圖示的該連接器220的一俯視圖。如於圖2C中所圖示，該第二組連接器250可以一或更多列之方式佈置，為了建立與一SD卡上的該等接腳連接。圖2D係為於圖2B中圖示的該連接器220的一俯視圖。如於圖2D中所圖示，該第二組連接器250可以一或更多列之方式佈置，為了建立與一SD卡上的該等接腳連接。 2C is a top plan view of the connector 220 illustrated in FIG. 2B. As illustrated in Figure 2C, the second set of connectors 250 can be arranged in one or more columns in order to establish a connection to the pins on an SD card. 2D is a top plan view of the connector 220 illustrated in FIG. 2B. As illustrated in Figure 2D, the second set of connectors 250 can be arranged in one or more columns in order to establish connection to the pins on an SD card.
圖3-4係為根據一些實例適合於包括一記憶卡連接器(TDP)的電子裝置之一架構的概略圖解。首先參考圖3，於一些實例中，該插座220包含一第一組連接器240，其經組配以與位在根據一第一標準的一記憶卡上的接腳連接，以及一第二組連接器250，其經組配以與位在根據一第二標準的一記憶卡上的接腳連接。 3-4 is a diagrammatic illustration of an architecture suitable for one of the electronic devices including a memory card connector (TDP), according to some examples. Referring first to Figure 3, in some examples, the socket 220 includes a first set of connectors 240 that are assembled to interface with pins on a memory card in accordance with a first standard, and a second set A connector 250 is assembled to connect to a pin located on a memory card in accordance with a second standard.
於一些實例中，位在第一組連接器240上的其中之一連接器可耦合至一安全數位(SD)介面332，同時位在第一組連接器240上的另一連接器可耦合至一超高速二代(UHS-II)介面334。再者，位在第二組連接器250上的其中之一連接器可耦合至一通用快閃儲存(UFS)介面336。該等各別的介面332、334、336可耦合至一處理裝置諸如一處理器或是一單晶片系統(SOC)320。 In some examples, one of the connectors on the first set of connectors 240 can be coupled to a secure digital (SD) interface 332, while another connector on the first set of connectors 240 can be coupled to A super high speed second generation (UHS-II) interface 334. Moreover, one of the connectors located on the second set of connectors 250 can be coupled to a Universal Flash Storage (UFS) interface 336. The respective interfaces 332, 334, 336 can be coupled to a processing device such as a processor or a single chip system (SOC) 320.
於一些實例中，一耦合感應器340可與該插座230結合以探測記憶卡何時***該插座230。經由實例，該耦合感應器340可包含一機械式開關，該開關係在記憶卡***該插座220時觸動。於一些實例中，耦合感應器340可為電氣電路，感應卡***該插座220之探測。 In some examples, a coupled inductor 340 can be coupled to the receptacle 230 to detect when the memory card is inserted into the receptacle 230. By way of example, the coupled inductor 340 can include a mechanical switch that is activated when the memory card is inserted into the receptacle 220. In some examples, the coupling inductor 340 can be an electrical circuit into which the proximity card is inserted into the socket 220 for detection.
簡要地參考圖4，於一些實例中，位在該SD卡上的該UHS-II介面及該UFS介面可結合成一單一介面334。於該等實例中，一或更多的連接器240可與一或更多的連接器250電氣地連接，例如，經由一跳線器或是其他的電氣連接器。 Referring briefly to FIG. 4, in some examples, the UHS-II interface and the UFS interface located on the SD card can be combined into a single interface 334. In such examples, one or more connectors 240 can be electrically coupled to one or more connectors 250, such as via a jumper or other electrical connector.
已說明一系統施用供電子裝置所用的一記憶卡連接器的不同結構，將參考圖5解釋系統的操作觀點，該圖係為根據一些實例的一流程圖，圖示施用電子裝置中的一記憶卡連接器之一方法的操作。於圖5之該流程圖中圖示的該等作業可藉由該處理器/SOC 320，獨自地或是結合電子裝置100的其他組件施用。 Having described a different configuration of a system for applying a memory card connector for an electronic device, an operational view of the system will be explained with reference to FIG. 5, which is a flow chart illustrating a memory in the application electronic device, according to some examples. The operation of one of the card connectors. The operations illustrated in the flow chart of FIG. 5 may be applied by the processor/SOC 320, either alone or in combination with other components of the electronic device 100.
參考圖5，於一些實例中，該處理器/SOC 320監控該(等)耦合感應器以判定記憶卡230是否已***該插座220中。因此，於作業510，該處理器/SOC 320接收來自於該耦合感應器340的數據輸出。 Referring to FIG. 5, in some examples, the processor/SOC 320 monitors the (etc.) coupled sensor to determine if the memory card 230 has been inserted into the outlet 220. Accordingly, at job 510, the processor/SOC 320 receives the data output from the coupled inductor 340.
於作業515，判定是否發生耦合情況。例如，假若在作業515該耦合感應器340之輸出指示記憶卡230已***該插座220，則該耦合感應器之輸出將指示已發生耦合情況。假若由於自該耦合感應器340接收的最後數據耦合未發 生，則控制回到作業510以及該處理器/SOC 320持續監控該感應器340。 At job 515, a determination is made as to whether a coupling has occurred. For example, if the output of the coupled sensor 340 at operation 515 indicates that the memory card 230 has been inserted into the outlet 220, the output of the coupled sensor will indicate that a coupling has occurred. If the last data coupling received from the coupled inductor 340 is not sent Raw, control is returned to job 510 and the processor/SOC 320 continuously monitors the sensor 340.
相比之下，假若在作業515該耦合感應器340之輸出指示已發生耦合情況，則控制跳到作業520。於作業520，該處理器/SOC 320判定***該插座220的記憶卡230之型式。經由實例，假若於作業515在該記憶卡230與該第一組連接器240之間建立連接，則該卡型式可判定為SD卡。相比之下，假若於作業515在該記憶卡230與該第一組連接器240之間建立連接，則該卡型式可判定為UFS卡。 In contrast, if the output of the coupled inductor 340 indicates that a coupling condition has occurred at job 515, then control jumps to job 520. At job 520, the processor/SOC 320 determines the type of memory card 230 inserted into the outlet 220. By way of example, if the job 515 establishes a connection between the memory card 230 and the first set of connectors 240, the card type can be determined to be an SD card. In contrast, if the job 515 establishes a connection between the memory card 230 and the first set of connectors 240, the card type can be determined to be a UFS card.
於作業525，該處理器/SOC 320依據可與該記憶卡230交換的數據和該記憶卡230開始通訊對話。 At job 525, the processor/SOC 320 initiates a communication session with the memory card 230 based on data exchanged with the memory card 230.
如以上所說明，於一些實例中，該電子裝置可具體化為一電腦系統。圖6圖示根據一實例的一計算系統600的一方塊圖。該計算系統600可包括一或更多個經由一互連網路(或匯流排)604通訊的中央處理單元602或處理器。該等處理器602可包括一個一般用途的處理器、一網路處理器(處理經由一電腦網路603通訊的數據)，或是其他型式的處理器(包括精簡指令集(RISC)處理器或是複雜指令集計算(CISC)處理器)。此外，該等處理器602可具有一單一或是多核心設計。具有多核心設計的該等處理器602可整合位在相同的積體電路(IC)晶粒上不同類型的處理器核心。同時，具有一多核心設計的該等處理器602可施用作為對稱或是非對稱的多重處理器。於一實例中，一或更多的處理器602可為與圖1之該等處理器102相同或是相似的。例如，一或更 多的處理器602可包括參考圖1-3論及的控制單元120。同時，參考圖3-5論及的該等作業可藉由該系統600之一或更多的組件執行。 As explained above, in some examples, the electronic device can be embodied as a computer system. FIG. 6 illustrates a block diagram of a computing system 600 in accordance with an example. The computing system 600 can include one or more central processing units 602 or processors that communicate via an interconnected network (or bus) 604. The processors 602 can include a general purpose processor, a network processor (processing data communicated via a computer network 603), or other types of processors (including a reduced instruction set (RISC) processor or It is a Complex Instruction Set Computing (CISC) processor. Moreover, the processors 602 can have a single or multi-core design. The processors 602 having a multi-core design can integrate different types of processor cores on the same integrated circuit (IC) die. At the same time, the processors 602 having a multi-core design can be applied as a symmetric or asymmetric multiprocessor. In one example, one or more processors 602 may be the same or similar to the processors 102 of FIG. For example, one or more The plurality of processors 602 can include the control unit 120 discussed with reference to Figures 1-3. At the same time, such operations as discussed with reference to Figures 3-5 may be performed by one or more components of the system 600.
晶片組606亦可與互連網路604通訊。該晶片組606可包括一記憶體控制集線器(MCH)608。該MCH 608可包括一與一記憶體612(其可與圖1之該記憶體130相同或是相似)通訊的記憶體控制器610。該記憶體412可儲存數據，包括指令序列，可由該處理器602，或是任何於該計算系統中包括的其他裝置執行。於一實例中，該記憶體612可包括一或更多的揮發性儲存(或記憶體)裝置諸如隨機存取記憶體(RAM)、動態RAM(DRAM)、同步DRAM(SDRAM)、靜態RAM(SRAM)、或其他類型的儲存裝置。諸如硬碟的非揮發性記憶體亦可使用。附加的裝置可經由該互連網路604通訊，諸如多重處理器及/或多重系統記憶體。 Wafer set 606 can also be in communication with interconnect network 604. The chipset 606 can include a memory control hub (MCH) 608. The MCH 608 can include a memory controller 610 in communication with a memory 612 (which can be the same as or similar to the memory 130 of FIG. 1). The memory 412 can store data, including sequences of instructions, that can be executed by the processor 602, or by any other device included in the computing system. In one example, the memory 612 can include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM ( SRAM), or other types of storage devices. Non-volatile memory such as a hard disk can also be used. Additional devices may communicate via the interconnection network 604, such as multiple processors and/or multiple system memories.
該MCH 608亦可包括一與一顯示器裝置616通訊的圖形介面614。於一實例中，該圖形介面614可經由一加速圖形埠(AGP)與該顯示器裝置616通訊。於一實例中，該顯示器裝置616(諸如一平面顯示器)可經由，例如，一信號轉換器與圖形介面614通訊，該信號轉換器將儲存在一諸如視訊記憶體或系統記憶體的儲存裝置中的一圖像之數位表現轉譯成由該顯示器616解譯並顯示的顯示信號。由該顯示器裝置產生的該等顯示信號可在由該顯示器616解譯並接續地在該顯示器616上顯示之前通過不同的控制裝置。 The MCH 608 can also include a graphical interface 614 that communicates with a display device 616. In one example, the graphical interface 614 can communicate with the display device 616 via an accelerated graphics (AGP). In one example, the display device 616 (such as a flat panel display) can communicate with the graphical interface 614 via, for example, a signal converter that will be stored in a storage device such as a video memory or system memory. The digital representation of an image is translated into a display signal that is interpreted and displayed by the display 616. The display signals generated by the display device can pass through different control devices before being interpreted by the display 616 and subsequently displayed on the display 616.
集線器介面618可容許該MCH 608及一輸入/輸 出控制集線器(ICH)620通訊。該ICH 620可對與該計算系統600通訊的I/O裝置提供一介面。該ICH 620可經由一周邊橋接器(或控制器)624，諸如一周邊組件互連(PCI)橋接器、一通用序列匯流排(USB)控制器，或是其他類型之周邊橋接器或控制器與一匯流排622通訊。該橋接器624可於該處理器602與周邊裝置之間提供一數據路徑。可使用其他類型的網路佈局。同時，多重匯流排可與該ICH 620通訊，例如，經由多重橋接器或控制器。此外，與該ICH 620通訊的其他周邊裝置可包括，於不同的實例中，整合驅動電子電路(IDE)或是小型電腦系統介面(SCSI)硬碟、USB埠、鍵盤、滑鼠、平行埠、序列埠、軟碟機、數位輸出支援(例如，數位視訊介面(DVI))、或其他裝置。 The hub interface 618 can tolerate the MCH 608 and an input/output Out of Control Hub (ICH) 620 communication. The ICH 620 can provide an interface to I/O devices that are in communication with the computing system 600. The ICH 620 can be via a peripheral bridge (or controller) 624, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other type of perimeter bridge or controller Communicate with a bus 622. The bridge 624 can provide a data path between the processor 602 and peripheral devices. Other types of network layouts can be used. At the same time, multiple busses can communicate with the ICH 620, for example, via multiple bridges or controllers. In addition, other peripheral devices communicating with the ICH 620 may include, in different instances, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drives, USB ports, keyboards, mice, parallel ports, Serial port, floppy disk, digital output support (for example, Digital Video Interface (DVI)), or other devices.
該匯流排622可與聲音裝置626、一或更多個磁碟機628及一網路介面裝置630(其係與該電腦網路603通訊)通訊。其他裝置可經由該匯流排622通訊。同時，於一些實例中，各種組件(諸如該網路介面裝置630)可與該MCH 608通訊。此外，該處理器602及本文中所論及的一或更多的其他組件可經結合以形成一單一晶片(例如，提供一單晶片系統(SOC))。再者，於其他實例中，該圖形加速器616可包括在該MCH 608中。 The busbar 622 can be in communication with the sound device 626, one or more disk drives 628, and a network interface device 630 that is in communication with the computer network 603. Other devices can communicate via the bus bar 622. Also, in some examples, various components, such as the network interface device 630, can communicate with the MCH 608. Moreover, the processor 602 and one or more other components discussed herein can be combined to form a single wafer (e.g., to provide a single wafer system (SOC)). Again, in other examples, the graphics accelerator 616 can be included in the MCH 608.
再者，該計算系統600可包括揮發性及/或非揮發性記憶體(或儲存裝置)。例如，非揮發性記憶體可包括下列一或更多個裝置：唯讀記憶體(ROM)、可程式化ROM(PROM)、可抹除PROM(EPROM)、電氣EPROM(EEPROM)、 磁碟機(例如，628)、軟碟機、光碟ROM(CD-ROM)、多功能數位光碟(DVD)、快閃記憶體、磁光碟、或者能夠儲存電子數據(例如，包括指令)的其他類型的非揮發性機器可讀取媒體。 Moreover, the computing system 600 can include volatile and/or non-volatile memory (or storage devices). For example, the non-volatile memory may include one or more of the following: a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrical EPROM (EEPROM), Disk drive (eg, 628), floppy disk drive, compact disc ROM (CD-ROM), multi-function digital compact disc (DVD), flash memory, magneto-optical disc, or other capable of storing electronic data (eg, including instructions) Types of non-volatile machines can read media.
圖7圖示根據一實例的一計算系統700的一方塊圖。該系統700可包括一或更多的處理器702-1至702-N(一般而言於本文視為“複數處理器702”或“處理器702”)。該等處理器702可經由一互連網路或匯流排704通訊。每一處理器可包括各種組件，為了清晰起見僅相關於處理器702-1討論其中一些組件。因此，剩餘的處理器702-2至702-N之每一者可包括相關於處理器702-1討論的相同或是相似的組件。 FIG. 7 illustrates a block diagram of a computing system 700 in accordance with an example. The system 700 can include one or more processors 702-1 through 702-N (generally referred to herein as "complex processor 702" or "processor 702"). The processors 702 can communicate via an internetwork or bus 704. Each processor may include various components, some of which are discussed with respect to processor 702-1 for clarity only. Thus, each of the remaining processors 702-2 through 702-N may include the same or similar components discussed with respect to processor 702-1.
於一實例中，該處理器702-1可包括一或更多的處理器核心706-1至706-N(本文中視為“複數核心706”或是更一般而言為“核心706”)，一共享的快取記憶體708、一路由器710、及/或一處理器控制邏輯或單元720。該處理器核心706可施用在一單一積體電路(IC)晶片上。此外，該晶片可包括一或更多的共享及/或私用快取記憶體(諸如快取記憶體708)、匯流排或互連(諸如匯流排或是互連網路712)、記憶體控制器或是其他的組件。 In one example, the processor 702-1 can include one or more processor cores 706-1 through 706-N (referred to herein as "plural core 706" or more generally "core 706"). A shared cache 708, a router 710, and/or a processor control logic or unit 720. The processor core 706 can be applied to a single integrated circuit (IC) wafer. In addition, the wafer may include one or more shared and/or private cache memories (such as cache memory 708), busbars or interconnects (such as busbars or interconnected network 712), memory controllers. Or other components.
於一實例中，該路由器710可作為該處理器702-1之不同的組件及/或系統700之間通訊所用。此外，該處理器702-1可包括一個以上的路由器710。再者，複數之路由器710可經通訊以使該處理器702-1之內或外部的不同組件 之間能夠作數據路由(data routing)。 In one example, the router 710 can be used as a communication between different components of the processor 702-1 and/or system 700. Additionally, the processor 702-1 can include more than one router 710. Moreover, the plurality of routers 710 can communicate to cause different components within or external to the processor 702-1. Can be used for data routing.
該共享的快取記憶體708可儲存能夠由該處理器702-1之一或更多的組件，諸如該等核心706，所使用的數據(例如，包括指令)。例如，該共享的快取記憶體708可局部地緩存儲存在一記憶體714中的數據，以供該處理器702之組件更快速存取。於一實例中，該快取記憶體708可包括一中級快取記憶體(諸如2級(L2)、3級(L3)、4級(L4)或其他級之快取記憶體)、末級快取記憶體(LLC)及/或其之結合。此外，該處理器702-1之不同組件可經由一匯流排(例如，匯流排712)、及/或一記憶體控制器或集線器，直接地與該共享快取記憶體708通訊。如圖7中所示，於一些實例中，該等核心706中的一或更多個可包括一1級(L1)快取記憶體716-1(一般而言視為“L1快取記憶體716”)。於一實例中，該控制單元720可包括邏輯以施作上述參考圖2中該記憶體控制器122所說明的該等作業。 The shared cache 708 can store data (eg, including instructions) that can be used by one or more components of the processor 702-1, such as the cores 706. For example, the shared cache 708 can locally cache data stored in a memory 714 for faster access by components of the processor 702. In an example, the cache memory 708 can include an intermediate cache memory (such as level 2 (L2), level 3 (L3), level 4 (L4) or other level of cache memory), and final stage. Cache memory (LLC) and/or combinations thereof. In addition, different components of the processor 702-1 can communicate directly with the shared cache 708 via a bus (eg, bus 712), and/or a memory controller or hub. As shown in FIG. 7, in some examples, one or more of the cores 706 may include a level 1 (L1) cache memory 716-1 (generally referred to as "L1 cache memory" 716"). In one example, the control unit 720 can include logic to perform the operations described above with respect to the memory controller 122 of FIG.
圖8圖示根據一實例之部分的處理器核心706及一計算系統的其他組件的一方塊圖。於一實例中，圖8中所顯示的箭頭圖示通過該核心706的指令之流程方向。一或更多的處理器核心(諸如該處理器核心706)可施用在一單一積體電路晶片(或晶粒)上，諸如參考圖7所論及者。此外，該晶片可包括一或更多的共享及/或私用快取記憶體(例如，圖7之快取記憶體708)、互連(例如，圖7之互連704及112)、控制單元、記憶體控制器或是其他組件。 FIG. 8 illustrates a block diagram of processor core 706 and other components of a computing system in accordance with an example portion. In one example, the arrows shown in FIG. 8 illustrate the flow direction of instructions through the core 706. One or more processor cores, such as the processor core 706, can be applied to a single integrated circuit die (or die), such as those discussed with reference to FIG. Additionally, the wafer may include one or more shared and/or private cache memories (eg, cache memory 708 of FIG. 7), interconnects (eg, interconnects 704 and 112 of FIG. 7), control Unit, memory controller or other component.
如於圖8中所示，該處理器核心706可包括一提取 單元802以提取供該核心706執行的指令(包括具有條件分支的指令)。該等指令可由諸如記憶體714的任何儲存裝置提取。該核心706亦可包括一解碼單元804以解碼該提取的指令。例如，該解碼單元804可將該提取指令解碼成複數之微操作(uop)。 As shown in FIG. 8, the processor core 706 can include an extraction Unit 802 extracts instructions (including instructions with conditional branches) for execution by the core 706. These instructions may be extracted by any storage device such as memory 714. The core 706 can also include a decoding unit 804 to decode the extracted instructions. For example, the decoding unit 804 can decode the fetch instruction into a complex micro-op (uop).
此外，該核心706可包括一排程單元806。該排程單元806可執行與儲存解碼指令(例如，由該解碼單元804接收的)相關連的各種作業，直至該等指令準備用於分派為止，例如，直至一解碼指令之所有的源值(source value)1變為可適用為止。於一實例中，該排程單元806可對一執行單元808排程及/或發佈(或分派)解碼指令以供執行。該執行單元808可在指令經解碼(例如，藉由該解碼單元804)並分派執行該等分派指令(例如，藉由該排程單元806)後執行該等分派指令。於一實例中，該執行單元808可包括一個以上的執行單元。該執行單元808亦可執行各種算數運算諸如加、減、乘及/或除，並可包括一或更多的算數邏輯單元(ALU)。於一實例中，一共同處理器(未顯示)可結合該執行單元808執行各種算數運算。 Additionally, the core 706 can include a scheduling unit 806. The scheduling unit 806 can execute various jobs associated with storing decoding instructions (e.g., received by the decoding unit 804) until the instructions are ready for dispatch, for example, up to all source values of a decoding instruction ( Source value)1 becomes applicable. In an example, the scheduling unit 806 can schedule and/or issue (or dispatch) decoding instructions to an execution unit 808 for execution. The execution unit 808 can execute the dispatch instructions after the instructions are decoded (eg, by the decoding unit 804) and dispatched to execute the dispatch instructions (eg, by the schedule unit 806). In an example, the execution unit 808 can include more than one execution unit. The execution unit 808 can also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and can include one or more arithmetic logic units (ALUs). In one example, a common processor (not shown) can perform various arithmetic operations in conjunction with the execution unit 808.
再者，該執行單元808可失序地執行指令。因此，於一實例中，該處理器核心706可為一失序處理器核心。該核心706亦可包括一回退單元810。該回退單元810可在指派執行指令後回退該等執行指令。於一實例中，該等執行指令之回退可導致處理器狀態係由指令之執行指派、由該等指令所使用的實體暫存器經取消分配等。 Moreover, the execution unit 808 can execute the instructions out of order. Thus, in one example, the processor core 706 can be an out-of-order processor core. The core 706 can also include a fallback unit 810. The fallback unit 810 can roll back the execution instructions after assigning the execution instructions. In an example, the fallback of the execution instructions may cause the processor state to be assigned by execution of the instructions, unassigned by the physical register used by the instructions, and the like.
該核心706亦可包括一匯流排單元714以經由一或更多的匯流排(例如，匯流排804及/或812)使該處理器核心706之組件與其他組件(諸如參考圖8所論及的該等組件)之間能夠通訊。該核心706亦可包括一或更多的暫存器816以儲存由該核心706之各種組件存取的數據(諸如與耗電狀態設定有關的數值)。 The core 706 can also include a bus unit 714 to cause components of the processor core 706 with other components via one or more bus bars (eg, bus bars 804 and/or 812) (such as discussed with reference to FIG. 8). Communication between these components). The core 706 can also include one or more registers 816 to store data accessed by various components of the core 706 (such as values related to power consumption state settings).
再者，即使圖7圖示該控制單元720經由互連812與該核心706耦合，於各種的實例中，該控制單元720可位設在別處，諸如該核心706內側，經由匯流排704耦合至該核心，等等。 Moreover, even though FIG. 7 illustrates the control unit 720 being coupled to the core 706 via an interconnect 812, in various examples, the control unit 720 can be located elsewhere, such as inside the core 706, coupled via bus bar 704 to The core, and so on.
於一些實例中，本文中所論及的一或更多的組件能夠具體化為一單晶片系統(SOC)裝置。圖9圖示根據一實例的一SOC封裝的一方塊圖。如於圖9中所示，SOC 902包括一或更多的處理器核心920、一或更多的圖形處理器核心930、一輸入/輸出(I/O)介面940、以及一記憶體控制器942。SOC封裝902之各種組件可耦合至一互連或匯流排，諸如本文參考其他圖式所論及者。同時，該SOC封裝902可包括或多或少的組件，諸如本文參考其他圖式所論及者。再者，該SOC封裝902之每一組件可包括一或更多的其他組件，例如，參考本文的其他圖式所論及者。於一實例中，SOC封裝902(及其之組件)係提供位在一或更多的積體電路(IC)晶粒上，例如，其係封裝進入一單一半導體裝置中。 In some examples, one or more of the components discussed herein can be embodied as a single wafer system (SOC) device. Figure 9 illustrates a block diagram of an SOC package in accordance with an example. As shown in FIG. 9, SOC 902 includes one or more processor cores 920, one or more graphics processor cores 930, an input/output (I/O) interface 940, and a memory controller. 942. The various components of SOC package 902 can be coupled to an interconnect or bus bar, such as those discussed herein with reference to other figures. At the same time, the SOC package 902 can include more or less components, such as those discussed herein with reference to other figures. Moreover, each component of the SOC package 902 can include one or more other components, for example, as discussed with respect to other figures herein. In one example, SOC package 902 (and components thereof) are provided on one or more integrated circuit (IC) dies, for example, packaged into a single semiconductor device.
如於圖9中所示，SOC封裝902係經由該記憶體控制器942耦合至一記憶體960(其可與本文中參考其他圖式 所論及的記憶體相似或是相同)。於一實例中，該記憶體960(或是其之一部分)可整合位在該SOC封裝902上。 As shown in FIG. 9, the SOC package 902 is coupled via a memory controller 942 to a memory 960 (which may be referenced to other figures herein). The memory in question is similar or identical). In one example, the memory 960 (or a portion thereof) can be integrated on the SOC package 902.
該I/O介面940可耦合至一或更多I/O裝置970，例如，經由一互連及/或匯流排，諸如本文中參考其他圖式所論及者。I/O裝置970可包括鍵盤、滑鼠、觸控墊、顯示器、影像/視訊捕捉裝置(諸如攝影機或攝錄影機/錄影機)、觸控表面、揚聲器、或是相同者的其中之一或更多種。 The I/O interface 940 can be coupled to one or more I/O devices 970, for example, via an interconnect and/or bus, such as those discussed herein with reference to other figures. The I/O device 970 can include a keyboard, a mouse, a touch pad, a display, an image/video capture device (such as a camera or a video camera/recorder), a touch surface, a speaker, or one of the same. Or more.
圖10圖示根據一實例的一計算系統1000，其係以一點對點(PtP)構態佈置。特別地，圖10顯示一系統，其中處理器、記憶體、及輸入/輸出裝置係藉由複數之點對點介面互連。參考圖2所論及的該等作業可藉由該系統1000之一或更多的組件執行。 FIG. 10 illustrates a computing system 1000 in accordance with an example that is arranged in a point-to-point (PtP) configuration. In particular, Figure 10 shows a system in which the processor, memory, and input/output devices are interconnected by a plurality of point-to-point interfaces. Such operations as discussed with respect to FIG. 2 may be performed by one or more components of the system 1000.
如於圖10中所示，該系統1000可包括多個處理器，為了清晰起見僅顯示其中之二處理器1002及1004。該等處理器1002及1004可分別包括一局部記憶體控制器集線器(MCH)1006及1008，使能夠與記憶體1010及1012通訊。於一些實例中，MCH 1006及1008可包括圖1之該記憶體控制器120及/或邏輯125。 As shown in FIG. 10, the system 1000 can include multiple processors, of which only two of the processors 1002 and 1004 are shown for clarity. The processors 1002 and 1004 can include a local memory controller hub (MCH) 1006 and 1008, respectively, to enable communication with the memory 1010 and 1012. In some examples, MCHs 1006 and 1008 can include the memory controller 120 and/or logic 125 of FIG.
於一實例中，該等處理器1002及1004可為參考圖7論及的該等處理器702的其中之一者。該等處理器1002及1004可經由分別地使用PtP介面電路1016及1018的一點對點(PtP)介面1014交換數據。同時，該等處理器1002及1004可分別地使用點對點介面電路1026、1028、1030及1032經由個別的PtP介面1022及1024與一晶片組1020交換數據。該 晶片組1020可進一步經由一高性能圖形介面1036，例如，使用一PtP介面電路1037，與一高性能圖形電路1034交換數據。 In one example, the processors 1002 and 1004 can be one of the processors 702 discussed with reference to FIG. The processors 1002 and 1004 can exchange data via a point-to-point (PtP) interface 1014 using PtP interface circuits 1016 and 1018, respectively. At the same time, the processors 1002 and 1004 can exchange data with a chipset 1020 via the individual PtP interfaces 1022 and 1024 using the point-to-point interface circuits 1026, 1028, 1030, and 1032, respectively. The Wafer set 1020 can be further exchanged with a high performance graphics circuit 1034 via a high performance graphics interface 1036, for example, using a PtP interface circuit 1037.
如於圖10中所顯示，圖1之該等核心106及/或快取記憶體108之一或更多者可位設在該等處理器1004內。其他的實例，然而，可存在於圖10之該系統1000內其他的電路、邏輯單元或是裝置中。再者，其他的實例可分佈遍及於圖10中所圖示的複數電路、邏輯單元或裝置。 As shown in FIG. 10, one or more of the cores 106 and/or cache memory 108 of FIG. 1 may be located within the processors 1004. Other examples, however, may be present in other circuits, logic units or devices within the system 1000 of FIG. Furthermore, other examples may be distributed throughout the complex circuits, logic units or devices illustrated in FIG.
該晶片組1020可使用一PtP介面電路1041與一匯流排1040通訊。該匯流排1040可具有一或更多的與之通訊的裝置，諸如一匯流排橋接器1042及I/O裝置1043。經由一匯流排1044，該匯流排橋接器1043可與其他裝置通訊，諸如鍵盤/滑鼠1045、通訊裝置1046(諸如數據機、網路介面裝置、或其他可與該電腦網路1003通訊的通訊裝置)、聲音I/O裝置、及/或一數據儲存裝置1048。該數據儲存裝置1048(其可為一硬碟機或是一NAND快閃基固態硬碟)可儲存由該等處理器1004執行的編碼1049。 The chipset 1020 can communicate with a busbar 1040 using a PtP interface circuit 1041. The busbar 1040 can have one or more devices in communication therewith, such as a bus bridge 1042 and an I/O device 1043. The bus bridge 1043 can communicate with other devices via a bus 1044, such as a keyboard/mouse 1045, a communication device 1046 (such as a data machine, a network interface device, or other communication that can communicate with the computer network 1003). Device), sound I/O device, and/or a data storage device 1048. The data storage device 1048 (which may be a hard disk drive or a NAND flash-based solid state drive) may store the code 1049 executed by the processors 1004.
以下實例關於進一步的實例。 The following examples pertain to further examples.
實例1係為一電子裝置，包含一主體、一位在該主體中包含一開口用於接受一記憶卡的插座，其中該插座包含一第一組連接器，其經組配以與位在根據一第一標準組配的一記憶卡上的接腳連接，以及一第二組連接器，其經組配以與位在根據一第二標準組配的一記憶卡上的接腳連接。 Example 1 is an electronic device comprising a main body, a socket including an opening in the main body for receiving a memory card, wherein the socket comprises a first set of connectors, which are assembled in accordance with the position A first standard set of pin connections on a memory card and a second set of connectors are assembled to connect to pins on a memory card that is assembled in accordance with a second standard.
於實例2中，實例1之該主題能夠可任擇地包括一佈置其中該第一組連接器係配置位在該插座之一第一側邊上，以及該第二組連接器係配置位在該插座之一第二側邊上。 In Example 2, the subject matter of Example 1 can optionally include an arrangement wherein the first set of connector configurations are on a first side of the socket and the second set of connector configurations are One of the sockets is on the second side.
於實例3中，實例1-2之任一者的主題可任擇地能夠包括一佈置，其中該第一組的連接器係經組配以與位在一安全數位(SD)記憶卡上的接腳連接，以及該第二組的連接器係經組配以與位在一通用快閃儲存(UFS)記憶卡上的接腳連接。 In Example 3, the subject matter of any of Examples 1-2 can optionally include an arrangement wherein the first set of connectors are assembled to be placed on a Secure Digital (SD) memory card. The pin connections, and the connectors of the second set are assembled to connect to pins on a Universal Flash Storage (UFS) memory card.
於實例4中，實例1-3之任一者的主題可任擇地能夠包括一佈置，其中該第一組連接器中的至少一連接器係連接至該第二組連接器中的至少一連接器。 In Example 4, the subject matter of any of Examples 1-3 can optionally include an arrangement wherein at least one of the first set of connectors is coupled to at least one of the second set of connectors Connector.
於實例5中，實例1-4之任一者的主題可任擇地能夠包括一佈置，其中一耦合感應器用於探測一記憶卡何時***該插座。 In Example 5, the subject matter of any of Examples 1-4 can optionally include an arrangement in which a coupled inductor is used to detect when a memory card is inserted into the socket.
於實例6中，實例1-5之任一者的主題可任擇地能夠包括一佈置，其中該耦合感應器包含機械式開關或是電氣電路的至少之一者。 In Example 6, the subject matter of any of Examples 1-5 can optionally include an arrangement wherein the coupled inductor comprises at least one of a mechanical switch or an electrical circuit.
於實例7中，實例6之主題可任擇地能夠包括邏輯，至少部分地包括硬體邏輯，以探測來自於該耦合感應器的一信號，其指示記憶卡已***該插座，回應於該信號以判定***該插座的記憶卡之類型，並開始與記憶卡之通訊。 In Example 7, the subject matter of Example 6 can optionally include logic, at least in part, to include hardware logic to detect a signal from the coupled sensor indicating that a memory card has been inserted into the socket in response to the signal To determine the type of memory card inserted into the outlet and start communication with the memory card.
實例8係為供電子裝置所用的一外殼，包含一主體，包含一主體、一位在該主體中包含一開口用於接受一 記憶卡的插座，其中該插座包含一第一組連接器，其經組配以與位在根據一第一標準組配的一記憶卡上的接腳連接，以及一第二組連接器，其經組配以與位在根據一第二標準組配的一記憶卡上的接腳連接。 Example 8 is an outer casing for an electronic device, comprising a main body, comprising a main body, and one bit includes an opening in the main body for receiving one a socket of a memory card, wherein the socket includes a first set of connectors that are assembled to be coupled to pins on a memory card that is assembled according to a first standard, and a second set of connectors that It is assembled to be connected to a pin on a memory card that is assembled according to a second standard.
於實例9中，該實例8之主題可任擇地能夠包括一佈置，其中該第一組連接器係配置在該插座之該第一側邊上以及該第二組連接器係配置在該插座之該第二側邊上。 In Example 9, the subject matter of Example 8 can optionally include an arrangement wherein the first set of connectors are disposed on the first side of the socket and the second set of connectors are disposed in the socket On the second side.
於實例10中，實例8-9之任一者的主題可任擇地能夠包括一佈置，其中該第一組的連接器係經組配以與位在一安全數位(SD)記憶卡上的接腳連接，以及該第二組的連接器係經組配以與位在一通用快閃儲存(UFS)記憶卡上的接腳連接。 In Example 10, the subject matter of any of Examples 8-9 can optionally include an arrangement wherein the first set of connectors are assembled to be placed on a Secure Digital (SD) memory card. The pin connections, and the connectors of the second set are assembled to connect to pins on a Universal Flash Storage (UFS) memory card.
於實例11中，實例8-10之任一者的主題可任擇地能夠包括一佈置，其中該第一組連接器中的至少一連接器係連接至該第二組連接器中的至少一連接器。 In Example 11, the subject matter of any of Examples 8-10 can optionally include an arrangement wherein at least one of the first set of connectors is coupled to at least one of the second set of connectors Connector.
於實例12中，實例8-11之任一者的主題可任擇地能夠包括一佈置，其中一耦合感應器用於探測一記憶卡何時***該插座。 In Example 12, the subject matter of any of Examples 8-11 can optionally include an arrangement in which a coupled inductor is used to detect when a memory card is inserted into the socket.
於實例13中，實例8-12之任一者的主題可任擇地能夠包括一佈置，其中該耦合感應器包含機械式開關或是電氣電路的至少之一者。 In Example 13, the subject matter of any of Examples 8-12 can optionally include an arrangement wherein the coupled inductor comprises at least one of a mechanical switch or an electrical circuit.
實例14係為供一電子裝置所用的一組件，包含一輸入/輸出介面、一與該輸入/輸出介面耦合並且包含一開口用於接受一記憶卡的插座，其中該插座包含一第一組連接 器，其經組配以與位在根據一第一標準組配的一記憶卡上的接腳連接，以及一第二組連接器，其經組配以與位在根據一第二標準組配的一記憶卡上的接腳連接。 Example 14 is a component for an electronic device, comprising an input/output interface, a socket coupled to the input/output interface and including an opening for receiving a memory card, wherein the socket includes a first set of connections And being coupled to a pin on a memory card that is assembled according to a first standard, and a second set of connectors that are assembled to match the bit according to a second standard A pin connection on a memory card.
於實例15中，該實例14之主題可任擇地能夠包括一佈置，其中該第一組連接器係配置在該插座之該第一側邊上以及該第二組連接器係配置在該插座之該第二側邊上。 In Example 15, the subject matter of the example 14 can optionally include an arrangement wherein the first set of connectors are disposed on the first side of the socket and the second set of connectors are disposed in the socket On the second side.
於實例16中，實例14-15之任一者的主題可任擇地能夠包括一佈置，其中該第一組的連接器係經組配以與位在一安全數位(SD)記憶卡上的接腳連接，以及該第二組的連接器係經組配以與位在一通用快閃儲存(UFS)記憶卡上的接腳連接。 In Example 16, the subject matter of any of Examples 14-15 can optionally include an arrangement wherein the first set of connectors are assembled to be placed on a Secure Digital (SD) memory card. The pin connections, and the connectors of the second set are assembled to connect to pins on a Universal Flash Storage (UFS) memory card.
於實例17中，實例14-16之任一者的主題可任擇地能夠包括一佈置，其中該第一組的連接器中的至少一連接器係連接至該第二組的連接器中的至少一連接器。 In Example 17, the subject matter of any of Examples 14-16 can optionally include an arrangement wherein at least one of the connectors of the first set is coupled to the connector of the second set At least one connector.
於實例18中，實例14-17之任一者的主題可任擇地能夠包括一佈置，其中一耦合感應器用於探測一記憶卡何時***該插座。 In Example 18, the subject matter of any of Examples 14-17 can optionally include an arrangement in which a coupled inductor is used to detect when a memory card is inserted into the socket.
於實例19中，實例14-19之任一者的主題可任擇地能夠包括一佈置，其中該耦合感應器包含機械式開關或是電氣電路的至少之一者。 In Example 19, the subject matter of any of Examples 14-19 can optionally include an arrangement wherein the coupled inductor comprises at least one of a mechanical switch or an electrical circuit.
於實例20中，實例14-19之主題可任擇地能夠包括邏輯，至少部分地包括硬體邏輯，以探測來自於該耦合感應器的一信號，其指示記憶卡已***該插座，對該信號 作出反應以判定***該插座的記憶卡之類型，並開始與記憶卡之通訊。 In Example 20, the subject matter of Examples 14-19 can optionally include logic, at least in part, to include hardware logic to detect a signal from the coupled sensor indicating that a memory card has been inserted into the socket, signal A response is made to determine the type of memory card inserted into the outlet and communication with the memory card begins.
本文所提及的用語“邏輯指令”涉及這樣的表達，即可被一個或更多機器瞭解以執行一或更多邏輯操作。例如，邏輯指令可包含通過處理器編譯器可解釋用於在一或更多數據對象上執行一或更多操作的指令。然而，這僅是可機器讀取指令的一實例，以及實例並未限制在此方面。 The term "logic instruction" as referred to herein relates to an expression that is known by one or more machines to perform one or more logical operations. For example, the logic instructions can include instructions executable by the processor compiler to perform one or more operations on one or more data objects. However, this is only one example of a machine readable instruction, and the examples are not limited in this respect.
本文所提及的術語“電腦可讀取媒體”涉及能夠保存可被一或更多機器接受的表達方式的媒體。例如，一電腦可讀取媒體可包含一或更多個用於儲存電腦可讀取指令或數據的儲存裝置。該等儲存裝置可包含儲存媒體諸如，例如，光學的、磁性的或半導體儲存媒體。然而，此僅是電腦可讀取媒體的一實例，並且該等實例不限定於此方面。 The term "computer readable medium" as referred to herein relates to media capable of holding expressions that are acceptable to one or more machines. For example, a computer readable medium can include one or more storage devices for storing computer readable instructions or data. The storage devices may include storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of computer readable media, and such examples are not limited in this respect.
本文所提及的用語“邏輯”涉及用於執行一或更多個邏輯操作的結構。例如，邏輯可包含基於一或更多個輸入信號來提供一或更多個輸出信號的電路。該電路可包含有限狀態機，其接收數位輸入並提供數位輸出，或電路，其回應於於一或更多個模擬輸入信號來提供一或更多個模擬輸出信號。該電路可被提供於特殊用途積體電路(ASIC)或現場可程式化閘陣列(FPGA)中。同時，邏輯可包含儲存在一記憶體中的機器可讀取指令，這些指令結合處理電路從而執行該等機器可讀取指令。然而，這些僅是可提供邏輯的結構的例子，該等實例並不限定於此方面。 The term "logic" as used herein relates to a structure for performing one or more logical operations. For example, the logic can include circuitry that provides one or more output signals based on one or more input signals. The circuit can include a finite state machine that receives the digital input and provides a digital output, or circuitry that provides one or more analog output signals in response to one or more analog input signals. The circuit can be provided in a special purpose integrated circuit (ASIC) or a field programmable gate array (FPGA). At the same time, the logic can include machine readable instructions stored in a memory that, in conjunction with the processing circuitry, execute the machine readable instructions. However, these are merely examples of structures that can provide logic, and such examples are not limited in this respect.
本文中說明的一些方法可具體化為電腦可讀取媒體上的邏輯指令。當在處理器上執行時，該等邏輯指令使處理器程式化為實現該等所說明方法的特別目的機器。當該處理器經藉由該等邏輯指令組配以執行本文所說明的該等方法時，該處理器構成用於執行該等所說明方法的結構。可交替地，本文所說明的該等方法可減少為例如現場可程式化閘陣列(FPGA)、特殊用途積體電路(ASIC)等上的邏輯。 Some of the methods described herein can be embodied as logical instructions on a computer readable medium. When executed on a processor, the logic instructions program the processor into a special purpose machine that implements the methods described. When the processor is coupled by the logic instructions to perform the methods described herein, the processor constitutes a structure for performing the methods described. Alternatively, the methods described herein can be reduced to logic on, for example, a field programmable gate array (FPGA), a special purpose integrated circuit (ASIC), and the like.
在詳細說明及申請專利範圍中，可使用該等用語耦合及連接連同其之衍生詞。在特別的實例中，連接可用於指示二或更多的元件彼此為直接物理接觸或電接觸。耦合可意指二或更多的元件係為直接物理接觸或電接觸。然而，耦合亦可意指為二或更多的元件彼此可以不直接地接觸，而是可彼此協作或相互作用。 In the context of the detailed description and claims, such terms may be used in conjunction with the <RTIgt; In a particular example, a connection can be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupling may mean that two or more elements are in direct physical or electrical contact. However, coupling may also mean that two or more elements may not be in direct contact with each other, but may cooperate or interact with each other.
說明書中所提及的“一個實例”或者“一些實例”意指為結合實例說明的具體特徵、結構或者特性被包含在至少一個實作中。說明書不同地方出現的短語“於一實例中”可以或不必全部涉及相同的實例。 The use of "an example" or "an" or "an" or "an" The appearances of the phrase "in one instance" in the various aspects of the specification may or may not necessarily refer to the same.
雖然已經用特定的結構特徵及/或方法動作的語言說明了該等實例，但是應瞭解的是所主張的主題不限於所說明的特定特徵或動作。相反地，公開的特定特徵和動作是實現所聲明主題的樣本形式。 Although the examples have been described in terms of specific structural features and/or methodological acts, it is understood that the claimed subject matter is not limited to the specific features or acts illustrated. Rather, the specific features and acts disclosed are a sample form of the claimed subject matter.
100‧‧‧電子裝置 100‧‧‧Electronic devices
210‧‧‧主體 210‧‧‧ Subject
220‧‧‧插座/連接器 220‧‧‧Socket/connector
230‧‧‧記憶卡/插座 230‧‧‧ Memory Card/Socket
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| US20110189866A1 (en) * | 2009-08-14 | 2011-08-04 | Yosi Pinto | Dual Interface Card with Backward and Forward Compatibility |
| TW201135471A (en) * | 2009-09-23 | 2011-10-16 | Sandisk Il Ltd | Multi-protocol storage device bridge |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20110189866A1 (en) * | 2009-08-14 | 2011-08-04 | Yosi Pinto | Dual Interface Card with Backward and Forward Compatibility |
| TW201135471A (en) * | 2009-09-23 | 2011-10-16 | Sandisk Il Ltd | Multi-protocol storage device bridge |
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