TWI548117B - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor light emitting device and manufacturing method thereof Download PDF

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Publication number
TWI548117B
TWI548117B TW104106369A TW104106369A TWI548117B TW I548117 B TWI548117 B TW I548117B TW 104106369 A TW104106369 A TW 104106369A TW 104106369 A TW104106369 A TW 104106369A TW I548117 B TWI548117 B TW I548117B
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layer
film
light
insulating film
semiconductor
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TW104106369A
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TW201537781A (en
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Susumu Obata
Akihiro Kojima
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Toshiba Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

半導體發光裝置及其製造方法 Semiconductor light emitting device and method of manufacturing same [相關申請案] [Related application]

本申請案享有以日本專利申請案2014-65822號(申請日：2014年3月27日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。 This application claims priority from Japanese Patent Application No. 2014-65822 (Application Date: March 27, 2014). This application contains all of the basic application by reference to the basic application.

本發明之實施形態係關於一種半導體發光裝置及其製造方法。 Embodiments of the present invention relate to a semiconductor light emitting device and a method of fabricating the same.

提出一種於包含發光層之半導體層之一側設置有螢光體層、於另一側設置有電極、配線層及樹脂層之晶片尺寸封裝(Chip Scale Package)構造之半導體發光裝置，於實用化方面要求較高之可靠性。 A semiconductor light-emitting device having a chip scale package structure in which a phosphor layer is provided on one side of a semiconductor layer including a light-emitting layer and an electrode, a wiring layer, and a resin layer are provided on the other side is proposed. Requires higher reliability.

本發明之實施形態提供一種可靠性較高之半導體發光裝置及其製造方法。 Embodiments of the present invention provide a semiconductor light emitting device having high reliability and a method of manufacturing the same.

根據實施形態，半導體發光裝置包括：半導體層，其包含：第1側、第2側、及設置於上述第1側與上述第2側之間之發光層；第1電極，其於上述半導體層之上述第2側，設置於上述半導體層；第2電極，其於上述半導體層之上述第2側，設置於上述半導體層；第1絕緣膜，其覆蓋上述半導體層之上述第2側；第1配線部，其設置於上述第1絕緣膜上，並且連接於上述第1電極；第2配線部，其設置於上述第1絕緣膜上，並且連接於上述第2電極；及第2絕緣膜，其設置於上述第1配線部與上述第2配線部之間。在上述第1絕緣膜與上述第1配線部之 間，設置有上述第2絕緣膜之一部分。 According to an embodiment, a semiconductor light emitting device includes: a semiconductor layer including: a first side, a second side, and a light emitting layer disposed between the first side and the second side; and a first electrode on the semiconductor layer The second side is provided on the semiconductor layer; the second electrode is provided on the second side of the semiconductor layer on the semiconductor layer; and the first insulating film covers the second side of the semiconductor layer; a wiring portion that is provided on the first insulating film and that is connected to the first electrode, and a second wiring portion that is provided on the first insulating film and that is connected to the second electrode and the second insulating film It is provided between the first wiring portion and the second wiring portion. The first insulating film and the first wiring portion One portion of the second insulating film described above is provided.

10‧‧‧基板 10‧‧‧Substrate

11‧‧‧第1半導體層 11‧‧‧1st semiconductor layer

12‧‧‧第2半導體層 12‧‧‧2nd semiconductor layer

13‧‧‧發光層 13‧‧‧Lighting layer

15‧‧‧半導體層 15‧‧‧Semiconductor layer

15a‧‧‧半導體層15之第1面 15a‧‧‧The first side of the semiconductor layer 15

15b‧‧‧半導體層15之第2面 15b‧‧‧The second side of the semiconductor layer 15

15c‧‧‧半導體層15之側面 15c‧‧‧Side of the semiconductor layer 15

15e‧‧‧包含發光層13之部分 15e‧‧‧Parts containing the luminescent layer 13

15f‧‧‧不包含發光層13之部分 15f‧‧‧ does not contain part of the luminescent layer 13

16‧‧‧p側電極 16‧‧‧p side electrode

17‧‧‧n側電極 17‧‧‧n side electrode

17c‧‧‧接觸部 17c‧‧‧Contacts

18‧‧‧絕緣膜 18‧‧‧Insulation film

18a‧‧‧第1開口 18a‧‧‧ first opening

18b‧‧‧第2開口 18b‧‧‧2nd opening

19‧‧‧絕緣膜 19‧‧‧Insulation film

21‧‧‧p側配線層 21‧‧‧p side wiring layer

21a‧‧‧通孔 21a‧‧‧through hole

21b‧‧‧p側配線層21之端部 End of 21b‧‧‧p side wiring layer 21

21c‧‧‧p側配線層21之邊緣 21c‧‧‧p edge of the side wiring layer 21

22‧‧‧n側配線層 22‧‧‧n side wiring layer

22a‧‧‧通孔 22a‧‧‧through hole

22b‧‧‧n側配線層22之端部 End of 22b‧‧‧n side wiring layer 22

22c‧‧‧n側配線層22之邊緣(側面) Edge of the 22c‧‧‧n side wiring layer 22 (side)

23‧‧‧p側金屬支柱 23‧‧‧p side metal pillar

23a‧‧‧p側外部端子 23a‧‧‧p side external terminal

24‧‧‧n側金屬支柱 24‧‧‧n side metal pillar

24a‧‧‧n側外部端子 24a‧‧‧n side external terminal

25‧‧‧樹脂層 25‧‧‧ resin layer

25a‧‧‧樹脂層25之一部分 25a‧‧‧One part of the resin layer 25

30‧‧‧螢光體層 30‧‧‧Fluorescent layer

31‧‧‧螢光體 31‧‧‧Fluorite

32‧‧‧結合材料 32‧‧‧Combined materials

35‧‧‧透明層 35‧‧‧Transparent layer

41‧‧‧p側配線部 41‧‧‧p side wiring section

43‧‧‧n側配線部 43‧‧‧n side wiring department

51‧‧‧反射膜 51‧‧‧Reflective film

60‧‧‧金屬膜 60‧‧‧Metal film

61‧‧‧基底金屬膜 61‧‧‧Base metal film

61a‧‧‧基底金屬膜61之邊緣 61a‧‧‧The edge of the base metal film 61

62‧‧‧密接層 62‧‧ ‧ close layer

62a‧‧‧密接層(鈦膜)62之邊緣 62a‧‧‧The edge of the adhesion layer (titanium film) 62

63‧‧‧籽晶層 63‧‧‧ seed layer

70‧‧‧空隙 70‧‧‧ gap

80‧‧‧金屬膜 80‧‧‧Metal film

90‧‧‧溝槽 90‧‧‧ trench

91‧‧‧抗蝕劑遮罩 91‧‧‧resist mask

92‧‧‧抗蝕劑遮罩 92‧‧‧resist mask

100‧‧‧支持體 100‧‧‧Support

A‧‧‧部分 Part A‧‧‧

c‧‧‧龜裂 C‧‧‧crack

L‧‧‧長度 L‧‧‧ length

t‧‧‧膜厚 T‧‧‧ film thickness

圖1係實施形態之半導體發光裝置之模式剖視圖。 Fig. 1 is a schematic cross-sectional view showing a semiconductor light-emitting device of an embodiment.

圖2(a)及(b)係實施形態之半導體發光裝置之模式俯視圖。 2(a) and 2(b) are schematic plan views of a semiconductor light emitting device according to an embodiment.

圖3(a)係圖3(b)中之A部之模式放大剖視圖，圖3(b)係實施形態之半導體發光裝置之局部剖面之電子顯微鏡圖像。 Fig. 3(a) is a schematic enlarged cross-sectional view of a portion A in Fig. 3(b), and Fig. 3(b) is an electron microscope image of a partial cross section of the semiconductor light-emitting device of the embodiment.

圖4(a)~圖11(b)係表示實施形態之半導體發光裝置之製造方法之模式剖視圖。 4(a) to 11(b) are schematic cross-sectional views showing a method of manufacturing the semiconductor light-emitting device of the embodiment.

圖12(a)及(b)係實施形態之半導體發光裝置之模式剖視圖。 12(a) and 12(b) are schematic cross-sectional views showing a semiconductor light emitting device according to an embodiment.

圖13(a)係實施形態之半導體發光裝置之模式剖視圖，圖13(b)係參照例之半導體發光裝置之模式剖視圖。 Fig. 13 (a) is a schematic cross-sectional view showing a semiconductor light emitting device according to an embodiment, and Fig. 13 (b) is a schematic cross-sectional view showing a semiconductor light emitting device according to a reference example.

圖14係另一實施形態之半導體發光裝置之模式剖視圖。 Fig. 14 is a schematic cross-sectional view showing a semiconductor light emitting device according to another embodiment.

以下，參照圖式，對實施形態進行說明。再者，於各圖式中，對相同要素標示相同之符號。 Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same symbols.

圖1係實施形態之半導體發光裝置之模式剖視圖。 Fig. 1 is a schematic cross-sectional view showing a semiconductor light-emitting device of an embodiment.

圖2(a)係表示實施形態之半導體發光裝置中之p側電極16與n側電極17之平面佈局之一例的模式俯視圖。圖1與圖2(a)中之A-A'剖面對應。圖2(a)與去掉圖1中之配線部41、43、樹脂層25、絕緣膜18、及反射膜51而觀察半導體層15之第2面側之圖對應。又，圖2(a)與圖5(b)之積層體(除基板10以外)之俯視圖對應。 Fig. 2 (a) is a schematic plan view showing an example of a planar layout of the p-side electrode 16 and the n-side electrode 17 in the semiconductor light-emitting device of the embodiment. Figure 1 corresponds to the A-A' profile in Figure 2(a). 2(a) corresponds to a view in which the wiring portions 41 and 43 in FIG. 1 , the resin layer 25, the insulating film 18, and the reflective film 51 are removed, and the second surface side of the semiconductor layer 15 is observed. 2(a) corresponds to a plan view of the laminated body (excluding the substrate 10) of FIG. 5(b).

圖2(b)係實施形態之半導體發光裝置之安裝面(圖1之半導體發光裝置之下表面)之模式俯視圖。 Fig. 2(b) is a schematic plan view showing a mounting surface of the semiconductor light-emitting device of the embodiment (the lower surface of the semiconductor light-emitting device of Fig. 1).

實施形態之半導體發光裝置包括具有發光層13之半導體層15。半導體層15具有作為光提取側之第1面(第1側)15a、及其相反側之第2面(第2側)15b(參照圖4(a))。 The semiconductor light-emitting device of the embodiment includes a semiconductor layer 15 having a light-emitting layer 13. The semiconductor layer 15 has a first surface (first side) 15a on the light extraction side and a second surface (second side) 15b on the opposite side (see FIG. 4(a)).

如圖5(a)所示，半導體層15之第2面15b具有包含發光層13之部分(發光區域)15e、及不包含發光層13之部分(非發光區域)15f。包含發光層13之部分15e係於半導體層15中積層有發光層13之部分。不包含發光層13之部分15f係於半導體層15中未積層發光層13之部分。包含發光層13之部分15e表示成為能夠將發光層13發出之光提取至外部之積層構造的區域。 As shown in FIG. 5(a), the second surface 15b of the semiconductor layer 15 has a portion (light-emitting region) 15e including the light-emitting layer 13 and a portion (non-light-emitting region) 15f not including the light-emitting layer 13. A portion 15e including the light-emitting layer 13 is a portion of the semiconductor layer 15 in which the light-emitting layer 13 is laminated. The portion 15f not including the light-emitting layer 13 is a portion of the semiconductor layer 15 where the light-emitting layer 13 is not laminated. The portion 15e including the light-emitting layer 13 indicates a region which is a laminated structure capable of extracting light emitted from the light-emitting layer 13 to the outside.

於第2面側，在包含發光層13之部分15e上，設置有p側電極16作為第1電極，於不包含發光層之部分15f上，設置有n側電極17作為第2電極。 On the second surface side, a p-side electrode 16 is provided as a first electrode on a portion 15e including the light-emitting layer 13, and an n-side electrode 17 is provided as a second electrode on a portion 15f not including the light-emitting layer.

於圖2(a)所示之例中，不包含發光層13之部分15f包圍包含發光層13之部分15e，n側電極17包圍p側電極16。 In the example shown in FIG. 2(a), the portion 15f not including the light-emitting layer 13 surrounds the portion 15e including the light-emitting layer 13, and the n-side electrode 17 surrounds the p-side electrode 16.

通過p側電極16與n側電極17對發光層13供給電流，從而發光層13發光。繼而，自發光層13放射之光係自第1面15a側向半導體發光裝置之外部出射。 The light is supplied to the light-emitting layer 13 through the p-side electrode 16 and the n-side electrode 17, and the light-emitting layer 13 emits light. Then, the light emitted from the light-emitting layer 13 is emitted from the side of the first surface 15a toward the outside of the semiconductor light-emitting device.

如圖1所示，於半導體層15之第2面側設置有支持體100。包含半導體層15、p側電極16及n側電極17之發光元件由設置於第2面側之支持體100支持。 As shown in FIG. 1, the support 100 is provided on the second surface side of the semiconductor layer 15. The light-emitting element including the semiconductor layer 15, the p-side electrode 16, and the n-side electrode 17 is supported by the support 100 provided on the second surface side.

於半導體層15之第1面15a側，設置有螢光體層30作為對半導體發光裝置之發射光賦予所需之光學特性之光學層。螢光體層30包含複數個粒子狀之螢光體31。螢光體31由發光層13之放射光激發，而放射與該放射光為不同波長之光。 On the first surface 15a side of the semiconductor layer 15, a phosphor layer 30 is provided as an optical layer that imparts desired optical characteristics to the emitted light of the semiconductor light-emitting device. The phosphor layer 30 includes a plurality of particulate phosphors 31. The phosphor 31 is excited by the emitted light of the light-emitting layer 13, and emits light of a different wavelength from the emitted light.

複數個螢光體31藉由結合材料32而一體化。結合材料32使發光層13之放射光及螢光體31之放射光透過。此處，所謂「透過」，並不限定於透過率為100%之情況，亦包含吸收光之一部分之情形。 The plurality of phosphors 31 are integrated by the bonding material 32. The bonding material 32 transmits the emitted light of the light-emitting layer 13 and the emitted light of the phosphor 31. Here, the term "transmission" is not limited to the case where the transmittance is 100%, and includes a case where one part of the light is absorbed.

半導體層15具有第1半導體層11、第2半導體層12、及發光層13。發光層13設置於第1半導體層11與第2半導體層12之間。第1半導體層 11及第2半導體層12例如含有氮化鎵。 The semiconductor layer 15 has a first semiconductor layer 11, a second semiconductor layer 12, and a light-emitting layer 13. The light emitting layer 13 is provided between the first semiconductor layer 11 and the second semiconductor layer 12. First semiconductor layer The 11 and second semiconductor layers 12 contain, for example, gallium nitride.

第1半導體層11例如包含基底緩衝層、n型GaN層。第2半導體層12例如包含p型GaN層。發光層13包含發出藍、紫、藍紫、紫外光等之材料。發光層13之發光峰值波長例如為430~470nm。 The first semiconductor layer 11 includes, for example, a base buffer layer and an n-type GaN layer. The second semiconductor layer 12 includes, for example, a p-type GaN layer. The light-emitting layer 13 contains a material that emits blue, violet, blue-violet, ultraviolet light, or the like. The emission peak wavelength of the light-emitting layer 13 is, for example, 430 to 470 nm.

半導體層15之第2面被加工成凹凸形狀。其凸部為包含發光層13之部分15e，凹部為不包含發光層13之部分15f。包含發光層13之部分15e之表面為第2半導體層12之表面，於第2半導體層12之表面設置有p側電極16。不包含發光層13之部分15f之表面為第1半導體層11之表面，於第1半導體層11之表面設置有n側電極17。 The second surface of the semiconductor layer 15 is processed into a concavo-convex shape. The convex portion is a portion 15e including the light-emitting layer 13, and the concave portion is a portion 15f not including the light-emitting layer 13. The surface of the portion 15e including the light-emitting layer 13 is the surface of the second semiconductor layer 12, and the p-side electrode 16 is provided on the surface of the second semiconductor layer 12. The surface of the portion 15f not including the light-emitting layer 13 is the surface of the first semiconductor layer 11, and the n-side electrode 17 is provided on the surface of the first semiconductor layer 11.

於半導體層15之第2面，包含發光層13之部分15e之面積較不包含發光層13之部分15f之面積大。又，設置於包含發光層13之部分15e之表面之p側電極16之面積較設置於不包含發光層13之部分15f之表面之n側電極17之面積大。藉此，可獲得較寬之發光面，而能夠使光輸出較高。 On the second surface of the semiconductor layer 15, the area of the portion 15e including the light-emitting layer 13 is larger than the area of the portion 15f not including the light-emitting layer 13. Further, the area of the p-side electrode 16 provided on the surface of the portion 15e including the light-emitting layer 13 is larger than the area of the n-side electrode 17 provided on the surface of the portion 15f not including the light-emitting layer 13. Thereby, a wider light-emitting surface can be obtained, and the light output can be made higher.

如圖2(a)所示，n側電極17具有例如4條直線部，於其中之1條直線部，設置有於該直線部之寬度方向上突出之接觸部17c。於該接觸部17c之表面，如圖1所示般連接n側配線層22之通孔22a。 As shown in Fig. 2(a), the n-side electrode 17 has, for example, four straight portions, and one of the straight portions is provided with a contact portion 17c that protrudes in the width direction of the straight portion. The through hole 22a of the n-side wiring layer 22 is connected to the surface of the contact portion 17c as shown in FIG.

如圖1所示，半導體層15之第2面、p側電極16及n側電極17由絕緣膜(第1絕緣膜)18覆蓋。絕緣膜18例如為氧化矽膜等無機絕緣膜。絕緣膜18亦設置於發光層13之側面及第2半導體層12之側面，並覆蓋該等側面。 As shown in FIG. 1, the second surface of the semiconductor layer 15, the p-side electrode 16, and the n-side electrode 17 are covered with an insulating film (first insulating film) 18. The insulating film 18 is, for example, an inorganic insulating film such as a ruthenium oxide film. The insulating film 18 is also provided on the side surface of the light-emitting layer 13 and the side surface of the second semiconductor layer 12, and covers the side surfaces.

又，絕緣膜18亦設置於半導體層15之自第1面15a連續之側面(第1半導體層11之側面)15c，並覆蓋該側面15c。 Further, the insulating film 18 is also provided on the side surface (the side surface of the first semiconductor layer 11) 15c of the semiconductor layer 15 from the continuous side of the first surface 15a, and covers the side surface 15c.

進而，絕緣膜18亦設置於半導體層15之側面15c周圍之晶片外區域。設置於晶片外區域之絕緣膜18於第1面15a側向遠離側面15c之方向延伸。 Further, the insulating film 18 is also provided on the outer surface of the wafer around the side surface 15c of the semiconductor layer 15. The insulating film 18 provided in the outer region of the wafer extends in the direction away from the side surface 15c on the side of the first surface 15a.

於絕緣膜18上，相互分離地設置有作為第1配線層之p側配線層21、及作為第2配線層之n側配線層22。如圖6(b)所示，於絕緣膜18，形成通向p側電極16之複數個第1開口18a、及通向n側電極17之接觸部17c之第2開口18b。再者，第1開口18a亦可為更大之1個開口。 On the insulating film 18, a p-side wiring layer 21 as a first wiring layer and an n-side wiring layer 22 as a second wiring layer are provided apart from each other. As shown in FIG. 6(b), in the insulating film 18, a plurality of first openings 18a leading to the p-side electrode 16 and a second opening 18b leading to the contact portion 17c of the n-side electrode 17 are formed. Furthermore, the first opening 18a may also be a larger opening.

p側配線層21設置於絕緣膜18上及第1開口18a之內部。p側配線層21係經由設置於第1開口18a內之通孔21a而與p側電極16電性連接。 The p-side wiring layer 21 is provided on the insulating film 18 and inside the first opening 18a. The p-side wiring layer 21 is electrically connected to the p-side electrode 16 via a via hole 21a provided in the first opening 18a.

n側配線層22設置於絕緣膜18上及第2開口18b之內部。n側配線層22係經由設置於第2開口18b內之通孔22a而與n側電極17之接觸部17c電性連接。 The n-side wiring layer 22 is provided on the insulating film 18 and inside the second opening 18b. The n-side wiring layer 22 is electrically connected to the contact portion 17c of the n-side electrode 17 via the through hole 22a provided in the second opening 18b.

p側配線層21及n側配線層22佔據第2面側之區域之大部分並於絕緣膜18上擴展。p側配線層21經由複數個通孔21a與p側電極16連接。 The p-side wiring layer 21 and the n-side wiring layer 22 occupy most of the region on the second surface side and spread over the insulating film 18. The p-side wiring layer 21 is connected to the p-side electrode 16 via a plurality of via holes 21a.

又，反射膜51介隔絕緣膜18覆蓋半導體層15之側面15c。反射膜51不與側面15c相接，而不相對於半導體層15電性連接。反射膜51相對於p側配線層21及n側配線層22分離。反射膜51對發光層13之放射光及螢光體31之放射光具有反射性。 Further, the reflective film 51 is insulated from the side surface 15c of the semiconductor layer 15 by the barrier film 18. The reflective film 51 is not in contact with the side surface 15c and is not electrically connected to the semiconductor layer 15. The reflective film 51 is separated from the p-side wiring layer 21 and the n-side wiring layer 22 . The reflective film 51 is reflective to the emitted light of the light-emitting layer 13 and the emitted light of the phosphor 31.

反射膜51、p側配線層21及n側配線層22包含藉由例如鍍敷法而同時形成於圖7(a)所示之共用之金屬膜60上之銅膜。 The reflective film 51, the p-side wiring layer 21, and the n-side wiring layer 22 include a copper film which is simultaneously formed on the common metal film 60 shown in FIG. 7(a) by, for example, a plating method.

構成反射膜51、p側配線層21及n側配線層22之例如銅膜係藉由鍍敷法而形成於絕緣膜18上所形成之金屬膜60上。反射膜51、p側配線層21及n側配線層22各自之厚度較金屬膜60之厚度厚。 For example, a copper film constituting the reflective film 51, the p-side wiring layer 21, and the n-side wiring layer 22 is formed on the metal film 60 formed on the insulating film 18 by a plating method. The thickness of each of the reflective film 51, the p-side wiring layer 21, and the n-side wiring layer 22 is thicker than the thickness of the metal film 60.

金屬膜60具有自絕緣膜18側起依序積層之基底金屬膜61、密接層62、及籽晶層63。 The metal film 60 has a base metal film 61, an adhesion layer 62, and a seed layer 63 which are sequentially laminated from the side of the insulating film 18.

基底金屬膜61為對發光層13之放射光具有較高之反射性之例如鋁膜。 The base metal film 61 is, for example, an aluminum film which has high reflectance to the emitted light of the light-emitting layer 13.

籽晶層63為用以藉由鍍敷而使銅析出之銅膜。密接層62為相對於鋁及銅之兩者之潤濕性優異之例如鈦膜。 The seed layer 63 is a copper film for depositing copper by plating. The adhesion layer 62 is, for example, a titanium film which is excellent in wettability with respect to both aluminum and copper.

再者，於半導體層15之側面15c周圍之晶片外區域，亦可不於金屬膜60上形成鍍敷膜(銅膜)，而由金屬膜60形成反射膜51。反射膜51至少包含鋁膜61，藉此對發光層13之放射光及螢光體31之放射光具有較高之反射率。 Further, a plating film (a copper film) may not be formed on the metal film 60 on the outer surface of the wafer around the side surface 15c of the semiconductor layer 15, and the reflective film 51 may be formed from the metal film 60. The reflective film 51 includes at least the aluminum film 61, whereby the emitted light of the light-emitting layer 13 and the emitted light of the phosphor 31 have a high reflectance.

又，於p側配線層21及n側配線層22之下方亦殘留基底金屬膜(鋁膜)61，因此鋁膜61係於第2面側之大部分區域擴展而形成。藉此，可增大朝向螢光體層30側之光之量。 Further, since the underlying metal film (aluminum film) 61 remains under the p-side wiring layer 21 and the n-side wiring layer 22, the aluminum film 61 is formed to extend over most of the second surface side. Thereby, the amount of light toward the side of the phosphor layer 30 can be increased.

於p側配線層21之與半導體層15為相反側之面，設置有作為第1金屬支柱之p側金屬支柱23。p側配線層21及p側金屬支柱23形成p側配線部(第1配線部)41。 On the surface of the p-side wiring layer 21 opposite to the semiconductor layer 15, a p-side metal pillar 23 as a first metal pillar is provided. The p-side wiring layer 21 and the p-side metal pillar 23 form a p-side wiring portion (first wiring portion) 41.

於n側配線層22之與半導體層15為相反側之面，設置有作為第2金屬支柱之n側金屬支柱24。n側配線層22及n側金屬支柱24形成n側配線部(第2配線部)43。 On the surface of the n-side wiring layer 22 opposite to the semiconductor layer 15, an n-side metal pillar 24 as a second metal pillar is provided. The n-side wiring layer 22 and the n-side metal pillar 24 form an n-side wiring portion (second wiring portion) 43.

在p側配線部41與n側配線部43之間，設置有樹脂層25作為第2絕緣膜。樹脂層25係以與p側金屬支柱23之側面及n側金屬支柱24之側面相接之方式，設置於p側金屬支柱23與n側金屬支柱24之間。即，在p側金屬支柱23與n側金屬支柱24之間，填充有樹脂層25。 A resin layer 25 is provided as a second insulating film between the p-side wiring portion 41 and the n-side wiring portion 43. The resin layer 25 is provided between the p-side metal pillar 23 and the n-side metal pillar 24 so as to be in contact with the side surface of the p-side metal pillar 23 and the side surface of the n-side metal pillar 24 . That is, the resin layer 25 is filled between the p-side metal pillar 23 and the n-side metal pillar 24 .

又，樹脂層25設置於p側配線層21與n側配線層22之間、p側配線層21與反射膜51之間、及n側配線層22與反射膜51之間。 Further, the resin layer 25 is provided between the p-side wiring layer 21 and the n-side wiring layer 22, between the p-side wiring layer 21 and the reflective film 51, and between the n-side wiring layer 22 and the reflective film 51.

樹脂層25設置於p側金屬支柱23之周圍及n側金屬支柱24之周圍，覆蓋p側金屬支柱23之側面及n側金屬支柱24之側面。 The resin layer 25 is provided around the p-side metal pillar 23 and around the n-side metal pillar 24, and covers the side surface of the p-side metal pillar 23 and the side surface of the n-side metal pillar 24.

又，樹脂層25亦設置於半導體層15之側面15c周圍之晶片外區域，並覆蓋反射膜51。 Further, the resin layer 25 is also provided on the outer surface of the wafer around the side surface 15c of the semiconductor layer 15, and covers the reflective film 51.

p側金屬支柱23之與p側配線層21為相反側之端部(面)自樹脂層25露出，作為可與安裝基板等之外部電路連接之p側外部端子23a而發揮功能。n側金屬支柱24之與n側配線層22為相反側之端部(面)自樹脂層 25露出，作為可與安裝基板等之外部電路連接之n側外部端子24a而發揮功能。p側外部端子23a及n側外部端子24a經由例如焊料、或導電性接合材料而接合於安裝基板之焊盤圖案。 An end portion (face) of the p-side metal post 23 opposite to the p-side wiring layer 21 is exposed from the resin layer 25, and functions as a p-side external terminal 23a that can be connected to an external circuit such as a mounting substrate. The end portion (face) of the n-side metal post 24 and the n-side wiring layer 22 on the opposite side from the resin layer The exposed portion 25 functions as an n-side external terminal 24a that can be connected to an external circuit such as a mounting board. The p-side external terminal 23a and the n-side external terminal 24a are bonded to the land pattern of the mounting substrate via, for example, solder or a conductive bonding material.

如圖2(b)所示，p側外部端子23a及n側外部端子24a係於樹脂層25之相同面內相隔且並列地形成。p側外部端子23a形成為例如矩形狀，n側外部端子24a形成為切除與p側外部端子23a之矩形為相同尺寸之矩形中之2個角所得之形狀。藉此，可辨別外部端子之極性。當然，亦可將n側外部端子24a設為矩形狀，將p側外部端子23a設為切除矩形之角所得之形狀。 As shown in FIG. 2(b), the p-side external terminal 23a and the n-side external terminal 24a are formed in parallel in the same plane of the resin layer 25, and are formed in parallel. The p-side external terminal 23a is formed, for example, in a rectangular shape, and the n-side external terminal 24a is formed in a shape obtained by cutting out two corners of a rectangle having the same size as the rectangle of the p-side external terminal 23a. Thereby, the polarity of the external terminal can be discerned. Needless to say, the n-side external terminal 24a may have a rectangular shape, and the p-side external terminal 23a may have a shape obtained by cutting a corner of a rectangle.

p側外部端子23a與n側外部端子24a之間隔較絕緣膜18上之p側配線層21與n側配線層22之間隔寬。p側外部端子23a與n側外部端子24a之間隔大於安裝時之焊料之擴展寬度。藉此，可防止通過焊料之p側外部端子23a與n側外部端子24a之間之短路。 The interval between the p-side external terminal 23a and the n-side external terminal 24a is wider than the interval between the p-side wiring layer 21 and the n-side wiring layer 22 on the insulating film 18. The interval between the p-side external terminal 23a and the n-side external terminal 24a is larger than the expanded width of the solder at the time of mounting. Thereby, a short circuit between the p-side external terminal 23a and the n-side external terminal 24a passing through the solder can be prevented.

相對於此，p側配線層21與n側配線層22之間隔可縮窄至製程上之極限。因此，可謀求p側配線層21之面積、及p側配線層21與p側金屬支柱23之接觸面積之擴大。藉此，可促進發光層13之熱之釋放。 On the other hand, the interval between the p-side wiring layer 21 and the n-side wiring layer 22 can be narrowed to the limit on the process. Therefore, the area of the p-side wiring layer 21 and the contact area of the p-side wiring layer 21 and the p-side metal pillar 23 can be increased. Thereby, the release of heat of the light-emitting layer 13 can be promoted.

又，p側配線層21通過複數個通孔21a而與p側電極16相接之面積較n側配線層22通過通孔22a而與n側電極17相接之面積大。藉此，可使於發光層13中流通之電流之分佈均勻化。 Further, the area of the p-side wiring layer 21 that is in contact with the p-side electrode 16 through the plurality of through holes 21a is larger than the area in which the n-side wiring layer 22 is in contact with the n-side electrode 17 through the through hole 22a. Thereby, the distribution of the current flowing in the light-emitting layer 13 can be made uniform.

於絕緣膜18上擴展之n側配線層22之面積可大於n側電極17之面積。而且，可使設置於n側配線層22上之n側金屬支柱24之面積(n側外部端子24a之面積)大於n側電極17。藉此，可確保可靠性較高且對安裝而言充分之n側外部端子24a之面積，並且可使n側電極17之面積縮小。即，可縮小半導體層15中之不包含發光層13之部分(非發光區域)15f之面積，擴大包含發光層13之部分(發光區域)15e之面積而提高光輸出。 The area of the n-side wiring layer 22 spread over the insulating film 18 may be larger than the area of the n-side electrode 17. Further, the area of the n-side metal post 24 (the area of the n-side external terminal 24a) provided on the n-side wiring layer 22 can be made larger than the n-side electrode 17. Thereby, the area of the n-side external terminal 24a which is highly reliable and sufficient for mounting can be ensured, and the area of the n-side electrode 17 can be reduced. In other words, the area of the portion (non-light-emitting region) 15f of the semiconductor layer 15 that does not include the light-emitting layer 13 can be reduced, and the area of the portion (light-emitting region) 15e including the light-emitting layer 13 can be enlarged to increase the light output.

第1半導體層11係經由n側電極17及n側配線層22而與n側金屬支柱24電性連接。第2半導體層12係經由p側電極16及p側配線層21而與p側金屬支柱23電性連接。 The first semiconductor layer 11 is electrically connected to the n-side metal post 24 via the n-side electrode 17 and the n-side wiring layer 22 . The second semiconductor layer 12 is electrically connected to the p-side metal pillar 23 via the p-side electrode 16 and the p-side wiring layer 21 .

p側金屬支柱23之厚度(將p側配線層21與p側外部端子23a連結之方向之厚度)較p側配線層21之厚度厚。n側金屬支柱24之厚度(將n側配線層22與n側外部端子24a連結之方向之厚度)較n側配線層22之厚度厚。p側金屬支柱23、n側金屬支柱24及樹脂層25各自之厚度較半導體層15厚。 The thickness of the p-side metal pillar 23 (the thickness in the direction in which the p-side wiring layer 21 and the p-side external terminal 23a are connected) is thicker than the thickness of the p-side wiring layer 21. The thickness of the n-side metal post 24 (the thickness in the direction in which the n-side wiring layer 22 and the n-side external terminal 24a are connected) is thicker than the thickness of the n-side wiring layer 22. The thickness of each of the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 is thicker than that of the semiconductor layer 15.

金屬支柱23、24之縱橫比(厚度相對於平面尺寸之比)既可大於等於1，亦可小於1。即，金屬支柱23、24既可較其平面尺寸厚，亦可較其平面尺寸薄。 The aspect ratio (ratio of thickness to plane size) of the metal pillars 23, 24 may be greater than or equal to 1 or less than 1. That is, the metal pillars 23, 24 may be thicker than their planar dimensions or thinner than their planar dimensions.

包含p側配線層21、n側配線層22、p側金屬支柱23、n側金屬支柱24及樹脂層25之支持體100之厚度較包含半導體層15、p側電極16及n側電極17之發光元件(LED(Light Emitting Diode，發光二極體)晶片)之厚度厚。 The thickness of the support 100 including the p-side wiring layer 21, the n-side wiring layer 22, the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 is larger than that of the semiconductor layer 15, the p-side electrode 16, and the n-side electrode 17. The light-emitting element (LED (Light Emitting Diode) wafer) has a large thickness.

如下上述，半導體層15係藉由磊晶成長法而形成於基板上。該基板於形成支持體100後被去除，從而半導體層15於第1面15a側不包含基板。半導體層15並非由剛直之板狀之基板支持，而是由包含金屬支柱23、24與樹脂層25之複合體之支持體100支持。 As described below, the semiconductor layer 15 is formed on the substrate by an epitaxial growth method. The substrate is removed after the support 100 is formed, so that the semiconductor layer 15 does not include the substrate on the first surface 15a side. The semiconductor layer 15 is not supported by a rigid plate-like substrate, but is supported by a support 100 including a composite of metal pillars 23, 24 and a resin layer 25.

作為p側配線部41及n側配線部43之材料，例如可使用銅、金、鎳、銀等。若使用其等中之銅，則可提高良好之導熱性、較高之遷移耐性及相對於絕緣材料之密接性。 As a material of the p-side wiring portion 41 and the n-side wiring portion 43, for example, copper, gold, nickel, silver, or the like can be used. When copper in the middle is used, good thermal conductivity, high migration resistance, and adhesion to an insulating material can be improved.

樹脂層25補強p側金屬支柱23及n側金屬支柱24。樹脂層25較理想為使用熱膨脹率與安裝基板相同或接近者。作為此種樹脂層25，例如可列舉主要包含環氧樹脂之樹脂、主要包含聚矽氧樹脂之樹脂、主要包含氟樹脂之樹脂。 The resin layer 25 reinforces the p-side metal pillar 23 and the n-side metal pillar 24 . The resin layer 25 desirably has the same or similar thermal expansion coefficient as the mounting substrate. Examples of such a resin layer 25 include a resin mainly containing an epoxy resin, a resin mainly containing a polyoxymethylene resin, and a resin mainly containing a fluororesin.

又，於成為樹脂層25中之基底之樹脂中包含遮光材料(光吸收劑、光反射劑、光散射劑等)，從而樹脂層25對發光層13發出之光具有遮光性。藉此，可抑制自支持體100之側面及安裝面側之漏光。 Further, a light-shielding material (a light absorber, a light-reflecting agent, a light-scattering agent, etc.) is contained in the resin which becomes the base of the resin layer 25, and the resin layer 25 has a light-shielding property with respect to the light emitted from the light-emitting layer 13. Thereby, light leakage from the side surface of the support body 100 and the mounting surface side can be suppressed.

因安裝半導體發光裝置時之熱循環，而將使p側外部端子23a及n側外部端子24a接合於安裝基板之焊盤之焊料等所引起之應力施加至半導體層15。p側金屬支柱23、n側金屬支柱24及樹脂層25吸收並緩和該應力。尤其是藉由將較半導體層15柔軟之樹脂層25用作支持體100之一部分，可提高應力緩和效果。 The stress caused by the solder or the like which bonds the p-side external terminal 23a and the n-side external terminal 24a to the pad of the mounting substrate is applied to the semiconductor layer 15 by the thermal cycle when the semiconductor light-emitting device is mounted. The p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 absorb and alleviate the stress. In particular, by using the resin layer 25 softer than the semiconductor layer 15 as a part of the support 100, the stress relieving effect can be improved.

反射膜51相對於p側配線部41及n側配線部43分離。因此，於安裝時施加至p側金屬支柱23及n側金屬支柱24之應力不會傳遞至反射膜51。因此，可抑制反射膜51之剝離。又，可抑制施加至半導體層15之側面15c側之應力。 The reflection film 51 is separated from the p-side wiring portion 41 and the n-side wiring portion 43. Therefore, the stress applied to the p-side metal post 23 and the n-side metal post 24 at the time of mounting is not transmitted to the reflective film 51. Therefore, peeling of the reflective film 51 can be suppressed. Moreover, the stress applied to the side surface 15c side of the semiconductor layer 15 can be suppressed.

如下所述，形成半導體層15所使用之基板係自半導體層15被去除。藉此，使半導體發光裝置薄化。又，藉由去除基板，可於半導體層15之第1面15a形成微小凹凸，從而可謀求光提取效率之提高。 As described below, the substrate used to form the semiconductor layer 15 is removed from the semiconductor layer 15. Thereby, the semiconductor light-emitting device is made thin. Further, by removing the substrate, minute irregularities can be formed on the first surface 15a of the semiconductor layer 15, and the light extraction efficiency can be improved.

例如，對第1面15a進行使用鹼系溶液之濕式蝕刻而形成微小凹凸。藉此，減少第1面15a中之全反射成分，從而可提高光提取效率。 For example, the first surface 15a is subjected to wet etching using an alkali solution to form minute irregularities. Thereby, the total reflection component in the first surface 15a is reduced, and the light extraction efficiency can be improved.

於去除基板後，在第1面15a上介隔絕緣膜19而形成螢光體層30。絕緣膜19作為提高半導體層15與螢光體層30之密接性之密接層而發揮功能，例如為氧化矽膜、氮化矽膜。 After the substrate is removed, the edge film 19 is isolated on the first surface 15a to form the phosphor layer 30. The insulating film 19 functions as an adhesion layer for improving the adhesion between the semiconductor layer 15 and the phosphor layer 30, and is, for example, a hafnium oxide film or a tantalum nitride film.

螢光體層30具有於結合材料32中分散有複數個粒子狀之螢光體31之構造。對於結合材料32，例如可使用聚矽氧樹脂。 The phosphor layer 30 has a structure in which a plurality of particulate phosphors 31 are dispersed in the bonding material 32. For the bonding material 32, for example, a polyoxynoxy resin can be used.

螢光體層30亦形成於半導體層15之側面15c周圍之晶片外區域上。因此，螢光體層30之平面尺寸大於半導體層15之平面尺寸。於晶片外區域內，在絕緣膜18上設置有螢光體層30。 The phosphor layer 30 is also formed on the outer surface of the wafer around the side 15c of the semiconductor layer 15. Therefore, the planar size of the phosphor layer 30 is larger than the planar size of the semiconductor layer 15. A phosphor layer 30 is provided on the insulating film 18 in the outer region of the wafer.

螢光體層30被限定於半導體層15之第1面15a上、及鄰接於半導體 層15之側面15c之區域上，並未包圍半導體層15之第2面側、金屬支柱23、24之周圍、及支持體100之側面而形成。螢光體層30之側面與支持體100之側面(樹脂層25之側面)對齊。 The phosphor layer 30 is defined on the first surface 15a of the semiconductor layer 15 and adjacent to the semiconductor The region of the side surface 15c of the layer 15 is not formed to surround the second surface side of the semiconductor layer 15, the periphery of the metal pillars 23, 24, and the side surface of the support 100. The side surface of the phosphor layer 30 is aligned with the side surface of the support 100 (the side surface of the resin layer 25).

即，實施形態之半導體發光裝置為晶片尺寸封裝構造之非常小型之半導體發光裝置。因此，於應用於例如照明用燈具等時，燈具設計之自由度變高。 That is, the semiconductor light-emitting device of the embodiment is a very small semiconductor light-emitting device having a wafer-sized package structure. Therefore, when applied to, for example, a lighting fixture or the like, the degree of freedom in design of the luminaire becomes high.

又，於不將光提取至外部之安裝面側未多餘地形成螢光體層30，從而可謀求降低成本。又，即便於第1面15a側不存在基板，亦能夠經由在第2面側擴展之p側配線層21及n側配線層22使發光層13之熱向安裝基板側釋放，儘管為小型，散熱性亦優異。 Moreover, the phosphor layer 30 is not excessively formed on the mounting surface side where light is not extracted to the outside, and the cost can be reduced. In addition, even if the substrate is not present on the first surface 15a side, the heat of the light-emitting layer 13 can be released to the mounting substrate side via the p-side wiring layer 21 and the n-side wiring layer 22 which are expanded on the second surface side, and although it is small, Excellent heat dissipation.

於普通之覆晶安裝時，於經由凸塊等將LED晶片安裝於安裝基板之後，以覆蓋晶片整體之方式形成螢光體層。或者，於凸塊間底填充樹脂。 In the conventional flip chip mounting, after the LED chip is mounted on the mounting substrate via bumps or the like, the phosphor layer is formed to cover the entire wafer. Alternatively, the resin is filled in between the bumps.

相對於此，根據實施形態，於安裝前之狀態下，在p側金屬支柱23之周圍及n側金屬支柱24之周圍設置與螢光體層30不同之樹脂層25，從而可對安裝面側賦予適於應力緩和之特性。又，由於已於安裝面側設置有樹脂層25，故而無需安裝後之底填充。 On the other hand, in the state before the mounting, the resin layer 25 different from the phosphor layer 30 is provided around the p-side metal pillar 23 and around the n-side metal pillar 24, and the mounting surface side can be provided. Suitable for stress relaxation properties. Further, since the resin layer 25 is provided on the mounting surface side, the underfill after the mounting is not required.

於第1面15a側，設置以光提取效率、色轉換效率、配光特性等優先而設計之層，於安裝面側，設置以安裝時之應力緩和、或作為取代基板之支持體之特性優先之層。例如，樹脂層25具有於成為基底之樹脂中高密度地填充有二氧化矽粒子等填料之構造，且調整為作為支持體適當之硬度。 On the side of the first surface 15a, a layer designed with priority in light extraction efficiency, color conversion efficiency, light distribution characteristics, and the like is provided, and the stress on the mounting surface side is relaxed, or the characteristics of the support as a substitute substrate are prioritized. Layer. For example, the resin layer 25 has a structure in which a filler such as cerium oxide particles is densely packed in a resin serving as a base, and is adjusted to have a suitable hardness as a support.

自發光層13向第1面15a側放射之光入射至螢光體層30，一部分光激發螢光體31，作為發光層13之光與螢光體31之光之混合光而獲得例如白色光。 Light emitted from the side of the first surface 15a from the light-emitting layer 13 is incident on the phosphor layer 30, and a part of the light-excited phosphor 31 is used as a mixture of light of the light-emitting layer 13 and light of the phosphor 31 to obtain, for example, white light.

此處，若於第1面15a上存在基板，則會產生不入射至螢光體層30 而自基板之側面向外部洩漏之光。即，發光層13之光之色彩較強之光自基板之側面洩漏，而可能導致於自上表面觀察螢光體層30之情形時可於外緣側看到藍色光環之現象等色分離或色不均。 Here, if the substrate is present on the first surface 15a, it is not incident on the phosphor layer 30. The light leaking from the side of the substrate to the outside. That is, the light having a stronger color of the light of the light-emitting layer 13 leaks from the side of the substrate, which may cause the color separation of the blue aura to be seen on the outer edge side when the phosphor layer 30 is viewed from the upper surface or Uneven color.

相對於此，根據實施形態，由於在第1面15a與螢光體層30之間不存在基板，故而可防止因發光層13之光之色彩較強之光在基板側面洩漏而引起之色分離或色不均。 On the other hand, according to the embodiment, since the substrate does not exist between the first surface 15a and the phosphor layer 30, it is possible to prevent color separation due to leakage of light having a strong color of light from the light-emitting layer 13 on the side surface of the substrate. Uneven color.

進而，根據實施形態，於半導體層15之側面15c，介隔絕緣膜18而設置有反射膜51。自發光層13朝向半導體層15之側面15c之光於反射膜51反射而不向外部洩漏。因此，與於第1面15a側不存在基板之特徵相輔相成，可防止因來自半導體發光裝置之側面側之漏光而引起之色分離或色不均。 Further, according to the embodiment, the reflective film 51 is provided on the side surface 15c of the semiconductor layer 15 by insulating the edge film 18. The light from the light-emitting layer 13 toward the side surface 15c of the semiconductor layer 15 is reflected by the reflection film 51 without leaking to the outside. Therefore, it is complementary to the feature that the substrate does not exist on the side of the first surface 15a, and color separation or color unevenness due to light leakage from the side surface side of the semiconductor light-emitting device can be prevented.

設置於反射膜51與半導體層15之側面15c之間之絕緣膜18防止反射膜51中所包含之金屬向半導體層15擴散。藉此，可防止半導體層15之例如GaN之金屬污染，從而可防止半導體層15之劣化。 The insulating film 18 provided between the reflective film 51 and the side surface 15c of the semiconductor layer 15 prevents the metal contained in the reflective film 51 from diffusing into the semiconductor layer 15. Thereby, metal contamination of the semiconductor layer 15, such as GaN, can be prevented, so that deterioration of the semiconductor layer 15 can be prevented.

又，設置於反射膜51與螢光體層30之間、及樹脂層25與螢光體層30之間之絕緣膜18提高反射膜51與螢光體層30之密接性、及樹脂層25與螢光體層30之密接性。 Moreover, the insulating film 18 provided between the reflective film 51 and the phosphor layer 30 and between the resin layer 25 and the phosphor layer 30 improves the adhesion between the reflective film 51 and the phosphor layer 30, and the resin layer 25 and the fluorescent layer. The adhesion of the body layer 30.

絕緣膜18例如為氧化矽膜、氮化矽膜等無機絕緣膜。即，半導體層15之第1面15a、第2面、第1半導體層11之側面15c、第2半導體層12之側面、發光層13之側面由無機絕緣膜覆蓋。無機絕緣膜包圍半導體層15，將半導體層15封閉使其免受金屬或水分等之影響。 The insulating film 18 is, for example, an inorganic insulating film such as a hafnium oxide film or a tantalum nitride film. That is, the first surface 15a of the semiconductor layer 15, the second surface, the side surface 15c of the first semiconductor layer 11, the side surface of the second semiconductor layer 12, and the side surface of the light-emitting layer 13 are covered with an inorganic insulating film. The inorganic insulating film surrounds the semiconductor layer 15, and the semiconductor layer 15 is sealed from metal, moisture, or the like.

此處，圖3(b)表示實施形態之半導體發光裝置之局部剖面之電子顯微鏡圖像。圖3(b)表示n側配線層22之靠近p側配線層21之端部附近。 Here, Fig. 3(b) shows an electron microscope image of a partial cross section of the semiconductor light-emitting device of the embodiment. 3(b) shows the vicinity of the end portion of the n-side wiring layer 22 close to the p-side wiring layer 21.

又，圖3(a)係圖3(b)中之A部之放大模式剖視圖。 3(a) is an enlarged schematic cross-sectional view of a portion A in FIG. 3(b).

如上文中參照圖7(a)所敍述般，於絕緣膜18上，依序形成基底金 屬膜(鋁膜)61、密接層(鈦膜)62、及籽晶層(銅膜)63。繼而，藉由鍍敷法於籽晶層(銅膜)63上形成銅配線層21、22。 As described above with reference to FIG. 7(a), the base gold is sequentially formed on the insulating film 18. It is a film (aluminum film) 61, an adhesion layer (titanium film) 62, and a seed layer (copper film) 63. Then, copper wiring layers 21, 22 are formed on the seed layer (copper film) 63 by plating.

由於籽晶層63與配線層21、22為相同之銅膜，故而於圖3(a)中，將籽晶層與n側配線層22一體化而表示。即，籽晶層亦作為配線層21、22之一部分而包含。 Since the seed layer 63 and the wiring layers 21 and 22 are the same copper film, the seed layer and the n-side wiring layer 22 are integrated and shown in FIG. 3(a). That is, the seed layer is also included as one of the wiring layers 21 and 22.

再者，密接層(鈦膜)62設置於配線層21、22之整個面。因此，亦可包含密接層62在內稱為配線層21、22。 Further, an adhesion layer (titanium film) 62 is provided on the entire surface of the wiring layers 21 and 22. Therefore, the wiring layers 21 and 22 may be referred to as including the adhesion layer 62.

根據實施形態，如圖3(a)所示，在n側配線層22與絕緣膜18之間存在未設置基底金屬膜(鋁膜)61之區域。在n側配線層22之端部22b與絕緣膜18之間，埋入有樹脂層25之一部分25a。 According to the embodiment, as shown in FIG. 3(a), a region where the underlying metal film (aluminum film) 61 is not provided exists between the n-side wiring layer 22 and the insulating film 18. A portion 25a of the resin layer 25 is buried between the end portion 22b of the n-side wiring layer 22 and the insulating film 18.

此處，圖13(b)表示參照例中之配線層22之端部附近之模式剖視圖。該參照例中，於n側配線層22與絕緣膜18之間之區域之整個面設置有基底金屬膜61。因此，n側配線層22之邊緣(側面)、密接層62之邊緣、及基底金屬膜61之邊緣對齊。 Here, FIG. 13(b) is a schematic cross-sectional view showing the vicinity of the end portion of the wiring layer 22 in the reference example. In this reference example, the base metal film 61 is provided over the entire surface of the region between the n-side wiring layer 22 and the insulating film 18. Therefore, the edge (side surface) of the n-side wiring layer 22, the edge of the adhesion layer 62, and the edge of the base metal film 61 are aligned.

有如下傾向：對無機膜與金屬膜之界面施加較無機膜與樹脂之界面強之應力。於圖13(b)之構造中，應力尤其易於集中在金屬膜80之邊緣附近之端部與絕緣膜18之界面，從而有可能於金屬膜80之邊緣附近之絕緣膜18產生龜裂c。 There is a tendency that a stress stronger than the interface between the inorganic film and the resin is applied to the interface between the inorganic film and the metal film. In the configuration of FIG. 13(b), the stress is particularly likely to concentrate on the interface between the end portion near the edge of the metal film 80 and the insulating film 18, so that it is possible to generate the crack c in the insulating film 18 near the edge of the metal film 80.

而且，若水分自n側外部端子24a與樹脂層25之界面浸入，則有可能該水分會通過n側金屬支柱24之側面與樹脂層25之界面、及n側配線層22與樹脂層25之界面而到達至產生於絕緣膜18之龜裂c。根據圖13(b)之參照例，成為水分之浸入路徑之金屬膜80之側面(邊緣)與樹脂層25之界面易於朝向龜裂c呈直線狀相連，從而易於容許水分向龜裂c浸入。 Further, when moisture is infiltrated from the interface between the n-side external terminal 24a and the resin layer 25, the moisture may pass through the interface between the side surface of the n-side metal post 24 and the resin layer 25, and the n-side wiring layer 22 and the resin layer 25. The interface reaches the crack c generated in the insulating film 18. According to the reference example of Fig. 13 (b), the interface between the side surface (edge) of the metal film 80 which is the water immersion path and the resin layer 25 is easily connected linearly toward the crack c, and it is easy to allow moisture to enter the crack c.

若水分通過絕緣膜18之龜裂c到達至電極16、17或半導體層15，則可能成為使可靠性下降之主要原因。 If moisture reaches the electrodes 16 and 17 or the semiconductor layer 15 through the crack c of the insulating film 18, the reliability may be lowered.

相對於此，根據實施形態，如圖3(a)所示，與絕緣膜18相接之(n側)基底金屬膜61之邊緣61a較n側配線層22之邊緣(側面)22c更後退，且在n側配線層22之端部22b與絕緣膜18之間設置有樹脂層25之一部分25a。 On the other hand, according to the embodiment, as shown in FIG. 3(a), the edge 61a of the (n-side) base metal film 61 that is in contact with the insulating film 18 is retracted from the edge (side surface) 22c of the n-side wiring layer 22, A portion 25a of the resin layer 25 is provided between the end portion 22b of the n-side wiring layer 22 and the insulating film 18.

即，成為水分之浸入路徑之金屬與樹脂層25之界面於朝向絕緣膜18側之中途沿橫向彎曲。 In other words, the interface between the metal which is the water immersion path and the resin layer 25 is curved in the lateral direction toward the side of the insulating film 18.

於圖3(a)之構造中，應力易於集中在基底金屬膜61之邊緣61a附近之端部與絕緣膜18之界面，從而易於在與基底金屬膜61之邊緣61a附近相接之絕緣膜18產生龜裂。 In the configuration of Fig. 3(a), the stress tends to concentrate on the interface between the end portion near the edge 61a of the base metal film 61 and the insulating film 18, thereby facilitating the insulating film 18 which is adjacent to the edge 61a of the base metal film 61. Cracks are produced.

然而，根據實施形態，即便於絕緣膜18產生龜裂，朝向該龜裂側之水分之浸入路徑亦會於中途彎曲，與圖13(b)所示之參照例相比，至龜裂為止之水分之浸入路徑較長，從而水分變得難以到達至龜裂。因此，可抑制水分向電極16、17或半導體層15浸入，從而能夠提供可靠性較高之半導體發光裝置。 However, according to the embodiment, even if a crack occurs in the insulating film 18, the water immersing path toward the crack side is curved in the middle, and the crack is compared with the reference example shown in Fig. 13 (b). The water immersion path is long, so that the water becomes difficult to reach to the crack. Therefore, it is possible to suppress the intrusion of moisture into the electrodes 16, 17 or the semiconductor layer 15, and it is possible to provide a highly reliable semiconductor light-emitting device.

設置於n側配線層22之端部22b(密接層62之端部)與絕緣膜18之間之樹脂層25之一部分25a之膜厚t與基底金屬膜61之膜厚相等。作為基底金屬膜61之鋁膜於厚度小於40nm時，反射率與膜厚成比例地增大，於膜厚大於等於40nm時，反射率不會再進一步變高。因此，上述膜厚t大於等於40nm，例如為100nm左右。 The film thickness t of one portion 25a of the resin layer 25 provided between the end portion 22b of the n-side wiring layer 22 (the end portion of the adhesion layer 62) and the insulating film 18 is equal to the film thickness of the underlying metal film 61. When the thickness of the aluminum film as the underlying metal film 61 is less than 40 nm, the reflectance increases in proportion to the film thickness, and when the film thickness is 40 nm or more, the reflectance does not further increase. Therefore, the above film thickness t is 40 nm or more, for example, about 100 nm.

又，與絕緣膜18相接之基底金屬膜61之邊緣61a距n側配線層22之邊緣22c之後退量、即n側配線層22之端部22b與絕緣膜18之間之樹脂層25a之長度L較長時，自水分之浸入路徑(樹脂層25與n側配線層22之邊緣22c之界面)至絕緣膜18中易於產生龜裂之位置為止之距離變長。 Further, the edge 61a of the base metal film 61 that is in contact with the insulating film 18 is retracted from the edge 22c of the n-side wiring layer 22, that is, the resin layer 25a between the end portion 22b of the n-side wiring layer 22 and the insulating film 18. When the length L is long, the distance from the water immersion path (the interface between the resin layer 25 and the edge 22c of the n-side wiring layer 22) to the position where the crack is likely to occur in the insulating film 18 becomes long.

為了抑制水分向龜裂浸入，上述長度L較理想為例如大於等於2~3μm。若長度L相對於上述膜厚t之比大於等於10，則即便於基底金屬膜61之邊緣61a附近之絕緣膜18產生龜裂，亦能夠充分地抑制水分 到達至龜裂。 In order to suppress the infiltration of moisture into the crack, the length L is preferably, for example, 2 to 3 μm or more. When the ratio of the length L to the film thickness t is 10 or more, even if the insulating film 18 in the vicinity of the edge 61a of the underlying metal film 61 is cracked, the moisture can be sufficiently suppressed. Arrived to the crack.

於圖3(a)中表示有n側配線層22之端部22b附近之構造，但如圖13(a)所示，於p側配線層21之端部21b附近，亦使基底金屬膜61之邊緣61a後退。 3(a) shows the structure in the vicinity of the end portion 22b of the n-side wiring layer 22. However, as shown in Fig. 13(a), the base metal film 61 is also formed in the vicinity of the end portion 21b of the p-side wiring layer 21. The edge 61a is retreated.

在p側配線層21與絕緣膜18之間存在未設置基底金屬膜(鋁膜)61之區域。而且，在p側配線層21之端部21b與絕緣膜18之間，埋入有樹脂層25之一部分25a。 A region where the underlying metal film (aluminum film) 61 is not provided exists between the p-side wiring layer 21 and the insulating film 18. Further, a portion 25a of the resin layer 25 is buried between the end portion 21b of the p-side wiring layer 21 and the insulating film 18.

於圖13(a)之構成中，即便於(p側)基底金屬膜61之邊緣61a附近之絕緣膜18產生有龜裂，水分朝向該龜裂之浸入路徑亦會於中途彎曲，與圖13(b)所示之參照例相比，至龜裂為止之水分之浸入路徑較長，從而水分變得不易到達至龜裂。因此，可抑制水分向電極16、17或半導體層15浸入，從而能夠提供可靠性較高之半導體發光裝置。 In the configuration of Fig. 13(a), even if the insulating film 18 in the vicinity of the edge 61a of the (p-side) base metal film 61 is cracked, the water immersing path toward the crack is also bent midway, and Fig. 13 In the reference example shown in (b), the water immersion path until the crack is long, and the water does not easily reach the crack. Therefore, it is possible to suppress the intrusion of moisture into the electrodes 16, 17 or the semiconductor layer 15, and it is possible to provide a highly reliable semiconductor light-emitting device.

設置於p側配線層21之端部21b(密接層62之端部)與絕緣膜18之間之樹脂層25之一部分25a之膜厚t與基底金屬膜61之膜厚相等。如上所述，膜厚t大於等於40nm，例如為100nm左右。 The film thickness t of one portion 25a of the resin layer 25 provided between the end portion 21b of the p-side wiring layer 21 (the end portion of the adhesion layer 62) and the insulating film 18 is equal to the film thickness of the underlying metal film 61. As described above, the film thickness t is 40 nm or more, for example, about 100 nm.

又，與絕緣膜18相接之基底金屬膜61之邊緣61a距p側配線層21之邊緣21c之後退量、即p側配線層21之端部21b與絕緣膜18之間之樹脂層25a之長度L較長時，自水分之浸入路徑(樹脂層25與p側配線層21之邊緣21c之界面)至絕緣膜18中易於產生龜裂之位置為止之距離變長。 Further, the edge 61a of the base metal film 61 that is in contact with the insulating film 18 is retracted from the edge 21c of the p-side wiring layer 21, that is, the resin layer 25a between the end portion 21b of the p-side wiring layer 21 and the insulating film 18. When the length L is long, the distance from the water immersion path (the interface between the resin layer 25 and the edge 21c of the p-side wiring layer 21) to the position where the crack is likely to occur in the insulating film 18 becomes long.

為了抑制水分向龜裂浸入，上述長度L較理想為例如大於等於2~3μm。若長度L相對於上述膜厚t之比大於等於10，則即便於基底金屬膜61之邊緣61a附近之絕緣膜18產生龜裂，亦能夠充分地抑制水分到達至龜裂。 In order to suppress the infiltration of moisture into the crack, the length L is preferably, for example, 2 to 3 μm or more. When the ratio of the length L to the film thickness t is 10 or more, even if cracks occur in the insulating film 18 in the vicinity of the edge 61a of the base metal film 61, it is possible to sufficiently suppress the moisture from reaching the crack.

再者，於n側配線層22之與p側配線層21為相反側之端部22b附近，與圖3(a)同樣地，基底金屬膜61之邊緣61a亦自n側配線層22之邊緣22c後退，且於其後退之區域設置有樹脂層25之一部分25a。 Further, in the vicinity of the end portion 22b of the n-side wiring layer 22 opposite to the p-side wiring layer 21, the edge 61a of the underlying metal film 61 is also from the edge of the n-side wiring layer 22, similarly to FIG. 3(a). 22c is retracted, and a portion 25a of the resin layer 25 is provided in a region where it retreats.

同樣地，於p側配線層21之與n側配線層22為相反側之端部21b附近，與圖13(a)同樣地，基底金屬膜61之邊緣61a亦自p側配線層21之邊緣21c後退，且於其後退之區域設置有樹脂層25之一部分25a。 Similarly, in the vicinity of the end portion 21b of the p-side wiring layer 21 opposite to the n-side wiring layer 22, the edge 61a of the underlying metal film 61 is also from the edge of the p-side wiring layer 21 as in Fig. 13(a). 21c is retracted, and a portion 25a of the resin layer 25 is provided in a region where it retreats.

其次，參照圖4(a)~圖11(b)，對半導體發光裝置之製造方法進行說明。 Next, a method of manufacturing a semiconductor light-emitting device will be described with reference to FIGS. 4(a) to 11(b).

如圖4(a)所示，例如藉由MOCVD(metal organic chemical vapor deposition，金屬有機化學氣相沈積)法，於基板10之主面上，依序磊晶成長第1半導體層11、發光層13及第2半導體層12。 As shown in FIG. 4(a), the first semiconductor layer 11 and the light-emitting layer are sequentially epitaxially grown on the main surface of the substrate 10 by MOCVD (metal organic chemical vapor deposition). 13 and the second semiconductor layer 12.

於半導體層15中，基板10側之面為第1面15a，基板10之相反側之面為第2面15b。 In the semiconductor layer 15, the surface on the substrate 10 side is the first surface 15a, and the surface on the opposite side of the substrate 10 is the second surface 15b.

基板10例如為矽基板。或者，基板10亦可為藍寶石基板。半導體層15例如為含有氮化鎵(GaN)之氮化物半導體層。 The substrate 10 is, for example, a tantalum substrate. Alternatively, the substrate 10 may also be a sapphire substrate. The semiconductor layer 15 is, for example, a nitride semiconductor layer containing gallium nitride (GaN).

第1半導體層11例如具有設置於基板10之主面上之緩衝層、及設置於緩衝層上之n型GaN層。第2半導體層12例如具有設置於發光層13上之p型AlGaN層、及設置於其上之p型GaN層。發光層13例如具有MQW(Multiple Quantum well，多量子井)構造。 The first semiconductor layer 11 has, for example, a buffer layer provided on the main surface of the substrate 10 and an n-type GaN layer provided on the buffer layer. The second semiconductor layer 12 has, for example, a p-type AlGaN layer provided on the light-emitting layer 13 and a p-type GaN layer provided thereon. The light-emitting layer 13 has, for example, an MQW (Multiple Quantum Well) structure.

圖4(b)表示選擇性地去除第2半導體層12及發光層13後之狀態。例如，藉由RIE(Reactive Ion Etching，反應性離子蝕刻)法，選擇性地蝕刻第2半導體層12及發光層13而使第1半導體層11露出。 FIG. 4(b) shows a state in which the second semiconductor layer 12 and the light-emitting layer 13 are selectively removed. For example, the second semiconductor layer 12 and the light-emitting layer 13 are selectively etched by RIE (Reactive Ion Etching) to expose the first semiconductor layer 11.

其次，如圖5(a)所示，選擇性地去除第1半導體層11而形成溝槽90。於基板10之主面上，半導體層15由溝槽90而分離成複數個。溝槽90係以例如格子狀圖案形成於晶圓狀之基板10上。 Next, as shown in FIG. 5(a), the first semiconductor layer 11 is selectively removed to form the trench 90. On the main surface of the substrate 10, the semiconductor layer 15 is separated into a plurality of grooves by the grooves 90. The trench 90 is formed on the wafer-shaped substrate 10 in, for example, a lattice pattern.

溝槽90貫通半導體層15，到達至基板10。根據蝕刻條件，亦存在如下情形：基板10之主面亦被略微蝕刻，從而溝槽90之底面較基板10與半導體層15之界面更向下方後退。再者，溝槽90亦可於形成p側電極16及n側電極17之後形成。 The trench 90 penetrates the semiconductor layer 15 and reaches the substrate 10. Depending on the etching conditions, there is also a case where the main surface of the substrate 10 is also slightly etched, so that the bottom surface of the trench 90 retreats more downward than the interface between the substrate 10 and the semiconductor layer 15. Further, the trench 90 may be formed after the p-side electrode 16 and the n-side electrode 17 are formed.

其次，如圖5(b)所示，於第2半導體層12之表面形成p側電極16。又，於第2半導體層12及發光層13被選擇性地去除後之區域之第1半導體層11之表面，形成n側電極17。 Next, as shown in FIG. 5(b), the p-side electrode 16 is formed on the surface of the second semiconductor layer 12. Moreover, the n-side electrode 17 is formed on the surface of the first semiconductor layer 11 in the region where the second semiconductor layer 12 and the light-emitting layer 13 are selectively removed.

形成於積層有發光層13之區域之p側電極16包含可反射發光層13之放射光之反射膜。例如，p側電極16含有銀、銀合金、鋁、鋁合金等。又，為了防止反射膜之硫化、氧化，p側電極16包含金屬保護膜(障壁金屬)。 The p-side electrode 16 formed in a region where the light-emitting layer 13 is laminated includes a reflective film that reflects the emitted light of the light-emitting layer 13. For example, the p-side electrode 16 contains silver, a silver alloy, aluminum, an aluminum alloy, or the like. Further, in order to prevent vulcanization and oxidation of the reflective film, the p-side electrode 16 includes a metal protective film (barrier metal).

其次，如圖6(a)所示，以覆蓋設置於基板10上之積層體之方式形成絕緣膜18。絕緣膜18覆蓋半導體層15之第2面、p側電極16及n側電極17。又，絕緣膜18覆蓋半導體層15之與第1面15a連續之側面15c。進而，絕緣膜18亦形成於溝槽90之底面之基板10之表面。 Next, as shown in FIG. 6(a), the insulating film 18 is formed so as to cover the laminate provided on the substrate 10. The insulating film 18 covers the second surface of the semiconductor layer 15, the p-side electrode 16, and the n-side electrode 17. Further, the insulating film 18 covers the side surface 15c of the semiconductor layer 15 which is continuous with the first surface 15a. Further, an insulating film 18 is also formed on the surface of the substrate 10 on the bottom surface of the trench 90.

絕緣膜18係例如藉由CVD(Chemical Vapor Deposition，化學氣相沈積)法而形成之氧化矽膜或氮化矽膜。於絕緣膜18，例如藉由使用抗蝕劑遮罩之濕式蝕刻，而如圖6(b)所示般形成第1開口18a與第2開口18b。第1開口18a到達至p側電極16，第2開口18b到達至n側電極17之接觸部17c。 The insulating film 18 is, for example, a hafnium oxide film or a tantalum nitride film formed by a CVD (Chemical Vapor Deposition) method. The first opening 18a and the second opening 18b are formed in the insulating film 18 by wet etching using a resist mask, for example, as shown in Fig. 6(b). The first opening 18a reaches the p-side electrode 16, and the second opening 18b reaches the contact portion 17c of the n-side electrode 17.

其次，如圖6(b)所示，於絕緣膜18之表面、第1開口18a之內壁(側壁及底面)、及第2開口18b之內壁(側壁及底面)上形成金屬膜60。如圖7(a)所示，金屬膜60具有基底金屬膜(鋁膜)61、密接層(鈦膜)62、及籽晶層(銅膜)63。金屬膜60係藉由例如濺鍍法而形成。 Next, as shown in FIG. 6(b), a metal film 60 is formed on the surface of the insulating film 18, the inner walls (side walls and bottom surfaces) of the first openings 18a, and the inner walls (side walls and bottom surfaces) of the second openings 18b. As shown in FIG. 7(a), the metal film 60 has a base metal film (aluminum film) 61, an adhesion layer (titanium film) 62, and a seed layer (copper film) 63. The metal film 60 is formed by, for example, a sputtering method.

其次，於金屬膜60上選擇性地形成圖7(b)所示之抗蝕劑遮罩91後，藉由將金屬膜60之銅膜63用作籽晶層之電解銅鍍敷法，形成p側配線層21、n側配線層22及反射膜51。 Next, after the resist mask 91 shown in FIG. 7(b) is selectively formed on the metal film 60, it is formed by electrolytic copper plating using the copper film 63 of the metal film 60 as a seed layer. The p-side wiring layer 21, the n-side wiring layer 22, and the reflective film 51.

p側配線層21亦形成於第1開口18a內，而與p側電極16電性連接。n側配線層22亦形成於第2開口18b內，而與n側電極17之接觸部17c電性連接。 The p-side wiring layer 21 is also formed in the first opening 18a, and is electrically connected to the p-side electrode 16. The n-side wiring layer 22 is also formed in the second opening 18b, and is electrically connected to the contact portion 17c of the n-side electrode 17.

其次，於使用例如溶劑或者氧電漿去除抗蝕劑遮罩91後，選擇性地形成圖8(a)所示之抗蝕劑遮罩92。或者，亦可不去除抗蝕劑遮罩91而形成抗蝕劑遮罩92。 Next, after the resist mask 91 is removed using, for example, a solvent or an oxygen plasma, the resist mask 92 shown in Fig. 8(a) is selectively formed. Alternatively, the resist mask 92 may be formed without removing the resist mask 91.

於形成抗蝕劑遮罩92後，藉由將p側配線層21及n側配線層22用作籽晶層之電解銅鍍敷法，形成p側金屬支柱23及n側金屬支柱24。 After the resist mask 92 is formed, the p-side metal pillar 23 and the n-side metal pillar 24 are formed by electrolytic copper plating using the p-side wiring layer 21 and the n-side wiring layer 22 as a seed layer.

p側金屬支柱23形成於p側配線層21上。p側配線層21與p側金屬支柱23係以相同之銅材料一體化。n側金屬支柱24形成於n側配線層22上。n側配線層22與n側金屬支柱24係以相同之銅材料一體化。 The p-side metal pillar 23 is formed on the p-side wiring layer 21. The p-side wiring layer 21 and the p-side metal pillar 23 are integrated by the same copper material. The n-side metal post 24 is formed on the n-side wiring layer 22. The n-side wiring layer 22 and the n-side metal pillar 24 are integrated with the same copper material.

抗蝕劑遮罩92係使用例如溶劑或者氧電漿而去除。於該時點，p側配線層21與n側配線層22經由金屬膜60相連。又，p側配線層21與反射膜51亦經由金屬膜60相連，n側配線層22與反射膜51亦經由金屬膜60相連。 The resist mask 92 is removed using, for example, a solvent or an oxygen plasma. At this time, the p-side wiring layer 21 and the n-side wiring layer 22 are connected via the metal film 60. Further, the p-side wiring layer 21 and the reflection film 51 are also connected via the metal film 60, and the n-side wiring layer 22 and the reflection film 51 are also connected via the metal film 60.

因此，藉由蝕刻去除p側配線層21與n側配線層22之間之金屬膜60、p側配線層21與反射膜51之間之金屬膜60、及n側配線層22與反射膜51之間之金屬膜60。此時，充分厚於金屬膜60之p側配線層21、n側配線層22、p側金屬支柱23、及n側金屬支柱24被用作遮罩。 Therefore, the metal film 60 between the p-side wiring layer 21 and the n-side wiring layer 22, the metal film 60 between the p-side wiring layer 21 and the reflective film 51, and the n-side wiring layer 22 and the reflective film 51 are removed by etching. The metal film 60 is between. At this time, the p-side wiring layer 21, the n-side wiring layer 22, the p-side metal pillar 23, and the n-side metal pillar 24 which are sufficiently thicker than the metal film 60 are used as a mask.

籽晶層(銅膜)63、密接層(鈦膜)62、及基底金屬膜(鋁膜)61係分別使用不同之蝕刻液選擇性地被蝕刻。 The seed layer (copper film) 63, the adhesion layer (titanium film) 62, and the base metal film (aluminum film) 61 are selectively etched using different etching liquids.

如圖9(a)至圖9(b)所示，首先，蝕刻籽晶層(銅膜)63，其次，蝕刻密接層(鈦膜)62。其後，蝕刻基底金屬膜(鋁膜)61。 As shown in FIGS. 9(a) to 9(b), first, the seed layer (copper film) 63 is etched, and next, the adhesion layer (titanium film) 62 is etched. Thereafter, a base metal film (aluminum film) 61 is etched.

藉此，切斷經由金屬膜60之p側配線層21與n側配線層22之電性連接、p側配線層21與反射膜51之電性連接、及n側配線層22與反射膜51之電性連接(圖8(b))。 Thereby, the p-side wiring layer 21 and the n-side wiring layer 22 via the metal film 60 are electrically connected, the p-side wiring layer 21 and the reflective film 51 are electrically connected, and the n-side wiring layer 22 and the reflective film 51 are cut. Electrical connection (Fig. 8(b)).

又，於蝕刻基底金屬膜(鋁膜)61時，於去除未設置n側配線層22之部分之基底金屬膜61後仍進行蝕刻，從而如圖9(C)所示，使基底金屬膜61之邊緣61a較n側配線層22之邊緣(側面)22c更後退。藉此，在n 側配線層22之端部22b(密接層62之端部)與絕緣膜18之間形成空隙70。於p側配線層21之端部亦相同。 Further, when the underlying metal film (aluminum film) 61 is etched, etching is performed after removing the underlying metal film 61 in which the n-side wiring layer 22 is not provided, so that the underlying metal film 61 is formed as shown in FIG. 9(C). The edge 61a is more retracted than the edge (side) 22c of the n-side wiring layer 22. Thereby, in n A gap 70 is formed between the end portion 22b of the side wiring layer 22 (the end portion of the adhesion layer 62) and the insulating film 18. The end portions of the p-side wiring layer 21 are also the same.

於作為鋁膜之基底金屬膜61之濕式蝕刻中，使用例如TMAH(氫氧化四甲基銨)水溶液、混酸(硝酸與硫酸之混合物)水溶液等鹼系藥液。對於該藥液，銅膜及鈦膜幾乎不會被蝕刻。 In the wet etching of the underlying metal film 61 as the aluminum film, an alkali-based chemical solution such as a TMAH (tetramethylammonium hydroxide) aqueous solution or a mixed acid (mixture of nitric acid and sulfuric acid) aqueous solution is used. For this chemical solution, the copper film and the titanium film are hardly etched.

其次，於圖8(b)所示之積層體上，形成圖10(a)所示之樹脂層25。樹脂層25覆蓋p側配線部41及n側配線部43。又，樹脂層25覆蓋反射膜51。 Next, on the laminated body shown in Fig. 8 (b), the resin layer 25 shown in Fig. 10 (a) is formed. The resin layer 25 covers the p-side wiring portion 41 and the n-side wiring portion 43. Further, the resin layer 25 covers the reflective film 51.

作為加強配線部之第2絕緣膜之樹脂層25係以具有流動性之液狀之狀態塗佈，且進入至配線層之端部與絕緣膜18之間之空隙70。其後，使樹脂層25硬化。或者，亦可藉由塗佈液狀玻璃並使其硬化而形成第2絕緣膜。 The resin layer 25 which is the second insulating film of the reinforcing wiring portion is applied in a liquid state having fluidity, and enters the gap 70 between the end portion of the wiring layer and the insulating film 18. Thereafter, the resin layer 25 is cured. Alternatively, the second insulating film may be formed by applying a liquid glass and hardening it.

樹脂層25與p側配線部41及n側配線部43一併構成支持體100。於在該支持體100支持有半導體層15之狀態下，去除基板10。 The resin layer 25 constitutes the support 100 together with the p-side wiring portion 41 and the n-side wiring portion 43. The substrate 10 is removed in a state where the support 100 supports the semiconductor layer 15.

例如，作為矽基板之基板10係藉由乾式蝕刻被去除。又，亦可藉由濕式蝕刻去除基板(矽基板)10。或者，於基板10為藍寶石基板之情形時，可藉由雷射剝離(laser lift off)法去除。 For example, the substrate 10 as a germanium substrate is removed by dry etching. Further, the substrate (tantalum substrate) 10 may be removed by wet etching. Alternatively, when the substrate 10 is a sapphire substrate, it can be removed by a laser lift off method.

磊晶成長於基板10上之半導體層15存在包含較大之內部應力之情形。又，p側金屬支柱23、n側金屬支柱24及樹脂層25例如為較GaN系材料之半導體層15柔軟之材料。因此，即便磊晶成長時之內部應力於剝離基板10時瞬間釋放，p側金屬支柱23、n側金屬支柱24及樹脂層25亦會吸收該應力。因此，可避免半導體層15於去除基板10之過程中破損。 The semiconductor layer 15 which is epitaxially grown on the substrate 10 has a case where it contains a large internal stress. Further, the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 are, for example, softer than the semiconductor layer 15 of the GaN-based material. Therefore, even if the internal stress at the time of epitaxial growth is instantaneously released when the substrate 10 is peeled off, the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 absorb the stress. Therefore, the semiconductor layer 15 can be prevented from being damaged during the process of removing the substrate 10.

藉由去除基板10，如圖10(b)所示，半導體層15之第1面15a露出。於露出之第1面15a形成微小凹凸。例如，利用KOH(氫氧化鉀)水溶液或TMAH等對第1面15a進行濕式蝕刻。於該蝕刻中，產生依存於 結晶面方位之蝕刻速度之差異。因此，可於第1面15a形成凹凸。藉由在第1面15a形成微小凹凸，可提高發光層13之放射光之提取效率。 By removing the substrate 10, as shown in FIG. 10(b), the first surface 15a of the semiconductor layer 15 is exposed. Fine unevenness is formed on the exposed first surface 15a. For example, the first surface 15a is wet-etched by a KOH (potassium hydroxide) aqueous solution or TMAH or the like. In this etching, it depends on The difference in etching speed of the crystal plane orientation. Therefore, irregularities can be formed on the first surface 15a. By forming minute irregularities on the first surface 15a, the extraction efficiency of the emitted light of the light-emitting layer 13 can be improved.

如圖11(a)所示，於第1面15a上，介隔絕緣膜19而形成螢光體層30。螢光體層30係藉由例如印刷、灌注、模塑、壓縮成形等方法而形成。絕緣膜19提高半導體層15與螢光體層30之密接性。 As shown in FIG. 11(a), the phosphor film layer 30 is formed by interposing the edge film 19 on the first surface 15a. The phosphor layer 30 is formed by a method such as printing, pouring, molding, compression molding, or the like. The insulating film 19 improves the adhesion between the semiconductor layer 15 and the phosphor layer 30.

又，作為螢光體層30，亦可將介隔結合材料燒結螢光體而成之燒結螢光體介隔絕緣膜19接著於螢光體層30。 Further, as the phosphor layer 30, a sintered phosphor dielectric film 19 which is formed by sintering a phosphor with a bonding material may be attached to the phosphor layer 30.

又，螢光體層30亦形成於半導體層15之側面15c周圍之晶片外區域上。於該晶片外區域亦設置有樹脂層25，於該樹脂層25上，介隔絕緣膜18而形成螢光體層30。 Further, the phosphor layer 30 is also formed on the outer surface of the wafer around the side surface 15c of the semiconductor layer 15. A resin layer 25 is also provided on the outer region of the wafer, and the phosphor layer 30 is formed on the resin layer 25 by insulating the edge film 18.

於形成螢光體層30後，研磨樹脂層25之表面(圖11(a)中之下表面)，從而如圖11(b)所示，p側金屬支柱23及n側金屬支柱24自樹脂層25露出。p側金屬支柱23之露出面成為p側外部端子23a，n側金屬支柱24之露出面成為n側外部端子24a。 After the phosphor layer 30 is formed, the surface of the resin layer 25 (the lower surface in FIG. 11(a)) is polished, so that the p-side metal pillar 23 and the n-side metal pillar 24 are self-resin layer as shown in FIG. 11(b). 25 exposed. The exposed surface of the p-side metal pillar 23 is the p-side external terminal 23a, and the exposed surface of the n-side metal pillar 24 is the n-side external terminal 24a.

其次，於形成有將複數個半導體層15分離之上述溝槽90之區域，切斷圖11(b)所示之構造體。即，切斷螢光體層30、絕緣膜18、及樹脂層25。其等係藉由例如切割刀片或雷射光被切斷。半導體層15由於不存在於切割區域，故而不會受到因切割所導致之損傷。 Next, a region in which the plurality of semiconductor layers 15 are separated from the trenches 90 is formed, and the structure shown in Fig. 11(b) is cut. That is, the phosphor layer 30, the insulating film 18, and the resin layer 25 are cut. They are cut off by, for example, a cutting blade or laser light. Since the semiconductor layer 15 is not present in the dicing region, it is not damaged by the dicing.

單片化前之上述各步驟係以包含複數個半導體層15之晶圓狀態進行。晶圓被單片化為包含至少1個半導體層15之半導體發光裝置。再者，半導體發光裝置既可為包含一個半導體層15之單晶片構造，亦可為包含複數個半導體層15之多晶片構造。 The above steps before singulation are performed in a wafer state including a plurality of semiconductor layers 15. The wafer is singulated into a semiconductor light emitting device including at least one semiconductor layer 15. Furthermore, the semiconductor light-emitting device may be a single-wafer structure including one semiconductor layer 15, or a multi-wafer structure including a plurality of semiconductor layers 15.

單片化前之上述各步驟係以晶圓狀態總括地進行，因此無需針對單片化後之各個器件進行配線層之形成、支柱之形成、利用樹脂層之封裝、及螢光體層之形成，從而可大幅地降低成本。 Since each of the above steps before singulation is performed in a wafer state, it is not necessary to form a wiring layer, form pillars, package with a resin layer, and form a phosphor layer for each device after singulation. This can greatly reduce costs.

於以晶圓狀態形成支持體100及螢光體層30後，將其等切斷，因 此螢光體層30之側面與支持體100之側面(樹脂層25之側面)對齊，該等側面形成經單片化所得之半導體發光裝置之側面。因此，亦與不存在基板10之情況相輔相成，從而可提供一種晶片尺寸封裝構造之小型之半導體發光裝置。 After the support 100 and the phosphor layer 30 are formed in a wafer state, they are cut off, etc. The side surface of the phosphor layer 30 is aligned with the side surface of the support 100 (the side surface of the resin layer 25) which forms the side surface of the semiconductor light-emitting device obtained by singulation. Therefore, it is also complementary to the case where the substrate 10 is not present, so that a small-sized semiconductor light-emitting device of a wafer-sized package structure can be provided.

於去除未設置配線層21、22之部分之金屬膜60時，如圖12(a)所示，亦可使密接層(鈦膜)62之邊緣62a相對於配線層22之邊緣22c後退。 When the metal film 60 in which the wiring layers 21 and 22 are not provided is removed, as shown in FIG. 12(a), the edge 62a of the adhesion layer (titanium film) 62 may be retreated with respect to the edge 22c of the wiring layer 22.

根據該構造，由於在自配線層22之邊緣22c與樹脂層25之界面至易於產生龜裂之基底金屬膜61之邊緣附近之路徑形成複數個彎曲部(階差)，故而通過配線層22之邊緣22c與樹脂層25之界面浸入而來之水分更難以到達至龜裂。 According to this configuration, since a plurality of curved portions (steps) are formed in the path from the interface between the edge 22c of the wiring layer 22 and the resin layer 25 to the edge of the base metal film 61 which is prone to cracking, the wiring layer 22 is passed. The moisture immersed in the interface between the edge 22c and the resin layer 25 is more difficult to reach the crack.

又，如圖12(b)所示，配線層22之端部22b(密接層62之端部)與絕緣膜18之間之樹脂25a之膜厚亦可小於基底金屬膜61之膜厚。 Further, as shown in FIG. 12(b), the film thickness of the resin 25a between the end portion 22b of the wiring layer 22 (the end portion of the adhesion layer 62) and the insulating film 18 may be smaller than the film thickness of the underlying metal film 61.

然而，擔心如下可能性：於密接層62中，形成於與基底金屬膜61之端部相接之部位之如圖12(b)所示之階差阻礙浸入至絕緣膜18側之水分於加熱步驟中向外部脫離。 However, there is a concern that in the adhesion layer 62, the step shown in FIG. 12(b), which is formed at a portion in contact with the end portion of the base metal film 61, hinders the moisture immersed in the side of the insulating film 18 from being heated. The step is to detach from the outside.

因此，配線層22之端部22b與絕緣膜18之間之樹脂25a之膜厚較理想為大於等於基底金屬膜61之膜厚。 Therefore, the film thickness of the resin 25a between the end portion 22b of the wiring layer 22 and the insulating film 18 is preferably equal to or larger than the film thickness of the underlying metal film 61.

圖14係另一實施形態之半導體發光裝置之模式剖視圖。 Fig. 14 is a schematic cross-sectional view showing a semiconductor light emitting device according to another embodiment.

如圖14所示，於半導體層15之第1面15a上，介隔絕緣膜19而設置有透明層35(光學層)。於透明層35之上表面、透明層35之側面及支持體100之側面設置有螢光體層30。 As shown in FIG. 14, a transparent layer 35 (optical layer) is provided on the first surface 15a of the semiconductor layer 15 by insulating the edge film 19. A phosphor layer 30 is provided on the upper surface of the transparent layer 35, the side surface of the transparent layer 35, and the side surface of the support 100.

透明層35使發光層13之放射光及螢光體31之放射光透過。作為透明層35，使用例如與結合材料32相同之材料。作為透明層35，亦可使用例如與結合材料32不同之材料。 The transparent layer 35 transmits the emitted light of the light-emitting layer 13 and the emitted light of the phosphor 31. As the transparent layer 35, for example, the same material as the bonding material 32 is used. As the transparent layer 35, for example, a material different from the bonding material 32 can be used.

透明層35亦形成於半導體層15之側面15c周邊之晶片外區域上。 因此，透明層35之平面尺寸大於半導體層15之平面尺寸。於晶片外區域，在絕緣膜18上設置有透明層35。 A transparent layer 35 is also formed on the outer surface of the wafer around the side 15c of the semiconductor layer 15. Therefore, the planar size of the transparent layer 35 is larger than the planar size of the semiconductor layer 15. A transparent layer 35 is provided on the insulating film 18 in the outer region of the wafer.

螢光體層30設置於透明層35之周圍、半導體層15之周圍、及支持體100之周圍，而形成半導體發光裝置之側面。透明層35之側面及支持體100之側面被螢光體層30覆蓋。藉此，可防止支持體100之側面之龜裂。 The phosphor layer 30 is disposed around the transparent layer 35, around the semiconductor layer 15, and around the support 100 to form a side surface of the semiconductor light-emitting device. The side surface of the transparent layer 35 and the side surface of the support 100 are covered by the phosphor layer 30. Thereby, cracking of the side surface of the support body 100 can be prevented.

又，通過螢光體層30與樹脂層25之邊界之水分之浸入路徑變長，從而水分不易到達至晶片。因此，可抑制水分向電極16、17或半導體層15侵入，從而能夠提供可靠性較高之半導體發光裝置。 Further, the water immersion path passing through the boundary between the phosphor layer 30 and the resin layer 25 becomes long, and moisture does not easily reach the wafer. Therefore, it is possible to suppress entry of moisture into the electrodes 16, 17 or the semiconductor layer 15, and it is possible to provide a highly reliable semiconductor light-emitting device.

於半導體層15之上表面15a與螢光體層30之間設置有透明層35。藉此，半導體層15所包含之發光面、與螢光體層30所包含之螢光體31之間之距離變遠。因此，螢光體31之溫度上升得以抑制，從而螢光體31之波長轉換效率之下降得以抑制。 A transparent layer 35 is provided between the upper surface 15a of the semiconductor layer 15 and the phosphor layer 30. Thereby, the distance between the light-emitting surface included in the semiconductor layer 15 and the phosphor 31 included in the phosphor layer 30 becomes longer. Therefore, the temperature rise of the phosphor 31 is suppressed, and the decrease in the wavelength conversion efficiency of the phosphor 31 is suppressed.

除上述內容以外，對透明層35，例如使用折射率高於螢光體層30之折射率之材料。透明層35具有半導體層15之折射率與螢光體層30之折射率之間之折射率。藉此，存在於光提取方向之介質間之折射率差變小，從而發光層13之放射光變得易於向螢光體層30之外部(空氣)放射。即，發光層13之放射光之提取效率提高。 In addition to the above, for the transparent layer 35, for example, a material having a refractive index higher than that of the phosphor layer 30 is used. The transparent layer 35 has a refractive index between the refractive index of the semiconductor layer 15 and the refractive index of the phosphor layer 30. Thereby, the difference in refractive index between the mediums existing in the light extraction direction becomes small, and the emitted light of the light-emitting layer 13 is easily emitted to the outside (air) of the phosphor layer 30. That is, the extraction efficiency of the emitted light of the light-emitting layer 13 is improved.

進而，發光層13被透明層35覆蓋之面積擴大。藉此，藉由透明層35使螢光體層30接收發光層13之光(例如藍色光)之入射之面積增大，從而可提高轉換效率。 Further, the area covered by the transparent layer 35 of the light-emitting layer 13 is enlarged. Thereby, the area where the phosphor layer 30 receives the light (for example, blue light) of the light-emitting layer 13 by the transparent layer 35 is increased, and the conversion efficiency can be improved.

又，根據本實施形態，可實現光學匹配調整之高精度化。藉此，光學特性提高。 Moreover, according to this embodiment, it is possible to achieve high precision of optical matching adjustment. Thereby, the optical characteristics are improved.

於上述實施形態中，作為設置於半導體層15之第1面15a側之光學層，並不限定於螢光體層，亦可為散射層。散射層包含使發光層13之放射光散射之複數個粒子狀之散射材料(例如鈦化合物)、及與複數個 散射材料一體化且使發光層13之放射光透過之結合材料(例如樹脂層)。除上述內容以外，透明層35亦可包含螢光體及散射材料中之至少任一種。 In the above embodiment, the optical layer provided on the first surface 15a side of the semiconductor layer 15 is not limited to the phosphor layer, and may be a scattering layer. The scattering layer includes a plurality of particulate scattering materials (for example, titanium compounds) for scattering the emitted light of the light-emitting layer 13, and a plurality of A bonding material (for example, a resin layer) in which the scattering material is integrated and the emitted light of the light-emitting layer 13 is transmitted. In addition to the above, the transparent layer 35 may also contain at least any one of a phosphor and a scattering material.

已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明主旨之範圍內，進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等之範圍內。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The various embodiments of the invention can be embodied in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. These embodiments and variations thereof are included in the scope of the invention and the scope of the invention as set forth in the appended claims.

15‧‧‧半導體層 15‧‧‧Semiconductor layer

16‧‧‧p側電極 16‧‧‧p side electrode

18‧‧‧絕緣膜 18‧‧‧Insulation film

22‧‧‧n側配線層 22‧‧‧n side wiring layer

22b‧‧‧n側配線層22之端部 End of 22b‧‧‧n side wiring layer 22

22c‧‧‧n側配線層22之邊緣(側面) Edge of the 22c‧‧‧n side wiring layer 22 (side)

25‧‧‧樹脂層 25‧‧‧ resin layer

25a‧‧‧樹脂層25之一部分 25a‧‧‧One part of the resin layer 25

61‧‧‧基底金屬膜 61‧‧‧Base metal film

61a‧‧‧基底金屬膜61之邊緣 61a‧‧‧The edge of the base metal film 61

62‧‧‧密接層 62‧‧ ‧ close layer

A‧‧‧部分 Part A‧‧‧

L‧‧‧長度 L‧‧‧ length

t‧‧‧膜厚 T‧‧‧ film thickness

Claims (17)

一種半導體發光裝置，其包括：半導體層，其包含：第1側、第2側、及設置於上述第1側與上述第2側之間之發光層；第1電極，其於上述半導體層之上述第2側，設置於上述半導體層；第2電極，其於上述半導體層之上述第2側，設置於上述半導體層；第1絕緣膜，其覆蓋上述半導體層之上述第2側；第1配線部，其設置於上述第1絕緣膜上，並且連接於上述第1電極；第2配線部，其設置於上述第1絕緣膜上，並且連接於上述第2電極；及第2絕緣膜，其設置於上述第1配線部與上述第2配線部之間；且在上述第1絕緣膜與上述第1配線部之端部之間，設置有上述第2絕緣膜之一部分。 A semiconductor light emitting device comprising: a semiconductor layer comprising: a first side, a second side; and a light emitting layer disposed between the first side and the second side; and a first electrode, wherein the semiconductor layer is The second side is provided on the semiconductor layer, and the second electrode is provided on the semiconductor layer on the second side of the semiconductor layer, and the first insulating film covers the second side of the semiconductor layer; a wiring portion that is provided on the first insulating film and that is connected to the first electrode, and a second wiring portion that is provided on the first insulating film and that is connected to the second electrode and the second insulating film. The first wiring portion is provided between the first wiring portion and the second wiring portion, and one of the second insulating films is provided between the first insulating film and the end portion of the first wiring portion. 如請求項1之半導體發光裝置，其中在上述第1絕緣膜與上述第2配線部之端部之間，設置有上述第2絕緣膜之一部分。 The semiconductor light-emitting device of claim 1, wherein one of the second insulating films is provided between the first insulating film and an end portion of the second wiring portion. 如請求項1或2之半導體發光裝置，其中上述第1配線部包含：與上述第1絕緣膜相接之第1基底金屬膜、及設置於上述第1基底金屬膜上之第1配線層，上述第2配線部包含：與上述第1絕緣膜相接之第2基底金屬膜、及設置於上述第2基底金屬膜上之第2配線層，在上述第1配線層之端部與上述第1絕緣膜之間，不介隔上述 第1基底金屬膜地設置有上述第2絕緣膜之一部分，在上述第2配線層之端部與上述第1絕緣膜之間，不介隔上述第2基底金屬膜地設置有上述第2絕緣膜之一部分。 The semiconductor light-emitting device of claim 1 or 2, wherein the first wiring portion includes: a first base metal film that is in contact with the first insulating film; and a first wiring layer that is provided on the first base metal film, The second wiring portion includes a second base metal film that is in contact with the first insulating film, and a second wiring layer that is provided on the second base metal film, and the end portion of the first wiring layer and the first portion 1 between the insulating films, without intervening above The first base metal film is provided with one of the second insulating films, and the second insulating layer is provided between the end portion of the second interconnect layer and the first insulating film without interposing the second base metal film. One part of the membrane. 如請求項3之半導體發光裝置，其中上述第1基底金屬膜及上述第2基底金屬膜為鋁膜。 The semiconductor light-emitting device of claim 3, wherein the first base metal film and the second base metal film are aluminum films. 如請求項1或2之半導體發光裝置，其中上述第2絕緣膜為樹脂。 The semiconductor light-emitting device of claim 1 or 2, wherein the second insulating film is a resin. 如請求項3之半導體發光裝置，其中上述第1配線層之上述端部與上述第1絕緣膜之間之上述第2絕緣膜之膜厚與上述第1基底金屬膜之膜厚相等，上述第2配線層之上述端部與上述第1絕緣膜之間之上述第2絕緣膜之膜厚與上述第2基底金屬膜之膜厚相等。 The semiconductor light-emitting device of claim 3, wherein a thickness of the second insulating film between the end portion of the first wiring layer and the first insulating film is equal to a film thickness of the first underlying metal film, The film thickness of the second insulating film between the end portion of the wiring layer and the first insulating film is equal to the film thickness of the second underlying metal film. 如請求項3之半導體發光裝置，其中上述第1配線層之上述端部與上述第1絕緣膜之間之上述第2絕緣膜之長度相對於上述一部分之膜厚之比為10以上，上述第2配線層之上述端部與上述第1絕緣膜之間之上述第2絕緣膜之長度相對於上述一部分之膜厚之比為10以上。 The semiconductor light-emitting device of claim 3, wherein a ratio of a length of the second insulating film between the end portion of the first wiring layer and the first insulating film to a film thickness of the portion is 10 or more, The ratio of the length of the second insulating film between the end portion of the wiring layer and the first insulating film to the film thickness of the portion is 10 or more. 如請求項3之半導體發光裝置，其中上述第1配線層較上述第1基底金屬膜厚，上述第2配線層較上述第2基底金屬膜厚。 The semiconductor light-emitting device of claim 3, wherein the first wiring layer is thicker than the first base metal film, and the second wiring layer is thicker than the second base metal film. 如請求項3之半導體發光裝置，其中上述第1配線部進而包含第1金屬支柱，上述第1金屬支柱設置於上述第1配線層上，且較上述第1配線層厚，上述第2配線部進而具有第2金屬支柱，上述第2金屬支柱設置於上述第2配線層上，且較上述第2配線層厚。 The semiconductor light-emitting device of claim 3, wherein the first wiring portion further includes a first metal pillar, and the first metal pillar is provided on the first wiring layer and is thicker than the first wiring layer, and the second wiring portion Further, the second metal pillar is provided on the second wiring layer and is thicker than the second wiring layer. 如請求項1或2之半導體發光裝置， 其進而包括光學層，上述光學層設置於上述半導體層之上述第1側，且對上述發光層之放射光具有穿透性。 The semiconductor light emitting device of claim 1 or 2, Further, the optical layer further includes an optical layer provided on the first side of the semiconductor layer and having transparency to the emitted light of the light-emitting layer. 如請求項10之半導體發光裝置，其中上述光學層係螢光體層，上述螢光體層包含：複數個螢光體，其等由上述發光層之放射光激發，放射與上述發光層之放射光為不同波長之光，結合材料，其將上述複數個螢光體一體化，且使上述發光層之放射光及上述螢光體之放射光穿透。 The semiconductor light-emitting device of claim 10, wherein the optical layer is a phosphor layer, the phosphor layer comprises: a plurality of phosphors excited by the emitted light of the light-emitting layer, and the emitted light of the light-emitting layer is Light of different wavelengths, in combination with a material, integrates the plurality of phosphors, and transmits the emitted light of the light-emitting layer and the emitted light of the phosphor. 如請求項11之半導體發光裝置，其中上述第2絕緣膜亦設置於上述第1配線部之側面及上述第2配線部之側面，上述螢光體層亦設置於上述半導體層之周圍及上述第2絕緣膜之周圍，而形成上述半導體發光裝置之側面。 The semiconductor light-emitting device of claim 11, wherein the second insulating film is also provided on a side surface of the first wiring portion and a side surface of the second wiring portion, and the phosphor layer is also provided around the semiconductor layer and the second surface The side of the insulating film is formed to form the side surface of the above semiconductor light-emitting device. 如請求項11之半導體發光裝置，其中上述光學層進而包含透明層，上述透明層設置於上述半導體層之上述第1側與上述螢光體層之間。 The semiconductor light-emitting device of claim 11, wherein the optical layer further comprises a transparent layer, and the transparent layer is provided between the first side of the semiconductor layer and the phosphor layer. 如請求項1或2之半導體發光裝置，其中上述第1絕緣膜亦設置於上述半導體層之與上述第1側連續之側面。 The semiconductor light-emitting device of claim 1 or 2, wherein the first insulating film is also provided on a side surface of the semiconductor layer that is continuous with the first side. 如請求項14之半導體發光裝置，其中於上述半導體層之上述側面，介隔上述第1絕緣膜而設置有反射膜。 The semiconductor light-emitting device of claim 14, wherein a reflective film is provided on the side surface of the semiconductor layer via the first insulating film. 一種半導體發光裝置之製造方法，其包括如下步驟：於包含包括發光層之半導體層、及設置於上述半導體層之第1電極及第2電極的積層體上形成第1絕緣膜，上述第1絕緣膜具有到達至上述第1電極之第1開口及到達至上述第2電極之第2開 口；於上述第1絕緣膜上，形成基底金屬膜；於上述基底金屬膜上，形成經由上述第1開口而與上述第1電極連接之第1配線層、及經由上述第2開口而與上述第2電極連接之第2配線層；將上述第1配線層之端部與上述第2配線層之端部之間之區域之上述第1絕緣膜上所形成之上述基底金屬膜去除，並且使上述基底金屬膜之端部較上述第1配線層之上述端部及上述第2配線層之上述端部後退，從而於上述第1配線層之上述端部與上述第1絕緣膜之間、及上述第2配線層之上述端部與上述第1絕緣膜之間形成空隙；及於上述空隙形成第2絕緣膜。 A method of manufacturing a semiconductor light-emitting device, comprising: forming a first insulating film on a laminated body including a semiconductor layer including a light-emitting layer; and a first electrode and a second electrode provided on the semiconductor layer, wherein the first insulating film The film has a first opening reaching the first electrode and a second opening reaching the second electrode a base metal film is formed on the first insulating film; a first wiring layer connected to the first electrode via the first opening is formed on the base metal film, and the second opening is formed through the second opening a second wiring layer to which the second electrode is connected; the base metal film formed on the first insulating film in a region between the end portion of the first wiring layer and the end portion of the second wiring layer is removed, and An end portion of the base metal film retreats from the end portion of the first wiring layer and the end portion of the second wiring layer, between the end portion of the first wiring layer and the first insulating film, and A gap is formed between the end portion of the second wiring layer and the first insulating film, and a second insulating film is formed in the gap. 如請求項16之半導體發光裝置之製造方法，其中藉由濕式蝕刻使上述基底金屬膜後退而形成上述空隙。 The method of manufacturing a semiconductor light-emitting device according to claim 16, wherein the underlying metal film is retreated by wet etching to form the void.
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