TWI548001B - Method for fabricating metal-oxide-semiconductor field-effect transistor - Google Patents
Method for fabricating metal-oxide-semiconductor field-effect transistor Download PDFInfo
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Description
本案係為一種金氧半電晶體製造方法,尤指應用於半導體製程中之金氧半電晶體製造方法。 The present invention is a method for manufacturing a gold oxide semi-transistor, and more particularly to a method for manufacturing a gold oxide semi-transistor used in a semiconductor process.
隨著閘極長度縮小化遇到瓶頸以及新材料尚未被發現與驗證,遷移率(mobility)調整工程成為改善積體電路性能的一個重要貢獻者。例如,金氧半電晶體的通道晶格應變(strain)已經普遍被用來增強遷移率,其中進行晶格應變的矽所能夠提供的電洞遷移率與電子遷移率約可以達到無晶格應變的矽的4倍與1.8倍。 As the gate length shrinks to encounter bottlenecks and new materials have not yet been discovered and validated, mobility adjustment engineering has become an important contributor to improving the performance of integrated circuits. For example, the channel lattice strain of MOS transistors has been commonly used to enhance mobility, where the lattice strain enthalpy can provide a hole mobility and electron mobility of approximately no lattice strain. The 矽 is 4 times and 1.8 times.
因此,設計者可透過對N通道金氧半電晶體之通道施加拉伸應力(tensile stress)來改善電子遷移率,或者是對P通道金氧半電晶體之通道施加壓縮應力(compression stress)來改善電洞遷移率,而應力記憶技術(Stress Memorization Techniques,簡稱SMT)便是被發展出來眾多遷移率調整工程技術中的一種。然而,利用現有應力記憶技術所形成的半導體元件仍無法獲致令人滿意的元件效能。因此,利用改良的應力記憶技術製造金氧半電晶體便是發展本案之主要目的。 Therefore, the designer can improve the electron mobility by applying tensile stress to the channel of the N-channel MOS transistor, or apply compression stress to the channel of the P-channel MOS transistor. Improve hole mobility, and Stress Memorization Techniques (SMT) is one of many migration rate adjustment engineering technologies developed. However, semiconductor components formed using existing stress memory technology still fail to achieve satisfactory component performance. Therefore, the use of improved stress memory technology to fabricate gold oxide semi-transistors is the main purpose of the development of this case.
本發明提出一種金氧半電晶體製造方法,此方法包含下列步 驟:提供一基板,基板上至少完成一閘極結構、一第一間隙壁、一第二間隙壁以及一源汲極結構,其中第二間隙壁包含一內層與一外層;對第二間隙壁進行厚度縮減而留下內層;於內層與源汲極結構表面上形成一應力膜後進行一回火製程;以及除去應力膜。 The invention provides a method for manufacturing a gold oxide semi-transistor, the method comprising the following steps Step: providing a substrate, the substrate is completed with at least one gate structure, a first spacer, a second spacer, and a source drain structure, wherein the second spacer comprises an inner layer and an outer layer; The wall is reduced in thickness to leave an inner layer; a stress film is formed on the surface of the inner layer and the source drain structure, and a tempering process is performed; and the stress film is removed.
在本發明之一實施例中,上述基板為一矽基板,上述閘極結構包含一閘極介電層、一阻障金屬、一假多晶矽閘極以及一硬罩幕,上述第一間隙壁之材質可為氮化矽或是氧化矽/氮化矽之多層結構,上述第二間隙壁之內層材料為氧化矽,上述第二間隙壁之外層材料為氮化矽。 In an embodiment of the invention, the substrate is a germanium substrate, and the gate structure comprises a gate dielectric layer, a barrier metal, a dummy polysilicon gate, and a hard mask, wherein the first spacer The material may be a multilayer structure of tantalum nitride or tantalum oxide/tantalum nitride. The inner layer material of the second spacer is yttrium oxide, and the outer material of the second spacer is tantalum nitride.
在本發明之一實施例中,上述閘極介電層包含一中間層以及一高介電係數介電層,上述高介電係數介電層之材料為氧化鉿,上述中間層之材料為氧化矽,上述阻障金屬之材料為氮化鈦,上述硬罩幕包含一氮化矽層與一氧化矽層。 In an embodiment of the invention, the gate dielectric layer comprises an intermediate layer and a high-k dielectric layer, the material of the high-k dielectric layer is yttrium oxide, and the material of the intermediate layer is oxidized. The material of the barrier metal is titanium nitride, and the hard mask comprises a tantalum nitride layer and a tantalum oxide layer.
在本發明之一實施例中,完成上述源汲極結構之方法包含下列步驟:進行一源汲極結構摻質植入製程,並將上述矽基板之晶相改變成非晶相。 In one embodiment of the invention, the method of completing the source drain structure includes the steps of performing a source-drain structure dopant implantation process and changing the crystal phase of the germanium substrate to an amorphous phase.
在本發明之一實施例中,對上述第二間隙壁進行厚度縮減之方法包含下列步驟:以熱磷酸對上述第二間隙壁進行一濕蝕刻,用以去除上述外層而留下上述內層。 In an embodiment of the invention, the method for thickness reduction of the second spacer comprises the steps of: wet etching the second spacer with hot phosphoric acid to remove the outer layer to leave the inner layer.
在本發明之一實施例中,於除去上述應力膜後更包含下列步驟:於上述基板上方形成一接觸蝕刻停止層及一內層介電層;利用一化學機械研磨製程去除部分接觸蝕刻停止層、部分內層介電層及上述硬罩幕而露出上述假多晶矽閘極;將露出之上述假多晶矽閘極去除而形成一空間;以及填入一金屬閘極結構於上述空間中。 In an embodiment of the present invention, after removing the stress film, the method further comprises the steps of: forming a contact etch stop layer and an inner dielectric layer over the substrate; removing a partial contact etch stop layer by a chemical mechanical polishing process And a portion of the inner dielectric layer and the hard mask to expose the dummy polysilicon gate; the exposed dummy polysilicon gate is removed to form a space; and a metal gate structure is filled in the space.
在本發明之一實施例中,填入上述金屬閘極結構之方法包 含下列步驟:填入一蝕刻阻擋層;填入一功函數金屬結構;以及填入一金屬閘極。 In an embodiment of the invention, a method package for filling in the above metal gate structure The method comprises the steps of: filling in an etch barrier; filling in a work function metal structure; and filling in a metal gate.
在本發明之一實施例中,上述蝕刻阻擋層之材料為氮化鉭(TaN),上述功函數金屬之材料為氮化鈦(TiN)或鋁化鈦(TiAl),上述金屬閘極之材料為鋁。 In an embodiment of the invention, the material of the etching stopper layer is tantalum nitride (TaN), and the material of the work function metal is titanium nitride (TiN) or titanium aluminide (TiAl), and the material of the metal gate is used. For aluminum.
在本發明之一實施例中,於除去上述應力膜後更包含下列步驟:在源汲極結構表面形成一金屬矽化物。 In an embodiment of the invention, after removing the stress film, the method further comprises the step of forming a metal halide on the surface of the source drain structure.
在本發明之一實施例中,上述應力膜之材料為氮化矽,或是由一緩衝氧化矽層加上一氮化矽膜來完成。 In an embodiment of the invention, the material of the stress film is tantalum nitride or a buffered hafnium oxide layer and a tantalum nitride film.
在本發明之一實施例中,上述金氧半電晶體為一P通道金氧半電晶體,且上述應力膜為一壓縮應力膜。 In an embodiment of the invention, the MOS transistor is a P-channel MOS transistor, and the stress film is a compressive stress film.
在本發明之一實施例中,上述金氧半電晶體為一N通道金氧半電晶體,且上述應力膜為一拉伸應力膜。 In an embodiment of the invention, the MOS transistor is an N-channel MOS transistor, and the stress film is a tensile stress film.
在本發明之一實施例中,除去上述應力膜之方法包含下列步驟:對上述應力膜進行一濕蝕刻。 In one embodiment of the invention, the method of removing the stress film described above comprises the step of subjecting the stress film to a wet etch.
在本發明之一實施例中,更包含下列步驟:於上述源汲極結構之上方形成一接觸孔,露出上述源汲極結構表面;以及於上述接觸孔露出之上述源汲極結構表面形成一金屬矽化物。 In an embodiment of the invention, the method further includes the steps of: forming a contact hole over the source drain structure to expose the surface of the source drain structure; and forming a surface of the source drain structure exposed by the contact hole Metal telluride.
請參見圖1A~圖1G,其係申請人為改善應力記憶技術所發展出之半導體製程流程示意圖。首先,圖1A中表示出於矽基板1上進行金氧半電晶體之前段製程後所完成之剖面結構,其中閘極結構主要由閘極介電層(gate dielectric layer)10、阻障金屬(barrier metal)11、假多晶矽閘極(dummy poly)12以及硬罩幕13來構成。 其中閘極介電層10之多層結構主要由介質層(interfacial layer)100以及高介電係數介電層101來完成,常見的高介電係數介電層101材料為氧化鉿(HfO2),而介質層100材料可為氧化矽(SiO2)。阻障金屬11材料可為氮化鈦(TiN),硬罩幕13則可由氮化矽層(SiN)132與氧化矽131來構成。 Please refer to FIG. 1A to FIG. 1G, which are schematic diagrams of a semiconductor process flow developed by the applicant for improving stress memory technology. First, FIG. 1A shows a cross-sectional structure completed after the MOS substrate is fabricated on the ruthenium substrate 1. The gate structure is mainly composed of a gate dielectric layer 10 and a barrier metal ( Barrier metal) 11, a dummy polysilicon 12 and a hard mask 13 are formed. The multilayer structure of the gate dielectric layer 10 is mainly performed by an interfacial layer 100 and a high-k dielectric layer 101. The common high-k dielectric layer 101 is hafnium oxide (HfO 2 ). The material of the dielectric layer 100 may be cerium oxide (SiO2). The barrier metal 11 material may be titanium nitride (TiN), and the hard mask 13 may be composed of a tantalum nitride layer (SiN) 132 and a tantalum oxide 131.
至於閘極結構之側壁形成有第一間隙壁15與第二間隙壁16,並可利用閘極結構與間隙壁為罩幕來對矽基板1進行輕摻雜汲極(LDD)17與源汲極結構18之摻質植入。而上述第一間隙壁15之材質可為氮化矽或是氧化矽/氮化矽之多層結構,至於第二間隙壁16則由一內層160與一外層161來構成,內層160之材料可為氧化矽,外層161之材料可為氮化矽。而進行上述輕摻雜汲極(LDD)17與源汲極結構18之摻質植入時,會將矽基板1之晶相改變成非晶相,如此可完成應力記憶技術之前期作業。 As for the sidewall of the gate structure, the first spacer 15 and the second spacer 16 are formed, and the gate structure and the spacer are used as a mask to lightly doped the drain (LDD) 17 and the source substrate. The dopant of the pole structure 18 is implanted. The material of the first spacer 15 may be a multilayer structure of tantalum nitride or tantalum oxide/tantalum nitride. The second spacer 16 is composed of an inner layer 160 and an outer layer 161. The material of the inner layer 160 The material of the outer layer 161 may be tantalum nitride. When the doping of the light-doped drain (LDD) 17 and the source-drain structure 18 is performed, the crystal phase of the germanium substrate 1 is changed into an amorphous phase, so that the previous work of the stress memory technology can be completed.
接著如圖1B所示,利用濕蝕刻來將第二間隙壁16進行厚度縮減,以第二間隙壁16之外層161之材料為氮化矽為例,可用熱磷酸(H3PO4)來除去氮化矽,而利用磷酸對於氮化矽與氧化矽之高蝕刻選擇比特性,因而留下第二間隙壁16之內層160的”L”型氧化矽層。 Next, as shown in FIG. 1B, the second spacer 16 is reduced in thickness by wet etching, and the material of the outer layer 161 of the second spacer 16 is nitrided, for example, and can be removed by hot phosphoric acid (H 3 PO 4 ). Tantalum nitride, while utilizing the high etching selectivity characteristics of phosphoric acid for tantalum nitride and tantalum oxide, thus leaving an "L" type tantalum oxide layer of inner layer 160 of second spacer 16.
然後如圖1C所示,於進行應力記憶技術中應力膜14的沉積,常見的應力膜材料為氮化矽,或是由緩衝氧化矽層(buffer oxide)加上氮化矽層來完成。由於在不同的沉積條件下,氮化矽薄膜可被控制成拉伸應力膜或是壓縮應力膜,例如,用以增強P通道之電洞遷移率的壓縮應力膜可透過簡單的化學氣相沉積法(CVD)來完成,而用以增強N通道之電子遷移率之拉伸應力膜則需要經過多個沉積-硬化(curing)的製程循環來完成。而於應力膜14沉積完成後,便對晶相改變成非晶相之輕摻雜汲極17與源汲極結構18 進行回火製程,如此一來,經過回火製程之輕摻雜汲極17與源汲極結構18將回復為晶相並記憶應力膜14所提供的應力。 Then, as shown in FIG. 1C, the stress film 14 is deposited in a stress memory technique. The common stress film material is tantalum nitride or a buffered oxide oxide layer plus a tantalum nitride layer. Since the tantalum nitride film can be controlled to a tensile stress film or a compressive stress film under different deposition conditions, for example, a compressive stress film for enhancing the hole mobility of the P channel can be transparent chemical vapor deposition. The method (CVD) is performed, and the tensile stress film for enhancing the electron mobility of the N channel needs to be completed by a plurality of deposition-curing process cycles. After the deposition of the stress film 14 is completed, the lightly doped gate 17 and the source drain structure 18 are changed to an amorphous phase. The tempering process is performed such that the lightly doped gates 17 and source drain structures 18 that have undergone the tempering process will revert to the crystalline phase and memorize the stress provided by the stress film 14.
接著如圖1D所示,再利用濕蝕刻將應力膜14去除而露出”L”型氧化矽層160,以氮化矽完成之應力膜14為例,可用熱磷酸(H3PO4)來進行去除。此時還可接著進行源汲極結構18表面的自行對準金屬矽化製程而形成金屬矽化物180,當然,金屬矽化物180也可在先前第二間隙壁16形成後便接著完成。 Next, as shown in FIG. 1D, the stress film 14 is removed by wet etching to expose the "L"-type yttrium oxide layer 160, and the stress film 14 completed by yttrium nitride is taken as an example, and can be performed by hot phosphoric acid (H 3 PO 4 ). Remove. At this time, the metal germanide 180 can be formed by performing a self-aligned metal deuteration process on the surface of the source drain structure 18. Of course, the metal germanide 180 can also be completed after the previous second spacer 16 is formed.
然後再如圖1E所示,於整個基板表面上方形成接觸蝕刻停止層(CESL)191及內層介電層(ILD)192。然後利用化學機械研磨製程來將閘極結構上方之硬罩幕打開而露出假多晶矽閘極12,進而形成如圖1F之所示之狀態。 Then, as shown in FIG. 1E, a contact etch stop layer (CESL) 191 and an inner dielectric layer (ILD) 192 are formed over the entire substrate surface. A chemical mechanical polishing process is then used to open the hard mask over the gate structure to expose the dummy polysilicon gate 12, thereby forming a state as shown in FIG. 1F.
然後可將露出之假多晶矽閘極(dummy poly)12利用濕蝕刻去除後再而填入金屬閘極結構,金屬閘極結構可包含圖中所示之蝕刻阻擋層120、功函數金屬結構121與金屬閘極122,進而完成如圖1G所示之後閘極(Gate-last)-高介電係數介電層金屬閘極(HKMG)的金氧半電晶體。其中蝕刻阻擋層120可為氮化鉭(TaN),P通道金氧半電晶體之功函數金屬可為氮化鈦(TiN),而N通道金氧半電晶體之功函數金屬可為鋁化鈦(TiAl),至於金屬閘極可用鋁(Al)來完成。而由於本實施例回蝕去除第二間隙壁16中之氮化矽層161,使得應力膜14更有效率地施加應力給需要記憶應力的輕摻雜汲極17與源汲極結構18。因此本案所完成之金氧半電晶體的通道將得到更佳的遷移率調整。 The exposed dummy poly 12 can then be removed by wet etching and then filled into a metal gate structure. The metal gate structure can include the etch barrier 120, the work function metal structure 121 and the The metal gate 122, in turn, completes a gate-last-high-dielectric dielectric metal gate (HKMG) metal oxide half-electrode as shown in FIG. 1G. The etching barrier layer 120 may be tantalum nitride (TaN), the work function metal of the P channel gold oxide semi-transistor may be titanium nitride (TiN), and the work function metal of the N-channel gold oxide semi-transistor may be aluminized. Titanium (TiAl), as for the metal gate, can be completed with aluminum (Al). Since the yttria layer 161 in the second spacer 16 is removed by the etch back in this embodiment, the stress film 14 applies stress to the lightly doped drain 17 and the source drain structure 18 which require memory stress more efficiently. Therefore, the channel of the gold-oxide semi-transistor completed in this case will have better mobility adjustment.
而除了上述後閘極-金氧半電晶體之外,本案技術也可應用於先閘極(Gate-first)金氧半電晶體之製作上,其技術本身並無不同,只是不需要進行將假多晶矽閘極12去除後再而填入功函數金屬121與金屬閘極122等製程。另外,高介電係數介電層101除了以 上述方法先完成外,也可先不製作,等到將假多晶矽閘極12去除再依序填入高介電係數介電層101及蝕刻阻擋層120、功函數金屬121、金屬閘極122。至於源汲極結構18表面之金屬矽化物180,除可利用上述步驟完成之外,也可如圖2所示,於接觸孔20完成後,再利用接觸孔20露出之源汲極結構18表面來完成,如此將可有利於輕摻雜汲極17與源汲極結構18得到更好的應力記憶效應。 In addition to the above-mentioned gate-gold oxide semi-transistor, the technology of the present invention can also be applied to the fabrication of a gate-first MOS transistor, and the technology itself is not different, but it does not need to be performed. After the dummy polysilicon gate 12 is removed, the work function metal 121 and the metal gate 122 are filled. In addition, the high-k dielectric layer 101 is in addition to The above method may be completed first, or may not be fabricated until the dummy polysilicon gate 12 is removed and the high-k dielectric layer 101 and the etch barrier layer 120, the work function metal 121, and the metal gate 122 are sequentially filled. As for the metal germanide 180 on the surface of the source drain structure 18, in addition to the above steps, as shown in FIG. 2, after the contact hole 20 is completed, the surface of the source drain structure 18 exposed by the contact hole 20 is used. To complete, this will facilitate a better stress memory effect for the lightly doped drain 17 and source drain structure 18.
綜上所述,在本發明對技術進行改良後,已可有效改善習用手段的問題。雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
1‧‧‧基板 1‧‧‧Substrate
10‧‧‧閘極介電層 10‧‧‧ gate dielectric layer
100‧‧‧介質層 100‧‧‧ dielectric layer
101‧‧‧高介電係數介電層 101‧‧‧High dielectric constant dielectric layer
11‧‧‧阻障金屬 11‧‧‧Resistance metal
12‧‧‧假多晶矽閘極 12‧‧‧Fake polysilicon gate
13‧‧‧硬罩幕 13‧‧‧hard mask
132‧‧‧氮化矽層 132‧‧‧矽 nitride layer
131‧‧‧氧化矽 131‧‧‧Oxide
14‧‧‧應力膜 14‧‧‧ stress film
15‧‧‧第一間隙壁 15‧‧‧First gap
16‧‧‧第二間隙壁 16‧‧‧Second gap
160‧‧‧內層 160‧‧‧ inner layer
161‧‧‧外層 161‧‧‧ outer layer
17‧‧‧輕摻雜汲極 17‧‧‧Lightly doped bungee
18‧‧‧源汲極結構 18‧‧‧ source 汲 structure
120‧‧‧蝕刻阻擋層 120‧‧‧etch barrier
121‧‧‧功函數金屬結構 121‧‧‧Work function metal structure
122‧‧‧金屬閘極 122‧‧‧Metal gate
180‧‧‧金屬矽化物 180‧‧‧Metal Telluride
191‧‧‧接觸蝕刻停止層 191‧‧‧Contact etch stop layer
192‧‧‧內層介電層 192‧‧‧ Inner dielectric layer
20‧‧‧接觸孔 20‧‧‧Contact hole
圖1A~圖1G,其係申請人為改善應力記憶技術所發展出之金氧半電晶體製程流程示意圖。 FIG. 1A to FIG. 1G are schematic diagrams showing the process flow of a gold-oxygen semi-transistor developed by the applicant for improving stress memory technology.
圖2,其係申請人為改善應力記憶技術所發展出之另一實施例之金氧半電晶體示意圖。 Figure 2 is a schematic view of a gold oxide semi-transistor of another embodiment developed by the Applicant for improving stress memory technology.
120‧‧‧蝕刻阻擋層 120‧‧‧etch barrier
121‧‧‧功函數金屬結構 121‧‧‧Work function metal structure
122‧‧‧金屬閘極 122‧‧‧Metal gate
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CN101276758A (en) * | 2007-03-26 | 2008-10-01 | 联华电子股份有限公司 | Method for preparing semiconductor transistor element |
TW201011860A (en) * | 2008-09-10 | 2010-03-16 | Taiwan Semiconductor Mfg | Resistive device for high-k metal gate techonolgy and method of making the same |
TW201013850A (en) * | 2008-09-26 | 2010-04-01 | Taiwan Semiconductor Mfg | Method for forming metal gates in a gate last process |
CN101179028B (en) * | 2006-11-08 | 2010-10-13 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
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CN101179028B (en) * | 2006-11-08 | 2010-10-13 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and manufacturing method thereof |
CN101276758A (en) * | 2007-03-26 | 2008-10-01 | 联华电子股份有限公司 | Method for preparing semiconductor transistor element |
TW201011860A (en) * | 2008-09-10 | 2010-03-16 | Taiwan Semiconductor Mfg | Resistive device for high-k metal gate techonolgy and method of making the same |
TW201013850A (en) * | 2008-09-26 | 2010-04-01 | Taiwan Semiconductor Mfg | Method for forming metal gates in a gate last process |
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