TWI543618B - The pixel circuit - Google Patents
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- TWI543618B TWI543618B TW103114628A TW103114628A TWI543618B TW I543618 B TWI543618 B TW I543618B TW 103114628 A TW103114628 A TW 103114628A TW 103114628 A TW103114628 A TW 103114628A TW I543618 B TWI543618 B TW I543618B
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本發明係有關於一種像素電路，特別係有關於一種用以提高像素效能之多模式像素電路。 The present invention relates to a pixel circuit, and more particularly to a multi-mode pixel circuit for improving pixel performance.
一種互補金氧半導體(Complementary Metal-Oxide-Semiconductor,CMOS)成像器電路包括複數像素單元之聚焦平面陣列，每一像素單元包括光感測器，例如發光閘(photogate)、光電導體(photoconductor)或光電二極體(photodiode)覆蓋的襯底在基體上，用以在基體之下方部分累積光產生之電荷。每個像素單元皆具有讀出電路，讀出電路包括至少形成在基體上的輸出場效應電晶體以及形成於連接到電晶體之閘極端之基體上的電荷儲存區域，電荷儲存區域可以作為浮動擴散節點。每個像素可包括至少一電子裝置，如用於從光感測器傳送電荷至儲存區域以及一個裝置之電晶體，通常也是電晶體，用以在電荷轉換之前重置儲存區域至一既定電荷位準。 A Complementary Metal-Oxide-Semiconductor (CMOS) imager circuit includes a focus plane array of a plurality of pixel units, each pixel unit including a photo sensor, such as a photogate, a photoconductor, or A photodiode-covered substrate is on the substrate to accumulate light-generated charges in a lower portion of the substrate. Each of the pixel units has a readout circuit including an output field effect transistor formed on at least the substrate and a charge storage region formed on the substrate connected to the gate terminal of the transistor, and the charge storage region can be used as a floating diffusion node. Each pixel may include at least one electronic device, such as a transistor for transferring charge from the photosensor to the storage region and a device, typically also a transistor for resetting the storage region to a predetermined charge level prior to charge transfer quasi.
在一CMOS顯像器中，像素單元的主動元 件執行以下之必要功能：(1)光子至電荷之轉換；(2)影像電荷之累積；(3)在電荷轉換至一已知狀態之前，重置儲存區域至該已知狀態；(4)電荷轉移至儲存區域；(5)選擇用以讀取之像素；(6)輸出以及放大代表像素電荷之信號。當光電荷從初始電荷累積區移動到儲存區域時，光電荷會被放大，在儲存區域的電荷通常藉由源極隨耦器(source follower)輸出電晶體轉換成像素輸出電壓。 In a CMOS imager, the active elements of the pixel unit The following functions are performed: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage area to the known state before the charge is converted to a known state; (4) The charge is transferred to the storage area; (5) the pixel for reading is selected; (6) the output and the signal representing the pixel charge are amplified. When photocharges move from the initial charge accumulation region to the storage region, the photocharges are amplified, and the charge in the storage region is typically converted to a pixel output voltage by a source follower output transistor.
有鑑於此，本發明提出一種像素電路，包括複數像素單元，其中上述像素單元之任一者包括：一光感測器、一讀取電路以及一開關電路。上述讀取電路耦接至一供應電壓以及上述光感測器，其中上述讀取電路包括一浮接擴散節點以及一輸出節點，上述浮接擴散節點用以儲存上述光感測器之資料，上述輸出節點用以輸出上述浮接擴散節點之資料。上述開關電路，耦接於上述光感測器以及一尾端節點之間，其中上述尾端節點耦接至另一像素單元之上述浮接擴散節點。 In view of this, the present invention provides a pixel circuit including a plurality of pixel units, wherein any of the pixel units includes: a photo sensor, a read circuit, and a switch circuit. The read circuit is coupled to a supply voltage and the photo sensor, wherein the read circuit includes a floating diffusion node and an output node, and the floating diffusion node is configured to store data of the photo sensor, The output node is configured to output the data of the floating diffusion node. The switching circuit is coupled between the photo sensor and a tail node, wherein the tail node is coupled to the floating diffusion node of another pixel unit.
根據本發明之一實施例，上述讀取電路包括一第一開關、一電晶體、一第二開關以及一第三開關。上述第一開關由一重置信號所控制，並且耦接於上述供應電壓以及上述浮接擴散節點之間。上述電晶體由 上述浮接擴散節點之一電壓位準所控制，並且汲極端耦接至上述供應電壓。上述第二開關由一選擇信號所控制，並且耦接於上述電晶體之源極端以及一輸出節點之間。上述第三開關由一讀取信號所控制，並且耦接於上述浮接擴散節點以及上述光感測器之間。 According to an embodiment of the invention, the read circuit includes a first switch, a transistor, a second switch, and a third switch. The first switch is controlled by a reset signal and coupled between the supply voltage and the floating diffusion node. The above transistor is composed of One of the floating diffusion nodes is controlled by a voltage level, and the 汲 is extremely coupled to the supply voltage. The second switch is controlled by a selection signal and coupled between the source terminal of the transistor and an output node. The third switch is controlled by a read signal and coupled between the floating diffusion node and the photo sensor.
根據本發明之一實施例，上述開關電路更包括一第四開關以及一第五開關。上述第四開關由一第一控制信號所控制，並且耦接於上述光感測器以及一第一節點之間，其中一虛擬電容器形成於上述第一節點。上述第五開關由一第二控制信號所控制，並且耦接於上述第一節點以及上述尾端節點之間。 According to an embodiment of the invention, the switch circuit further includes a fourth switch and a fifth switch. The fourth switch is controlled by a first control signal and coupled between the photo sensor and a first node, wherein a dummy capacitor is formed at the first node. The fifth switch is controlled by a second control signal and coupled between the first node and the tail node.
根據本發明之一實施例，經由上述第三開關至上述輸出節點之轉換增益係大於由上述第四開關以及上述第五開關至上述另一像素單元之上述輸出節點之轉換增益。 According to an embodiment of the invention, the conversion gain through the third switch to the output node is greater than the conversion gain of the output node from the fourth switch and the fifth switch to the other pixel unit.
根據本發明之一實施例，當上述像素電路操作於一溢光控制模式時，上述第三開關係為不導通、上述第四開關係由一臨限電壓所控制、上述第五開關係為不導通，則上述光感測器之複數溢出電子流入上述虛擬電容器，其中上述光感測器之資料經由上述第三開關、上述電晶體以及上述第二開關而於上述輸出節點被讀出，上述虛擬電容器之資料經由上述第五開關、上述另一像素單元之上述電晶體以及上述另一像素單元之 上述第二開關於上述另一像素單元之上述輸出節點被讀出，隨後將上述光感測器之資料以及上述虛擬電容器之資料相加總。 According to an embodiment of the present invention, when the pixel circuit is operated in an overflow control mode, the third open relationship is non-conductive, the fourth open relationship is controlled by a threshold voltage, and the fifth open relationship is not Turning on, the plurality of overflow electrons of the photo sensor flow into the dummy capacitor, wherein the data of the photo sensor is read at the output node via the third switch, the transistor, and the second switch, the virtual The data of the capacitor is via the fifth switch, the transistor of the other pixel unit, and the other pixel unit The second switch is read out at the output node of the other pixel unit, and then the data of the photo sensor and the data of the virtual capacitor are added together.
根據本發明之一實施例，當上述像素電路操作於一對數模式時，上述第四開關、上述第五官以及上述另一像素單元之上述第一開關於上述光感測器之一積分週期內同時導通。 According to an embodiment of the present invention, when the pixel circuit is operated in a one-dot mode, the fourth switch, the fifth official, and the first switch of the another pixel unit are in an integration period of one of the photo sensors. Turn on at the same time.
根據本發明之一實施例，當上述像素電路操作於一全域快門模式時，首先，在上述光感測器之一積分週期後，上述光感測器之資料經由上述第四開關傳送至上述虛擬電容器，隨後上述第四開關不導通，並且上述第一開關以及上述第二開關導通以重置上述光感測器，接著上述虛擬電容器之資料經由上述第五開關、上述另一像素單元之上述電晶體以及上述另一像素單元之上述第二開關於上述另一像素單元之上述輸出節點被讀出。 According to an embodiment of the present invention, when the pixel circuit operates in a global shutter mode, first, after an integration period of one of the photo sensors, the data of the photo sensor is transmitted to the virtual via the fourth switch. Capacitor, then the fourth switch is not turned on, and the first switch and the second switch are turned on to reset the photo sensor, and then the data of the virtual capacitor is passed through the fifth switch and the other pixel unit The crystal and the second switch of the other pixel unit are read out at the output node of the other pixel unit.
根據本發明之一實施例，自上述虛擬電容器讀取資料後，上述另一像素單元之上述第一開關以及上述第五開關導通以重置上述虛擬電容器。 According to an embodiment of the invention, after the data is read from the dummy capacitor, the first switch and the fifth switch of the other pixel unit are turned on to reset the dummy capacitor.
100、200‧‧‧像素電路 100, 200‧‧‧ pixel circuits
101‧‧‧讀取電路 101‧‧‧Read circuit
102‧‧‧光感測器 102‧‧‧Light sensor
103‧‧‧開關電路 103‧‧‧Switch circuit
110‧‧‧第一像素單元 110‧‧‧first pixel unit
120‧‧‧第二像素單元 120‧‧‧second pixel unit
130‧‧‧第三像素單元 130‧‧‧ third pixel unit
201‧‧‧第一開關 201‧‧‧First switch
202‧‧‧電晶體 202‧‧‧Optoelectronics
203‧‧‧第二開關 203‧‧‧Second switch
204‧‧‧第三開關 204‧‧‧third switch
205‧‧‧第四開關 205‧‧‧fourth switch
206‧‧‧第五開關 206‧‧‧ fifth switch
VDD‧‧‧供應電壓 V DD ‧‧‧ supply voltage
FD‧‧‧浮接擴散節點 FD‧‧‧Floating diffusion node
C‧‧‧虛擬電容器 C‧‧‧Virtual Capacitor
OUT‧‧‧輸出節點 OUT‧‧‧ output node
TN‧‧‧尾端節點 TN‧‧ End node
RST‧‧‧重置信號 RST‧‧‧Reset signal
SEL‧‧‧選擇信號 SEL‧‧‧Selection signal
READ‧‧‧讀取信號 READ‧‧‧ read signal
CON1‧‧‧第一控制信號 CON 1 ‧‧‧First control signal
CON2‧‧‧第二控制信號 CON 2 ‧‧‧second control signal
N1‧‧‧第一節點 N 1 ‧‧‧ first node
T‧‧‧積分週期 T‧‧·Integral Cycle
T1‧‧‧既定時間 T1‧‧‧definite time
第1圖係顯示根據本發明之一實施例所述之像素電 路100之方塊圖；第2圖係顯示根據本發明之一實施例所述之像素電路200之電路圖；第3圖係顯示根據本發明之一實施例所述之第一像素單元110以及第二像素單元120操作於雙轉換增益模式之示意圖；第4圖係顯示根據本發明之一實施例所述之操作於線性/對數模式之光感測器於一積分週期T時累積電子之曲線圖；第5A-5D圖係顯示根據本發明之一實施例所述之操作於全域快門模式之動作示意圖；第6圖係顯示根據本發明之一實施例所述之全域快門模式之操作順序；以及第7A、7B圖係顯示根據本發明之一實施例所述之光感測器以及虛擬電容器之行為之示意圖。 1 is a diagram showing pixel power according to an embodiment of the present invention. A block diagram of a circuit 100; a second diagram showing a circuit diagram of a pixel circuit 200 according to an embodiment of the invention; and a third diagram showing a first pixel unit 110 and a second according to an embodiment of the invention. A schematic diagram of the pixel unit 120 operating in a double conversion gain mode; and FIG. 4 is a graph showing cumulative electrons of the optical sensor operating in the linear/logarithmic mode during an integration period T according to an embodiment of the invention; 5A-5D are diagrams showing an operation of operating in a global shutter mode according to an embodiment of the present invention; and FIG. 6 is a diagram showing an operation sequence of a global shutter mode according to an embodiment of the present invention; 7A, 7B are diagrams showing the behavior of a photosensor and a virtual capacitor in accordance with an embodiment of the present invention.
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特例舉一較佳實施例，並配合所附圖式，來作詳細說明如下：以下將介紹係根據本發明所述之較佳實施例。必須要說明的是，本發明提供了許多可應用之發明概念，在此所揭露之特定實施例，僅是用於說明達成與 運用本發明之特定方式，而不可用以侷限本發明之範圍。 The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims appended claims A good example. It must be noted that the present invention provides many applicable inventive concepts, and the specific embodiments disclosed herein are merely illustrative of The specific mode of the invention is not intended to limit the scope of the invention.
第1圖係顯示根據本發明之一實施例所述之像素電路100之方塊圖。如第1圖所示，像素電路100包括複數像素單元，在此僅以第一像素單元110、第二像素單元120以及第三像素單元130作為範例說明。第一像素單元110、第二像素單元120以及第三像素單元130之任一者包括讀取電路101、光感測器102以及開關電路103。供應電壓VDD係供應至讀取電路101，供應電路101將由光感測器102轉移之電子集合於浮接擴散(floating diffusion)節點FD，並且於輸出節點OUT發送輸出信號。開關電路103耦接於光感測器102以及尾端節點TN之間。根據本發明之一實施例，尾端節點TN係耦接於另一像素單元之浮接擴散節點FD。 1 is a block diagram showing a pixel circuit 100 in accordance with an embodiment of the present invention. As shown in FIG. 1, the pixel circuit 100 includes a plurality of pixel units, and only the first pixel unit 110, the second pixel unit 120, and the third pixel unit 130 are exemplified herein. Any of the first pixel unit 110, the second pixel unit 120, and the third pixel unit 130 includes a read circuit 101, a photo sensor 102, and a switch circuit 103. The supply voltage V DD is supplied to the read circuit 101, which collects the electrons transferred by the photo sensor 102 to a floating diffusion node FD, and transmits an output signal at the output node OUT. The switch circuit 103 is coupled between the photo sensor 102 and the tail end node TN. According to an embodiment of the invention, the tail end node TN is coupled to the floating diffusion node FD of another pixel unit.
根據本發明第1圖之實施例，第三像素單元130之開關電路103耦接至第二像素單元120之浮接擴散節點FD，第二像素單元120之開關電路103係耦接至第一像素單元110之浮接擴散節點FD。換句話說，第1圖之實施例之像素單元相互串聯。 According to the embodiment of the first embodiment of the present invention, the switching circuit 103 of the third pixel unit 130 is coupled to the floating diffusion node FD of the second pixel unit 120, and the switching circuit 103 of the second pixel unit 120 is coupled to the first pixel. The floating diffusion node FD of unit 110. In other words, the pixel units of the embodiment of Fig. 1 are connected in series with each other.
第2圖係顯示根據本發明之一實施例所述之像素電路200之電路圖。如第2圖所示，讀取電路101包括第一開關201、電晶體202、第二開關203以及第三開關204。第一開關201由重置信號RST所控制，並且第 一開關201耦接於供應電壓VDD以及浮接擴散節點FD之間。電晶體202由浮接擴散節點FD之電壓位準所控制，電晶體202之汲極端耦接至供應電壓VDD。第二開關203係由選擇信號SEL所控制，並且第二開關203耦接於電晶體202之源極端以及輸出節點OUT之間。第三開關204係由讀取信號READ所控制，並且第三開關204係耦接於浮接擴散節點FD以及光感測器102之間。 2 is a circuit diagram showing a pixel circuit 200 according to an embodiment of the present invention. As shown in FIG. 2, the read circuit 101 includes a first switch 201, a transistor 202, a second switch 203, and a third switch 204. The first switch 201 is controlled by the reset signal RST, and the first switch 201 is coupled between the supply voltage V DD and the floating diffusion node FD. The transistor 202 is controlled by the voltage level of the floating diffusion node FD, and the transistor 202 is coupled to the supply voltage V DD . The second switch 203 is controlled by the selection signal SEL, and the second switch 203 is coupled between the source terminal of the transistor 202 and the output node OUT. The third switch 204 is controlled by the read signal READ, and the third switch 204 is coupled between the floating diffusion node FD and the photo sensor 102.
開關電路103包括第四開關205以及第五開關206。第四開關205係由第一控制信號CON1所控制，並且第四開關205耦接於光感測器102以及第一節點N1之間。第五開關206係由第二控制信號CON2所控制，並且第五開關206耦接於第一節點N1以及尾端節點TN之間。虛擬電容器C係形成於第一節點N1與接地端之間。根據本發明之一實施例，虛擬電容器C係為一寄生電容。此外，尾端節點TN係耦接至另一像素單元之浮接擴散節點FD，第2圖之開關可以金氧半導體(MOS)實現。 The switch circuit 103 includes a fourth switch 205 and a fifth switch 206. The fourth switch 205 is controlled by the first control signal CON 1 , and the fourth switch 205 is coupled between the photo sensor 102 and the first node N 1 . The fifth switch 206 is controlled by the second control signal CON 2 , and the fifth switch 206 is coupled between the first node N 1 and the tail end node TN. The dummy capacitor C is formed between the first node N 1 and the ground. According to an embodiment of the invention, the virtual capacitor C is a parasitic capacitance. In addition, the tail node TN is coupled to the floating diffusion node FD of another pixel unit, and the switch of FIG. 2 can be implemented by a metal oxide semiconductor (MOS).
第1圖之像素電路100可操作於雙轉換增益模式、溢光控制模式、線性/對數模式或全域快門模式，以下將針對這相模式予以詳加說明。第2圖之開關係以N型半導體實現，並非以任何型式限定於此。 The pixel circuit 100 of FIG. 1 can operate in a double conversion gain mode, an overflow control mode, a linear/logarithmic mode, or a global shutter mode, which will be described in detail below. The open relationship of Fig. 2 is realized by an N-type semiconductor, and is not limited to this by any type.
為了詳細說明像素電路100之行為，在此僅以第二像素單元120之行為舉例說明。第3圖係顯示根據 本發明之一實施例所述之第一像素單元110以及第二像素單元120操作於雙轉換增益模式之示意圖。 To elaborate on the behavior of the pixel circuit 100, only the behavior of the second pixel unit 120 is exemplified herein. Figure 3 shows the basis A schematic diagram of the first pixel unit 110 and the second pixel unit 120 operating in a double conversion gain mode according to an embodiment of the invention.
由第二像素單元120之光感測器102於積分週期所累積之電子可轉換成一電壓位準，而該電壓位準可由第二像素單元120之輸出節點OUT讀取，獲由第一像素單元110之輸出節點OUT讀取，而從不同位置讀取則產生不同的轉換增益。若是由第二像素單元120之輸出節點OUT讀取對應第二像素單元120之光感測器102之對應的電壓位準時，由光感測器102所累積之電子，經由第三開關204轉移至第二像素單元120之浮接擴散節點FD，其中浮接擴散節點FD之電壓位準首先被重置至供應電壓VDD。 The electrons accumulated by the photo sensor 102 of the second pixel unit 120 during the integration period can be converted into a voltage level, and the voltage level can be read by the output node OUT of the second pixel unit 120 to obtain the first pixel unit. The output node OUT of 110 reads, while reading from different locations produces different conversion gains. If the corresponding voltage level of the photo sensor 102 corresponding to the second pixel unit 120 is read by the output node OUT of the second pixel unit 120, the electrons accumulated by the photo sensor 102 are transferred to the third switch 204 via the third switch 204. The floating diffusion node FD of the second pixel unit 120, wherein the voltage level of the floating diffusion node FD is first reset to the supply voltage V DD .
對於電子的轉移，浮接擴散節點FD之電壓位準係與浮接擴散節點FD之寄生電容成反比，若能夠將浮接擴散節點FD之寄生電容降低的話，則可產生高轉換增益。另外，電晶體202係為源極隨耦器。當第二開關203由選擇信號SEL所致能時，輸出節點OUT之電壓位準等於浮接擴散節點FD之電壓位準減去電晶體202之臨限電壓。 For the transfer of electrons, the voltage level of the floating diffusion node FD is inversely proportional to the parasitic capacitance of the floating diffusion node FD, and if the parasitic capacitance of the floating diffusion node FD can be lowered, a high conversion gain can be generated. Additionally, transistor 202 is a source follower. When the second switch 203 is enabled by the selection signal SEL, the voltage level of the output node OUT is equal to the voltage level of the floating diffusion node FD minus the threshold voltage of the transistor 202.
為了在第一像素單元110之輸出節點OUT 讀出第二像素單元120之光感測器102之資訊，由第二像素單元120之光感測器102所累積之電子係經由開關電路103(即為第四開關205以及第五開關206)而轉移至浮接擴散節點FD，然後轉換成第一像素單元110之輸出節點OUT輸出之電壓位準。然而，由於第五開關206同時耦接至第一像素單元110之浮接擴散節點FD以及第二像素單元120之第一節點N1，第一像素單元101之電晶體202之閘極電容應等於浮接擴散節點FD之寄生電容加上第二像素單元120之虛擬電容器C之電容值，將造成在第一像素單元110之輸出節點OUT讀取時之轉換增益小於在第二像素單元120之輸出節點OUT讀取之轉換增益(因為轉換增益係與電容值成反比)。在此情況下，具有不同轉換增益之路徑因而產生。 In order to read the information of the photo sensor 102 of the second pixel unit 120 at the output node OUT of the first pixel unit 110, the electrons accumulated by the photo sensor 102 of the second pixel unit 120 are via the switch circuit 103 (ie, The fourth switch 205 and the fifth switch 206) are transferred to the floating diffusion node FD, and then converted to the voltage level of the output of the output node OUT of the first pixel unit 110. However, since the fifth switch 206 is simultaneously coupled to the floating diffusion node FD of the first pixel unit 110 and the first node N 1 of the second pixel unit 120, the gate capacitance of the transistor 202 of the first pixel unit 101 should be equal to The parasitic capacitance of the floating diffusion node FD plus the capacitance value of the virtual capacitor C of the second pixel unit 120 will cause the conversion gain when the output node OUT of the first pixel unit 110 is read to be smaller than the output of the second pixel unit 120. The conversion gain read by node OUT (because the conversion gain is inversely proportional to the capacitance value). In this case, paths with different conversion gains are thus produced.
根據本發明之一實施例，經由第三開關204至輸出節點OUT之轉換增益係為190uV/e，而經由第四開關205以及第五開關206而至另一像素單元之輸出節點OUT係為60uV/e。 According to an embodiment of the invention, the conversion gain via the third switch 204 to the output node OUT is 190 uV/e, and the output node OUT via the fourth switch 205 and the fifth switch 206 to the other pixel unit is 60 uV. /e.
第7A、7B圖係顯示根據本發明之一實施例所述之光感測器以及虛擬電容器之行為之示意圖。參考第3圖，當第二像素單元120操作於溢光控制模式時，第 一控制信號CON1係為偏壓第五開關205之一既定電壓(如第7A圖所示，小於光感測器102以及虛擬電容C之間的能障)，而第三開關204以及第五開關206皆為不導通。當光感測器102於積分週期中將光子轉換成電子且電子超過一既定位準時，超過的電子亦流至第四開關205且儲存於第一節點N1之虛擬電容器C。光感測器102之電子以及儲存於虛擬電容器C之電子，可分別經由第二像素單元120之輸出節點OUT以及第一像素單元110之輸出節點OUT所讀取。在此實施例中，第3圖之每一開關皆以電晶體實現，因此既定電壓係小於供應電壓VDD。以此方式，第四開關205提供光感測器102以及虛擬電容器C間之電子路徑。如第7A圖所示，當電子超過既定位準時，電子自光感測器102溢流至虛擬電容器C。若既定電壓越靠近供應電壓VDD時，則既定位準越高。要注意的是，當讀取光感測器102之電子以及儲存於虛擬電容器C之電子時，既定電壓可設定為供應電壓VDD，如第7B圖所示，用以形成光感測器102之電子以及儲存於虛擬電容器C之電子間的屏障。 7A and 7B are schematic views showing the behavior of a photo sensor and a dummy capacitor according to an embodiment of the present invention. Referring to FIG. 3, when the second pixel unit 120 is operated in the overflow control mode, the first control signal CON 1 is a predetermined voltage biased by one of the fifth switches 205 (as shown in FIG. 7A, smaller than the photo sensor) 102 and the energy barrier between the virtual capacitors C, and the third switch 204 and the fifth switch 206 are both non-conductive. When the light sensor 102 to convert photons into electrons in the integration period exceeds a positioning both electronic and time, electrons also flow over the fourth switch 205 to the first node and stored in the virtual capacitor 1 C. N The electrons of the photo sensor 102 and the electrons stored in the virtual capacitor C can be read via the output node OUT of the second pixel unit 120 and the output node OUT of the first pixel unit 110, respectively. In this embodiment, each of the switches of FIG. 3 is implemented by a transistor, and thus the predetermined voltage is less than the supply voltage V DD . In this manner, the fourth switch 205 provides an electronic path between the photo sensor 102 and the virtual capacitor C. As shown in FIG. 7A, the electrons overflow from the photosensor 102 to the dummy capacitor C when the electrons exceed the alignment. If the predetermined voltage is closer to the supply voltage V DD, it is both accurate positioning is higher. It should be noted that when reading the electrons of the photo sensor 102 and the electrons stored in the virtual capacitor C, the predetermined voltage can be set to the supply voltage V DD , as shown in FIG. 7B , to form the photo sensor 102 . The electrons and the barrier between the electrons stored in the virtual capacitor C.
在積分週期時，光感測器102將光子轉換成電子，並且第一開關201導通以重置浮接擴散節點FD至供應電壓VDD。若第四開關205並未以既定電壓偏壓時，當浮接擴散節點FD重置的時候，溢出的電子會溢流進浮接擴散節點FD，也就是，部分由光感測器102感測的 資訊會被清除。 At the integration period, the photo sensor 102 converts the photons into electrons, and the first switch 201 is turned on to reset the floating diffusion node FD to the supply voltage V DD . If the fourth switch 205 is not biased by a predetermined voltage, when the floating diffusion node FD is reset, the overflowed electrons may overflow into the floating diffusion node FD, that is, partially sensed by the photo sensor 102. The information will be cleared.
因此，在第四開關205以及虛擬電容器C的幫助下，溢出的電子可被保存且可於另一像素單元之輸出節點OUT被讀出，隨後光感測器102以及虛擬電容器C之資訊會由數位影像處理(digital image processing,DIP)系統加總。 Therefore, with the help of the fourth switch 205 and the virtual capacitor C, the overflowed electrons can be saved and can be read out at the output node OUT of the other pixel unit, and then the information of the photo sensor 102 and the virtual capacitor C can be Digital image processing (DIP) system summing up.
對數(Logarithmic)響應係用以延長在高亮度環境中之動態區域，但在低光線情況下較差。第4圖係顯示根據本發明之一實施例所述之操作於線性/對數模式之光感測器於一積分週期T時累積電子之曲線圖。當數位影像處理系統偵測到環境係為高亮度時，可在既定時間T1之後啟動對數模式。 Logarithmic responses are used to extend dynamic regions in high-brightness environments, but are poor in low light conditions. Figure 4 is a graph showing the accumulation of electrons during an integration period T of a light sensor operating in a linear/logarithmic mode, in accordance with an embodiment of the present invention. When the digital image processing system detects that the environment is high brightness, the logarithmic mode can be started after a predetermined time T1.
在既定時間T1之前，第三開關204以及第四開關205皆為不導通，而光感測器102累積電子。在既定時間T1之後，為了避免電子流向浮接擴散節點FD，第3圖之第四開關205、第五開關206以及第一像素單元110的第一開關201導通，累積的電子因而以對數曲線增加。 Before the predetermined time T1, the third switch 204 and the fourth switch 205 are both non-conductive, and the photo sensor 102 accumulates electrons. After a predetermined time T1, in order to prevent electrons from flowing to the floating diffusion node FD, the fourth switch 205, the fifth switch 206 of FIG. 3 and the first switch 201 of the first pixel unit 110 are turned on, and the accumulated electrons are thus increased by a logarithmic curve. .
利用第一節點N1之虛擬電容器C以及失能高轉移增益之路徑，全域快門能夠被實現。第5A-5D圖係顯示根據本發明之一實施例所述之操作於全域快門模式之動作示意圖。在第5A-5D圖中，第3圖之第二像素單元120以及部分第一像素單元110係用以說明全域快門模式之動作，並且只有相關的開關會以開關符號顯示，以簡化此說明。第6圖係顯示根據本發明之一實施例所述之全域快門模式之操作順序。 Using the virtual node N 1 of the capacitor C and the gain of disabling a high transfer path, a global shutter can be realized. 5A-5D are diagrams showing the operation of operating in the global shutter mode in accordance with an embodiment of the present invention. In FIGS. 5A-5D, the second pixel unit 120 of FIG. 3 and a portion of the first pixel unit 110 are used to illustrate the action of the global shutter mode, and only the relevant switches are displayed with switch symbols to simplify the description. Figure 6 is a diagram showing the operational sequence of the global shutter mode in accordance with an embodiment of the present invention.
如第5A圖所示，第一開關201以及第三開關204皆導通以重置光感測器102，第5B圖顯示像素單元操作於積分週期，第三開關204以及第四開關205皆為不導通，使得光感測器102能夠累積電子，並且第五開關206以及另一像素單元之第二開關203係為導通，用以輸出儲存於虛擬電容器C之資訊，其中儲存於虛擬電容器C之資訊係代表前一積分週期之資訊。在第5C圖中，第五開關206以及另一像素單元之第一開關201導通用以重置虛擬電容器C。 As shown in FIG. 5A, the first switch 201 and the third switch 204 are both turned on to reset the photo sensor 102, and FIG. 5B shows that the pixel unit operates in the integration period, and the third switch 204 and the fourth switch 205 are both Turning on, the photo sensor 102 is capable of accumulating electrons, and the fifth switch 206 and the second switch 203 of the other pixel unit are turned on for outputting information stored in the virtual capacitor C, wherein the information stored in the virtual capacitor C is It represents the information of the previous integration cycle. In FIG. 5C, the fifth switch 206 and the first switch 201 of the other pixel unit are turned on to reset the dummy capacitor C.
隨後，第5D圖顯示第四開關205係為導通，用以轉移光感測器102之電子至虛擬電容器C。在電子轉移至虛擬電容器C之後，回到第5A圖以重置光感測器102，隨後再到第5B圖，於另一像素單元之輸出節點OUT輸出儲存於虛擬電容器C之資料。最後，操作順序係顯示於第6圖。 Subsequently, the 5D diagram shows that the fourth switch 205 is turned on for transferring the electrons of the photo sensor 102 to the virtual capacitor C. After the electrons are transferred to the virtual capacitor C, the image is returned to the fifth sensor to reset the photo sensor 102, and then to the fifth node BB, and the data stored in the virtual capacitor C is outputted to the output node OUT of the other pixel unit. Finally, the sequence of operations is shown in Figure 6.
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解本說明書的形態。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容為基礎以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。 The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
100‧‧‧像素電路 100‧‧‧pixel circuit
101‧‧‧讀取電路 101‧‧‧Read circuit
102‧‧‧光感測器 102‧‧‧Light sensor
103‧‧‧開關電路 103‧‧‧Switch circuit
110‧‧‧第一像素單元 110‧‧‧first pixel unit
120‧‧‧第二像素單元 120‧‧‧second pixel unit
130‧‧‧第三像素單元 130‧‧‧ third pixel unit
VDD‧‧‧供應電壓 V DD ‧‧‧ supply voltage
FD‧‧‧浮接擴散節點 FD‧‧‧Floating diffusion node
OUT‧‧‧輸出節點 OUT‧‧‧ output node
TN‧‧‧尾端節點 TN‧‧ End node
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