TWI541791B - Blue phase liquid crystal display apparatus - Google Patents
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本發明是有關於一種液晶顯示裝置，尤其是有關於一種藍相液晶顯示裝置。 The present invention relates to a liquid crystal display device, and more particularly to a blue phase liquid crystal display device.
液晶顯示裝置目前已經廣泛地應用於日常生活中，而為了使液晶顯示裝置具有更佳的顯示表現，已經有許多研究人員正在研究具有更佳顯示表現的液晶材料。藍相(Blue Phase)液晶由於具有快速響應的優點，因此藍相液晶的驅動頻率可達到240Hz以上，相較於傳統液晶的驅動頻率在120Hz而言，藍相液晶在理論上可以具有更流暢的顯示表現。除此之外，藍相液晶的結構相較於傳統液晶而言更簡單，因此在製作時不需要設置配向膜，不僅製程更簡化且成品更輕薄。 Liquid crystal display devices have been widely used in daily life, and in order to make liquid crystal display devices have better display performance, many researchers have been studying liquid crystal materials having better display performance. The blue phase liquid crystal has a fast response, so the driving frequency of the blue phase liquid crystal can reach 240 Hz or more. Compared with the driving frequency of the conventional liquid crystal at 120 Hz, the blue phase liquid crystal can theoretically have a smoother Show performance. In addition, the structure of the blue phase liquid crystal is simpler than that of the conventional liquid crystal, so that it is not necessary to provide an alignment film at the time of fabrication, which is not only a simple process but also a lighter and thinner product.
然而，藍相液晶由於具有較高的驅動頻率，因此其所需要的驅動電壓也較高，而在習知技術中提出用來改善藍相液晶驅動電壓的方式多為改變電極的形狀或是顯示器的內部結構，在製程上較複雜而不易實現。在大尺寸的藍相液晶顯示裝置中，為了改善藍相液晶的驅動電壓，每一個像素除了接收掃描訊號外，其液晶電容還用以接收兩個資料訊號以及兩個共同訊號，藉此拉大液晶電容兩端的電位差以提高驅動效率，但是利用這種做法，則必須要在顯示器的顯示陣列基板(Array)之外額外外接提供 上述共同訊號的驅動電路，如此一來會使得顯示器的邊框無法窄化。 However, since the blue phase liquid crystal has a higher driving frequency, the driving voltage required for the blue phase liquid crystal is also higher, and in the prior art, the method for improving the driving voltage of the blue phase liquid crystal is mostly to change the shape of the electrode or the display. The internal structure is more complicated and difficult to implement in the process. In the large-size blue-phase liquid crystal display device, in order to improve the driving voltage of the blue-phase liquid crystal, in addition to receiving the scanning signal, each pixel of the pixel is used to receive two data signals and two common signals, thereby expanding The potential difference between the two ends of the liquid crystal capacitor to improve the driving efficiency, but in this way, it must be provided externally outside the display array substrate (Array) of the display. The driving circuit of the above common signal can make the frame of the display not narrow.
本發明提供一種藍相液晶顯示裝置，其可改善前述的問題。 The present invention provides a blue phase liquid crystal display device which can ameliorate the aforementioned problems.
本發明所提供的藍相液晶顯示裝置包括基板以及資料驅動單元。所述的基板具有由多條掃描線以及多條資料線而構成的多個像素。所述的資料驅動單元電連接於所述的資料線，並用以提供資料訊號至所述的資料線。所述的基板還具有第一移位暫存單元，所述的第一移位暫存單元用以提供掃描訊號至所述的掃描線，並用以提供至少一個交流訊號以作為所述的多個像素之共同電壓。 The blue phase liquid crystal display device provided by the present invention comprises a substrate and a data driving unit. The substrate has a plurality of pixels composed of a plurality of scanning lines and a plurality of data lines. The data driving unit is electrically connected to the data line and configured to provide a data signal to the data line. The substrate further has a first shift temporary storage unit, wherein the first shift temporary storage unit is configured to provide a scan signal to the scan line, and is configured to provide at least one alternating current signal as the plurality of The common voltage of the pixels.
在本發明的較佳實施例中，上述之基板具有第一顯示區、第二顯示區以及第二移位暫存單元。所述的第一移位暫存單元用以提供對應的掃描訊號以及對應的交流訊號至所述的第一顯示區內之掃描線以及像素。所述的第二移位暫存單元用以提供對應的掃描訊號以及對應的交流訊號至所述的第二顯示區內之掃描線以及像素。所述的第一移位暫存單元以及所述的第二移位暫存單元各自具有一個掃描訊號產生電路以及一個交流訊號產生電路，以分別產生所述的掃描訊號以及所述的交流訊號。 In a preferred embodiment of the present invention, the substrate has a first display area, a second display area, and a second shift temporary storage unit. The first shift register unit is configured to provide a corresponding scan signal and a corresponding alternating signal to the scan lines and pixels in the first display area. The second shift register unit is configured to provide a corresponding scan signal and a corresponding alternating signal to the scan lines and pixels in the second display area. The first shift register unit and the second shift register unit each have a scan signal generating circuit and an alternating current signal generating circuit for respectively generating the scan signal and the alternating signal.
本發明藉由將移位暫存單元設置於藍相液晶顯示裝置的基板上，因此不需要在顯示裝置的基板之外額外地外接用來提供交流訊號的驅動電路，藉此使藍相液晶顯示裝置的邊框得以窄化。 According to the present invention, since the shift register unit is disposed on the substrate of the blue phase liquid crystal display device, it is not necessary to additionally externally connect the driving circuit for providing the alternating current signal to the substrate of the display device, thereby enabling the blue phase liquid crystal display. The frame of the device is narrowed.
100‧‧‧藍相液晶顯示裝置 100‧‧‧Blue phase liquid crystal display device
101‧‧‧基板 101‧‧‧Substrate
102‧‧‧資料驅動單元 102‧‧‧Data Drive Unit
103_1、103_2‧‧‧移位暫存單元 103_1, 103_2‧‧‧Shift register unit
104、104_1、104_2‧‧‧顯示區 104, 104_1, 104_2‧‧‧ display area
105‧‧‧掃描訊號產生電路 105‧‧‧Scan signal generation circuit
106‧‧‧交流訊號產生電路 106‧‧‧AC signal generation circuit
106_1‧‧‧驅動電路 106_1‧‧‧Drive circuit
106_2、106_4‧‧‧輸出電路 106_2, 106_4‧‧‧ output circuit
106_3‧‧‧反相電路 106_3‧‧‧Inverter circuit
COM(N)‧‧‧驅動訊號 COM(N)‧‧‧ drive signal
106_3in‧‧‧輸入端 106_3in‧‧‧ input
106_3out‧‧‧輸出端 106_3out‧‧‧output
D1-Dn‧‧‧資料線 D1-Dn‧‧‧ data line
S1-Sm‧‧‧掃描線 S1-Sm‧‧‧ scan line
COM1-COMm‧‧‧訊號線 COM1-COMm‧‧‧ signal line
P‧‧‧像素 P‧‧ ‧ pixels
21‧‧‧上拉控制模組 21‧‧‧ Pull-up control module
22‧‧‧上拉模組 22‧‧‧ Pull-up module
23‧‧‧下拉控制模組 23‧‧‧ Pulldown Control Module
24、25‧‧‧下拉模組 24, 25‧‧‧ pulldown module
T1~T13‧‧‧電晶體 T1~T13‧‧‧O crystal
T1-1~T13-1‧‧‧第一端 T1-1~T13-1‧‧‧ first end
T1-2~T13-2‧‧‧第二端 T1-2~T13-2‧‧‧ second end
T1-3~T13-3‧‧‧控制端 T1-3~T13-3‧‧‧ control terminal
C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor
G(N-1)‧‧‧起始訊號 G(N-1)‧‧‧ start signal
VGH_1、VGL_1、VGH_2、VGL_2‧‧‧電位 VGH_1, VGL_1, VGH_2, VGL_2‧‧‧ potential
G(N)‧‧‧掃描訊號 G(N)‧‧‧ scan signal
G(N+1)‧‧‧下一級掃描訊號 G(N+1)‧‧‧Next level scan signal
CK_1、XCK_1‧‧‧時序訊號 CK_1, XCK_1‧‧‧ timing signals
LC1、LC2‧‧‧控制訊號 LC1, LC2‧‧‧ control signals
COM1(N)、COM2(N)‧‧‧交流訊號之準位 COM1(N), COM2(N) ‧‧‧ exchange signal level
圖1為本發明一實施例之藍相液晶顯示裝置的示意圖； 圖2為本發明一實施例之掃描訊號產生電路的電路圖；圖3為本發明一實施例之掃描訊號產生電路的操作時序圖；圖4為本發明另一實施例之掃描訊號產生電路的電路圖；圖5為本發明一實施例之交流訊號產生電路的電路圖；圖6為本發明一實施例之輸出電路的操作時序圖；圖7為本發明另一實施例之輸出電路的電路圖。 1 is a schematic view of a blue phase liquid crystal display device according to an embodiment of the present invention; 2 is a circuit diagram of a scanning signal generating circuit according to an embodiment of the present invention; FIG. 3 is an operation timing diagram of a scanning signal generating circuit according to an embodiment of the present invention; and FIG. 4 is a circuit diagram of a scanning signal generating circuit according to another embodiment of the present invention; 5 is a circuit diagram of an alternating current signal generating circuit according to an embodiment of the present invention; FIG. 6 is an operational timing diagram of an output circuit according to an embodiment of the present invention; and FIG. 7 is a circuit diagram of an output circuit according to another embodiment of the present invention.
圖1為本發明一實施例之藍相液晶顯示裝置的示意圖。如圖1所示，藍相液晶顯示裝置100包括基板101以及資料驅動單元102。基板102具有由m條的掃描線S1-Sm以及n條的資料線D1-Dn而構成的多個像素P，其中m、n為正整數。資料驅動單元102連接於資料線D1-Dn，並用以提供資料訊號至資料線D1-Dn。基板101還具有第一移位暫存單元103_1。第一移位暫存單元103_1用以提供掃描訊號至掃描線S1-Sm，並藉由m條的訊號線COM1-COMm而提供交流訊號至對應的像素P，以作為像素P之共同電壓。在本實施例中，每一個像素P係連接於一條對應的掃描線、兩條對應的資料線以及兩條對應的訊號線，並藉此在一幀(frame)的期間內對應地接收一個掃描訊號、兩個資料訊號以及兩個做為像素P之共同電壓的交流訊號，但本發明並不以此為限。 1 is a schematic view of a blue phase liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 1, the blue phase liquid crystal display device 100 includes a substrate 101 and a data driving unit 102. The substrate 102 has a plurality of pixels P composed of m scanning lines S1-Sm and n data lines D1-Dn, where m and n are positive integers. The data driving unit 102 is connected to the data lines D1-Dn and is used to provide data signals to the data lines D1-Dn. The substrate 101 also has a first shift register unit 103_1. The first shift register unit 103_1 is configured to provide the scan signal to the scan lines S1-Sm, and provide the AC signal to the corresponding pixel P by the m signal lines COM1-COMm as the common voltage of the pixels P. In this embodiment, each pixel P is connected to a corresponding scan line, two corresponding data lines, and two corresponding signal lines, and accordingly receives a scan correspondingly during a frame period. The signal, the two data signals, and the two alternating signals as the common voltage of the pixel P, but the invention is not limited thereto.
承上述，在本實施例中，基板101的兩側各自具有第一移位暫存單元103_1以及第二移位暫存單元103_2，而基板101的中間具有由多個像素P而構成的顯示區104。為了方便說明，以下將顯示區104進一步劃分為第一顯示區104_1以及第二顯示區104_2。第一移位暫存單元103_1用以提供掃描訊號以及做為共同訊號之用的交流訊 號至第一顯示區104_1內之掃描線S1-Sm以及像素P。第二移位暫存單元103_2用以提供掃描訊號以及交流訊號至第二顯示區104_2內之掃描線S1-Sm以及像素P。第一移位暫存單元103_1以及第二移位暫存單元103_2各自具有掃描訊號產生電路105以及交流訊號產生電路106，以分別產生掃描訊號以及做為共同訊號的交流訊號至對應的像素P。基於上述的架構，當藍相液晶顯示裝置100的基板101的尺寸較大時，藉由配置於基板101兩側的移位暫存單元103_1、103_2來分別對顯示區104_1以及104_2內的像素P以雙邊驅動的方式提供所需的掃描訊號以及做為共同訊號之用的交流訊號，可以改善訊號因為傳遞路徑長度不同而造成的阻抗不匹配問題，也可以進一步平衡藍相液晶顯示裝置100的左右邊框大小，但本發明並不以此為限。 As described above, in the present embodiment, each side of the substrate 101 has a first shift temporary storage unit 103_1 and a second shift temporary storage unit 103_2, and the middle of the substrate 101 has a display area composed of a plurality of pixels P. 104. For convenience of explanation, the display area 104 is further divided into a first display area 104_1 and a second display area 104_2. The first shift register unit 103_1 is configured to provide a scan signal and an exchange signal for use as a common signal. The number is to the scanning lines S1-Sm and the pixels P in the first display area 104_1. The second shift register unit 103_2 is configured to provide the scan signal and the AC signal to the scan lines S1-Sm and the pixels P in the second display area 104_2. The first shift register unit 103_1 and the second shift register unit 103_2 each have a scan signal generating circuit 105 and an alternating current signal generating circuit 106 for respectively generating a scan signal and an alternating signal as a common signal to the corresponding pixel P. Based on the above-described structure, when the size of the substrate 101 of the blue phase liquid crystal display device 100 is large, the pixels P in the display regions 104_1 and 104_2 are respectively respectively disposed by the shift register units 103_1 and 103_2 disposed on both sides of the substrate 101. Providing the required scanning signals and the alternating current signals for the common signals in a bilaterally driven manner can improve the impedance mismatch caused by the different lengths of the transmission paths, and can further balance the left and right of the blue phase liquid crystal display device 100. The size of the frame, but the invention is not limited thereto.
圖2為本發明一實施例之掃描訊號產生電路的電路圖。以下將藉由圖2來說明圖1中的掃描訊號產生電路105的具體架構。如圖2所示，掃描訊號產生電路105用以接收起始訊號G(N-1)、第一高電位VGH_1、第一低電位VGL_1、第一時序訊號CK_1以及第二時序訊號XCK_1，並依據所接收之起始訊號G(N-1)、第一時序訊號CK_1以及第二時序訊號XCK_1而對應輸出掃描訊號G(N)。除此之外，掃描訊號G(N)並用以作為下一級掃描訊號產生電路之起始訊號。在本實施例中，第一高電位VGH_1是一個高準位的直流訊號而第一低電位VGL_1是一個低準位的直流訊號。 2 is a circuit diagram of a scan signal generating circuit according to an embodiment of the present invention. The specific structure of the scanning signal generating circuit 105 of Fig. 1 will be explained below with reference to Fig. 2. As shown in FIG. 2, the scan signal generating circuit 105 is configured to receive the start signal G(N-1), the first high potential VGH_1, the first low potential VGL_1, the first timing signal CK_1, and the second timing signal XCK_1, and The scan signal G(N) is output according to the received start signal G(N-1), the first timing signal CK_1, and the second timing signal XCK_1. In addition, the scanning signal G(N) is used as a starting signal for the next-stage scanning signal generating circuit. In this embodiment, the first high potential VGH_1 is a high level DC signal and the first low potential VGL_1 is a low level DC signal.
請繼續參照圖2，掃描訊號產生電路105包括上拉控制模組21、上拉模組22、下拉控制模組23、第一下拉模組24以及第二下拉模組25。上拉控制模組21用以接收起始訊號G(N-1)、第一高電位VGH_1以及第一時序訊號 CK_1並用以控制上拉模組22。上拉模組22用以接收第一時序訊號CK_1並用以輸出掃描訊號G(N)。第一下拉模組24用以接收下一級掃描訊號產生電路所輸出的掃描訊號G(N+1)以及第一低電位VGL_1。下拉控制模組23用以接收第二時序訊號XCK_1以及第一低電位VGL_1並用以控制第二下拉模組24。第二下拉模組25用以接收第一低電位VGL_1。第一下拉模組24以及第二下拉模組25用以將掃描訊號G(N)下拉至第一低電位VGL_1。 Referring to FIG. 2 , the scan signal generating circuit 105 includes a pull-up control module 21 , a pull-up module 22 , a pull-down control module 23 , a first pull-down module 24 , and a second pull-down module 25 . The pull-up control module 21 is configured to receive the start signal G(N-1), the first high potential VGH_1, and the first timing signal CK_1 is used to control the pull-up module 22. The pull-up module 22 is configured to receive the first timing signal CK_1 and output the scan signal G(N). The first pull-down module 24 is configured to receive the scan signal G(N+1) output by the next-stage scan signal generating circuit and the first low potential VGL_1. The pull-down control module 23 is configured to receive the second timing signal XCK_1 and the first low potential VGL_1 and to control the second pull-down module 24. The second pull-down module 25 is configured to receive the first low potential VGL_1. The first pull-down module 24 and the second pull-down module 25 are used to pull the scan signal G(N) down to the first low potential VGL_1.
請繼續參照圖2，掃描訊號產生電路105包括第一電晶體T1、第二電晶體T2、第三電晶體T3、第四電晶體T4、第五電晶體T5、第六電晶體T6、第七電晶體T7、第八電晶體T8、第九電晶體T9、第十電晶體T10以及電容C1。第一電晶體T1具有第一端T1-1、第二端T1-2以及控制端T1-3。第一電晶體T1的第一端T1-1用以接收第一高電位VGH_1，第一電晶體的控制端T1-3用以接收起始訊號G(N-1)。第二電晶體T2具有第一端T2-1、第二端T2-2以及控制端T2-3。第二電晶體T2的第一端T2-1電連接於第一電晶體T1的第二端T1-2，第二電晶體T2的控制端T2-3用以接收下一級掃描訊號產生電路所輸出的掃描訊號G(N+1)，第二電晶體T2的第二端T2-2用以接收第一低電位VGL_1。第三電晶體T3具有第一端T3-1、第二端T3-2以及控制端T3-3。 Referring to FIG. 2, the scan signal generating circuit 105 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh. The transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the capacitor C1. The first transistor T1 has a first end T1-1, a second end T1-2, and a control end T1-3. The first terminal T1-1 of the first transistor T1 is configured to receive the first high potential VGH_1, and the control terminal T1-3 of the first transistor is configured to receive the start signal G(N-1). The second transistor T2 has a first end T2-1, a second end T2-2, and a control end T2-3. The first end T2-1 of the second transistor T2 is electrically connected to the second end T1-2 of the first transistor T1, and the control end T2-3 of the second transistor T2 is configured to receive the output of the next-stage scan signal generating circuit. The scanning signal G(N+1), the second end T2-2 of the second transistor T2 is used to receive the first low potential VGL_1. The third transistor T3 has a first end T3-1, a second end T3-2, and a control end T3-3.
承上述，第三電晶體T3的第一端T3-1用以接收第一時序訊號CK_1，第三電晶體T3的控制端T3-3電連接於第一電晶體T1的第二端T1-2。第四電晶體T4具有第一端T4-1、第二端T4-2以及控制端T4-3。第四電晶體T4的第一端T4-1電連接於第三電晶體T3的第二端T3-2，第四電晶體T4的控制端T4-3用以接收下一級掃描訊號產 生電路所輸出的掃描訊號G(N+1)，第四電晶體T4的第二端T4-2用以接收第一低電位VGL_1。第五電晶體T5具有第一端T5-1、第二端T5-2以及控制端T5-3。第五電晶體T5的第一端T5-1用以接收第一時序訊號CK_1，第五電晶體T5的控制端T5-3電連接於第一電晶體T1的第二端T1-2，第五電晶體T5的第二端T5-2用以輸出掃描訊號G(N)。 The first terminal T3-1 of the third transistor T3 is configured to receive the first timing signal CK_1, and the control terminal T3-3 of the third transistor T3 is electrically connected to the second terminal T1- of the first transistor T1. 2. The fourth transistor T4 has a first end T4-1, a second end T4-2, and a control terminal T4-3. The first end T4-1 of the fourth transistor T4 is electrically connected to the second end T3-2 of the third transistor T3, and the control end T4-3 of the fourth transistor T4 is used to receive the next-level scanning signal. The scanning signal G(N+1) output by the circuit is used, and the second terminal T4-2 of the fourth transistor T4 is used to receive the first low potential VGL_1. The fifth transistor T5 has a first end T5-1, a second end T5-2, and a control end T5-3. The first terminal T5-1 of the fifth transistor T5 is configured to receive the first timing signal CK_1, and the control terminal T5-3 of the fifth transistor T5 is electrically connected to the second terminal T1-2 of the first transistor T1. The second end T5-2 of the five transistor T5 is used to output the scanning signal G(N).
承上述，電容C1其中一端電連接於第五電晶體T5的控制端T3，電容C1的另外一端電連接於第五電晶體T5的第二端T5-2。第六電晶體T6具有第一端T6-1、第二端T6-2以及控制端T6-3。第六電晶體T6的第一端T6-1電連接於第五電晶體T5的第二端T5-2，第六電晶體T6的控制端T6-3用以接收下一級掃描訊號產生電路所輸出的掃描訊號G(N+1)，第六電晶體T6的第二端T6-2用以接收第一低電位VGL_1。第七電晶體T7具有第一端T7-1、第二端T7-2以及控制端T7-3。第七電晶體T7的第一端T7-1以及第七電晶體T7的控制端T7-3用以接收第二時序訊號XCK_1。第八電晶體T8具有第一端T8-1、第二端T8-2以及控制端T8-3。第八電晶體T8的第一端T8-1電連接於第七電晶體T7的第二端T7-2，第八電晶體T8的控制端T8-3電連接於第三電晶體T3的第二端T3-2，第八電晶體T8的第二端T8-2用以接收第一低電位VGL_1。 In the above, one end of the capacitor C1 is electrically connected to the control terminal T3 of the fifth transistor T5, and the other end of the capacitor C1 is electrically connected to the second end T5-2 of the fifth transistor T5. The sixth transistor T6 has a first end T6-1, a second end T6-2, and a control end T6-3. The first end T6-1 of the sixth transistor T6 is electrically connected to the second end T5-2 of the fifth transistor T5, and the control end T6-3 of the sixth transistor T6 is configured to receive the output of the next-stage scanning signal generating circuit. The scanning signal G(N+1), the second end T6-2 of the sixth transistor T6 is for receiving the first low potential VGL_1. The seventh transistor T7 has a first end T7-1, a second end T7-2, and a control terminal T7-3. The first terminal T7-1 of the seventh transistor T7 and the control terminal T7-3 of the seventh transistor T7 are configured to receive the second timing signal XCK_1. The eighth transistor T8 has a first end T8-1, a second end T8-2, and a control terminal T8-3. The first end T8-1 of the eighth transistor T8 is electrically connected to the second end T7-2 of the seventh transistor T7, and the control end T8-3 of the eighth transistor T8 is electrically connected to the second end of the third transistor T3. The terminal T3-2, the second end T8-2 of the eighth transistor T8 is configured to receive the first low potential VGL_1.
承上述，第九電晶體T9具有第一端T9-1、第二端T9-2以及控制端T9-3。第九電晶體T9的第一端T9-1電連接於第五電晶體T5的第二端T5-2，第九電晶體T9的控制端T9-3電連接於第八電晶體T8的第一端T8-1，第九電晶體T9的第二端T9-2用以接收第一低電位VGL_1。第十電晶體T10具有第一端T10-1、第二端T10-2以及控制端T10-3。第十電晶體T10的第一端T10-1電連接於第一電晶 體T1的第二端T1-2，第十電晶體T10的控制端T10-3電連接於第八電晶體T8的第一端T8-1，第十電晶體T10的第二端T10-2用以接收第一低電位VGL_1。在本實施例中，上拉控制模組21包括第一電晶體T1以及第三電晶體T3，上拉模組22包括第五電晶體T5以及電容C1，下拉控制模組23包括第七電晶體T7以及第八電晶體T8，第一下拉模組24包括第二電晶體T2、第四電晶體T4以及第六電晶體T6，第二下拉模組24包括第九電晶體T9以及第十電晶體T10，但本發明並不以此為限。 In the above, the ninth transistor T9 has a first end T9-1, a second end T9-2, and a control end T9-3. The first end T9-1 of the ninth transistor T9 is electrically connected to the second end T5-2 of the fifth transistor T5, and the control terminal T9-3 of the ninth transistor T9 is electrically connected to the first end of the eighth transistor T8. The terminal T8-1, the second terminal T9-2 of the ninth transistor T9 is configured to receive the first low potential VGL_1. The tenth transistor T10 has a first end T10-1, a second end T10-2, and a control end T10-3. The first end T10-1 of the tenth transistor T10 is electrically connected to the first transistor The second end T1-2 of the body T1, the control end T10-3 of the tenth transistor T10 is electrically connected to the first end T8-1 of the eighth transistor T8, and the second end T10-2 of the tenth transistor T10 is used. To receive the first low potential VGL_1. In this embodiment, the pull-up control module 21 includes a first transistor T1 and a third transistor T3, the pull-up module 22 includes a fifth transistor T5 and a capacitor C1, and the pull-down control module 23 includes a seventh transistor. T7 and the eighth transistor T8, the first pull-down module 24 includes a second transistor T2, a fourth transistor T4, and a sixth transistor T6, and the second pull-down module 24 includes a ninth transistor T9 and a tenth power Crystal T10, but the invention is not limited thereto.
圖3為本發明一實施例之掃描訊號產生電路的操作時序圖。如圖3所示，在藍相液晶顯示裝置100顯示一幀的期間內，掃描訊號產生電路105係依序操作於第一期間、第二期間以及第三期間。當操作於第一期間，第一時序訊號CK_1用以禁能，起始訊號G(N-1)以及第二時序訊號XCK_1用以致能，第一電晶體T1、第三電晶體T3、第五電晶體T5、第七電晶體T7、第九電晶體T9以及第十電晶體T10用以導通，而第二電晶體T2、第四電晶體T4、第六電晶體T6以及第八電晶體T8用以截止。當操作於第二期間，第一時序訊號CK_1用以致能，起始訊號G(N-1)以及第二時序訊號XCK_1用以禁能，第三電晶體T3、第五電晶體T5以及第八電晶體T8用以導通，並藉由電容C1的耦合作用而使第五電晶體T5的第二端T5-2輸出掃描訊號G(N)，第一電晶體T1、第二電晶體T2、第四電晶體T4、第六電晶體T6、第七電晶體T7、第九電晶體T9以及第十電晶體T10用以截止。當操作於第三期間，第二時序訊號XCK_1用以致能，起始訊號G(N-1)以及第一時序訊號CK_1用以禁能，第二電晶體T2、第四電晶體T4、第六電晶體T6、第七電晶體T7、第九電晶體T9以及第十電晶體T10用以導通，第一 電晶體T1、第三電晶體T3、第五電晶體T5以及第八電晶體T8用以截止。 3 is a timing chart showing the operation of a scan signal generating circuit according to an embodiment of the present invention. As shown in FIG. 3, during a period in which the blue phase liquid crystal display device 100 displays one frame, the scanning signal generating circuit 105 sequentially operates in the first period, the second period, and the third period. When operating in the first period, the first timing signal CK_1 is disabled, the start signal G(N-1) and the second timing signal XCK_1 are used to enable, the first transistor T1, the third transistor T3, the first The fifth transistor T5, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned on, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 Used to cut off. When operating in the second period, the first timing signal CK_1 is used to enable, the start signal G(N-1) and the second timing signal XCK_1 are disabled, the third transistor T3, the fifth transistor T5, and the The eighth transistor T8 is turned on, and the second terminal T5-2 of the fifth transistor T5 outputs the scanning signal G(N) by the coupling of the capacitor C1, the first transistor T1 and the second transistor T2. The fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned off. When operating in the third period, the second timing signal XCK_1 is used to enable, the start signal G(N-1) and the first timing signal CK_1 are disabled, the second transistor T2, the fourth transistor T4, the first Six transistors T6, seventh transistor T7, ninth transistor T9, and tenth transistor T10 are used for conduction, first The transistor T1, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are turned off.
圖4為本發明另一實施例之掃描訊號產生電路的電路圖。如圖4所示，為了更有效率地控制掃描訊號產生電路105所輸出的掃描訊號G(N)，使其在第二期間以外的時候能更穩定地維持在禁能狀態，本實施例中增設第二低電位VGL_2以使第二電晶體T2的第二端T2-2以及第十電晶體T10的第二端T10-2接收此第二低電位VGL_2，此第二低電位VGL_2例如是一個準位更低於第一低電位VGL_1的直流訊號，如此一來，當第二時序訊號XCK_1致能的時候，第一電晶體T1的第二端T1-2的電位將會被更進一步下拉至第二低電位VGL_2，藉此可以確保掃描訊號G(N)穩定地維持在禁能狀態。除此之外，圖4所示的其餘電路架構以及操作時序都與圖2相同，因此不再贅述。 4 is a circuit diagram of a scan signal generating circuit according to another embodiment of the present invention. As shown in FIG. 4, in order to more effectively control the scanning signal G(N) outputted by the scanning signal generating circuit 105, it can be more stably maintained in the disabled state outside the second period, in this embodiment. Adding a second low potential VGL_2 such that the second end T2-2 of the second transistor T2 and the second end T10-2 of the tenth transistor T10 receive the second low potential VGL_2, for example, a second low potential VGL_2 The level is lower than the DC signal of the first low potential VGL_1, so that when the second timing signal XCK_1 is enabled, the potential of the second terminal T1-2 of the first transistor T1 is further pulled down to The second low potential VGL_2 can thereby ensure that the scanning signal G(N) is stably maintained in the disabled state. Except for this, the remaining circuit architecture and operation timing shown in FIG. 4 are the same as those in FIG. 2, and therefore will not be described again.
圖5為本發明一實施例之交流訊號產生電路的電路圖。如圖5所示，交流訊號產生電路106包括驅動電路106_1以及輸出電路106_2。驅動電路106_1係用以產生驅動訊號COM(N)。在本實施例中，驅動電路106_1的電路架構以及操作時序與圖2或圖4的掃描訊號產生電路105相同，但是所接收的各訊號或是電位可以視需求而決定要與掃描訊號產生電路105相同或是不同，因此本領域通常知識者可利用與產生掃描訊號G(N)相同的技術手段來使驅動電路106_1產生驅動訊號COM(N)，因此關於驅動電路106_1的電路架構以及操作細節不再於此贅述。 FIG. 5 is a circuit diagram of an alternating current signal generating circuit according to an embodiment of the present invention. As shown in FIG. 5, the alternating current signal generating circuit 106 includes a driving circuit 106_1 and an output circuit 106_2. The driving circuit 106_1 is used to generate the driving signal COM(N). In the present embodiment, the circuit structure and operation timing of the driving circuit 106_1 are the same as those of the scanning signal generating circuit 105 of FIG. 2 or FIG. 4, but the received signals or potentials can be determined with the scanning signal generating circuit 105 as needed. The same or different, so the general knowledge in the art can use the same technical means as the generation of the scanning signal G (N) to cause the driving circuit 106_1 to generate the driving signal COM (N), so the circuit structure and operation details of the driving circuit 106_1 are not I will repeat this.
請參照圖5，在本實施例中，輸出電路106_2用以接收驅動訊號COM(N)、第二高電位VGH_2、第一低電位VGL_1、第一控制訊號LC1以及第二控制訊號LC2，並對應地輸出交流訊號的第一準位COM1(N)，在本實施例 中交流訊號的第一準位COM1(N)例如是一個高準位的訊號。在本實施例中，第二高電位VGH_2例如是一個高準位的直流訊號。舉例來說，本實施例中的第一高電位VGH_1與第二高電位VGH_2的準位不同，但本發明並不以此為限。具體來說，輸出電路106_2包括第十一電晶體T11、第十二電晶體T12、第十三電晶體T13以及電容C2。第十一電晶體T11、第十二電晶體T12以及第十三電晶體T13各自具有第一端、第二端以及控制端。第十一電晶體T11的控制端T11-3用以接收由驅動電路106_1所產生的驅動訊號COM(N)，第十一電晶體T11的第一端T11-1用以接收第一控制訊號LC1，第十二電晶體T12的控制端T12-3用以接收第二控制訊號LC2，第十二電晶體T12的第一端T12-1電連接於第十一電晶體T11的第二端T11-2，第十二電晶體T12的第二端T12-2用以接收第一低電位VGL_1，第十三電晶體T13的第一端T13-1用以接收第二高電位VGH_2，第十三電晶體T13的控制端T13-3電連接於第十一電晶體T11的第二端T11-2以及電容C2的其中一端，第十三電晶體T13的第二端T13-2電連接於電容C2的另外一端並用以輸出交流訊號的第一準位COM1(N)。 Referring to FIG. 5, in the embodiment, the output circuit 106_2 is configured to receive the driving signal COM(N), the second high potential VGH_2, the first low potential VGL_1, the first control signal LC1, and the second control signal LC2, and corresponding to First output COM1 (N) of the AC signal, in this embodiment The first level COM1(N) of the intermediate communication signal is, for example, a high level signal. In this embodiment, the second high potential VGH_2 is, for example, a high-level DC signal. For example, the first high potential VGH_1 in this embodiment is different from the second high potential VGH_2, but the invention is not limited thereto. Specifically, the output circuit 106_2 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a capacitor C2. The eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 each have a first end, a second end, and a control end. The control terminal T11-3 of the eleventh transistor T11 is configured to receive the driving signal COM(N) generated by the driving circuit 106_1, and the first terminal T11-1 of the eleventh transistor T11 is configured to receive the first control signal LC1 The control terminal T12-3 of the twelfth transistor T12 is configured to receive the second control signal LC2, and the first end T12-1 of the twelfth transistor T12 is electrically connected to the second end T11 of the eleventh transistor T11. 2, the second end T12-2 of the twelfth transistor T12 is for receiving the first low potential VGL_1, and the first end T13-1 of the thirteenth transistor T13 is for receiving the second high potential VGH_2, the thirteenth electric The control terminal T13-3 of the crystal T13 is electrically connected to the second end T11-2 of the eleventh transistor T11 and one end of the capacitor C2, and the second end T13-2 of the thirteenth transistor T13 is electrically connected to the capacitor C2. The other end is used to output the first level COM1(N) of the AC signal.
請參照圖5，交流訊號產生電路106更包括反相電路106_3。反相電路106_3具有輸入端106_3in以及輸出端106_3out，反相電路106_3之輸入端106_3in用以接收交流訊號的第一準位COM1(N)，反相電路106_3之輸出端106_3out用以輸出交流訊號的第二準位COM2(N)，交流訊號的第二準位COM2(N)與交流訊號的第一準位COM1(N)互為反相，交流訊號的第二準位COM2(N)與交流訊號的第一準位COM1(N)係分別用以做為同一個像素P之二個共同電壓。在本時實施例中，交流訊號的第二準位COM2(N)例如 是一個低準位的訊號。 Referring to FIG. 5, the AC signal generating circuit 106 further includes an inverter circuit 106_3. The inverter circuit 106_3 has an input terminal 106_3in and an output terminal 106_3out. The input terminal 106_3in of the inverter circuit 106_3 is used for receiving the first level COM1(N) of the AC signal, and the output terminal 106_3out of the inverter circuit 106_3 is for outputting the AC signal. The second level COM2(N), the second level COM2(N) of the alternating current signal and the first level COM1(N) of the alternating current signal are mutually inverted, and the second level COM2(N) of the alternating current signal is communicated with The first level COM1(N) of the signal is used as the two common voltages of the same pixel P, respectively. In the present embodiment, the second level COM2(N) of the alternating signal is, for example, It is a low level signal.
圖6為本發明一實施例的輸出電路的操作時序圖。請參照圖5以及圖6，第一控制訊號LC1以及第二控制訊號LC2互為反相，因此當第十一電晶體T11的控制端T11-3接收驅動訊號COM(N)的時候，若第一控制訊號LC1為致能狀態，則第二控制訊號LC2為禁能狀態，此時第十一電晶體T11以及第十三電晶體T13處於導通，而第十二電晶體T12處於截止，且第十三電晶體T13的第二端T13-2所輸出的是高準位的交流訊號COM1(N)，因此藉由反相電路106_3所輸出的交流訊號的第二準位COM2(M)此時為低準位。在本實施例中，第一控制訊號LC1以及第二控制訊號LC2的工作週期大於驅動訊號COM(N)，但本發明並不以此為限。 Fig. 6 is a timing chart showing the operation of an output circuit according to an embodiment of the present invention. Referring to FIG. 5 and FIG. 6, the first control signal LC1 and the second control signal LC2 are mutually inverted. Therefore, when the control terminal T11-3 of the eleventh transistor T11 receives the driving signal COM(N), When the control signal LC1 is in an enabled state, the second control signal LC2 is in an disabled state, and the eleventh transistor T11 and the thirteenth transistor T13 are turned on, and the twelfth transistor T12 is turned off, and the first The second terminal T13-2 of the thirteenth transistor T13 outputs a high-level AC signal COM1(N), so the second level COM2(M) of the AC signal output by the inverter circuit 106_3 is at this time. Low level. In this embodiment, the duty cycle of the first control signal LC1 and the second control signal LC2 is greater than the driving signal COM(N), but the invention is not limited thereto.
承上述，除了藉由反相電路106_3來將交流訊號的第一準位COM1(N)做反相處理而據以輸出交流訊號的第二準位COM2(N)之外，在本發明其它的實施例中，亦可以省略反相電路106_3，而是藉由另外一個輸出電路來產生交流訊號的第二準位COM2(N)。圖7為本發明另一實施例的輸出電路的電路圖。在圖7與圖5當中相同的標號表示相同的元件或訊號。圖7與圖5不同的地方在於，圖7中輸出電路106_4的第十一電晶體T11的第一端T11-1是用以接收第二控制訊號LC2，而第十二電晶體T12的控制端T12-3則是用以接收第一控制訊號LC1，且第十二電晶體T12的第二端T12-2用以接收第二高電位VGH_2。請參照圖6以及圖7，如此一來，當第十一電晶體T11的控制端T11-3接收驅動訊號COM(N)的時候，由於第十一電晶體T11的第一端T11-1接收低準位的控制訊號LC2，因此第13電晶體的控制端T13-3的電位會被下拉至低準位而使得第十三電晶 體T13的第二端T13-2輸出的是交流訊號的低準位COM2(N)。 In addition to the second level COM2(N) for outputting the alternating current signal by inverting the first level COM1(N) of the alternating current signal by the inverting circuit 106_3, in addition to the second level COM2(N) of the alternating current signal, In the embodiment, the inverting circuit 106_3 may be omitted, but the second level COM2(N) of the alternating current signal is generated by another output circuit. FIG. 7 is a circuit diagram of an output circuit according to another embodiment of the present invention. The same reference numerals in Fig. 7 and Fig. 5 denote the same elements or signals. 7 is different from FIG. 5 in that the first end T11-1 of the eleventh transistor T11 of the output circuit 106_4 of FIG. 7 is for receiving the second control signal LC2, and the control end of the twelfth transistor T12. T12-3 is for receiving the first control signal LC1, and the second end T12-2 of the twelfth transistor T12 is for receiving the second high potential VGH_2. Referring to FIG. 6 and FIG. 7 , when the control terminal T11-3 of the eleventh transistor T11 receives the driving signal COM(N), the first terminal T11-1 of the eleventh transistor T11 receives The low level control signal LC2, so the potential of the control terminal T13-3 of the 13th transistor will be pulled down to the low level to make the thirteenth crystal The second end T13-2 of the body T13 outputs the low level COM2(N) of the alternating current signal.
綜上所述，本發明藉由將習知技術中外接於基板的共同訊號驅動電路設置於基板上，藉此窄化邊框，並且藉由雙邊驅動的方式來提供像素所需的共同訊號以及掃描訊號，因此在大尺寸的藍相液晶顯示裝置中，可以改善由於訊號傳遞路徑長度不同所造成的訊號不匹配，更可以進一步平衡兩側邊框的大小。 In summary, the present invention provides a common signal driving circuit externally connected to the substrate on the substrate by the prior art, thereby narrowing the frame and providing common signals and scanning required by the pixels by bilateral driving. The signal, therefore, in the large-size blue-phase liquid crystal display device, the signal mismatch caused by the difference in the length of the signal transmission path can be improved, and the size of the side frames can be further balanced.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100‧‧‧藍相液晶顯示裝置 100‧‧‧Blue phase liquid crystal display device
101‧‧‧基板 101‧‧‧Substrate
102‧‧‧資料驅動單元 102‧‧‧Data Drive Unit
103_1、103_2‧‧‧移位暫存單元 103_1, 103_2‧‧‧Shift register unit
104、104_1、104_2‧‧‧顯示區 104, 104_1, 104_2‧‧‧ display area
105‧‧‧掃描訊號產生電路 105‧‧‧Scan signal generation circuit
106‧‧‧交流訊號產生電路 106‧‧‧AC signal generation circuit
D1-Dn‧‧‧資料線 D1-Dn‧‧‧ data line
S1-Sm‧‧‧掃描線 S1-Sm‧‧‧ scan line
COM1-COMm‧‧‧訊號線 COM1-COMm‧‧‧ signal line
P‧‧‧像素 P‧‧ ‧ pixels
Claims (16)
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| TW104132149A TWI541791B (en) | 2015-09-30 | 2015-09-30 | Blue phase liquid crystal display apparatus |
| CN201510873508.7A CN105304055B (en) | 2015-09-30 | 2015-12-02 | Blue phase liquid crystal display device |
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| TW104132149A TWI541791B (en) | 2015-09-30 | 2015-09-30 | Blue phase liquid crystal display apparatus |
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| TW201712664A TW201712664A (en) | 2017-04-01 |
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| TWI416498B (en) * | 2010-12-30 | 2013-11-21 | Au Optronics Corp | Liquid crystal display and driving method thereof |
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