TWI540702B - Integrated circuit module and manufacturing methods and application thereof - Google Patents
Integrated circuit module and manufacturing methods and application thereof Download PDFInfo
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本發明是有關於一種積體電路模組及其製造方法與應用，且特別是有關於一種包含具有反短通道效應(Reverse Short Channel Effect，RSCE)之電晶體的積體電路模組及其應用方法。 The invention relates to an integrated circuit module, a manufacturing method thereof and an application thereof, and particularly to an integrated circuit module including a transistor having a reverse short channel effect (RSCE) and an application thereof method.
隨著積體電路的日益複雜，特徵尺寸以及佈線空間日益限縮，為了滿足特大型積體電路(super large scale integration)對效能及體密度與日俱增的要求，提高製程密度，將元件縮小，對於半導體製程與設計者而言，仍是一項持續不間斷的挑戰。 With the increasing complexity of integrated circuits, feature size and wiring space are increasingly limited, in order to meet the ever-increasing requirements for performance and bulk density of super large scale integration, increase process density, reduce components, and semiconductors. Processes and designers are still a constant challenge.
然而，由於目前製程的特徵尺寸已迫近光學機具之物理極限，是故在定位、顯影、蝕刻、化學機械研磨等諸多步驟，皆無法如傳統製程一般，輕易達成預期之精準度。因此在進行電路設計時，若完全不考慮製程極限，將可能誘發短通道效應(Short Channel Effect，SCE)、導致電晶體臨界電壓(Threshold Voltage，Vth)漂移、穿遂效應(Punch-Through)以及漏電流增加增加等問題，進而導致良率下降。 However, since the feature size of the current process is approaching the physical limit of the optical tool, it is impossible to achieve the desired precision in many steps such as positioning, development, etching, chemical mechanical polishing, and the like. Therefore, when the circuit design is performed, if the process limit is not considered at all, the Short Channel Effect (SCE), the Threshold Voltage (Vth) drift, and the Punch-Through effect may be induced. And problems such as an increase in leakage current increase, which in turn leads to a decrease in yield.
為了改善短通道效應，環型佈植(pocket implant)結構是一種普遍採用的方式。其係於p型金屬-氧化物-半導體元件(例如pMOS)中植入n型摻雜物質(nMOS反之)。其佈植位置在源極與汲極靠近閘極的外圍，將源極與汲極包圍住，這樣可抑制穿遂效應，提高元件臨界電壓降低漏電流。 In order to improve the short channel effect, a pocket implant structure is a commonly used method. It is implanted in a p-type metal-oxide-semiconductor element (eg pMOS) with an n-type dopant (nMOS is the opposite). The implantation position is at the periphery of the source and the drain near the gate, and the source and the drain are surrounded, so that the piercing effect can be suppressed, and the critical voltage of the component can be increased to reduce the leakage current.
但是如此一來，當半導體元件在次臨界電壓下操作時，將造成元件負面的反短通道效應的發生。這是因為，環型佈植會減弱汲極導致能障降低(Drain Induce Barrier Lowing，DIBL)的效應，使得環型佈植過度補嘗元件臨界電壓，造成元件驅動能力減弱，電力消耗增加，以及時脈偏差(timing violation)。 However, when the semiconductor component is operated at the sub-threshold voltage, it will cause a negative anti-short channel effect of the component. This is because the ring-shaped implant reduces the effect of Drain Induce Barrier Lowing (DIBL), causing the ring-shaped implant to over-compensate the component's threshold voltage, resulting in weaker component drive capability and increased power consumption. Timing violation.
為了解決這些問題，目前已有利用全面地增加元件通道長度，來稀釋反短通道效應在互補式金屬-氧化物-半導體元件所造成的臨界電壓增加現象。然而，全面增加元件通道長度，將同時使關鍵尺寸增加，有違降低製程密度的設計目的。 In order to solve these problems, it has been possible to comprehensively increase the length of the element channel to dilute the threshold voltage increase caused by the complementary metal-oxide-semiconductor element. However, increasing the component channel length in a comprehensive manner will increase the critical size at the same time, which is contrary to the design goal of reducing the process density.
另一種習知作法，則藉由將積體電路的操作電壓，固定在次臨界電下，利用反短通道效應的效果，將電晶體尺寸縮小，以省下佈局面積，降低汲極與源極電容負載，改善電路功率表現。然而此一作法，嚴重限制了邏輯電路的設計空間及應用範圍。 Another conventional method is to reduce the size of the transistor by using the effect of the anti-short channel effect by fixing the operating voltage of the integrated circuit to the sub-critical power to save the layout area and reduce the drain and source. Capacitive load to improve circuit power performance. However, this practice severely limits the design space and application range of the logic circuit.
因此有需要提供一種先進的積體電路模組及其應用方法，可適用在任何範圍的操作電壓，並在兼顧積體電路的操作速度與節省電力消耗的前提下，降低製程密度與製造成本。 Therefore, there is a need to provide an advanced integrated circuit module and its application method, which can be applied to any range of operating voltages, and reduce process density and manufacturing cost while taking into account the operating speed of the integrated circuit and saving power consumption.
本發明的目的之一，是在提供一種積體電路模組，其包括：具有第一通道以及第一臨界電壓(threshold voltage)絕對值的第一電晶體，以及與第一電晶體電性連結的第二電晶體。其中第二電晶體具有第二通道，其長度大於第一通道的長度，以及具有小於第一臨界電壓絕對值的第二臨界電壓絕對值，且第一電晶體與第二電晶體具有相同的臨界電壓摻雜(Threshold Voltage implant，Vt implant)濃度。 An object of the present invention is to provide an integrated circuit module including: a first transistor having a first channel and a first threshold voltage absolute value, and electrically connected to the first transistor The second transistor. Wherein the second transistor has a second channel having a length greater than a length of the first channel and having a second threshold voltage absolute value less than an absolute value of the first threshold voltage, and the first transistor has the same critical value as the second transistor Threshold Voltage implant (Vt implant) concentration.
在本發明的一實施例中，第二電晶體的源極接地。在本發明的一實施例中，第二通道長度為第一通道長度的2倍。在本發明的一實施例中，第一電晶體和第二電晶體，皆具有環型佈植(pocket implant)結構。 In an embodiment of the invention, the source of the second transistor is grounded. In an embodiment of the invention, the second channel length is twice the length of the first channel. In an embodiment of the invention, the first transistor and the second transistor each have a pocket implant structure.
在本發明的一實施例中，積體電路模組係在次臨界電壓 (sub threshold voltage)之下進行操作。其中，其操作電壓實質不大於0.5V。在本發明的一實施例中，積體電路模組具有實質高於、低於或等於範圍介於0.9V至1.2V的操作電壓。 In an embodiment of the invention, the integrated circuit module is tied to a sub-threshold voltage The operation is performed under (sub threshold voltage). Among them, the operating voltage is substantially no more than 0.5V. In an embodiment of the invention, the integrated circuit module has an operating voltage substantially above, below or equal to ranging from 0.9V to 1.2V.
在本發明的一實施例中，積體電路模組，更包含與第一電晶體和第二電晶體電性連結的第三電晶體。其中，第三電晶體具有與第二電晶體相同的臨界電壓摻雜濃度，且具有長度小於第二通道的第三通道，以及大於第二臨界電壓絕對值的第三臨界電壓絕對值。 In an embodiment of the invention, the integrated circuit module further includes a third transistor electrically coupled to the first transistor and the second transistor. Wherein the third transistor has the same threshold voltage doping concentration as the second transistor, and has a third channel having a length smaller than the second channel, and a third threshold voltage absolute value greater than the absolute value of the second threshold voltage.
本發明的另一目的，是在提供一種積體電路模組的製造方法，包括下述步驟：首先提供基材；並於基材上依序形成閘介電層以及閘極材料層。接著，於閘極材料層上進行臨界電壓摻雜製程，以於基材中定義出臨界電壓摻雜區。然後，於基材上形成彼此電性連結的第一電晶體及第二電晶體，使其分別於臨界電壓摻雜區中，定義出第一通道以及第二通道，其中第二通道的長度大於第一通道的長度。 Another object of the present invention is to provide a method of fabricating an integrated circuit module comprising the steps of: first providing a substrate; and sequentially forming a gate dielectric layer and a gate material layer on the substrate. Next, a threshold voltage doping process is performed on the gate material layer to define a threshold voltage doping region in the substrate. Then, a first transistor and a second transistor electrically connected to each other are formed on the substrate to define a first channel and a second channel respectively in the threshold voltage doping region, wherein the length of the second channel is greater than The length of the first channel.
在本發明的一實施例中，第一電晶體及第二電晶體的形成，包括下述步驟：先圖案化閘介電層和閘極材料層，以形成第一閘極和第二閘極。接著，進行至少一次的離子摻雜製程，於基材之中，定義出第一源極/汲極和第二源極/汲極，鄰接第一閘極和第二閘極。 In an embodiment of the invention, the forming of the first transistor and the second transistor includes the steps of: first patterning the gate dielectric layer and the gate material layer to form the first gate and the second gate . Next, at least one ion doping process is performed to define a first source/drain and a second source/drain in the substrate adjacent to the first gate and the second gate.
在本發明的一實施例中，積體電路模組的製造方法，還包括進行環型佈植製程，分別於第一通道以及第二通道下方，形成第一環型佈植區及第二環型佈植區，鄰接第一源極/汲極和第二源極/汲極。在本發明的一實施例中，更包括形成接地迴路，使第二電晶體的源極接地。 In an embodiment of the invention, the method for manufacturing an integrated circuit module further includes performing a ring-shaped implant process to form a first ring-shaped implant region and a second ring under the first channel and the second channel, respectively. A type of implanted region adjacent to the first source/drain and the second source/drain. In an embodiment of the invention, the method further includes forming a ground loop to ground the source of the second transistor.
在本發明的一實施例中，第二通道長度為第一通道長度的2倍。 In an embodiment of the invention, the second channel length is twice the length of the first channel.
在本發明的一實施例中，形成第一電晶體及第二電晶體的同時，更包括，形成第三電晶體，與第一電晶體和第二電晶體電性連結，並具有小於第二通道長度的第三通道長度。 In an embodiment of the invention, the first transistor and the second transistor are formed, and further comprising: forming a third transistor electrically connected to the first transistor and the second transistor, and having a smaller than the second The length of the third channel of the channel length.
本發明的又一目的，是在提供一種邏輯電路的設計方 法，包括下述步驟：先模擬設計一個由複數個標準積體電路模組所組成的邏輯電路。接著，分析此一邏輯電路，以決定關鍵路徑(critical path)。然後提供一個反短通道效應積體電路模組，來替換關鍵路徑中的至少一個標準積體電路模組。其中，反短通道效應積體電路模組包括：具有第一通道以及第一臨界電壓絕對值的第一電晶體，以及與第一電晶體電性連結的第二電晶體。其中第二電晶體具有第二通道，其長度大於第一通道的長度，以及具有小於第一臨界電壓絕對值的第二臨界電壓絕對值，且第一電晶體與第二電晶體具有相同的臨界電壓摻雜濃度。 Yet another object of the present invention is to provide a design circuit for a logic circuit The method includes the following steps: first simulating and designing a logic circuit composed of a plurality of standard integrated circuit modules. Next, analyze this logic circuit to determine the critical path. An anti-short channel effect integrated circuit module is then provided to replace at least one standard integrated circuit module in the critical path. The anti-short channel effect integrated circuit module includes: a first transistor having a first channel and a first threshold voltage absolute value, and a second transistor electrically coupled to the first transistor. Wherein the second transistor has a second channel having a length greater than a length of the first channel and having a second threshold voltage absolute value less than an absolute value of the first threshold voltage, and the first transistor has the same critical value as the second transistor Voltage doping concentration.
在本發明的一實施例中，第二電晶體的源極接地。在本發明的一實施例中，反短通道效應積體電路模組，係在次臨界電壓之下進行操作，具有實質不大於0.5V的操作電壓。在本發明的一實施例中，反短通道效應積體電路模組，具有實質高於、低於或等於範圍介於0.9V至1.2V的操作電壓。 In an embodiment of the invention, the source of the second transistor is grounded. In an embodiment of the invention, the anti-short channel effect integrated circuit module operates under a sub-threshold voltage and has an operating voltage substantially no greater than 0.5V. In an embodiment of the invention, the anti-short channel effect integrated circuit module has an operating voltage substantially higher than, lower than or equal to ranging from 0.9V to 1.2V.
在本發明的一實施例中，第一電晶體和第二電晶體，皆具有環型佈植結構。 In an embodiment of the invention, the first transistor and the second transistor each have a ring-shaped implant structure.
在本發明的一實施例中，反短通道效應積體電路模組，更包含第三電晶體，與第一電晶體和第二電晶體電性連結，並具有與第二電晶體相同的臨界電壓摻雜濃度，且具有小於第二通道長度的第三通道長度，以及大於第二臨界電壓絕對值的第三臨界電壓絕對值。 In an embodiment of the present invention, the anti-short channel effect integrated circuit module further includes a third transistor electrically coupled to the first transistor and the second transistor and having the same threshold as the second transistor. And a voltage doping concentration, and having a third channel length that is less than a second channel length, and a third threshold voltage absolute value that is greater than an absolute value of the second threshold voltage.
根據上述，本發明的實施例，是在同一個半導體製程中，製作出一個積體電路模組，其包含至少兩種不同通道長度，且具有反短通道效應的電晶體。將其運用在邏輯電路的設計時，僅需選擇關鍵路徑的部份電路模組，進行低電壓操作，以增加電路效能，即可改善時脈偏差的問題；而不需將邏輯電路中的電晶體，全部替換成具有反短通道效應的電晶體；更不需要將邏輯電路的操作電壓，固定在次臨界電之下，故可保留電路設計的自由度。又因積體電路模組，是利用的固有電晶體製程來加長部分電晶體的通道長度，並未改變電晶體的關鍵尺寸，並不會減少製程密度。反而因通道長度拉長，相對地 增加了電晶體製程的抗變異能力，更可節省製程成本。因此可解決習知的問題，達成上述發明目的。 In accordance with the above, embodiments of the present invention are in the same semiconductor process in which an integrated circuit module is fabricated that includes at least two different channel lengths and has an anti-short channel effect. When it is applied to the design of the logic circuit, only some circuit modules of the critical path need to be selected, and low voltage operation is performed to increase the circuit performance, thereby improving the problem of clock deviation; without the power in the logic circuit The crystals are all replaced by transistors with anti-short channel effects; there is no need to fix the operating voltage of the logic circuit under the sub-critical power, so the degree of freedom in circuit design can be retained. Moreover, due to the integrated circuit module, the intrinsic transistor process is utilized to lengthen the channel length of a part of the transistor, which does not change the critical size of the transistor and does not reduce the process density. Instead, because the length of the channel is elongated, relatively The resistance to variation of the transistor process is increased, and the process cost is saved. Therefore, the conventional problem can be solved and the above object of the invention can be achieved.
100‧‧‧互補式金屬-氧化物半導體反向器 100‧‧‧Complementary Metal-Oxide Semiconductor Inverter
101‧‧‧基材 101‧‧‧Substrate
102‧‧‧閘介電層 102‧‧‧gate dielectric layer
103‧‧‧閘極材料層 103‧‧‧ gate material layer
104‧‧‧臨界電壓摻雜製程 104‧‧‧Critical voltage doping process
105‧‧‧臨界電壓摻雜區 105‧‧‧Critical voltage doping area
106‧‧‧第一閘極 106‧‧‧First Gate
107‧‧‧第二閘極 107‧‧‧second gate
108‧‧‧離子摻雜製程 108‧‧‧Ion doping process
109‧‧‧第一源極/汲極 109‧‧‧First source/bungee
109a‧‧‧汲極 109a‧‧‧汲polar
110‧‧‧第二源極/汲極 110‧‧‧Second source/dip
110a‧‧‧源極 110a‧‧‧ source
110b‧‧‧汲極 110b‧‧‧汲polar
111a‧‧‧第一輕摻雜區 111a‧‧‧First lightly doped area
111b‧‧‧第二輕摻雜區 111b‧‧‧Second lightly doped area
112‧‧‧間隙壁 112‧‧‧ spacer
113‧‧‧第一通道 113‧‧‧First Passage
114‧‧‧第二通道 114‧‧‧second channel
115a‧‧‧第一環型佈植區 115a‧‧‧First ring type planting area
115b‧‧‧第二環型佈植區 115b‧‧‧Second ring planting area
116‧‧‧第一電晶體 116‧‧‧First transistor
117‧‧‧第二電晶體 117‧‧‧Second transistor
118‧‧‧內連線 118‧‧‧Interconnection
119‧‧‧接地迴路 119‧‧‧Ground circuit
120‧‧‧第三電晶體 120‧‧‧ Third transistor
200‧‧‧及閘 200‧‧‧ and gate
300‧‧‧邏輯閘電路 300‧‧‧Logic gate circuit
301‧‧‧及閘 301‧‧‧ and gate
302‧‧‧及閘 302‧‧‧ and gate
303‧‧‧及閘 303‧‧‧ and gate
304‧‧‧或閘 304‧‧‧ or gate
305‧‧‧互斥或閘 305‧‧‧ Mutual exclusion or gate
306‧‧‧反相器 306‧‧‧Inverter
307‧‧‧反相器 307‧‧‧Inverter
308‧‧‧反相器 308‧‧‧Inverter
309‧‧‧反相器 309‧‧‧Inverter
310‧‧‧反相器 310‧‧‧Inverter
311‧‧‧反相器 311‧‧‧Inverter
第1A圖到第1F係根據本發明的一較佳實施例，所繪示的一種具有反短通道效應之互補式金屬-氧化物半導體反向器的製程剖面圖。 1A through 1F are process cross-sectional views of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, in accordance with a preferred embodiment of the present invention.
圖1G係根據第1A圖到第1F的較佳實施例，所繪示之具有反短通道效應的互補式金屬-氧化物半導體反向器的結構上視圖。 1G is a structural top view of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, according to a preferred embodiment of FIGS. 1A through 1F.
圖1H係根據第1A圖到第1F的較佳實施例，所繪示的具有反短通道效應的互補式金屬-氧化物半導體反向器的電晶體級電路圖。 1H is a transistor-level circuit diagram of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, according to a preferred embodiment of FIGS. 1A through 1F.
圖2係根據本發明另一較佳實施例所繪示，具有反短通道效應的及閘的電晶體級電路圖。 2 is a circuit diagram of a transistor level of a gate having an anti-short channel effect, according to another preferred embodiment of the present invention.
圖3係根據本發明又一較佳實施例，所繪示的一種邏輯閘電路設計圖。 FIG. 3 is a schematic diagram of a logic gate circuit according to another preferred embodiment of the present invention.
本發明的目的就是在提供一種積體電路模組及其製造方法與應用，可適用在任何範圍的操作電壓，並兼顧積體電路的操作速度與電力消耗，降低製程密度與製造成本。為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉數個具有反短通道效應的積體電路模組及其應用方法做較佳實施例，並配合所附圖式，作詳細說明如下。 SUMMARY OF THE INVENTION The object of the present invention is to provide an integrated circuit module and a method and a manufacturing method thereof, which can be applied to any range of operating voltages, and take into account the operating speed and power consumption of the integrated circuit, and reduce the process density and manufacturing cost. The above and other objects, features and advantages of the present invention will become more apparent and understood. The formula is described in detail below.
請參照第1A圖到第1F圖，第1A圖到第1F圖係根據本發明的一較佳實施例，所繪示的一種具有反短通道效應之互補式金屬-氧化物半導體反向器(CMOS inverter)100的製程剖面圖。 Referring to FIGS. 1A to 1F, FIGS. 1A to 1F are diagrams showing a complementary metal-oxide semiconductor inverter having an anti-short channel effect according to a preferred embodiment of the present invention. CMOS inverter) 100 process profile.
其中，互補式金屬-氧化物半導體反向器100的製造方法包含下述步驟：首先提供基材101，並於基材101上依序形成閘介 電層102以及閘極材料層103(如圖1A所繪示)。接著，於閘極材料層103上進行臨界電壓摻雜製程104，以於基材101中定義出臨界電壓摻雜區105(如圖1B所繪示)。在本發明的較佳實施例之中，臨界電壓摻雜製程104是採用p型掺質(但不限定)，例如硼，在基材101表面進行摻雜製程，以形成由基材表面向下延伸的臨界電壓摻雜區105。 The manufacturing method of the complementary metal-oxide semiconductor inverter 100 includes the steps of: first providing a substrate 101, and sequentially forming a gate dielectric on the substrate 101. The electrical layer 102 and the gate material layer 103 (as shown in FIG. 1A). Next, a threshold voltage doping process 104 is performed on the gate material layer 103 to define a threshold voltage doping region 105 (shown in FIG. 1B) in the substrate 101. In a preferred embodiment of the present invention, the threshold voltage doping process 104 is performed by a doping process on the surface of the substrate 101 using a p-type dopant (but not limited to), such as boron, to form a surface down from the substrate. An extended threshold voltage doping region 105.
然後，圖案化閘介電層102和閘極材料層103，以形成第一閘極106和第二閘極107(如圖1C所繪示)。接著以第一閘極106為罩幕，選擇性地進行一輕摻雜製程，藉以在基材101之中形成P型第一輕摻雜區111a；以第二閘極107為罩幕，進行另一輕摻雜製程，藉以在基材101之中形成N型第二輕摻雜區111b，並在臨界電壓摻雜區105中，分別定義出第一通道113以及第二通道114(如圖1D所繪示)。其中第二通道114的長度大於第一通道113的長度；第二通道114較佳為第一通道113長度的2倍。 Then, the gate dielectric layer 102 and the gate material layer 103 are patterned to form a first gate 106 and a second gate 107 (as shown in FIG. 1C). Then, the first gate 106 is used as a mask to selectively perform a light doping process, thereby forming a P-type first lightly doped region 111a in the substrate 101; and using the second gate 107 as a mask. Another lightly doping process is used to form an N-type second lightly doped region 111b among the substrates 101, and in the threshold voltage doping region 105, a first channel 113 and a second channel 114 are respectively defined (as shown in the figure). 1D is shown). The length of the second channel 114 is greater than the length of the first channel 113; the second channel 114 is preferably twice the length of the first channel 113.
之後，選擇性地進行環型佈植製程，分別於第一輕摻雜區111a和第二輕摻雜區111b下方，形成N型的第一環型佈植區115a及P型的第二環型佈植區115b(如圖1E所繪示)。接著，藉由沉積及/或熱氧化製程，在第一閘極106和第二閘極107側壁上形成間隙壁112。再以第一閘極106、第二閘極107及間隙壁112為罩幕，進行離子植入製程108，以定義出P型第一源極/汲極109和N型第二源極/汲極110，而形成第一電晶體116和第二電晶體117(如圖1F所繪示)。 Thereafter, the ring-shaped implant process is selectively performed to form an N-type first ring-shaped implant region 115a and a P-type second ring under the first lightly doped region 111a and the second lightly doped region 111b, respectively. Type implant area 115b (as shown in Figure 1E). Next, spacers 112 are formed on the sidewalls of the first gate 106 and the second gate 107 by a deposition and/or thermal oxidation process. Then, using the first gate 106, the second gate 107 and the spacer 112 as a mask, an ion implantation process 108 is performed to define a P-type first source/drain 109 and an N-type second source/汲The pole 110 forms a first transistor 116 and a second transistor 117 (as shown in FIG. 1F).
後續再由後段製程，形成一導線，例如內連線118，使第一電晶體116和第二電晶體117電性連結，完成具有反短通道效應的互補式金屬-氧化物半導體反向器100的製備。 Subsequent to the subsequent process, a wire, such as an interconnect 118, is formed to electrically connect the first transistor 116 and the second transistor 117 to complete the complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect. Preparation.
請參照圖1G，圖1G係根據上述較佳實施例所繪示的具有反短通道效應的互補式金屬-氧化物半導體反向器100的結構上視圖。其中，第一電晶體116和第二電晶體117兩者係共用同一閘極線；第一電晶體116的第一閘極106寬度，實質為第二電晶體117之第二閘極107寬度的二分之一。另外，第二電晶體117的源極110a與接地迴路119導通。第二電晶體117的汲極110b，則經由內連線118，與 第一電晶體116的汲極109a導通。 Referring to FIG. 1G, FIG. 1G is a structural top view of a complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect according to the above preferred embodiment. The first transistor 116 and the second transistor 117 share the same gate line; the width of the first gate 106 of the first transistor 116 is substantially the width of the second gate 107 of the second transistor 117. Half. In addition, the source 110a of the second transistor 117 is electrically connected to the ground circuit 119. The drain 110b of the second transistor 117 is connected via the interconnect 118, The drain 109a of the first transistor 116 is turned on.
值得注意的是，由於第一電晶體116和第二電晶體117，是利用的同一製作流程，圖案化相同的基材101、閘介電層102和閘極材料層103所產生。因此，可使第一電晶體116與第二電晶體117具有相同的臨界電壓摻雜濃度絕對值。根據反短通道效應，當元件通道長度增加時，元件的臨界電壓值會降低，同時可以獲得較高的驅動電流。因此，當第一電晶體116的第一通道113長度，在不改變具有反短通道效應的互補式金屬-氧化物半導體反向器100之整體的關鍵尺寸的前提下相對地縮短時，第一通道113長度相對地小於第二電晶體117的第二通道114長度，第二電晶體117的第二臨界電壓絕對值，便會小於第一電晶體116的第一臨界電壓絕對值。亦即是，第二電晶體117的臨界電壓值相對地降低，通過第二電晶體117的電流相對地增加。 It is noted that since the first transistor 116 and the second transistor 117 are produced using the same fabrication process, the same substrate 101, the gate dielectric layer 102, and the gate material layer 103 are patterned. Therefore, the first transistor 116 and the second transistor 117 can have the same absolute value of the threshold voltage doping concentration. According to the anti-short channel effect, when the length of the component channel increases, the critical voltage value of the component decreases, and a higher driving current can be obtained. Therefore, when the length of the first channel 113 of the first transistor 116 is relatively shortened without changing the critical dimension of the entirety of the complementary metal-oxide semiconductor inverter 100 having the anti-short channel effect, the first The length of the channel 113 is relatively smaller than the length of the second channel 114 of the second transistor 117, and the absolute value of the second threshold voltage of the second transistor 117 is less than the absolute value of the first threshold voltage of the first transistor 116. That is, the threshold voltage value of the second transistor 117 is relatively lowered, and the current passing through the second transistor 117 is relatively increased.
利用反短通道效應，又由於，第一電晶體116和第二電晶體117係共用同一閘極線，可在不改變第一閘極106原有之關鍵尺寸的前提下，縮短第二閘極107的尺寸，來達到加長第二電晶體117通道長度的目的。故不需要增加額外的光罩或蝕刻步驟，即可形成兩種具有不同通道長度的電晶體。加上，第二電晶體117通道長度拉長，相對地增加了電晶體製程的抗變異能力。例如，通道長度加長，可稀釋摻雜步驟對抗隨機摻雜擾動(Random Dopant Fluctuation，RDF)對電晶體臨界電壓的影響，因此可增加一定程度的製程良率。另外，將本發明所提供的積體電路模組套用於邏輯電路，可明顯改善元件驅動能力減弱，電力消耗增加，以及時脈偏差問題。由於邏輯電路中相互疊接的兩相鄰電晶體，通常會在金屬導線間所產生寄生電容，導致電晶體切換速度遲延，造成邏輯電路的反應速度下降。例如，在本實施例之中，利用第二電晶體117所提供的反短通道效應，有助於降低第二電晶體117的臨界電壓值，提高流經第二電晶體117的操作電流，進而加速互補式金屬-氧化物半導體反向器100的反應。 By using the anti-short channel effect, and since the first transistor 116 and the second transistor 117 share the same gate line, the second gate can be shortened without changing the original critical dimension of the first gate 106. The size of 107 is to achieve the purpose of lengthening the length of the second transistor 117 channel. Therefore, two kinds of transistors having different channel lengths can be formed without adding an additional mask or etching step. In addition, the length of the second transistor 117 is elongated, which relatively increases the resistance of the transistor process to variation. For example, the length of the channel is lengthened, and the doping step can be used to counteract the influence of Random Dopant Fluctuation (RDF) on the critical voltage of the transistor, so that a certain degree of process yield can be increased. In addition, by using the integrated circuit module provided by the present invention for the logic circuit, the component driving capability is reduced, the power consumption is increased, and the clock deviation problem is significantly improved. Due to the two adjacent transistors stacked in the logic circuit, parasitic capacitance is usually generated between the metal wires, which causes the transistor switching speed to be delayed, resulting in a decrease in the response speed of the logic circuit. For example, in the present embodiment, the use of the anti-short channel effect provided by the second transistor 117 helps to lower the threshold voltage of the second transistor 117 and increase the operating current flowing through the second transistor 117. The reaction of the complementary metal-oxide semiconductor inverter 100 is accelerated.
一般而言，本發明所提供的積體電路模組，係套用於最 靠近接地線路的電晶體上。請參照圖1H，圖1H係根據上述較佳實施例所繪示的具有反短通道效應的互補式金屬-氧化物半導體反向器100的電晶體級電路圖(transistor-level schematic)。在本實施例之中，具有反短通道效應的積體電路模組的第二電晶體117，就是最靠近接地線路的電晶體。由於，這樣的設計方法，並不需要改變邏輯電路中的每個電晶體的通道長度，只需要相對地加大最靠近接地線路之第二電晶體117的通道長度，即可加速邏輯閘的切換速度。既可以省下佈局面積，又可改善邏輯電路時脈偏差的問題。 In general, the integrated circuit module provided by the present invention is used for the most On the transistor close to the ground line. Referring to FIG. 1H, FIG. 1H is a transistor-level diagram of a complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect according to the above preferred embodiment. In the present embodiment, the second transistor 117 of the integrated circuit module having the anti-short channel effect is the transistor closest to the ground line. Because of such a design method, it is not necessary to change the channel length of each transistor in the logic circuit, and only the channel length of the second transistor 117 closest to the ground line needs to be relatively increased, thereby speeding up the switching of the logic gate. speed. It can save the layout area and improve the clock skew of the logic circuit.
不過，為了突顯互補式金屬-氧化物半導體反向器100的反短通道效應，互補式金屬-氧化物半導體反向器100較佳係在次臨界電壓之下，例如操作電壓實質不大於0.5V，進行操作。 However, in order to highlight the anti-short channel effect of the complementary metal-oxide semiconductor inverter 100, the complementary metal-oxide semiconductor inverter 100 is preferably below the sub-critical voltage, for example, the operating voltage is substantially no more than 0.5V. , to operate.
這是因為反短通道效應會改變了元件的臨界電壓值，而臨界電壓對於次臨界電流呈指數倍的影響，所以驅動電流會隨著通道長度持續增加至飽和點。若互補式金屬-氧化物半導體反向器100是在範圍介於0.9V至1.2V的一般電壓之下操作，由於反短通道效應所改變的臨界電壓值，比起電晶體通道尺寸改變對於飽和區電流的影響要來的微小，故反短通道效應可能較不明顯。但在本發明的一些實施例中，積體電路模組仍可在實質高於、低於或等於一般操作電壓下進行操作。 This is because the anti-short channel effect changes the critical voltage value of the component, and the threshold voltage is exponentially affected by the sub-critical current, so the drive current continues to increase to the saturation point with the channel length. If the complementary metal-oxide semiconductor inverter 100 is operated under a general voltage ranging from 0.9V to 1.2V, the threshold voltage value changed due to the anti-short channel effect is changed compared to the transistor channel size for saturation. The influence of the current of the zone is small, so the anti-short channel effect may be less obvious. However, in some embodiments of the invention, the integrated circuit module can still operate at substantially higher, lower or equal to the normal operating voltage.
值得注意的是，上述實施例僅係用以說明本發明的特徵，具有反短通道效應的積體電路模組，仍可運用於其他積體電路模組，例如標準的邏輯閘。請參照圖2，圖2係根據本發明另一較佳實施例所繪示，具有反短通道效應的及閘(AND gate)200的電晶體級電路圖。 It should be noted that the above embodiments are merely used to illustrate the features of the present invention. The integrated circuit module with anti-short channel effect can still be applied to other integrated circuit modules, such as standard logic gates. Please refer to FIG. 2. FIG. 2 is a circuit diagram of a transistor level of an AND gate 200 having an anti-short channel effect according to another preferred embodiment of the present invention.
及閘200除了包含第一電晶體116及第二電晶體117之外，還包括複數個與第一電晶體116和第二電晶體117電性連結的第三電晶體120。其中，第三電晶體120的通道長度小於第二電晶體117之通道長度。在本發明的一些實施例之中，第三電晶體120與第一電晶體116和第二電晶體117，係藉由同一製程步驟所完成。且第三電 晶體120的通道長度，較佳係等於第一電晶體116的通道長度。但在另外一些實施例之中，第三電晶體120與第一電晶體116和第二電晶體117，係藉由不同製程步驟完成，且第三電晶體120的通道長度雖然小於第二電晶體117的通道長度，但第三電晶體120的通道長度，並不等於第一電晶體116的通道長度。 The gate 200 includes a plurality of third transistors 120 electrically coupled to the first transistor 116 and the second transistor 117 in addition to the first transistor 116 and the second transistor 117. The channel length of the third transistor 120 is smaller than the channel length of the second transistor 117. In some embodiments of the invention, the third transistor 120 and the first transistor 116 and the second transistor 117 are completed by the same process step. Third electric The channel length of the crystal 120 is preferably equal to the channel length of the first transistor 116. However, in other embodiments, the third transistor 120 and the first transistor 116 and the second transistor 117 are completed by different process steps, and the channel length of the third transistor 120 is smaller than that of the second transistor. The channel length of 117, but the channel length of the third transistor 120, is not equal to the channel length of the first transistor 116.
另外，上述具有反短通道效應的積體電路模組，可整合為電路設計的標準元件(standard cells)，用來進行邏輯電路的模擬設計。 In addition, the above-mentioned integrated circuit module with anti-short channel effect can be integrated into the standard cells of the circuit design for analog design of the logic circuit.
請參照圖3，圖3係根據本發明又一較佳實施例，所繪示的一種邏輯閘電路300設計圖。其中邏輯閘電路300是一種經由實驗室根據產品需求，所設計的邏輯電路圖。其係由複數個標準元件，例如反及閘(NAND gate)301、302和303、或閘(OR gate)304、互斥或閘(XOR gate)305及反相器306、307、308、309、310和311所組成。 Please refer to FIG. 3. FIG. 3 is a schematic diagram of a logic gate circuit 300 according to another preferred embodiment of the present invention. The logic gate circuit 300 is a logic circuit diagram designed according to product requirements through a laboratory. It is composed of a plurality of standard components, such as NAND gates 301, 302 and 303, or OR gate 304, XOR gate 305, and inverters 306, 307, 308, 309. , 310 and 311.
為了改善改善邏輯閘電路300的時脈偏差的問題，首先藉由模擬工具，例如半導體設計自動化(Electronic Design Automation EDA)工具，分析此一邏輯電路300，以決定一條關鍵路徑(如箭頭所示，此即由反相器306、307、308和309反及閘301和303以及或閘304所構成的最長延遲路徑)。然後，由標準元件庫(standard cells library)中，選用至少一個具有反短通道效應之積體電路模組，來替換關鍵路徑中的一般標準元件，例如反及閘301和303以及或閘304。藉由反短通道效應，縮短長延遲路徑與短延遲路徑的差距，進而改善因最長延遲路徑限制的最快工作頻率值，減低時脈偏差。 In order to improve the problem of improving the clock skew of the logic gate circuit 300, the logic circuit 300 is first analyzed by a simulation tool, such as an Electronic Design Automation EDA tool, to determine a critical path (as indicated by the arrow). This is the longest delay path formed by inverters 306, 307, 308 and 309 and gates 301 and 303 and OR gate 304. Then, from the standard cells library, at least one integrated circuit module having an anti-short channel effect is selected to replace the general standard components in the critical path, such as the gates 301 and 303 and the gate 304. By the anti-short channel effect, the gap between the long delay path and the short delay path is shortened, thereby improving the fastest operating frequency value limited by the longest delay path and reducing the clock deviation.
雖然，為了凸顯反短通道效應，具有反短通道效應之標準積體電路模組，較佳係在次臨界電壓之下，例如操作電壓實質不大於0.5V，進行操作。但在本發明的一些實施例中，邏輯電路300仍可在實質高於、低於或等於範圍介於0.9V至1.2V的一般操作電壓下進行操作。 Although, in order to highlight the anti-short channel effect, the standard integrated circuit module having an anti-short channel effect is preferably operated below the sub-threshold voltage, for example, the operating voltage is substantially no more than 0.5V. However, in some embodiments of the invention, logic circuit 300 can still operate at substantially higher, lower, or equal normal operating voltages ranging from 0.9V to 1.2V.
根據上述，本發明的實施例，是在同一個半導體製程中，製作出一個積體電路模組，其包含至少兩種不同通道長度，且具 有反短通道效應的電晶體。將其運用在邏輯電路的設計時，僅需選擇關鍵路徑的部份電路模組，進行低電壓操作，以增加電路效能，即可改善時脈偏差的問題；而不需將邏輯電路中的電晶體，全部替換成具有反短通道效應的電晶體；更不需要將邏輯電路的操作電壓，固定在次臨界電之下，故可保留電路設計的自由度。又因積體電路模組，是利用的固有電晶體製程來加長部分電晶體的通道長度，並未改變電晶體的關鍵尺寸，並不會減少製程密度。反而因通道長度拉長，相對地增加了電晶體製程的抗變異能力，更可節省製程成本。因此可解決解決習知的問題，達成上述發明目的。 According to the above, in an embodiment of the present invention, an integrated circuit module is formed in the same semiconductor process, which includes at least two different channel lengths, and has A transistor with an anti-short channel effect. When it is applied to the design of the logic circuit, only some circuit modules of the critical path need to be selected, and low voltage operation is performed to increase the circuit performance, thereby improving the problem of clock deviation; without the power in the logic circuit The crystals are all replaced by transistors with anti-short channel effects; there is no need to fix the operating voltage of the logic circuit under the sub-critical power, so the degree of freedom in circuit design can be retained. Moreover, due to the integrated circuit module, the intrinsic transistor process is utilized to lengthen the channel length of a part of the transistor, which does not change the critical size of the transistor and does not reduce the process density. On the contrary, because the length of the channel is elongated, the resistance to the variation of the transistor process is relatively increased, and the process cost can be saved. Therefore, it is possible to solve the conventional problem and achieve the above object.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100‧‧‧互補式金屬-氧化物半導體反向器 100‧‧‧Complementary Metal-Oxide Semiconductor Inverter
106‧‧‧第一閘極 106‧‧‧First Gate
107‧‧‧第二閘極 107‧‧‧second gate
109a‧‧‧汲極 109a‧‧‧汲polar
110a‧‧‧源極 110a‧‧‧ source
110b‧‧‧汲極 110b‧‧‧汲polar
113‧‧‧第一通道 113‧‧‧First Passage
114‧‧‧第二通道 114‧‧‧second channel
116‧‧‧第一電晶體 116‧‧‧First transistor
117‧‧‧第二電晶體 117‧‧‧Second transistor
118‧‧‧內連線 118‧‧‧Interconnection
119‧‧‧接地迴路 119‧‧‧Ground circuit
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