TWI540579B - Semiconductor storage device - Google Patents

Description

半導體儲存裝置 Semiconductor storage device

本發明主要關於一種半導體儲存裝置，特別關於NADN型快閃記憶體的編程(寫入)。 The present invention relates generally to a semiconductor memory device, and more particularly to programming (writing) of a NADN type flash memory.

快閃記憶廣泛的用於數位相機、智慧型手機等電子機器中作為儲存裝置。在這樣的市場下對於快閃記憶體有體積小、容量大的需求，更有高速、低電源消耗的需求。再者，快閃記憶體更有一定的資料可覆寫次數及資料維持特性的需求。 Flash memory is widely used as a storage device in electronic devices such as digital cameras and smart phones. In such a market, there is a need for a small size and a large capacity for flash memory, and there is a demand for high speed and low power consumption. Furthermore, flash memory has a certain amount of data to be able to overwrite and maintain data.

典型的快閃記憶體以N型MOS結構的記憶體單元所構成。電子累積於記憶體單元的電荷累積層中，記憶體單元的臨界值往正方向偏移，舉例來說，此狀態係作為「0」。另一方面，電子從記憶體單元的電荷累積層放出，記憶體單元的臨界值往負方向偏移，舉例來說，此狀態係作為「1」。第1圖係顯示記憶體單元內「0」與「1」的臨界值分布範圍，記憶體單元的臨界值在此分布範圍內作寫入控制。 A typical flash memory is constructed of a memory cell of an N-type MOS structure. The electrons are accumulated in the charge accumulation layer of the memory cell, and the critical value of the memory cell is shifted in the positive direction. For example, this state is "0". On the other hand, electrons are emitted from the charge accumulation layer of the memory cell, and the threshold value of the memory cell is shifted in the negative direction. For example, this state is "1". The first figure shows the critical value distribution range of "0" and "1" in the memory cell, and the threshold value of the memory cell is written and controlled within this distribution range.

由於存在製程的參數變動與時間的變化等變動的要素，各記憶體的通道氧化膜與電荷累積層，並不一定在所有記憶體單元中都是均勻的。換句話說，有些記憶體單元容易注入電子，有些記憶體單元不容易注入電子，施加相同的寫入電 壓至二者，兩者的臨界值的偏移量(變動量)也相對地不同。因此，舉例來說，在進行寫入頁面時，有些記憶體單元累積了充分的電子而可達到「0」的臨界值的分佈範圍內，然而有些記憶體單元累積了不充分的電子而無法達到「0」的臨界值的分佈範圍內。一般來說，藉由寫入的驗證可再次施加寫入電壓至電子注入不充分的記憶體單元，以達到「0」的臨界值分布範圍內。 The channel oxide film and the charge accumulating layer of each memory are not necessarily uniform in all the memory cells because there are elements such as variations in parameters of the process and changes in time. In other words, some memory cells are easy to inject electrons, some memory cells are not easy to inject electrons, and the same write power is applied. Pressing on both, the offset (variation) of the critical values of the two is also relatively different. Therefore, for example, when writing a page, some memory cells accumulate sufficient electrons to reach a critical value range of "0", but some memory cells accumulate insufficient electrons and cannot be reached. The distribution of the critical value of "0" is within the range. In general, the write voltage can be applied again to the memory cell with insufficient electron injection by the verification of the write to reach the critical value distribution range of “0”.

日本專利第3626221號公報揭露了可縮小記憶體單元的臨界值分布範圍，以及可進行高速電子注入之快閃記憶體。該快閃記憶體將寫入電壓分為複數脈衝，並且施加到記憶體單元的閘極。如第2A所示，施加至控制閘的最初的Vpp脈衝電壓為Vcgo，寫入脈衝僅僅緩慢上升△Vpp。脈衝寬度為一既定時間△t，而用於一次電子注入操作的記憶體單元臨界值的最大變化量△Vth等於△Vpp。此外，如第2B圖所示的寫入脈衝，各Vpp脈衝維持一定的dVpp/dt，僅連續上升△Vpp。因此，注入電子期間的浮動閘極電位可以大致固定，抑制通道氧化膜的劣化到最小。 Japanese Patent No. 3,262,221 discloses a flash memory that can reduce the critical value distribution range of a memory cell and can perform high-speed electron injection. The flash memory divides the write voltage into complex pulses and applies them to the gates of the memory cells. As shown in FIG. 2A, the initial Vpp pulse voltage applied to the control gate is Vcgo, and the write pulse is only slowly increased by ΔVpp. The pulse width is a predetermined time Δt, and the maximum variation ΔVth of the threshold value of the memory cell used for the one-time electron injection operation is equal to ΔVpp. Further, as in the write pulse shown in FIG. 2B, each Vpp pulse maintains a constant dVpp/dt, and only continuously rises by ΔVpp. Therefore, the floating gate potential during electron injection can be substantially fixed, and the deterioration of the channel oxide film can be suppressed to a minimum.

在快閃記憶體中，區塊內的頁面在編程完成後，有幾個要素會造成記憶體臨界值的分布範圍變動。臨界值變動的主要原因包括，背景圖案相依度(Background Pattern Dependency；BPD)、浮動閘的電容耦合、驗證對讀取的補償等。第3A圖用以說明藉由此寄生影響造成記憶體單元臨界值變動 的實施例。理想的記憶體單元中在編程完成後相對的臨界值的範圍在0.15V的範圍內，而驗證對讀取的補償、背景圖案相依度、浮動閘的電容耦合(FG coupling)相對的臨界值分布範圍較廣。 In flash memory, after the programming of the page in the block, there are several factors that will cause the distribution range of the memory threshold to change. The main reasons for the change in threshold value include: Background Pattern Dependency (BPD), capacitive coupling of floating gates, verification of compensation for reading, and so on. Figure 3A is used to illustrate the change in the critical value of the memory cell caused by the parasitic influence. An embodiment. In the ideal memory cell, the relative critical value after the programming is completed is in the range of 0.15V, and the compensation for the read compensation, the background pattern dependency, and the floating gate capacitive coupling (FG coupling) relative critical value distribution are verified. A wide range.

此外，隨著電路線縮小，由於隨機電報雜訊(Random Telegraph Noise；RTN)電晶體的臨界值產生變化為已知。再者，頁面編程的驗證降低用於減少刪除狀態的記憶體單元之電流，亦即源極的反彈下降，此記憶體單元的臨界值有變動的可能性。藉由隨機電報雜訊與源極的次要影響(源極的浮動/反彈)，編程的驗證中原先應該無法「PASS(合格)」的位元被表示為「PASS」。該位元在編程結束之後，如第3B圖所示，臨界值分布於區域Q而無法到達臨界值分布範圍。 In addition, as the circuit line shrinks, changes in the critical value of the Random Telegraph Noise (RTN) transistor are known. Furthermore, the verification of the page programming reduces the current used to reduce the memory cell of the deleted state, that is, the bounce of the source decreases, and the threshold value of the memory cell may vary. With the secondary influence of the random telegram noise and the source (floating/bounce of the source), the bit that should not be able to "PASS" in the verification of the program is indicated as "PASS". After the end of the programming, as shown in FIG. 3B, the critical value is distributed in the region Q and cannot reach the critical value distribution range.

為了解決這些舊有問題，本發明用以提供一種半導體記憶體裝置以抑制記憶體單元臨界值的變動。 In order to solve these old problems, the present invention is to provide a semiconductor memory device for suppressing variations in the threshold value of a memory cell.

本發明之快閃記憶體，具有複數NAND型記憶體單元所構成的一記憶體陣列，包括：一選擇元件，選擇上述記憶體陣列之一頁面；一設定元件，設定對一位元線編程或編程禁止之一位元線電壓；一施加元件，施加一編程脈衝至所選擇之頁面；一驗證元件，判斷編程是否合格；一判斷元件，根據驗證結果辨識從合格變為不合格之一不合格偏移記憶體單元，其中，當具有上述不合格偏移記憶體單元時，上述設定元件將上述不合格偏移記憶體單元的上述位元線電壓設定為一緩和電壓以緩和下一個編程脈衝的電壓。 The flash memory of the present invention has a memory array formed by a plurality of NAND type memory cells, comprising: a selection component for selecting one of the memory array pages; a setting component for setting a bit line programming or Programming prohibits one bit line voltage; an application component applies a programming pulse to the selected page; a verification component determines whether the programming is qualified; and a determination component that identifies one of the failed from the qualified to the unqualified according to the verification result An offset memory unit, wherein, when having the above-mentioned defective offset memory unit, the setting component sets the bit line voltage of the defective offset memory unit to a relaxation voltage to alleviate a next programming pulse Voltage.

較佳的上述緩和電壓為二編程脈衝之間的步進電壓。較佳的上述緩和電壓於編程用的電壓與編程禁止用的電壓之間。較佳的上述判斷元件藉由比較編程脈衝施加的前後之驗證結果，判斷是否具有上述不合格偏移記憶體單元。較佳的上述判斷元件具有一儲存元件用以儲存上述驗證元件所產生的驗證結果，所儲存的驗證結果用於辨識上述不合格偏移記憶體單元。 Preferably, the relaxation voltage is a step voltage between two programming pulses. Preferably, the relaxation voltage is between a voltage for programming and a voltage for programming inhibition. Preferably, the judging element judges whether or not the non-conforming offset memory unit is provided by comparing the result of the verification before and after the application of the program pulse. Preferably, the determining component has a storage component for storing the verification result generated by the verification component, and the stored verification result is used to identify the non-conforming offset memory unit.

本發明之編程方法，適用於具有複數NAND型記憶體單元所構成的一記憶體陣列之一快閃記憶體，上述編程方法包括：根據編程資料將位元線設置為編程用的電壓或編程禁止用的電壓；施加編程脈衝至所選擇的頁面；對所選擇頁面的編程進行驗證；以及當驗證結果係為具有從合格變為不合格之一不合格偏移記憶體單元時，將上述不合格偏移記憶體單元的上述位元線電壓設定為一緩和電壓以緩和下一個編程脈衝的電壓。 The programming method of the present invention is applicable to a flash memory having a memory array formed by a plurality of NAND type memory cells. The programming method includes: setting a bit line to a programming voltage or a program inhibit according to programming data. The voltage used; applying a programming pulse to the selected page; verifying the programming of the selected page; and failing the above when the verification result is one of the failed memory cells having passed from pass to fail The above bit line voltage of the offset memory cell is set to a relaxation voltage to moderate the voltage of the next programming pulse.

較佳的上述緩和電壓為二編程脈衝之間的步進電壓。較佳的實施例中，藉由比較編程脈衝施加的前後之驗證結果，辨識上述不合格偏移記憶體單元。 Preferably, the relaxation voltage is a step voltage between two programming pulses. In a preferred embodiment, the failed offset memory cell is identified by comparing the results of the verification before and after the application of the programming pulse.

藉由本發明可減少由隨機電報雜訊或源極反彈等造成的記憶體單元臨界值的變化。 By the invention, the change of the threshold value of the memory unit caused by random telegraph noise or source bounce can be reduced.

100‧‧‧快閃記憶體 100‧‧‧flash memory

110‧‧‧記憶體陣列 110‧‧‧Memory array

120‧‧‧輸入輸出緩衝器 120‧‧‧Input and output buffers

130‧‧‧位址暫存器 130‧‧‧ address register

140‧‧‧資料暫存器 140‧‧‧data register

150‧‧‧控制器 150‧‧‧ Controller

152‧‧‧驗證記憶體 152‧‧‧Verification memory

160‧‧‧字元線選擇電路 160‧‧‧Word line selection circuit

170‧‧‧頁面緩衝器/感測電路 170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧列選擇電路 180‧‧‧ column selection circuit

190‧‧‧內部電壓產生電路 190‧‧‧Internal voltage generation circuit

Ax‧‧‧行位址訊息 Ax‧‧‧ address message

Ay‧‧‧列位址訊息 Ay‧‧‧ address information

C1、C2、C3‧‧‧控制信號 C1, C2, C3‧‧‧ control signals

GBL0、GBL1、GBLn-1、GBLn‧‧‧位元線 GBL0, GBL1, GBLn-1, GBLn‧‧‧ bit line

MC0、MC1、MC2、MC31‧‧‧記憶體單元 MC0, MC1, MC2, MC31‧‧‧ memory unit

NU‧‧‧單元組 NU‧‧ unit group

P1、P2、P3、P4、P5‧‧‧編程脈衝 P1, P2, P3, P4, P5‧‧‧ programming pulses

Q‧‧‧區域 Q‧‧‧Area

SGD、SGS‧‧‧選擇閘極線 SGD, SGS‧‧‧ select gate line

SL‧‧‧共同源極線 SL‧‧‧Common source line

TD、TS‧‧‧選擇電晶體 TD, TS‧‧‧ select transistor

Vers‧‧‧刪除電壓 Vers‧‧‧Delete voltage

Vfy‧‧‧驗證電壓 Vfy‧‧‧Verification voltage

Vpass‧‧‧通過電壓 Vpass‧‧‧ pass voltage

Vprog‧‧‧編程電壓 Vprog‧‧‧ programming voltage

Vread‧‧‧讀出電壓 Vread‧‧‧ read voltage

Vcc、Vcgo、Vdd、△Vprog、△Vpp‧‧‧電壓 Vcc, Vcgo, Vdd, △Vprog, △Vpp‧‧‧ voltage

Vt‧‧‧臨界值 Vt‧‧‧ threshold

WL0、WL1、WL2、WL31‧‧‧字元線 WL0, WL1, WL2, WL31‧‧‧ character line

第1圖係顯示快閃記憶體的刪除狀態以及寫入狀態的臨 界值之示意圖。 Figure 1 shows the deletion status of the flash memory and the write status. Schematic diagram of the boundary value.

第2A、2B圖係顯示一實施之傳統的快閃記憶體的記憶體單元施加寫入的脈衝之說明圖。 2A and 2B are explanatory views showing pulses applied by a memory unit of a conventional flash memory of an embodiment.

第3A圖係為記憶體單元的臨界值分布的變化的要素之說明圖。 Fig. 3A is an explanatory diagram of elements that change the critical value distribution of the memory cell.

第3B圖係為傳統的快閃記憶體單元的編程的問題之說明圖。 Figure 3B is an illustration of the problem of programming a conventional flash memory cell.

第4圖係為根據本發明一實施例之快閃記憶體的組成之方塊圖。 Figure 4 is a block diagram showing the composition of a flash memory in accordance with an embodiment of the present invention.

第5圖係為根據本發明一實施例之記憶體陣列的NAND串的組成之電路圖。 Figure 5 is a circuit diagram showing the composition of a NAND string of a memory array in accordance with an embodiment of the present invention.

第6圖係顯示根據本發明一實施例之快閃記憶體的編程時施加至各單元的電壓。 Figure 6 is a diagram showing voltages applied to respective cells during programming of a flash memory in accordance with an embodiment of the present invention.

第7圖係顯示根據本發明之一實施例快閃記憶體的編程操作的流程圖。 Figure 7 is a flow chart showing the programming operation of the flash memory in accordance with one embodiment of the present invention.

第8圖係顯示施加編程脈衝時的臨界值的偏移的示意圖。 Figure 8 is a schematic diagram showing the shift of the critical value when a programming pulse is applied.

第9圖係顯示施加編程脈衝時的驗證結果與位元縣電壓之間的關係之示意圖。 Fig. 9 is a view showing the relationship between the verification result when the program pulse is applied and the voltage of the bit cell.

接著，配合所附圖式對本發明之實施例作詳細說明如下。在本發明較佳的實施型態中，以NAND型的快閃記憶體作為例子。此外，為了方便辨別，在圖式中會強調各個部分，需注意的是圖式的比例與實際裝置並不一定要相同。 Next, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In a preferred embodiment of the invention, a NAND type flash memory is taken as an example. In addition, in order to facilitate the identification, each part will be emphasized in the drawing. It should be noted that the scale of the drawing is not necessarily the same as the actual device.

第4圖係顯示根據本發明一實施例之快閃記憶體 組成之方塊圖。然而，所示之快閃記憶體的組成僅為舉例，本發明並非限制於此。 4 is a view showing a flash memory according to an embodiment of the present invention. The block diagram of the composition. However, the composition of the flash memory shown is merely an example, and the present invention is not limited thereto.

本發明之快閃記憶體100包括記憶體陣列110以行列狀排列的複數記憶體單元所構成、輸入輸出緩衝器120，暫存外部輸入輸出端I/O所連接之輸入輸出資料、位址暫存器130，接收輸入輸出緩衝器120之位址資料、資料暫存器140，暫存輸入輸出的資料、控制器150，接收來自輸入輸出資料緩衝器120的命令資料，以及根據外部控制信號(圖示中未顯示的晶片致能信號或位址閂鎖致能信號等)提供控制信號C1、C2、C3以控制各單元、驗證記憶體152，儲存編程驗證的結果、字元線選擇電路160，根據解碼來自位址暫存器130的行位址訊息Ax的解碼結果，進行區塊選擇以及字元線選擇、頁面緩衝器/感測電路170，暫存字元線選擇電路160選取的頁面讀取出之資料，暫存選取的頁面寫入之資料、列選擇電路180，根據解碼來自位址暫存器130的列位址訊息Ay解碼結果，進行位元線選擇、以及內部電壓產生電路190產生資料的讀取、編程、以及刪除所必需的電壓(編程電壓Vprog、通過電壓Vpass、讀出電壓Vread、刪除電壓Vers等等)。 The flash memory 100 of the present invention comprises a memory array 110 composed of a plurality of memory cells arranged in a matrix, an input/output buffer 120, and temporary storage of input and output data connected to an external input/output terminal I/O, and a temporary address. The buffer 130 receives the address data of the input/output buffer 120, the data register 140, temporarily stores the input and output data, the controller 150, receives the command data from the input/output data buffer 120, and according to the external control signal ( A wafer enable signal or an address latch enable signal (not shown) is provided to provide control signals C1, C2, C3 to control the cells, verify memory 152, store the result of the program verify, and word line select circuit 160. According to the decoding result of decoding the row address information Ax from the address register 130, the block selection and word line selection, the page buffer/sense circuit 170, and the page selected by the temporary word line selection circuit 160 are performed. Reading the data, temporarily storing the data written by the selected page, the column selection circuit 180, performing bit line selection according to the decoding result of decoding the column address information Ay from the address register 130, and The internal voltage generating circuit 190 generates voltages necessary for reading, programming, and erasing of data (program voltage Vprog, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

本發明之一實施例之記憶體陣列110，具有以列方向配置的複數區塊BLK(L)0、BLK(L)2、...、BLK(L)m-1區塊一側的端點設置頁面緩衝器/感測電路170。然而，頁面緩衝器/感測電路170亦可設置於另一側的端點，或者是設置於二側的端點。 The memory array 110 of one embodiment of the present invention has a plurality of blocks BLK(L)0, BLK(L)2, ..., BLK(L)m-1 arranged on the side of the block in the column direction. The page buffer/sensing circuit 170 is set. However, the page buffer/sense circuit 170 can also be placed at the end of the other side, or at the end of the two sides.

在一個記憶體區塊中，如第5圖所示，形成複數個 NAND單元組，其中NAND單元組Nu為複數串聯之記憶體單元，一個記憶體區塊內有n+1個單元組NU以行方向配置。每個單元組NU，包括由串聯之複數記憶體單元MCi(i=0、1、...、31)、在其中一端耦接至記憶體單元MC31的汲極側的選擇電晶體TD以及另一端耦接至記憶體單元MC0的源極側的選擇電晶體TS所組成。選擇電晶體TD的汲極耦接至對應的位元線GBL，而選擇電晶體TS的源極則耦接至共同源極線SL。 In a memory block, as shown in Figure 5, a plurality of The NAND cell group, wherein the NAND cell group Nu is a plurality of memory cells in series, and n+1 cell groups NU in one memory block are arranged in a row direction. Each cell group NU includes a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series, a selective transistor TD coupled to the drain side of the memory cell MC31 at one end thereof, and another One end is coupled to the selection transistor TS on the source side of the memory cell MC0. The drain of the selected transistor TD is coupled to the corresponding bit line GBL, and the source of the selected transistor TS is coupled to the common source line SL.

記憶體單元MCi的控制閘極分別耦接至對應的字元線WLi，選擇電晶體TD、TS的閘極分別耦接至與字元線WL平行的選擇閘極線SGD、SGS。字元線選擇電路160，在根據行位址Ax作區塊選擇時，藉由該區塊的選擇閘極信號SGS、SGD選擇性地驅動選擇電晶體TD以及TS。另外，雖第5圖係顯示一種典型的單元組結構，然而單元組亦可包括虛擬單元。 The control gates of the memory cells MCi are respectively coupled to the corresponding word lines WLi, and the gates of the selection transistors TD and TS are respectively coupled to the selection gate lines SGD, SGS parallel to the word lines WL. The word line selection circuit 160 selectively drives the selection transistors TD and TS by the selection gate signals SGS, SGD of the block when the block address is selected according to the row address Ax. In addition, although FIG. 5 shows a typical cell group structure, the cell group may also include a virtual cell.

典型的記憶體單元具有一MOS構造，其包括在P型井內形成的N型擴散區域的源極/汲極，形成於源極/汲極之間的通道上之通道氧化膜(tunnel oxide film)，形成於通道氧化膜上的浮動閘極(電荷蓄積層)，藉由浮動閘極上之介質膜形成的控制閘極。當沒有電荷蓄積於浮動閘極時，即寫入資料為「1」時，臨界值為負的狀態，記憶體單元一般為導通。當有電荷蓄積於浮動閘極時，即寫入資料為「0」時，臨界值為正的狀態，記憶體單元一般為不導通。 A typical memory cell has a MOS structure including a source/drain of an N-type diffusion region formed in a P-type well, and a tunnel oxide film formed on a channel between the source/drain a floating gate (charge accumulating layer) formed on the channel oxide film, a control gate formed by a dielectric film on the floating gate. When no charge is accumulated in the floating gate, that is, when the write data is "1", the threshold value is negative, and the memory cell is generally turned on. When there is charge accumulated in the floating gate, that is, when the written data is "0", the critical value is positive, and the memory cell is generally non-conductive.

第6圖係顯示根據一實施例之快閃記憶體在各操作下時所被施加的偏壓電壓之一表格圖。在讀取操作中，既定正電壓施加至位元線，既定電壓(例如，0V)施加至選擇的字元 線，通過電壓Vpass(例如，4.5V)施加至未選擇的字元線，正電壓(例如，4.5V)施加至選擇閘極線SGD、SGS，導通位元線選擇電晶體TD以及源極線選擇電晶體TS，以及施加0V至共通源極線。在編程(寫入)的操作中，高電壓的編程電壓Vprog(15~20V)施加至選擇的字元線，中間電位(例如10V)施加至未選擇的字元線，導通位元線選擇電晶體TD，不導通源極線選擇電晶體TS，對應於「0」或「1」的資料之電位提供至位元線GBL。在刪除操作中，0V施加至區塊內選擇的字元線，高電壓(例如20V)施加至P型井中，在基板將浮動閘極的電子拉出，以區塊為單位刪除資料。 Figure 6 is a table showing one of the bias voltages applied by the flash memory under various operations in accordance with an embodiment. In a read operation, a predetermined positive voltage is applied to the bit line, and a predetermined voltage (eg, 0V) is applied to the selected character. A line is applied to an unselected word line by a voltage Vpass (for example, 4.5 V), and a positive voltage (for example, 4.5 V) is applied to the selection gate lines SGD, SGS, the conduction bit line selection transistor TD, and the source line. The transistor TS is selected and 0V is applied to the common source line. In the programming (write) operation, a high voltage programming voltage Vprog (15~20V) is applied to the selected word line, an intermediate potential (for example, 10V) is applied to the unselected word line, and the turn bit line selects electricity. The crystal TD does not conduct the source line selection transistor TS, and the potential of the data corresponding to "0" or "1" is supplied to the bit line GBL. In the delete operation, 0V is applied to the selected word line in the block, and a high voltage (for example, 20V) is applied to the P-type well, and the electrons of the floating gate are pulled out on the substrate, and the data is deleted in units of blocks.

接著，說明關於本發明實施例之快閃記憶體的編程操作。輸入輸出緩衝器120接收來自外部控制器的命令與編程資料及位址，外部控制信號在輸入端子接收。控制器150對所接收到的命令解碼並執行編程，控制寫入的操作。頁面緩衝器/感測電路170藉由資料暫存器140暫存所接收到的編程資料，而字元線選擇電路160根據所接收到的位址選擇頁面。 Next, a programming operation of the flash memory relating to the embodiment of the present invention will be described. The input and output buffer 120 receives commands and programming data and addresses from an external controller, and external control signals are received at the input terminals. The controller 150 decodes and executes the command of the received command to control the operation of the write. The page buffer/sense circuit 170 temporarily stores the received programming data by the data register 140, and the word line selection circuit 160 selects a page based on the received address.

字元線選擇電路160根據行位址資料Ax施加編程脈衝至所選擇的頁面。編程脈衝Vprog藉由如第4圖所示之的內部電壓產生電路190來產生，對應驗證的結果產生如第2A、2B所示之步級電壓遞增的編程脈衝。施加大約15~20V的範圍的編程脈衝Vprog至所選擇的頁面，而施加10V的通過電壓Vpass至未選擇的頁面，施加Vcc至選擇閘極線SGD，施加0V至選擇閘極線SGS。此外，施加0V至欲編程為「0」的位元線，施加Vdd或Vcc至「1」即寫入禁止的位元線。 Word line select circuit 160 applies a programming pulse to the selected page based on row address data Ax. The program pulse Vprog is generated by the internal voltage generating circuit 190 as shown in Fig. 4, and the result of the verification produces a program pulse whose step voltage is increased as shown in Figs. 2A and 2B. A programming pulse Vprog in the range of approximately 15-20 V is applied to the selected page, and a pass voltage Vpass of 10 V is applied to the unselected page, Vcc is applied to the select gate line SGD, and 0 V is applied to the select gate line SGS. In addition, applying 0V to the bit line to be programmed to "0", applying Vdd or Vcc to "1" means writing the disabled bit line.

第7圖係為根據本發明之一實施例之編程操作之說明流程圖。如上所述，頁面緩衝器/感測電路170根據所接收到的編程資料將編程的記憶體單元的位元線BL設定為0V，將寫入禁止的記憶體單元的位元線BL設置為Vdd(S100)。 Figure 7 is a flow diagram illustrating the programming operation in accordance with an embodiment of the present invention. As described above, the page buffer/sense circuit 170 sets the bit line BL of the programmed memory cell to 0V according to the received programming material, and sets the bit line BL of the write-disabled memory cell to Vdd. (S100).

接著，控制器150根據頁面編程的驗證結果以辨識在頁面編程前後由合格(Pass)變為不合格(Fail)的記憶體單元(以下稱作「不合格偏移記憶體單元」)(S102)。施加一個編程脈衝後進行的驗證結果儲存於驗證記憶體152中，用以比較施加下一個編程脈衝後進行的驗證結果。亦即，藉由比較施加編程脈衝前後的驗證結果來判斷是否有不合格偏移記憶體單元。因此，事實上此判斷藉由二次的編程脈衝施加後的驗證來獲得。 Next, the controller 150 recognizes the memory unit (hereinafter referred to as "failed offset memory unit") which is changed from "pass" to "fail" before and after the page programming based on the verification result of the page programming (S102). . The verification result performed after applying a program pulse is stored in the verification memory 152 for comparing the verification result performed after the application of the next program pulse. That is, it is judged whether or not there is a defective offset memory cell by comparing the verification results before and after the application of the program pulse. Therefore, in fact, this judgment is obtained by verification after the application of the secondary programming pulse.

接著，在判斷有不合格偏移記憶體單元的情況下，將不合格偏移記憶體單元的位元線BL設定為+△Vprog，緩慢地校正下一次施加的編程脈衝的編程電壓(S104)。判斷是否具有不合格偏移記憶體單元，由於第二次施加編程脈衝後的驗證，對不合格偏移記憶體單元的編程電壓校正，事實上，第三次以後為施加編程脈衝的目標。 Next, when it is determined that there is a defective offset memory cell, the bit line BL of the defective offset memory cell is set to +ΔVprog, and the programming voltage of the next applied programming pulse is slowly corrected (S104). . Determining whether there is a defective offset memory cell, the programming voltage correction for the failed offset memory cell due to the verification after the second application of the programming pulse, in fact, the target of the application of the programming pulse after the third time.

接著，字元線選擇電路160施加編程脈衝至所選擇的頁面(S106)，選擇的頁面則執行編程。接著，進行判斷編程是否合格的驗證(S108)。換句話說，驗證係為判斷所選擇的頁面的記憶體單元之臨界值是否達到「0」的分佈範圍。在驗證中，驗證電壓(或讀取電壓)施加至所選擇的頁面，藉由緩衝器/感測電路170檢測位元線的電位或是電流，並根據檢測的結 果，所選擇的記憶體單元可導通的話則判定為編程不充分(不合格)，所選擇的記憶體單元不可導通的話則判定為資料編程正常(合格)。控制器150儲存此驗證結果至驗證記憶體152中(S110)。 Next, the word line selection circuit 160 applies a program pulse to the selected page (S106), and the selected page performs programming. Next, verification is performed to judge whether or not the programming is acceptable (S108). In other words, the verification is to determine whether the threshold value of the memory unit of the selected page reaches a distribution range of “0”. In the verification, the verify voltage (or read voltage) is applied to the selected page, and the potential/current of the bit line is detected by the buffer/sense circuit 170, and according to the detected junction If the selected memory cell can be turned on, it is determined that the programming is insufficient (failed), and if the selected memory cell is not conductive, it is determined that the data programming is normal (passed). The controller 150 stores the verification result in the verification memory 152 (S110).

控制器150根據所選擇頁面的驗證結果判斷所選擇的頁面是否所有的記憶體單元皆合格(S112)。若所有記憶體單元合格，則所選擇頁面的編程完成。 The controller 150 determines whether all of the selected memory cells are qualified according to the verification result of the selected page (S112). If all memory cells are qualified, the programming of the selected page is completed.

若所選擇的記憶體單元並非全部合格的情況下，增加步進電壓△Vprog於前一編程脈衝以產生編程脈衝(S114)，並以此施加至所選擇的頁面。與此並行地，藉由驗證判定為合格的記憶體單元之位元線BL設定為編程禁止的Vdd，仍屬於不合格的記憶體單元的位元線BL則繼續設定為0V。 If the selected memory cells are not all qualified, the step voltage ΔVprog is added to the previous programming pulse to generate a programming pulse (S114), and is applied to the selected page. In parallel with this, the bit line BL of the memory cell judged to be qualified is set to the program-inhibited Vdd, and the bit line BL which is still the unqualified memory cell continues to be set to 0V.

以此步驟S100到步驟S114為迴圈重複進行。第二次以後的編程脈衝施加後，控制器150比較驗證記憶體152所記憶的驗證結果，藉以辨識先前判定為合格但此次判定為不合格的記憶體單元(S102)。這樣的事件下，上述記憶體的超小型化所伴隨的隨機電報雜訊造成的臨界值急遽變化，以及源極反彈所造成的臨界值變動會發生，如第3圖所示，結果臨界值分布於區域Q而無法到達臨界值「0」的分佈範圍。 This step S100 to step S114 is repeated for the loop. After the second and subsequent programming pulses are applied, the controller 150 compares the verification results memorized by the verification memory 152, thereby identifying the memory cells that were previously determined to be qualified but are judged to be unqualified this time (S102). Under such an event, the critical value caused by the random telegraph noise accompanying the ultra-compacting of the memory is rapidly changed, and the threshold value fluctuation caused by the source bounce occurs, as shown in Fig. 3, the result is a critical value distribution. In the region Q, the distribution range of the critical value "0" cannot be reached.

發現此不合格偏移記憶體單元的情況下，在控制器150的控制下，雖將不合格偏移記憶體單元的位元線BL設置為可再編程的電壓，但通常並非為編程的電壓(0V)，而是更為略大的電壓，較佳設定為編程脈衝再加上步進電壓△Vprog。其 理由在於，位元線BL的電壓設定為0V時，施加只大於合格時編程脈衝2×△Vprog的電壓至不合格偏移記憶體單元，提供至不合格偏移記憶體單元的編程電壓太強，會有過編程(overprogram)的風險。因此，為了緩和2×△Vprog的電壓，將△Vpgm施加至位元線BL以其作為階差補償。此外，不合格偏移記憶體單元的位元線所設定的電壓，並非限制於△Vprog，亦可設置為大於編程電壓(0V)而小於編程禁止電壓(Vdd)的電壓。較佳的實施例中，設定不合格偏移記憶體單元的位元線的電壓藉由緩衝器/感測電路170來執行。此外，在設定不合格偏移記憶體單元的位元線於△Vprog的情況，緩衝器/感測電路170亦可藉由內部電壓產生電路190產生的△Vprog來提供至位元線。 In the case where this defective offset memory cell is found, under the control of the controller 150, although the bit line BL of the defective offset memory cell is set to a reprogrammable voltage, it is usually not a programmed voltage. (0V), but a slightly larger voltage, preferably set to the programming pulse plus the step voltage ΔVprog. its The reason is that when the voltage of the bit line BL is set to 0 V, a voltage greater than the pass-time programming pulse 2 × ΔVprog is applied to the defective offset memory cell, and the programming voltage supplied to the defective offset memory cell is too strong. There is a risk of overprogram. Therefore, in order to alleviate the voltage of 2 × ΔVprog, ΔVpgm is applied to the bit line BL as the step compensation. Further, the voltage set by the bit line of the defective offset memory cell is not limited to ΔVprog, and may be set to a voltage larger than the program voltage (0 V) and smaller than the program inhibit voltage (Vdd). In a preferred embodiment, the voltage of the bit line that sets the failed offset memory cell is performed by the buffer/sense circuit 170. Further, in the case where the bit line of the defective offset memory cell is set to ΔVprog, the buffer/sense circuit 170 can also be supplied to the bit line by ΔVprog generated by the internal voltage generating circuit 190.

第8圖係顯示施加編程脈衝P1、P2、P3、P4、P5時的編程記憶體單元(資料「0」)的臨界值分布範圍。於施加編程脈衝P2時，並不存在臨界值Vt被偏移至大於驗證電壓Vfy之記憶體單元，亦即不存在驗證下合格的記憶體單元，但在施加編程脈衝P3時，一部分的記憶體單元較驗證電壓Vfy大並判定為合格。在施加編程脈衝P4後的驗證，前次驗證為合格的部分記憶體單元，分布於小於分布下限值的區域Q中，而判定為不合格。換句話說，產生了不合格偏移記憶體單元。接著，施加編程脈衝P5時，對區域Q中的不合格偏移記憶體單元進行緩和地編程，不合格偏移記憶體單元的臨界值被偏移至資料0的分佈範圍內。 Figure 8 shows the critical value distribution range of the program memory cell (data "0") when the program pulses P1, P2, P3, P4, P5 are applied. When the programming pulse P2 is applied, there is no memory cell whose threshold value Vt is shifted to be larger than the verification voltage Vfy, that is, there is no memory cell that is qualified under verification, but a part of the memory is applied when the programming pulse P3 is applied. The cell is larger than the verification voltage Vfy and is judged to be acceptable. After the application of the program pulse P4, the partial memory cells that were previously verified as being qualified are distributed in the region Q smaller than the lower limit of the distribution, and are judged to be unacceptable. In other words, a defective offset memory cell is generated. Next, when the program pulse P5 is applied, the defective offset memory cell in the region Q is gently programmed, and the critical value of the defective offset memory cell is shifted to the distribution range of the data 0.

第9圖對應第8圖，係顯示施加編程脈衝P1、P2、P3、P4、P5時的驗證結果與位元線電壓的關係。編程脈衝的步 進電壓為△Vprog，理想的記憶體單元△Vth對應於△Vprog偏移。 Fig. 9 corresponds to Fig. 8, showing the relationship between the verification result when the program pulses P1, P2, P3, P4, and P5 are applied and the bit line voltage. Programming pulse step The input voltage is ΔVprog, and the ideal memory cell ΔVth corresponds to the ΔVprog shift.

在施加編程脈衝P3後判定為驗證合格的記憶體單元中，將位元線電壓設定為Vdd或Vcc以禁止編程。接著，施加編程脈衝P4，並在編程脈衝P4施加後的驗證中，發現先前判定為驗證合格但此次判定為驗證不合格的記憶體單元的狀況下，施加編程脈衝P5至該不合格偏移記憶體單元。相較於編程脈衝P3，編程脈衝P5僅大2×△Vprog的電壓，預定偏移2×△Vth，但可能造成過度編程。因此，位元線由0V設定為△Vprog。藉此，不合格偏移記憶體單元的通道電位由0V上升至△Vprog，而與編程脈衝P5的電壓的差異可緩和為△Vprog。因此，隨機電報雜訊或源極反彈等產生的臨界值變化藉此校正，且可使臨界值包括在目標的分布範圍內。 In the memory cell determined to be verified after the application of the program pulse P3, the bit line voltage is set to Vdd or Vcc to prohibit programming. Next, the program pulse P4 is applied, and in the verification after the application of the program pulse P4, the program pulse P5 is applied to the failed offset in the case where the memory cell previously determined to be verified but determined to be failed in verification is found. Memory unit. Compared to the programming pulse P3, the programming pulse P5 is only a voltage of 2 × ΔVprog, a predetermined offset of 2 × ΔVth, but may cause excessive programming. Therefore, the bit line is set from 0V to ΔVprog. Thereby, the channel potential of the defective offset memory cell rises from 0V to ΔVprog, and the difference from the voltage of the programming pulse P5 can be moderated to ΔVprog. Therefore, the threshold value change caused by random telegraph noise or source bounce or the like is thereby corrected, and the threshold value can be included in the distribution range of the target.

上述實施例為一個記憶體單元儲存二值資料作為例子，然而亦可適用於儲存多值資料的記憶體單元的快閃記憶體。再者，具有通常技術者可使用公知的電路技術簡單地完成編程脈衝的產生，此外，編程脈衝的數量，脈衝電壓，脈衝寬度時間可根據快閃記憶體的設計對應的作適當的設定。 The above embodiment is an example in which a memory unit stores binary data, but can also be applied to a flash memory of a memory unit that stores multi-value data. Furthermore, a person skilled in the art can simply complete the generation of the programming pulse using well-known circuit techniques. Further, the number of programming pulses, the pulse voltage, and the pulse width time can be appropriately set according to the design of the flash memory.

雖然已詳述本發明較佳的實施例之型態，但是本發明並非限定於特別指定的實施形態，在專利申請範圍所記載的本發明要點的範圍內，可做各種的變形或改變。 While the preferred embodiment of the present invention has been described in detail, the invention is not limited thereto, and various modifications and changes can be made without departing from the scope of the invention.

Claims (8)

一種快閃記憶體，具有複數NAND型記憶體單元所構成的一記憶體陣列，包括：一選擇元件，選擇上述記憶體陣列之一頁面；一設定元件，設定對一位元線編程或編程禁止之一位元線電壓；一施加元件，施加一第一編程脈衝以及一第二編程脈衝至所選擇之頁面；一驗證元件，判斷上述記憶體單元之臨界值是否大於一驗證電壓；以及一判斷元件，根據對應於上述第一編程脈衝之一第一驗證結果辨識是否有上述臨界值大於上述驗證電壓之一合格記憶體單元，當辨識有上述合格記憶體單元時，根據對應於上述第二編程脈衝之一第二驗證結果辨識是否有從上述合格記憶體單元變為上述臨界值小於上述驗證電壓之一不合格偏移記憶體單元；其中，當辨識有上述不合格偏移記憶體單元時，上述設定元件將上述不合格偏移記憶體單元的上述位元線電壓設定為一緩和電壓以緩和下一個編程脈衝的電壓。 A flash memory body having a memory array formed by a plurality of NAND type memory cells, comprising: a selection component for selecting one of the memory array pages; and a setting component for setting a bit line programming or programming prohibition a bit line voltage; an application component, applying a first programming pulse and a second programming pulse to the selected page; a verification component determining whether the threshold value of the memory cell is greater than a verification voltage; and determining And identifying, by the first verification result corresponding to one of the first programming pulses, whether the threshold value is greater than one of the verification voltages, and when the qualified memory unit is identified, according to the second programming a second verification result of the pulse identifies whether there is a defective memory cell from the qualified memory cell that is less than one of the verification voltages; wherein, when the non-conforming offset memory cell is identified, The setting component sets the bit line voltage of the non-conforming offset memory unit to a moderate voltage Press to relieve the voltage of the next programming pulse. 如申請專利範圍第1項所述之快閃記憶體，其中，上述緩和電壓為二編程脈衝之間的步進電壓。 The flash memory of claim 1, wherein the relaxation voltage is a step voltage between two programming pulses. 如申請專利範圍第1項所述之快閃記憶體，其中，上述緩和電壓於編程用的電壓與編程禁止用的電壓之間。 The flash memory according to claim 1, wherein the relaxation voltage is between a voltage for programming and a voltage for programming prohibition. 如申請專利範圍第1項所述之快閃記憶體，其中，上述判斷 元件藉由比較編程脈衝施加的前後之驗證結果，辨識上述不合格偏移記憶體單元。 The flash memory according to claim 1, wherein the above judgment The component identifies the failed offset memory cell by comparing the verification results before and after the application of the programming pulse. 如申請專利範圍第1項所述之快閃記憶體，其中，上述判斷元件具有一儲存元件用以儲存上述驗證元件所產生的驗證結果，所儲存的驗證結果用於辨識上述不合格偏移記憶體單元。 The flash memory of claim 1, wherein the determining component has a storage component for storing the verification result generated by the verification component, and the stored verification result is used to identify the non-conforming offset memory. Body unit. 一種編程方法，適用於具有複數NAND型記憶體單元所構成的一記憶體陣列之一快閃記憶體，上述編程方法包括：根據編程資料將位元線設置為編程用的電壓或編程禁止用的電壓；施加一第一編程脈衝至所選擇的頁面；對所選擇頁面的編程進行驗證；根據對應於上述第一編程脈衝之一第一驗證結果辨識是否有一臨界值大於一驗證電壓之一合格記憶體單元；當辨識有上述合格記憶體單元時，施加一第二編程脈衝至所選擇的頁面；根據對應於上述第二編程脈衝之一第二驗證結果辨識是否有從上述合格記憶體單元變為上述臨界值小於上述驗證電壓之一不合格偏移記憶體單元；以及當辨識有上述不合格偏移記憶體單元時，將上述不合格偏移記憶體單元的上述位元線電壓設定為一緩和電壓以緩和下一個編程脈衝的電壓。 A programming method is applicable to a flash memory of a memory array formed by a plurality of NAND type memory cells. The programming method includes: setting a bit line to a programming voltage or a program prohibition according to programming data. Voltage; applying a first programming pulse to the selected page; verifying programming of the selected page; identifying whether a threshold value is greater than one of the verifying voltages according to a first verification result corresponding to one of the first programming pulses a body unit; when the qualified memory unit is recognized, applying a second programming pulse to the selected page; identifying whether the memory is changed from the qualified memory unit according to a second verification result corresponding to one of the second programming pulses The threshold value is less than one of the verification voltages of the offset memory unit; and when the defective offset memory unit is identified, setting the bit line voltage of the defective offset memory unit to a mitigation The voltage is used to moderate the voltage of the next programming pulse. 如申請專利範圍第6項之編程方法，其中，上述緩和電壓為二編程脈衝之間的步進電壓。 The programming method of claim 6, wherein the relaxation voltage is a step voltage between two programming pulses. 如申請專利範圍第6項之編程方法，更包括：藉由比較編程脈衝施加的前後之驗證結果，辨識上述不合格偏移記憶體單元。 The programming method of claim 6 further includes: identifying the non-conforming offset memory unit by comparing the verification results before and after the application of the programming pulse.