TWI538410B

TWI538410B - Pulse calibration circuit

Info

Publication number: TWI538410B
Application number: TW103144754A
Authority: TW
Inventors: 劉深淵; 魏志旅
Original assignee: 國立臺灣大學
Priority date: 2014-12-22
Filing date: 2014-12-22
Publication date: 2016-06-11
Also published as: TW201624926A

Description

脈波校正電路 Pulse correction circuit

本發明是有關於一種校正電路，且特別是有關於一種脈波校正電路。 The present invention relates to a correction circuit, and more particularly to a pulse wave correction circuit.

針對習知的鎖相迴路(phase lock loop，PLL)中存在的時脈抖動(clock jitter)問題，目前已有文獻指出可透過次諧波注入(sub-harmonically injection)技術來獲得改善。然而，文獻上並未探討注入鎖相迴路中的電壓控制振盪器(voltage controlled oscillator，VCO)的注入脈波的寬度對於時脈抖動效能的影響。實際上，當環境改變(例如，電源電壓或是環境溫度的改變)時，傳統的注入脈波產生電路會隨之而產生變異，進而對所產生的注入脈波產生負面的影響。並且，傳統的注入脈波產生電路並未針對時脈抖動效能來設計適當的注入脈波寬度。 In view of the clock jitter problem existing in the conventional phase lock loop (PLL), it has been pointed out that the sub-harmonically injection technique can be used to obtain an improvement. However, the influence of the width of the injected pulse wave injected into the phase-locked loop (VCO) on the clock jitter performance is not discussed in the literature. In fact, when the environment changes (for example, the power supply voltage or the change in the ambient temperature), the conventional injection pulse generation circuit will mutate, which will have a negative impact on the generated injection pulse. Moreover, the conventional injection pulse generation circuit does not design an appropriate injection pulse width for the clock jitter performance.

本發明提供一種脈波校正電路，包括脈波注入時間點校正電路以及脈波寬度校正電路。脈波注入時間點校正電路依據模式訊號以及來自於鎖相迴路中的電壓控制振盪器第一時脈訊號校正參考時脈訊號以產生校正後時脈訊號，其中參考時脈訊號亦輸入至鎖相迴路。脈波寬度校正電路接收比例控制訊號以及校正後時脈訊號，並據以產生注入脈波，其中比例控制訊號用於控制注入脈波的脈波寬度與校正後時脈訊號的時脈週期之間的特定比例值。脈波注入時間點校正電路依據模式訊號產生啟動訊號，且脈波寬度校正電路因應於啟動訊號而將注入脈波注入至鎖相迴路中的電壓控制振盪器。 The invention provides a pulse wave correction circuit, including a pulse wave injection time point Positive circuit and pulse width correction circuit. The pulse injection time point correction circuit corrects the reference clock signal according to the mode signal and the first clock signal from the voltage controlled oscillator in the phase locked loop to generate the corrected clock signal, wherein the reference clock signal is also input to the phase lock signal. Loop. The pulse width correction circuit receives the proportional control signal and the corrected clock signal, and generates an injection pulse wave, wherein the proportional control signal is used to control the pulse width of the injected pulse wave and the clock period of the corrected clock signal The specific ratio value. The pulse injection time point correction circuit generates a start signal according to the mode signal, and the pulse width correction circuit injects the injection pulse into the voltage controlled oscillator in the phase locked loop according to the start signal.

在本發明之一實施例中，比例控制訊號為數位訊號，而脈波寬度校正電路包括電壓控制延遲線、第一及閘、第一電流源、電容、多個第二電流源、解碼器、第一開關、多個第二開關以及第二及閘。電壓控制延遲線接收校正後時脈訊號，並依據迴授電壓延遲校正後時脈訊號以產生延遲時脈訊號。第一及閘依據延遲時脈訊號以及校正後時脈訊號產生注入脈波。第一電流源輸出第一電流至節點。電容耦接於節點與接地點之間，用以依據第一電流產生迴授電壓。多個第二電流源，輸出多個第二電流。解碼器將數位訊號轉換為多個導通訊號。多個第一開關個別耦接於所述多個第二電流源與接地點之間。所述多個第一開關中的一部分因應於所述多個導通訊號而導通，以將所述多個第二電流中的一部分傳輸至接地點。第二開關耦接於節點以及所述多個第二電流源之間，因應於注入脈波而導通。 In an embodiment of the invention, the proportional control signal is a digital signal, and the pulse width correction circuit includes a voltage control delay line, a first AND gate, a first current source, a capacitor, a plurality of second current sources, a decoder, The first switch, the plurality of second switches, and the second AND gate. The voltage control delay line receives the corrected clock signal and delays the corrected clock signal according to the feedback voltage delay to generate a delayed clock signal. The first gate generates an injection pulse wave according to the delayed clock signal and the corrected clock signal. The first current source outputs the first current to the node. The capacitor is coupled between the node and the ground point for generating a feedback voltage according to the first current. A plurality of second current sources output a plurality of second currents. The decoder converts the digital signal into a plurality of pilot numbers. The plurality of first switches are individually coupled between the plurality of second current sources and the ground point. A portion of the plurality of first switches are turned on in response to the plurality of pilot signals to transmit a portion of the plurality of second currents to a ground point. The second switch is coupled between the node and the plurality of second current sources, and is turned on in response to the injection of the pulse wave.

在本發明之一實施例中，所述的脈波校正電路，更包括第二及閘，用以依據注入脈波以及啟動訊號輸出注入脈波至鎖相迴路中的電壓控制振盪器。 In an embodiment of the invention, the pulse wave correcting circuit further includes a second sum gate for injecting a pulse wave into the voltage controlled oscillator in the phase locked loop according to the injected pulse wave and the start signal output.

在本發明之一實施例中，當第一電流的電流值等於所述多個第二電流的電流值時，注入脈波的脈波寬度等於校正後時脈訊號的時脈週期乘以特定比例值。 In an embodiment of the invention, when the current value of the first current is equal to the current value of the plurality of second currents, the pulse width of the injected pulse wave is equal to the clock period of the corrected clock signal multiplied by a specific ratio. value.

在本發明之一實施例中，注入脈波的脈波寬度為鎖相迴路的輸出訊號的週期的1/4。 In one embodiment of the invention, the pulse width of the injected pulse wave is 1/4 of the period of the output signal of the phase locked loop.

基於上述，本發明實施例提出的脈波校正電路中的脈波寬度校正電路可依據比例控制訊號以及校正後時脈訊號產生具有適當脈波寬度的注入脈波，並因應於啟動訊號而將注入脈波注入鎖相迴路中的電壓控制振盪器。 Based on the above, the pulse width correction circuit in the pulse wave correction circuit according to the embodiment of the present invention can generate an injection pulse wave having an appropriate pulse width according to the proportional control signal and the corrected clock signal, and inject according to the start signal. The pulse wave is injected into the voltage controlled oscillator in the phase locked loop.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧脈波校正電路 100‧‧‧ Pulse Correction Circuit

110‧‧‧鎖相迴路 110‧‧‧ phase-locked loop

111‧‧‧頻率偵測器 111‧‧‧Frequency Detector

112‧‧‧電荷幫浦 112‧‧‧Charging pump

113‧‧‧迴路濾波器 113‧‧‧ Loop Filter

114‧‧‧自動頻率控制器 114‧‧‧Automatic frequency controller

115‧‧‧電壓控制振盪器 115‧‧‧Voltage Controlled Oscillator

116‧‧‧除頻器 116‧‧‧Delephone

120‧‧‧脈波注入時間點校正電路 120‧‧‧ Pulse injection time point correction circuit

121‧‧‧有限狀態機 121‧‧‧ finite state machine

122‧‧‧及閘 122‧‧‧ and gate

123‧‧‧可重置數位控制延遲線 123‧‧‧Resettable digital control delay line

124‧‧‧數位控制延遲線 124‧‧‧Digital Control Delay Line

125‧‧‧數位迴路濾波器 125‧‧‧Digital loop filter

126‧‧‧砰砰相位偵測器 126‧‧‧砰砰 phase detector

130‧‧‧脈波寬度校正電路 130‧‧‧ Pulse width correction circuit

202‧‧‧電壓控制延遲線 202‧‧‧Voltage control delay line

204‧‧‧第一及閘 204‧‧‧First Gate

206‧‧‧第一電流源 206‧‧‧First current source

C1‧‧‧電容 C1‧‧‧ capacitor

208_1~208_M‧‧‧第二電流源 208_1~208_M‧‧‧second current source

210‧‧‧解碼器 210‧‧‧Decoder

212_1~212_M‧‧‧第一開關 212_1~212_M‧‧‧First switch

214‧‧‧第二開關 214‧‧‧second switch

216‧‧‧第二及閘 216‧‧‧second gate

310~330、310’~330’、410~330、410’~330’、510~530、510’~530’‧‧‧曲線 310~330, 310'~330', 410~330, 410'~330', 510~530, 510'~530'‧‧‧ curves

CK_REF‧‧‧參考時脈訊號 CK _REF ‧‧‧Reference clock signal

CK_VCO+‧‧‧第一時脈訊號 CK _VCO+ ‧‧‧ first clock signal

CK_RDCL‧‧‧校正後時脈訊號 CK _RDCL ‧‧‧corrected clock signal

CK’‧‧‧延遲時脈訊號 CK’‧‧‧Delayed clock signal

CD_1~CD_M‧‧‧導通訊號 CD_1~CD_M‧‧‧Direction number

CK_DLF‧‧‧時脈訊號 CK _DLF ‧‧‧ clock signal

CK_DCL‧‧‧時脈訊號 CK _DCL ‧‧‧ clock signal

C_DL、C_RDL‧‧‧控制訊號 C _DL , C _RDL ‧‧‧ control signals

EN_INJ‧‧‧啟動訊號 EN _INJ ‧‧‧Start signal

EN_DLF‧‧‧致能訊號 EN _DLF ‧‧‧Enable signal

GND‧‧‧接地點 GND‧‧‧ Grounding point

INJ‧‧‧注入脈波 INJ‧‧‧Injected pulse wave

I1‧‧‧第一電流 I1‧‧‧First current

I2‧‧‧第二電流 I2‧‧‧second current

MODE‧‧‧模式訊號 MODE‧‧‧ mode signal

N1‧‧‧節點 N1‧‧‧ node

RC‧‧‧比例控制訊號 RC‧‧‧ proportional control signal

R1‧‧‧第一參考訊號 R1‧‧‧ first reference signal

V_CTRL‧‧‧電壓控制訊號 V _CTRL ‧‧‧ voltage control signal

V_C‧‧‧迴授電壓 Feedback voltage V _C ‧‧‧

圖1是依據本發明之一實施例繪示的脈波注入時間點校正電路、脈波寬度校正電路以及鎖相迴路的示意圖。 1 is a schematic diagram of a pulse wave injection time point correction circuit, a pulse width correction circuit, and a phase locked loop according to an embodiment of the invention.

圖2是依據本發明之一實施例繪示的脈波寬度校正電路示意圖。 2 is a schematic diagram of a pulse width correction circuit according to an embodiment of the invention.

圖3A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路頻寬的變化圖。 FIG. 3A is a diagram showing changes in the bandwidth of a phase-locked loop when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention.

圖3B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的頻寬變化圖。 FIG. 3B is a diagram showing the bandwidth variation of the phase-locked loop when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

圖4A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路的時脈抖動相對於電源電壓變化的趨勢圖。 4A is a graph showing a trend of clock jitter of a phase-locked loop with respect to a power supply voltage when the frequency of the output signal CK _OUT is 400 MHz, according to an embodiment of the invention.

圖4B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的時脈抖動相對於電源電壓變化的趨勢圖。 FIG. 4B is a graph showing the trend of the clock jitter of the phase locked loop with respect to the power supply voltage when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

圖5A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路的時脈抖動相對於環境溫度變化的趨勢圖。 FIG. 5A is a graph showing a trend of clock jitter of a phase-locked loop with respect to ambient temperature when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention.

圖5B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的時脈抖動相對於環境溫度變化的趨勢圖。 FIG. 5B is a graph showing the trend of the clock jitter of the phase-locked loop with respect to the ambient temperature when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention.

圖1是依據本發明之一實施例繪示的脈波注入時間點校正電路、脈波寬度校正電路以及鎖相迴路的示意圖。在本實施例中，鎖相迴路110包括相位頻率偵測器111、電荷幫浦112、迴路濾波器113、自動頻率控制器114、電壓控制振盪器115及除頻器116。相位頻率偵測器111、電荷幫浦112、迴路濾波器113及電壓控制振盪器115依序耦接。相位頻率偵測器111透過除頻器116耦接至相位頻率偵測器111，而迴路濾波器113更透過自動頻率控制器114耦接至電壓控制振盪器115。 1 is a schematic diagram of a pulse wave injection time point correction circuit, a pulse width correction circuit, and a phase locked loop according to an embodiment of the invention. In the present embodiment, the phase locked loop 110 includes a phase frequency detector 111, a charge pump 112, a loop filter 113, an automatic frequency controller 114, a voltage controlled oscillator 115, and a frequency divider 116. Phase frequency detector 111, charge pump 112, loop filter 113, and voltage The control oscillator 115 is coupled in sequence. The phase frequency detector 111 is coupled to the phase frequency detector 111 through the frequency divider 116, and the loop filter 113 is coupled to the voltage controlled oscillator 115 through the automatic frequency controller 114.

在鎖相迴路110中，相位頻率偵測器111可偵測參考時脈訊號CK_REF的相位是領先或是落後第一參考訊號R1的相位，並依據偵測結果輸出對應的高準位訊號或是低準位訊號至電荷幫浦112。接著，電荷幫浦112可依據相位頻率偵測器111所輸出的高/低準位訊號對應地進行充電或是放電的操作，並輸出一訊號至迴路濾波器113。迴路濾波器113可對電荷幫浦112所輸出的訊號進行濾波以產生電壓控制訊號V_CTRL。自動頻率控制器114可針對電壓控制訊號V_CTRL進行鎖頻操作，並將鎖頻後的電壓控制訊號V_CTRL輸出至電壓控制振盪器115。 In the phase-locked loop 110, the phase frequency detector 111 detects whether the phase of the reference clock signal CK _REF is leading or falling behind the phase of the first reference signal R1, and outputs a corresponding high-level signal according to the detection result. It is a low level signal to the charge pump 112. Then, the charge pump 112 can perform charging or discharging operation according to the high/low level signal output by the phase frequency detector 111, and output a signal to the loop filter 113. The loop filter 113 filters the signal output by the charge pump 112 to generate a voltage control signal V _CTRL . Automatic frequency controller 114 may be locked for operation of the voltage control signal V _CTRL, and the voltage control signal V _CTRL-locked output to the voltage controlled oscillator 115.

接著，電壓控制振盪器115可依據注入脈波INJ、電壓控制訊號V_CTRL以及鎖頻後的電壓控制訊號V_CTRL對應地改變輸出訊號CK_OUT的頻率，並產生第一時脈訊號CK_VCO+。之後，除頻器116可將輸出訊號CK_OUT的頻率除以N倍(N為正整數)以產生第一參考訊號R1，並將第一參考訊號R1迴授至相位頻率偵測器111。 Next, the voltage controlled oscillator 115 may correspond to varying the frequency output signal CK _OUT according to the INJ injection pulse, the voltage control signal V _CTRL and the voltage control signal V _CTRL-locked, and generates a first clock signal CK _{VCO +.} Thereafter, the frequency divider 116 divides the frequency of the output signal CK _OUT by N times (N is a positive integer) to generate a first reference signal R1, and returns the first reference signal R1 to the phase frequency detector 111.

值得注意的是，本實施例中注入電壓控制振盪器115的注入脈波INJ的注入時間點以及脈波寬度是分別經由本發明實施例提出的脈波校正電路100中的脈波注入時間點校正電路120以及脈波寬度校正電路130所校正。如此一來，當環境改變時，注入脈波INJ的特性(例如脈波寬度)即不會隨之而變動，因而能夠最佳化鎖相迴路110的時脈抖動情形。以下將進行詳細說明。 It is to be noted that the injection time point and the pulse width of the injection pulse wave INJ of the injection voltage control oscillator 115 in this embodiment are the pulse injection time point corrections in the pulse wave correction circuit 100 proposed by the embodiment of the present invention, respectively. The circuit 120 and the pulse width correction circuit 130 are corrected. In this way, when the environment changes, the characteristics of the injected pulse wave INJ (for example, the pulse width) do not change accordingly, and thus The clock jitter condition of the phase locked loop 110 is optimized. The details will be described below.

在本實施例中，脈波注入時間點校正電路120包括有限狀態機121、及閘122、可重置數位控制延遲線123、數位控制延遲線124、數位迴路濾波器125及砰砰相位偵測器126。概略而言，脈波注入時間點校正電路120可依據模式訊號MODE以及來自於鎖相迴路110中的電壓控制振盪器115的第一時脈訊號CK_VCO+校正參考時脈訊號CK_REF以產生校正後時脈訊號CK_RDCL。模式訊號MODE例如是由兩個位元組成的訊號，其可經由使用者的調整而讓脈波注入時間點校正電路120運作於四個模式的其中之一。所述四個模式例如是一般鎖相迴路模式、粗調模式、細調模式以及注入模式。在所述一般鎖相迴路模式中，脈波注入時間點校正電路120可不進行任何操作，進而使得脈波寬度校正電路130也不進行任何操作。如此一來，鎖相迴路110則將以一般的方式運作，在此不再贅述。在粗調模式及細調模式中，脈波注入時間點校正電路120將分別對於注入脈波INJ注入電壓控制振盪器115的時間點進行粗略地校正以及細微地校正。因應於對應於粗調模式及細調模式的模式訊號MODE，有限狀態機121可分別產生具有第一寬度及第二寬度的致能訊號EN_DLF，其中，第一寬度大於第二寬度。 In this embodiment, the pulse injection time point correction circuit 120 includes a finite state machine 121, a gate 122, a resettable digital control delay line 123, a digital control delay line 124, a digital loop filter 125, and a phase detection. 126. In summary, the pulse injection time point correction circuit 120 can correct the reference clock signal CK _REF according to the mode signal MODE and the first clock signal CK _VCO+ from the voltage control oscillator 115 in the phase locked loop 110 to generate the corrected image. Clock signal CK _RDCL . The mode signal MODE is, for example, a signal composed of two bits, which allows the pulse injection time point correction circuit 120 to operate in one of four modes via user adjustment. The four modes are, for example, a general phase locked loop mode, a coarse tuning mode, a fine tuning mode, and an injection mode. In the general phase-locked loop mode, the pulse injection time point correction circuit 120 may perform no operation, so that the pulse width correction circuit 130 does not perform any operation. As a result, the phase-locked loop 110 will operate in a general manner and will not be described herein. In the coarse adjustment mode and the fine adjustment mode, the pulse injection time point correction circuit 120 roughly corrects and finely corrects the time point at which the injection pulse wave INJ is injected into the voltage control oscillator 115, respectively. In response to the mode signal MODE corresponding to the coarse mode and the fine mode, the finite state machine 121 can respectively generate the enable signal EN _DLF having the first width and the second width, wherein the first width is greater than the second width.

接著，及閘122可依據具有特定寬度的致能訊號EN_DLF以及反相後的參考時脈訊號CK_REF產生時脈訊號CK_DLF，並輸出至數位迴路濾波器125。數位迴路濾波器125可依據時脈訊號CK_DLF以及砰砰相位偵測器126對於時脈訊號CK_DCL以及第一時脈訊號CK_VCO+ 的相位比較結果來產生控制訊號C_DL以及C_RDL，其中，時脈訊號CK_DCL是由數位控制延遲線124基於參考時脈訊號CK_REF以及控制訊號C_DL所產生。接著，可重置數位控制延遲線123可基於參考時脈訊號CK_REF以及控制訊號C_RDL來產生校正後時脈訊號CK_RDCL，並輸出時脈訊號CK_RDCL至脈波寬度校正電路130。應了解的是，脈波注入時間點校正電路120中各個元件的運作方式及原理可參照相關的文獻，在此不再贅述。 Then, the gate 122 generates a clock signal CK _DLF according to the enable signal EN _DLF having a specific width and the inverted reference clock signal CK _REF , and outputs the signal to the digital loop filter 125. The digital loop filter 125 generates the control signals C _DL and C _RDL according to the phase comparison result of the clock signal CK _DLF and the phase detector 126 for the clock signal CK _DCL and the first clock signal CK _VCO+ , wherein The clock signal CK _DCL is generated by the digitally controlled delay line 124 based on the reference clock signal CK _REF and the control signal C _DL . Then, the resettable digital control delay line 123 can generate the corrected clock signal CK _RDCL based on the reference clock signal CK _REF and the control signal C _RDL , and output the clock signal CK _RDCL to the pulse width correction circuit 130. It should be understood that the operation mode and principle of each component in the pulse injection time point correction circuit 120 can be referred to related documents, and details are not described herein again.

在其他實施例中，脈波寬度校正電路130接收比例控制訊號RC以及校正後時脈訊號CK_RDCL，並依據比例控制訊號RC產生注入脈波INJ。比例控制訊號RC用於控制注入脈波INJ的脈波寬度(以D表示)與校正後時脈訊號CK_RDCL的時脈週期T_REF之間的特定比例值。 In other embodiments, the pulse width correction circuit 130 receives the proportional control signal RC and the corrected clock signal CK _RDCL and generates an injection pulse INJ according to the proportional control signal RC. The proportional control signal RC is used to control a specific ratio between the pulse width (indicated by D) of the injected pulse wave INJ and the clock period T _{REF of the} corrected pulse signal CK _RDCL .

請參照圖2，圖2是依據本發明之一實施例繪示的脈波寬度校正電路示意圖。在本實施例中，脈波寬度校正電路130包括電壓控制延遲線202、第一及閘204、第一電流源206、電容C1、第二電流源208_1~208_M(M為正整數)、解碼器210、第一開關212_1~212_M、第二開關214以及第二及閘216。 Please refer to FIG. 2. FIG. 2 is a schematic diagram of a pulse width correction circuit according to an embodiment of the invention. In this embodiment, the pulse width correction circuit 130 includes a voltage control delay line 202, a first AND gate 204, a first current source 206, a capacitor C1, a second current source 208_1~208_M (M is a positive integer), and a decoder. 210, first switches 212_1~212_M, second switch 214, and second AND gate 216.

電壓控制延遲線202接收校正後時脈訊號CK_RDCL，並依據迴授電壓V_C延遲校正後時脈訊號CK_RDCL以產生延遲時脈訊號CK’。第一及閘204依據延遲時脈訊號CK’以及校正後時脈訊號CK_RDCL產生注入脈波INJ。應了解的是，迴授電壓V_C越小，電壓控制延遲線202延遲校正後時脈訊號CK_RDCL的幅度越大，因而使得注入脈波INJ的脈波寬度(即，D)越小，反之亦反。 The voltage control delay line 202 receives the corrected clock signal CK _RDCL and delays the corrected clock signal CK _RDCL according to the feedback voltage V _C to generate a delayed clock signal CK ′. The first gate 204 generates an injection pulse INJ according to the delayed clock signal CK' and the corrected clock signal CK _RDCL . It should be understood that the smaller the feedback voltage V _C is, the larger the amplitude of the pulse signal CK _RDCL after the voltage control delay line 202 is delayed, so that the pulse width (ie, D) of the injected pulse wave INJ is smaller, and vice versa. Also counter.

第一電流源206輸出第一電流I1至節點N1。電容C1耦接於節點N1與接地點GND之間，用以依據第一電流I1產生迴授電壓V_C。第二電流源208_1~208_M個別輸出第二電流I2。第一開關212_1~212_M個別耦接於第二電流源208_1~208_M與接地點GND之間。第二開關214耦接於節點N1以及第二電流源208_1~208_M之間，因應於注入脈波INJ而導通。 The first current source 206 outputs the first current I1 to the node N1. The capacitor C1 is coupled between the node N1 and the ground point GND for generating the feedback voltage V _C according to the first current I1. The second current sources 208_1~208_M individually output the second current I2. The first switches 212_1 212 212_M are individually coupled between the second current sources 208_1 208 208_M and the ground point GND. The second switch 214 is coupled between the node N1 and the second current sources 208_1 208 208_M, and is turned on according to the injection pulse INJ.

在一實施例中，比例控制訊號RC例如可實現為3個位元的數位訊號，而解碼器210可用於將此數位訊號轉換為多個導通訊號CD_1~CD_M。假設比例控制訊號RC所對應的特定比例值被設定為1/K(K為正整數)，則解碼器210可對應地透過導通訊號CD_1~CD_M的其中K個訊號來控制第一開關212_1~212_M其中的K個開關導通，進而讓第二電流源208_1~208_M之中的K個電流源能夠輸出K個第二電流I2至接地點GND。 In one embodiment, the proportional control signal RC can be implemented, for example, as a 3-bit digital signal, and the decoder 210 can be used to convert the digital signal into a plurality of pilot numbers CD_1~CD_M. Assuming that the specific proportional value corresponding to the proportional control signal RC is set to 1/K (K is a positive integer), the decoder 210 can correspondingly control the first switches 212_1~212_M through the K signals of the communication numbers CD_1~CD_M. The K switches are turned on, and the K current sources among the second current sources 208_1~208_M can output K second currents I2 to the ground point GND.

承上，假設校正後時脈訊號CK_RDCL的時脈週期為T_REF，且第一電流I1及第二電流I2的電流值皆為I，則在T_REF中流進節點N1的電荷可表徵為I×T_REF。在此情況下，當比例控制訊號RC所對應的特定比例值被設定為1/K，且注入脈波INJ的脈波寬度為D時，即可推得在T_REF中流出節點N1的電荷為K×I×D。依據電荷守恆原理可得知，流進節點N1的電荷將等於流出節點N1的電荷，因而可推得「I×T_REF=K×I×D」的關係式，化簡後可得「D=T_REF/K」的關係式。換言之，在圖2所示的架構下，當第一電流I1及第二電流I2的電流值相等時，注入脈波INJ的脈波寬度(即，D)等於校正後時脈訊號CK_RDCL的時脈週期(即，T_REF)乘以特定比例值(即，1/K)。 Assume that, after the clock period of the corrected clock signal CK _RDCL is T _REF , and the current values of the first current I1 and the second current I2 are both I, the charge flowing into the node N1 in T _REF can be characterized as I × T _REF . In this case, when the specific proportional value corresponding to the proportional control signal RC is set to 1/K, and the pulse width of the injection pulse INJ is D, the charge flowing out of the node N1 in T _REF can be derived as K × I × D. According to the principle of conservation of charge, it can be known that the charge flowing into node N1 will be equal to the charge flowing out of node N1, so that the relationship of "I × T _REF = K × I × D" can be derived, and "D = " The relationship of T _REF /K". In other words, under the architecture shown in FIG. 2, when the current values of the first current I1 and the second current I2 are equal, the pulse width (ie, D) of the injected pulse wave INJ is equal to the time of the corrected clock signal CK _RDCL . The pulse period (ie, T _REF ) is multiplied by a specific scale value (ie, 1/K).

在一實施例中，當模式訊號MODE被切換為對應於注入模式的訊號時，有限狀態機121可依據模式訊號MODE產生啟動訊號EN_INJ，而脈波寬度校正電路130可因應於啟動訊號EN_INJ而將注入脈波INJ注入至鎖相迴路110中的電壓控制振盪器115。具體而言，脈波寬度校正電路130可由第二及閘216接收啟動訊號EN_INJ以及來自於第一及閘204的注入脈波INJ，並依據注入脈波INJ以及啟動訊號EN_INJ輸出注入脈波INJ至鎖相迴路110中的電壓控制振盪器115。 In an embodiment, when the mode signal MODE is switched to the signal corresponding to the injection mode, the finite state machine 121 can generate the start signal EN _INJ according to the mode signal MODE, and the pulse width correction circuit 130 can respond to the start signal EN _INJ. The injection pulse INJ is injected into the voltage controlled oscillator 115 in the phase locked loop 110. Specifically, the pulse width correction circuit 130 can receive the start signal EN _INJ and the injection pulse INJ from the first AND gate 204 by the second AND gate 216, and output the pulse wave according to the injection pulse INJ and the start signal EN _INJ. The voltage in INJ to phase-locked loop 110 controls oscillator 115.

從另一觀點而言，在使用者依據特定比例值調整比例控制訊號RC之後，脈波寬度校正電路130可在不受環境影響的情況下準確地產生脈波寬度符合「D=T_REF/K」關係式的注入脈波INJ。因此，在使用者推導出可最佳化鎖相迴路110的時脈抖動的最佳特定比例值之後，脈波寬度校正電路130即可據以產生適當的注入脈波INJ，並因應於啟動訊號EN_INJ將注入脈波INJ注入至電壓控制振盪器115。如此一來，鎖相迴路110的時脈抖動即可因應於所述最佳特定比例值而被最佳化。 From another point of view, after the user adjusts the proportional control signal RC according to the specific proportional value, the pulse width correction circuit 130 can accurately generate the pulse width according to the environment: "D=T _REF /K The relational injection pulse INJ. Therefore, after the user derives the optimum specific ratio value of the clock jitter that can optimize the phase-locked loop 110, the pulse width correction circuit 130 can generate an appropriate injection pulse INJ accordingly, and respond to the start signal. The EN _INJ injects the injection pulse INJ into the voltage controlled oscillator 115. As such, the clock jitter of the phase locked loop 110 can be optimized in response to the optimum specific ratio value.

經推導，當注入脈波INJ的脈波寬度為輸出訊號CK_OUT的週期(以T_VCO表示)的1/4(即，D=T_VCO/4，以下稱最佳脈波寬度)時可最佳化鎖相迴路110的時脈抖動，以下將透過不同的實驗波形圖來進行驗證。 It is deduced that when the pulse width of the injection pulse INJ is 1/4 of the period of the output signal CK _OUT (indicated by T _VCO ) (ie, D=T _VCO /4, hereinafter referred to as the optimum pulse width) The clock jitter of the phase-locked loop 110 is verified by different experimental waveforms.

圖3A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路的相位雜訊圖。在本實施例中，橫軸為頻率偏移，而縱軸為鎖相迴路的頻寬。曲線310~330分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖3A所示，曲線330所對應的時脈抖動均方根值(約為10.65ps)明顯小於曲線310或320所對應的時脈抖動均方根值(分別約為16.73ps及12.01ps)。也就是說，曲線330對應的注入脈波INJ的脈波寬度確實能夠使鎖相迴路達到較佳的時脈抖動抑制效果。 FIG. 3A is a phase noise diagram of a phase locked loop when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the frequency offset and the vertical axis is the bandwidth of the phase locked loop. The curves 310 to 330 correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (that is, the optimum pulse width). As shown in FIG. 3A, the root mean square value of the clock jitter corresponding to the curve 330 (about 10.65 ps) is significantly smaller than the root mean square value of the clock jitter corresponding to the curve 310 or 320 (about 16.73 ps and 12.01 ps, respectively). . That is to say, the pulse width of the injection pulse wave INJ corresponding to the curve 330 can surely achieve a better clock jitter suppression effect of the phase locked loop.

圖3B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的相位雜訊圖。在本實施例中，橫軸為頻率偏移，而縱軸為鎖相迴路的頻寬。曲線310’~330’分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖3B所示，曲線330’所涵蓋的面積(約為2.29ps)明顯小於曲線310’或320’所涵蓋的面積(分別約為3.42ps及2.52ps)。也就是說，即便輸出訊號CK_OUT的頻率有所改變，曲線330’對應的注入脈波INJ的脈波寬度仍能夠使鎖相迴路達到較佳的時脈抖動抑制效果。 FIG. 3B is a phase noise diagram of a phase locked loop when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the frequency offset and the vertical axis is the bandwidth of the phase locked loop. Curves 310'-330' correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimal pulse width). As shown in Figure 3B, the area covered by curve 330' (approximately 2.29 ps) is significantly smaller than the area covered by curve 310' or 320' (approximately 3.42 ps and 2.52 ps, respectively). That is, even if the frequency of the output signal CK _OUT change, curve 330 'corresponding to the injection pulse width of the pulse INJ is still possible to achieve better phase-locked loop clock jitter suppressing effect.

圖4A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路的時脈抖動相對於電源電壓變化的趨勢圖。在本實施例中，橫軸為應用於鎖相迴路的電源電壓，而縱軸為鎖相迴路的時脈抖動均方根值。曲線410~430分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖4A所示，無論電源電壓如何變化，曲線430的時脈抖動均方根值皆低於曲線410及420。也就是說，即便電源電壓發生變化，曲線430對應的注入脈波INJ的脈波寬度仍能夠使鎖相迴路達到較佳的時脈抖動抑制效果。 4A is a graph showing a trend of clock jitter of a phase-locked loop with respect to a power supply voltage when the frequency of the output signal CK _OUT is 400 MHz, according to an embodiment of the invention. In this embodiment, the horizontal axis is the power supply voltage applied to the phase locked loop, and the vertical axis is the clock rms value of the phase locked loop. Curves 410 to 430 correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimum pulse width). As shown in FIG. 4A, the clock rms value of curve 430 is lower than curves 410 and 420 regardless of the change in supply voltage. That is to say, even if the power supply voltage changes, the pulse width of the injection pulse wave INJ corresponding to the curve 430 can still achieve a better clock jitter suppression effect of the phase locked loop.

圖4B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的時脈抖動相對於電源電壓變化的趨勢圖。在本實施例中，橫軸為應用於鎖相迴路的電源電壓，而縱軸為鎖相迴路的時脈抖動均方根值。曲線410’~430’分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖4B所示，無論電源電壓如何變化，曲線430’的時脈抖動均方根值皆低於曲線410’及420’。也就是說，即便輸出訊號CK_OUT的頻率有所改變，曲線430’對應的注入脈波INJ的脈波寬度仍能夠在不同的電源電壓下使鎖相迴路達到較佳的時脈抖動抑制效果。 FIG. 4B is a graph showing the trend of the clock jitter of the phase locked loop with respect to the power supply voltage when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the power supply voltage applied to the phase locked loop, and the vertical axis is the clock jitter rms value of the phase locked loop. The curves 410' to 430' correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, the optimum pulse width). As shown in FIG. 4B, the clock rms value of curve 430' is lower than curves 410' and 420' regardless of the change in supply voltage. That is to say, even if the frequency of the output signal CK _OUT is changed, the pulse width of the injection pulse INJ corresponding to the curve 430' can achieve a better clock jitter suppression effect of the phase locked loop under different power supply voltages.

圖5A是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為400MHz時，鎖相迴路的時脈抖動相對於環境溫度變化的趨勢圖。在本實施例中，橫軸為鎖相迴路的環境溫度，而縱軸為鎖相迴路的時脈抖動均方根值。曲線510~530分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖5A所示，無論環境溫度如何變化，曲線530的時脈抖動均方根值皆低於曲線510及520。也就是說，即便環境溫度發生變化，曲線530對應的注入脈波INJ的脈波寬度仍能夠使鎖相迴路達到較佳的時脈抖動抑制效果。 FIG. 5A is a graph showing a trend of clock jitter of a phase-locked loop with respect to ambient temperature when the frequency of the output signal CK _OUT is 400 MHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the ambient temperature of the phase locked loop, and the vertical axis is the clock root mean square value of the phase locked loop. The curves 510 to 530 correspond to the cases of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, the optimum pulse width). As shown in FIG. 5A, the clock rms value of curve 530 is lower than curves 510 and 520 regardless of changes in ambient temperature. That is to say, even if the ambient temperature changes, the pulse width of the injection pulse INJ corresponding to the curve 530 can still achieve a better clock jitter suppression effect of the phase locked loop.

圖5B是依據本發明之一實施例繪示的當輸出訊號CK_OUT的頻率為1.6GHz時，鎖相迴路的時脈抖動相對於環境溫度變化的趨勢圖。在本實施例中，橫軸為應用於鎖相迴路的環境溫度，而縱軸為鎖相迴路的時脈抖動均方根值。曲線510’~530’分別對應於「D=T_VCO/2」、「D=T_VCO/8」以及「D=T_VCO/4」(即，最佳脈波寬度)的情形。如圖5B所示，無論環境溫度如何變化，曲線530’的時脈抖動均方根值皆低於曲線510’及520’。也就是說，即便輸出訊號CK_OUT的頻率有所改變，曲線530’對應的注入脈波INJ的脈波寬度仍能夠在不同的環境溫度下使鎖相迴路達到較佳的時脈抖動抑制效果。 FIG. 5B is a graph showing the trend of the clock jitter of the phase-locked loop with respect to the ambient temperature when the frequency of the output signal CK _OUT is 1.6 GHz according to an embodiment of the invention. In this embodiment, the horizontal axis is the ambient temperature applied to the phase locked loop, and the vertical axis is the clock rms value of the phase locked loop. Curves 510'-530' correspond to the case of "D=T _VCO /2", "D=T _VCO /8", and "D=T _VCO /4" (ie, optimal pulse width). As shown in FIG. 5B, the clock rms value of curve 530' is lower than curves 510' and 520' regardless of changes in ambient temperature. That is to say, even if the frequency of the output signal CK _OUT is changed, the pulse width of the injection pulse INJ corresponding to the curve 530' can achieve a better clock jitter suppression effect at different ambient temperatures.

綜上所述，本發明實施例提出的脈波校正電路中的脈波寬度校正電路可依據比例控制訊號以及校正後時脈訊號產生具有適當脈波寬度的注入脈波，並因應於啟動訊號而將注入脈波注入鎖相迴路中的電壓控制振盪器。如此一來，在使用者推導出可最佳化鎖相迴路的時脈抖動的特定脈波寬度(例如，D=T_VCO/4)之後，脈波寬度校正電路即可據以產生具有此特定脈波寬度的注入脈波，進而讓鎖相迴路的時脈抖動能夠被最佳化。並且，經實驗驗證，所述特定脈波寬度相較於其他的脈波寬度確實能達到較低的時脈抖動。 In summary, the pulse width correction circuit in the pulse wave correction circuit according to the embodiment of the present invention can generate an injection pulse wave having an appropriate pulse width according to the proportional control signal and the corrected clock signal, and respond to the start signal. The injection pulse is injected into the voltage controlled oscillator in the phase locked loop. In this way, after the user derives a specific pulse width (for example, D=T _VCO /4) that can optimize the clock jitter of the phase-locked loop, the pulse width correction circuit can generate the specific The pulse width is injected into the pulse wave, which in turn allows the clock jitter of the phase-locked loop to be optimized. Moreover, it has been experimentally verified that the specific pulse width can indeed achieve lower clock jitter than other pulse widths.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

202‧‧‧電壓控制延遲線 202‧‧‧Voltage control delay line

204‧‧‧第一及閘 204‧‧‧First Gate

206‧‧‧第一電流源 206‧‧‧First current source

C1‧‧‧電容 C1‧‧‧ capacitor

208_1~208_M‧‧‧第二電流源 208_1~208_M‧‧‧second current source

210‧‧‧解碼器 210‧‧‧Decoder

212_1~212_M‧‧‧第一開關 212_1~212_M‧‧‧First switch

214‧‧‧第二開關 214‧‧‧second switch

216‧‧‧第二及閘 216‧‧‧second gate

CK_RDCL‧‧‧校正後時脈訊號 CK _RDCL ‧‧‧corrected clock signal

CK’‧‧‧延遲時脈訊號 CK’‧‧‧Delayed clock signal

CD_1~CD_M‧‧‧導通訊號 CD_1~CD_M‧‧‧Direction number

EN_INJ‧‧‧啟動訊號 EN _INJ ‧‧‧Start signal

GND‧‧‧接地點 GND‧‧‧ Grounding point

INJ‧‧‧注入脈波 INJ‧‧‧Injected pulse wave

I1‧‧‧第一電流 I1‧‧‧First current

I2‧‧‧第二電流 I2‧‧‧second current

N1‧‧‧節點 N1‧‧‧ node

RC‧‧‧比例控制訊號 RC‧‧‧ proportional control signal

V_C‧‧‧迴授電壓 Feedback voltage V _C ‧‧‧

Claims

一種脈波校正電路，包括：一脈波注入時間點校正電路，依據一模式訊號以及來自於該鎖相迴路中的一電壓控制振盪器一第一時脈訊號校正一參考時脈訊號以產生一校正後時脈訊號，其中該參考時脈訊號亦輸入至一鎖相迴路；以及一脈波寬度校正電路，接收一比例控制訊號以及該校正後時脈訊號，並據以產生一注入脈波，其中該比例控制訊號用於控制該注入脈波的一脈波寬度與該校正後時脈訊號的一時脈週期之間的一特定比例值，其中，該脈波注入時間點校正電路依據該模式訊號產生一啟動訊號，且該脈波寬度校正電路因應於該啟動訊號而將該注入脈波注入至該鎖相迴路中的該電壓控制振盪器。 A pulse wave correction circuit includes: a pulse injection time point correction circuit for correcting a reference clock signal according to a mode signal and a first clock signal from a voltage controlled oscillator in the phase locked loop to generate a The corrected clock signal, wherein the reference clock signal is also input to a phase locked loop; and a pulse width correction circuit receives a proportional control signal and the corrected clock signal, and generates an injection pulse wave, The proportional control signal is used to control a specific ratio between a pulse width of the injected pulse wave and a clock period of the corrected pulse signal, wherein the pulse injection time point correction circuit is based on the mode signal An activation signal is generated, and the pulse width correction circuit injects the injection pulse into the voltage controlled oscillator in the phase locked loop according to the startup signal.

如申請專利範圍第1項所述的脈波校正電路，其中該比例控制訊號為一數位訊號，而該脈波寬度校正電路包括：一電壓控制延遲線，接收該校正後時脈訊號，並依據一迴授電壓延遲該校正後時脈訊號以產生一延遲時脈訊號；一第一及閘，依據該延遲時脈訊號以及該校正後時脈訊號產生該注入脈波；一第一電流源，輸出一第一電流至一節點；一電容，耦接於該節點與一接地點之間，用以依據該第一電流產生該迴授電壓；多個第二電流源，輸出多個第二電流；一解碼器，將該數位訊號轉換為多個導通訊號；多個第一開關，個別耦接於該些第二電流源與該接地點之間，其中該些第一開關中的一部分因應於該些導通訊號而導通，以將該些第二電流中的一部分傳輸至該接地點；一第二開關，耦接於該節點以及該些第二電流源之間，因應於該注入脈波而導通。 The pulse wave correction circuit of claim 1, wherein the proportional control signal is a digital signal, and the pulse width correction circuit comprises: a voltage control delay line, receiving the corrected clock signal, and a feedback voltage delays the corrected clock signal to generate a delayed clock signal; a first gate, the injection pulse wave is generated according to the delayed clock signal and the corrected clock signal; a first current source, And outputting a first current to a node; a capacitor coupled between the node and a ground point for generating the feedback voltage according to the first current; a plurality of second current sources outputting a plurality of second currents; a decoder converting the digital signals into a plurality of conductive communication numbers; and a plurality of first switches individually coupled to the second current sources and the grounding point a portion of the first switches is turned on in response to the conductive signals to transmit a portion of the second currents to the ground point; a second switch coupled to the node and the plurality of The two current sources are turned on in response to the injection pulse.

如申請專利範圍第2項所述的脈波校正電路，更包括：一第二及閘，依據該注入脈波以及該啟動訊號輸出該注入脈波至該鎖相迴路中的該電壓控制振盪器。 The pulse wave correcting circuit of claim 2, further comprising: a second gate, the output pulse wave is output to the voltage controlled oscillator in the phase locked loop according to the injection pulse wave and the start signal .

如申請專利範圍第2項所述的脈波校正電路，其中當該第一電流的電流值等於該些第二電流的電流值時，該注入脈波的該脈波寬度等於該校正後時脈訊號的該時脈週期乘以該特定比例值。 The pulse wave correcting circuit of claim 2, wherein when the current value of the first current is equal to the current value of the second currents, the pulse width of the injected pulse wave is equal to the corrected clock pulse. The clock cycle of the signal is multiplied by the particular ratio value.

如申請專利範圍第4項所述的脈波校正電路，其中該注入脈波的該脈波寬度為該鎖相迴路的一輸出訊號的週期的1/4。 The pulse wave correcting circuit of claim 4, wherein the pulse width of the injected pulse wave is 1/4 of a period of an output signal of the phase locked loop.