TWI534966B - Semiconductor structure having contact plug and method of making the same - Google Patents
Semiconductor structure having contact plug and method of making the same Download PDFInfo
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Description
本發明是關於一種具有接觸插栓的半導體結構與其形成方法，特別來說，是關於一種半導體結構，其具有的接觸插栓是以雙鑲嵌製程來形成。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor structure having a contact plug and a method of forming the same, and more particularly to a semiconductor structure having a contact plug formed in a dual damascene process.
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor,MOS)電晶體中，作為標準的閘極材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗以新的閘極材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(high-k)閘極介電層的控制電極。 In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work function metal instead of the traditional polysilicon gate for control of matching high-k gate dielectric layers. electrode.
此外，習知形成具有金屬閘極的電晶體製程後，還會在其上形成對外線路以分別電性連接電晶體的金屬閘極以及源極/汲極區，作為和對外電子訊號的輸入/輸出端。然而在習知製程中，連接源極/汲極區的對外線路通常會包含多個上下相連的接觸插栓，這使得對外電路存在著電阻過高的問題。並且，隨著元件尺寸的日益縮小， 連接源極/汲極區的接觸插栓容易和金屬閘極接觸產生短路的情況，造成元件品質下降，而成為一個需要解決的問題。 In addition, it is conventional to form a metal gate having a metal gate, and then form an external gate to electrically connect the metal gate and the source/drain region of the transistor, respectively, as input to the external electronic signal/ Output. However, in the conventional process, the external line connecting the source/drain regions usually includes a plurality of contact plugs connected up and down, which causes a problem of excessive resistance in the external circuit. And, as component sizes shrink, The contact plug connected to the source/drain region is likely to be short-circuited by contact with the metal gate, resulting in degradation of component quality, which becomes a problem to be solved.
本發明於是提供一種具有接觸插栓的半導體結構以及其形成方法，以提升整體半導體結構的電性表現。 The present invention thus provides a semiconductor structure having a contact plug and a method of forming the same to enhance the electrical performance of the overall semiconductor structure.
根據本發明的一個實施方式，本發明提供了一種具有接觸插栓的半導體結構，包含一基底、一電晶體、一第一內層介電層、一第二內層介電層以及一第一接觸插栓。電晶體設置在基底上，且電晶體包含一閘極以及一源極/汲極區。第一內層介電層設置在電晶體上，且與電晶體的閘極的一頂面齊平。第二內層介電層設置在第一內層介電層上。第一接觸插栓設置在第一內層介電層以及第二內層介電層中，第一接觸插栓包含一第一溝渠部分以及一第一介質孔部分，其中第一溝渠部分以及第一介質孔部分的一交界高於閘極的該頂面。 According to an embodiment of the present invention, a semiconductor structure having a contact plug includes a substrate, a transistor, a first inner dielectric layer, a second inner dielectric layer, and a first Contact the plug. The transistor is disposed on the substrate, and the transistor includes a gate and a source/drain region. The first inner dielectric layer is disposed on the transistor and is flush with a top surface of the gate of the transistor. The second inner dielectric layer is disposed on the first inner dielectric layer. The first contact plug is disposed in the first inner dielectric layer and the second inner dielectric layer, the first contact plug includes a first trench portion and a first dielectric hole portion, wherein the first trench portion and the first A junction of a dielectric aperture portion is higher than the top surface of the gate.
根據本發明的另外一個實施方式，本發明提供了一種形成具有接觸插栓的半導體結構的方法。首先提供一基底，接著形成一電晶體以及一第一內層介電層於基底上，其中第一內層介電層與電晶體的一閘極的一頂面齊平，使得閘極暴露出來。然後於第一內層介電層上形成一第二內層介電層。最後形成一第一接觸插栓於第二內層介電層以及第一內層介電層中，以電性連接電晶體的一源極/汲極 區，其中形成第一接觸插栓的步驟包含一第一雙鑲嵌製程。 In accordance with another embodiment of the present invention, the present invention provides a method of forming a semiconductor structure having contact plugs. First, a substrate is provided, and then a transistor and a first inner dielectric layer are formed on the substrate, wherein the first inner dielectric layer is flush with a top surface of a gate of the transistor, so that the gate is exposed. . A second inner dielectric layer is then formed on the first inner dielectric layer. Finally, a first contact plug is formed in the second inner dielectric layer and the first inner dielectric layer to electrically connect a source/drain of the transistor The zone, wherein the step of forming the first contact plug comprises a first dual damascene process.
本發明提供了一種形成接觸插栓的方法，以及一種具有此接觸插栓的半導體結構。通過一雙鑲嵌步驟來形成第一接觸插栓，不僅使第一接觸插栓不容易和金屬閘極短路，只有一層的阻障層也第一接觸插栓的電性表性更良好。此外，第一接觸插栓和第二接觸插栓中的金屬層較佳的選用金屬銅或鎢，可以有效降低電阻值而增加了電性的表現。 The present invention provides a method of forming a contact plug and a semiconductor structure having the contact plug. The first contact plug is formed by a double damascene step, which not only makes the first contact plug not easily short-circuited with the metal gate, but only one layer of the barrier layer and the first contact plug has better electrical properties. In addition, the metal layer in the first contact plug and the second contact plug is preferably made of metal copper or tungsten, which can effectively reduce the resistance value and increase the electrical performance.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。 The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.
請參考第1圖至第10圖，所繪示為本發明一種形成具有接觸插栓的半導體結構的步驟示意圖，其中第2圖是第1圖中沿著AA’切線的剖面示意圖，而第9圖是第10圖中沿著AA’切線的剖面示意圖。如第1圖與第2圖所示，首先提供一基底300，並在基底300中形成複數個淺溝渠隔離(shallow trench isolation,STI)302。基底300可以例如是矽基底(silicon substrate)、磊晶矽(epitaxial silicon substrate)、矽鍺半導體基底(silicon germanium substrate)、碳化矽基底(silicon carbide substrate)或矽覆絕緣(silicon-on-insulato,SOI)基底，但不以上述為限。接著於基底300上形成一電晶體400。電晶 體400具有一閘極402以及一源極/汲極區408。於本發明較佳實施例中，電晶體400是透過一後閘極(gate last)半導體製程而形成具有金屬閘極402的電晶體400。舉例來說，後閘極製程是先在基底300形成一虛擬閘極(圖未示)，再依序形成一側壁子406、一源極/汲極區408、一接觸洞蝕刻停止層(contact etch stop layer,CESL)304以及一第一內層介電層(inter-layer dielectric,ILD)306，接著移除虛擬閘極以形成一溝渠(圖未示)，最後在溝渠中填入一閘極介電層404以及一閘極402，然後進行一平坦化製程使得閘極402的一頂面403與第一內層介電層306齊平。於一個實施例中，如第2圖所示，閘極介電層404具有一「U型」剖面，其材質可以包含二氧化矽，亦可包含高介電常數(high-K)材料；閘極402可以包含一層或多層的金屬材質，例如包含一功函數金屬層(work function metal layer)、一阻障層(barrier layer)以及一低電阻金屬層。 Please refer to FIG. 1 to FIG. 10 , which are schematic diagrams showing the steps of forming a semiconductor structure having a contact plug according to the present invention, wherein FIG. 2 is a cross-sectional view along the line AA′ in FIG. 1 , and FIG. 9 . The figure is a schematic cross-sectional view taken along line AA' in Fig. 10. As shown in FIGS. 1 and 2, a substrate 300 is first provided, and a plurality of shallow trench isolation (STI) 302 are formed in the substrate 300. The substrate 300 may be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulato (silicon-on-insulato). SOI) substrate, but not limited to the above. A transistor 400 is then formed on the substrate 300. Electron crystal Body 400 has a gate 402 and a source/drain region 408. In a preferred embodiment of the invention, transistor 400 is formed into a transistor 400 having a metal gate 402 through a gate last semiconductor process. For example, the back gate process first forms a dummy gate (not shown) on the substrate 300, and then sequentially forms a sidewall 406, a source/drain region 408, and a contact hole etch stop layer. An etch stop layer, CESL) 304 and a first inter-layer dielectric (ILD) 306, followed by removing the dummy gate to form a trench (not shown), and finally filling a gate in the trench The pole dielectric layer 404 and a gate 402 are then subjected to a planarization process such that a top surface 403 of the gate 402 is flush with the first inner dielectric layer 306. In one embodiment, as shown in FIG. 2, the gate dielectric layer 404 has a "U-shaped" cross section, and the material may include germanium dioxide or a high dielectric constant (high-K) material; The pole 402 may comprise one or more layers of metal material, such as a work function metal layer, a barrier layer, and a low resistance metal layer.
值得注意的是，電晶體400中的各元件可以依照不同設計而具有不同的實施態樣，舉例來說，如第2圖所示，源極/汲極區408可以包含以選擇性磊晶成長(selective epitaxial growth,SEG)形成的矽化鍺(SiGe)或碳化矽(SiC)以分別適用於PMOS或NMOS電晶體，或者如第3圖所示，亦可以離子植入等方式形成源極/汲極區408a，且源極/汲極區之形狀亦可依閘極通道所需之應力而進行調整；而於另一實施例中，接觸洞蝕刻停止層304更可具有一應力(stress)，以作為一選擇性應力系統(selective strain scheme,SSS)。而於本發明另一實施例中，如第3圖所示，有別於第2圖的實施例中閘極介電層404 是以「後高介電常數層(high-k last)」製程形成(即閘極介電層404是在移除虛擬閘極之後形成)，第3圖的實施例中閘極介電層404是以「先高介電層數層(high-k first)」製程形成(即閘極介電層是在虛擬閘極之前形成)，因此閘極介電層404a是具有「-型」剖面，另一方面，第3圖的實施例中，源極/汲極區408a上亦可具有一金屬矽化物層(silicide)層409a。上述的實施方式僅為示例，本發明電晶體400可以具有各種不同實施態樣，在此不一一贅述。以下實施例將以第2圖中電晶體400的實施態樣進行描述。 It should be noted that the various components in the transistor 400 can have different implementations according to different designs. For example, as shown in FIG. 2, the source/drain regions 408 can include selective epitaxial growth. (Selective epitaxial growth, SEG) formed by bismuth telluride (SiGe) or tantalum carbide (SiC) for PMOS or NMOS transistors, respectively, or as shown in Figure 3, ion implantation or other methods can be used to form source/汲The shape of the source/drain region can also be adjusted according to the stress required by the gate channel; in another embodiment, the contact hole etch stop layer 304 can have a stress. As a selective strain scheme (SSS). In another embodiment of the present invention, as shown in FIG. 3, the gate dielectric layer 404 is different from the embodiment of FIG. The formation is performed by a "high-k last" process (ie, the gate dielectric layer 404 is formed after the dummy gate is removed). In the embodiment of FIG. 3, the gate dielectric layer 404 is formed. The "high-k first" process is formed (ie, the gate dielectric layer is formed before the dummy gate), so the gate dielectric layer 404a has a "-type" profile. On the other hand, in the embodiment of Fig. 3, the source/drain region 408a may also have a metal silicide layer 409a. The above embodiments are merely examples, and the transistor 400 of the present invention may have various implementations, which are not described herein. The following embodiments will be described with respect to an embodiment of the transistor 400 of Fig. 2.
如第4圖所述，在形成電晶體400之後，接著在基底300上全面形成一第二內層介電層308。第二內層介電層308的材質可以和第一內層介電層306的材質相同也可以不同。於一實施例中，第二內層介電層308例如是透過一化學氣相沈積(chemical vapor deposition,CVD)、旋轉塗布(spin-coating)或是任何可供形成介電材料之製程形成。此外，依蝕刻製程需要而定，第二內層介電層308可包含多層具有不同蝕刻選擇率之介電層，例如，底層可為蝕刻率較低之介電層，頂層可為蝕刻率較高之介電層，以利於蝕刻時先選擇性停在特定膜層。在形成第二內層介電層308後，接著利用一微影暨蝕刻製程，於源極/汲極區408上的第二內層介電層308中形成一溝渠(trench)310。 As shown in FIG. 4, after the transistor 400 is formed, a second inner dielectric layer 308 is then formed over the substrate 300. The material of the second inner dielectric layer 308 may be the same as or different from the material of the first inner dielectric layer 306. In one embodiment, the second inner dielectric layer 308 is formed, for example, by a chemical vapor deposition (CVD), spin-coating, or any process for forming a dielectric material. In addition, depending on the needs of the etching process, the second inner dielectric layer 308 may comprise a plurality of dielectric layers having different etching selectivity. For example, the bottom layer may be a dielectric layer having a lower etching rate, and the top layer may be an etching rate. The high dielectric layer is used to selectively stop at a specific film layer during etching. After forming the second inner dielectric layer 308, a trench 310 is formed in the second inner dielectric layer 308 on the source/drain region 408 by a lithography and etching process.
如第5圖所示，隨後再利用另一微影暨蝕刻製程，於溝渠310的底面中向下形成一介質孔(via)312，以暴露出源極/汲極區408，介 質孔312的寬度較佳小於溝渠310的寬度。值得注意的是，此時溝渠310的底面(即溝渠310與介質孔312的交界處)還是位於第二內層介電層308中。 As shown in FIG. 5, another dielectric etch process is subsequently used to form a via 312 downwardly in the bottom surface of the trench 310 to expose the source/drain region 408. The width of the aperture 312 is preferably less than the width of the trench 310. It should be noted that the bottom surface of the trench 310 (ie, the interface between the trench 310 and the dielectric hole 312) is still located in the second inner dielectric layer 308.
如第6圖所示，接著進行一自對準金屬矽化物(salicide)製程，在介質孔312所暴露的源極/汲極區408上形成一金屬矽化物層409，例如是一矽化鎳(NiSi)層。而於本發明之另一實施例中，若是依照第3圖的實施態樣，即金屬矽化物層409a已經形成在源極/汲極區408a上，則此形成金屬矽化物的步驟可以省略。 As shown in FIG. 6, a self-aligned metal salicide process is then performed to form a metal telluride layer 409 on the source/drain region 408 exposed by the dielectric via 312, such as a nickel telluride ( NiSi) layer. In another embodiment of the present invention, if the metal telluride layer 409a has been formed on the source/drain region 408a in accordance with the embodiment of FIG. 3, the step of forming the metal halide may be omitted.
接著如第7圖所示，在溝渠310以及介質孔312中依序填入一第一阻障層314以及一第一金屬層316，其中第一阻障層314會共形地沿著溝渠310以及介質孔312的表面形成，而第一金屬層316則會完全填滿溝渠310以及介質孔312。於本發明之一實施例中，第一阻障層314例如是鈦(Ti)或氮化鈦(TiN)或是鉭化鈦(TaN)且可包含多層不同金屬材料，例如鈦/氧化鈦，而第一金屬層316則包含各種低電阻金屬材料，例如是鋁(Al)、鈦(Ti)、鉭(Ta)、鎢(W)、鈮(Nb)、鉬(Mo)、銅(Cu)等材料，較佳是鎢或銅，最佳是鎢，以和金屬矽化物層409或下方的源極/汲極區408形成適當的歐姆接觸(Ohmic contact)。在形成第一金屬層316後，可進行一平坦化(planarization)步驟，使得第一金屬層316、第一阻障層314與第二內層介電層308齊平。 Then, as shown in FIG. 7 , a first barrier layer 314 and a first metal layer 316 are sequentially filled in the trench 310 and the dielectric hole 312 , wherein the first barrier layer 314 conformally follows the trench 310 . The surface of the dielectric hole 312 is formed, and the first metal layer 316 completely fills the trench 310 and the dielectric hole 312. In one embodiment of the present invention, the first barrier layer 314 is, for example, titanium (Ti) or titanium nitride (TiN) or titanium telluride (TaN) and may comprise multiple layers of different metal materials, such as titanium/titanium oxide. The first metal layer 316 comprises various low-resistance metal materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu). The material, preferably tungsten or copper, is preferably tungsten, to form an appropriate ohmic contact with the metal telluride layer 409 or the underlying source/drain regions 408. After forming the first metal layer 316, a planarization step may be performed such that the first metal layer 316, the first barrier layer 314, and the second inner dielectric layer 308 are flush.
如第8圖所示，於第二內層介電層308上再全面形成一犧牲層318，其材質可以和第二內層介電層308相同也可以不同。接著再利用另一微影暨蝕刻製程在犧牲層318以及第二內層介電層308中形成一開口320，以暴露出電晶體400中的閘極402。 As shown in FIG. 8 , a sacrificial layer 318 is further formed on the second inner dielectric layer 308 , and the material thereof may be the same as or different from the second inner dielectric layer 308 . An opening 320 is then formed in the sacrificial layer 318 and the second inner dielectric layer 308 by another lithography and etching process to expose the gate 402 in the transistor 400.
接著如第9圖與第10圖所示，在開口320中依序填入一第二阻障層322以及一第二金屬層324，其中第二阻障層322會共形地沿著開口320的表面形成，而第二金屬層324則會完全填滿開口320。於本發明之一實施例中，第二阻障層322例如是鈦(Ti)或氮化鈦或是鉭化鈦且可包含多層不同金屬材料，例如鈦/氧化鈦，而第二金屬層324則包含各種低電阻金屬材料，例如是鋁、鈦、鉭、鎢、鈮、鉬、銅等材料，較佳是鎢或銅，最佳是銅，以降低和下方的閘極402之間的電阻值。最後，進行一平坦化步驟，移除全部的犧牲層318、部分的第二阻障層322以及部分的第二金屬層324，使得第二金屬層324與第二內層介電層308齊平。而於本發明另一實施例中，亦可省略形成犧牲層318的步驟，而在平坦化第一金屬層316與第一阻障層314之後，直接在第二內層介電層308中形成開口320而直接填入第二阻障層322與第二金屬層324。 Then, as shown in FIG. 9 and FIG. 10 , a second barrier layer 322 and a second metal layer 324 are sequentially filled in the opening 320 , wherein the second barrier layer 322 conformally follows the opening 320 . The surface is formed while the second metal layer 324 will completely fill the opening 320. In one embodiment of the present invention, the second barrier layer 322 is, for example, titanium (Ti) or titanium nitride or titanium telluride and may comprise multiple layers of different metal materials, such as titanium/titanium oxide, and the second metal layer 324. It comprises various low-resistance metal materials, such as aluminum, titanium, tantalum, tungsten, tantalum, molybdenum, copper, etc., preferably tungsten or copper, preferably copper, to reduce the electrical resistance between the lower and lower gates 402. value. Finally, a planarization step is performed to remove all of the sacrificial layer 318, a portion of the second barrier layer 322, and a portion of the second metal layer 324 such that the second metal layer 324 is flush with the second inner dielectric layer 308. . In another embodiment of the present invention, the step of forming the sacrificial layer 318 may be omitted, and after the first metal layer 316 and the first barrier layer 314 are planarized, directly formed in the second inner dielectric layer 308. The second barrier layer 322 and the second metal layer 324 are directly filled in the opening 320.
通過前述的步驟，即可在第一內層介電層306以及第二內層介電層308中形成一第一接觸插栓317以及一第二接觸插栓325(合稱metal 0)。第一接觸插栓317設置在第一內層介電層306與第二內層介電層308中，且包含一第一溝渠部分317a與一第一介質孔部分 317b，並通過金屬矽化物層409電性連接下方的源極/汲極區408。第二接觸插栓325設置在第二內層介電層308中，並電性連接下方的閘極402。 Through the foregoing steps, a first contact plug 317 and a second contact plug 325 (collectively referred to as metal 0) can be formed in the first inner dielectric layer 306 and the second inner dielectric layer 308. The first contact plug 317 is disposed in the first inner dielectric layer 306 and the second inner dielectric layer 308, and includes a first trench portion 317a and a first dielectric hole portion. 317b, and electrically connected to the underlying source/drain region 408 through the metal telluride layer 409. The second contact plug 325 is disposed in the second inner dielectric layer 308 and electrically connected to the lower gate 402.
後續，進行一金屬內連線製程，在第二內層介電層308上形成一金屬內連線系統(metal interconnection system)(圖未示)，其包含複數層金屬層間介電層(inter-metal dielectric layer,IMD layer)以及複數層金屬層(即所謂的metal 1,metal 2...等)，以作為電晶體400對外訊號的輸入/輸出。 Subsequently, a metal interconnect process is performed to form a metal interconnection system (not shown) on the second inner dielectric layer 308, which includes a plurality of metal interlayer dielectric layers (inter- A metal dielectric layer (IMD layer) and a plurality of metal layers (so-called metal 1, metal 2, etc.) are used as input/output of the external signal of the transistor 400.
本發明其中一個特點在於，第一接觸插栓317是透過一溝渠優先(trench first)之雙鑲嵌(dual damascene)製程來形成，即先形成寬度較大的溝渠310(第4圖)，接著再形成寬度較小的介質孔312(第5圖)，最後再填入第一阻障層314以及第一金屬層316(第7圖)。相較於習知技術是分別在第一內層介電層306與第二內層介電層308中各自形成一個接觸插栓，其具有各自的阻障層以及金屬層，本發明使用雙鑲嵌製程的其中一個好處在於：第一接觸插栓317僅具有一層第一阻層障314以及一層第一金屬層316，而第一阻障層314是形成在第一接觸插栓317的表面，即第一溝渠部分317a與第一介質孔部分317b之間並沒有第一阻障層314，故可以具有較低的電阻。使用雙鑲嵌製程另外一個好處在於，可以形成「上大下小」的第一接觸插栓317，即上方較寬的第一溝渠部分317a以及下方較窄的第一介質孔部分317b，且兩者的交界位在第二內層介電層308中 (即第一溝渠部分317a底部與閘極402的頂面403還有一垂直高度h)，這使得第一接觸插栓317向下不容易和閘極402產生短路，向上也可以增加接觸面積，大幅增加了製程寬裕度(process window)。而本領域的通常知識者都可以了解，於本發明其他實施例中，第一接觸插栓317也可以利用其他雙鑲嵌製程來形成，例如是「介質孔優先(via first)」(先形成介質孔再形成溝渠)或「部份介質孔優先(partial-via-first)」等的方式。 One of the features of the present invention is that the first contact plug 317 is formed by a trench first dual damascene process, that is, a trench 310 having a larger width is formed first (Fig. 4), and then A dielectric hole 312 having a small width is formed (Fig. 5), and finally a first barrier layer 314 and a first metal layer 316 (Fig. 7) are filled. Compared with the prior art, a contact plug is formed in each of the first inner dielectric layer 306 and the second inner dielectric layer 308, respectively, having a respective barrier layer and a metal layer. The present invention uses dual damascene. One of the advantages of the process is that the first contact plug 317 has only one first barrier layer 314 and one first metal layer 316, and the first barrier layer 314 is formed on the surface of the first contact plug 317, ie There is no first barrier layer 314 between the first trench portion 317a and the first dielectric via portion 317b, and thus may have a lower resistance. Another advantage of using the dual damascene process is that a first contact plug 317 of "upper and lower" can be formed, that is, a wider first trench portion 317a above and a narrower first dielectric hole portion 317b, and both The junction is in the second inner dielectric layer 308 (ie, the bottom of the first trench portion 317a and the top surface 403 of the gate 402 have a vertical height h), which makes the first contact plug 317 not easy to short-circuit with the gate 402, and the contact area can be increased upwards. Increased process window. It can be understood by those skilled in the art that in other embodiments of the present invention, the first contact plug 317 can also be formed by using other dual damascene processes, such as "via first" (first forming medium) Holes form trenches or "partial-via-first".
此外，前述實施例是先形成電連接電晶體400之源極/汲極區408的第一接觸插栓317後(第5圖至第7圖)，再形成電連接電晶體400之閘極402的第二接觸插栓325(第8圖至第9圖)，而於本發明另一實施例中，亦可先形成第二接觸插栓325後，再形成第一接觸插栓317。而於本發明另外一個實施例中，第二接觸插栓325也可以透過雙鑲嵌的製程來形成，即第二接觸插栓325也可以具有一第二溝渠部分(圖未示)以及一第二介質孔部分(圖未示)。 In addition, the foregoing embodiment is to form the first contact plug 317 of the source/drain region 408 of the transistor 400 (FIG. 5 to FIG. 7), and then form the gate 402 of the electrical connection transistor 400. The second contact plug 325 (Fig. 8 to Fig. 9), and in another embodiment of the present invention, the second contact plug 325 may be formed first, and then the first contact plug 317 is formed. In another embodiment of the present invention, the second contact plug 325 can also be formed by a dual damascene process, that is, the second contact plug 325 can also have a second trench portion (not shown) and a second Media hole part (not shown).
由於第一接觸插栓317與第二接觸插栓325係分別利用不同的製程先後分別製得，因此在本發明中，構成第一接觸插栓317之第一阻障層314及第一金屬層316的材料可以相同、部分相同或完全不同於構成第一接觸插栓317之第二阻障層322及第二金屬層324的材料。 Since the first contact plug 317 and the second contact plug 325 are respectively manufactured by different processes, respectively, in the present invention, the first barrier layer 314 and the first metal layer constituting the first contact plug 317 are formed. The material of 316 may be the same, partially identical, or completely different than the material of the second barrier layer 322 and the second metal layer 324 that make up the first contact plug 317.
如第9圖所示，本發明提供了一種具有接觸插栓的半導體結 構，包含一基底300、一電晶體400、一第一內層介電層306、一第二內層介電層308、一第一接觸插栓317以及一第二接觸插栓325。電晶體400設置在基底300上，且電晶體300包含一閘極402以及一源極/汲極區408。第一內層介電層306設置在電晶體400上，且與電晶體400的閘極402的一頂面403齊平。第二內層介電層308設置在第一內層介電層306上。第一接觸插栓317設置在第一內層介電層306以及第二內層介電層308中，第一接觸插栓317包含一第一溝渠部分317a以及一第一介質孔部分317b，其中第一溝渠部分317a以及第一介質孔部分317b的一交界高於閘極402的頂面403。 As shown in FIG. 9, the present invention provides a semiconductor junction having a contact plug The structure comprises a substrate 300, a transistor 400, a first inner dielectric layer 306, a second inner dielectric layer 308, a first contact plug 317 and a second contact plug 325. The transistor 400 is disposed on the substrate 300, and the transistor 300 includes a gate 402 and a source/drain region 408. The first inner dielectric layer 306 is disposed on the transistor 400 and is flush with a top surface 403 of the gate 402 of the transistor 400. A second inner dielectric layer 308 is disposed on the first inner dielectric layer 306. The first contact plug 317 is disposed in the first inner dielectric layer 306 and the second inner dielectric layer 308. The first contact plug 317 includes a first trench portion 317a and a first dielectric hole portion 317b. A junction of the first trench portion 317a and the first dielectric aperture portion 317b is higher than the top surface 403 of the gate 402.
綜上而言，本發明提供了一種形成具有接觸插栓的半導體結構以及其形成方法。通過一雙鑲嵌步驟來形成第一接觸插栓，不僅使第一接觸插栓不容易和金屬的閘極短路，只有一層阻障層的第一接觸插栓的電性表性更良好。此外，第一接觸插栓和第二接觸插栓中的金屬層較佳的選用金屬銅或鎢，可以有效降低電阻值而增加了電性的表現。 In summary, the present invention provides a semiconductor structure having a contact plug and a method of forming the same. The first contact plug is formed by a double damascene step, which not only makes the first contact plug not easily short-circuit with the metal gate, but only the first contact plug of one layer of the barrier layer has better electrical properties. In addition, the metal layer in the first contact plug and the second contact plug is preferably made of metal copper or tungsten, which can effectively reduce the resistance value and increase the electrical performance.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
300‧‧‧基底 300‧‧‧Base
302‧‧‧淺溝渠隔離 302‧‧‧Shallow trench isolation
304‧‧‧接觸洞蝕刻停止層 304‧‧‧Contact hole etch stop layer
306‧‧‧第一內層介電層 306‧‧‧First inner dielectric layer
308‧‧‧第二內層介電層 308‧‧‧Second inner dielectric layer
310‧‧‧溝渠 310‧‧‧ Ditch
312‧‧‧介質孔 312‧‧‧Medium hole
314‧‧‧第一阻障層 314‧‧‧First barrier layer
316‧‧‧第一金屬層 316‧‧‧First metal layer
317‧‧‧第一接觸插栓 317‧‧‧First contact plug
317a‧‧‧第一溝渠部分 317a‧‧‧The first ditch section
317b‧‧‧第一介質孔部分 317b‧‧‧First media hole section
318‧‧‧犧牲層 318‧‧‧ sacrificial layer
320‧‧‧開口 320‧‧‧ openings
322‧‧‧第二阻障層 322‧‧‧second barrier layer
324‧‧‧第二金屬層 324‧‧‧Second metal layer
325‧‧‧第二接觸插栓 325‧‧‧Second contact plug
400‧‧‧電晶體 400‧‧‧Optoelectronics
402‧‧‧閘極 402‧‧‧ gate
403‧‧‧頂面 403‧‧‧ top
404‧‧‧閘極介電層 404‧‧‧gate dielectric layer
406‧‧‧側壁子 406‧‧‧ Sidewall
408‧‧‧源極/汲極區 408‧‧‧Source/Bungee Area
408a‧‧‧源極/汲極區 408a‧‧‧Source/Bungee Area
409‧‧‧金屬矽化物層 409‧‧‧metal telluride layer
409a‧‧‧金屬矽化物層 409a‧‧‧metal telluride layer
第1圖至第10圖所示為本發明一種形成具有接觸插栓的半導體結構的步驟示意圖。 1 to 10 are schematic views showing the steps of forming a semiconductor structure having a contact plug according to the present invention.
300‧‧‧基底 300‧‧‧Base
302‧‧‧淺溝渠隔離 302‧‧‧Shallow trench isolation
304‧‧‧接觸洞蝕刻停止層 304‧‧‧Contact hole etch stop layer
306‧‧‧第一內層介電層 306‧‧‧First inner dielectric layer
308‧‧‧第二內層介電層 308‧‧‧Second inner dielectric layer
314‧‧‧第一阻障層 314‧‧‧First barrier layer
316‧‧‧第一金屬層 316‧‧‧First metal layer
317‧‧‧第一接觸插栓 317‧‧‧First contact plug
317a‧‧‧第一溝渠部分 317a‧‧‧The first ditch section
317b‧‧‧第一介質孔部分 317b‧‧‧First media hole section
322‧‧‧第二阻障層 322‧‧‧second barrier layer
324‧‧‧第二金屬層 324‧‧‧Second metal layer
325‧‧‧第二接觸插栓 325‧‧‧Second contact plug
400‧‧‧電晶體 400‧‧‧Optoelectronics
402‧‧‧閘極 402‧‧‧ gate
403‧‧‧頂面 403‧‧‧ top
404‧‧‧閘極介電層 404‧‧‧gate dielectric layer
406‧‧‧側壁子 406‧‧‧ Sidewall
408‧‧‧源極/汲極區 408‧‧‧Source/Bungee Area
409‧‧‧金屬矽化物層 409‧‧‧metal telluride layer
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