TWI533619B

TWI533619B - Time-to-digital converter and operation method thereof

Info

Publication number: TWI533619B
Application number: TW103119911A
Authority: TW
Inventors: 李鎮宜
Original assignee: 華邦電子股份有限公司
Priority date: 2014-06-09
Filing date: 2014-06-09
Publication date: 2016-05-11
Also published as: TW201547212A

Description

時間數位轉換器及其運作方法 Time digital converter and its operation method

本發明是有關於一種資料轉換器及其運作方法，且特別是有關於一種時間數位轉換器及其運作方法。 The present invention relates to a data converter and a method of operating the same, and more particularly to a time digital converter and method of operating the same.

物聯網(Internet of Things，IOT)是一個基於網際網路、傳統電信網等信息承載體，讓所有能夠被獨立定址的普通物理對象實現互聯互通的網路，其中物聯網一般為無線網路。換言之，可把所有物品通過射頻識別等信息感測設備與互聯網連接起來，以實現智能化識別和管理。 The Internet of Things (IOT) is an information carrier based on the Internet, a traditional telecommunication network, and the like. All Internet objects that can be independently addressed are interconnected. The Internet of Things is generally a wireless network. In other words, all items can be connected to the Internet through information sensing devices such as radio frequency identification for intelligent identification and management.

在物聯網中，可透過無線感知網路測得週遭環境變化狀況的無線技術，其中無線感知技術是透過感知器(Sensor)和無線網路的結合，以提供週遭環境變化所對應的資料，讓遠端的人員/裝置透過這些資料判斷環境發生的狀況。並且，隨著無線通訊技術的發展，透過信號的致能時間長度來傳送資料的技術逐漸成熟且較不受週遭雜訊的干擾，因此如何使信號的致能時間轉換為數位資料則成為發展物聯網的一個重點技術。 In the Internet of Things, wireless technology that measures the environmental changes around a wireless sensing network. Wireless sensing technology is a combination of a sensor and a wireless network to provide information about changes in the surrounding environment. The remote personnel/devices use this information to determine the state of the environment. Moreover, with the development of wireless communication technology, the technology for transmitting data through the length of time of signal generation is mature and less susceptible to interference from surrounding noise. Therefore, how to convert the enabling time of signals into digital data becomes a development. A key technology for networking.

本發明提供一種時間數位轉換器及其運作方法，可自行調整時間轉換的解析度，以提高時間數位轉換器的通用性及適用性。 The invention provides a time digital converter and a method for operating the same, which can adjust the resolution of time conversion to improve the versatility and applicability of the time digital converter.

本發明的時間數位轉換器，用以轉換一時間信號的致能時間為一輸出資料，包括一比較單元、一數位鎖相迴路及一計數單元。比較單元用以比較時間信號的致能時間與一最小時間，以提供一比較結果。數位鎖相迴路接收一參考時脈信號以提供一計數時脈信號。計數單元接收計數時脈信號，以依據計數時脈信號及時間信號進行計數而提供一計數結果。當時間信號的致能時間大於最小時間時，依據比較結果輸出計數結果作為輸出資料。 The time digital converter of the present invention converts the enable time of a time signal into an output data, and includes a comparison unit, a digital phase lock loop and a counting unit. The comparison unit is configured to compare the enable time of the time signal with a minimum time to provide a comparison result. The digital phase locked loop receives a reference clock signal to provide a count clock signal. The counting unit receives the counting clock signal to provide a counting result according to counting the clock signal and the time signal. When the enable time of the time signal is greater than the minimum time, the count result is output as the output data according to the comparison result.

本發明的時間數位轉換器的運作方法，用以轉換一時間信號的致能時間為一輸出資料，包括下列步驟。透過一數位鎖相迴路依據一參考時脈信號提供一計數時脈信號。透過一計數單元依據計數時脈信號及時間信號進行計數而提供一計數結果。透過一比較單元比較時間信號的致能時間與一最小時間。當時間信號的致能時間大於最小時間時，依據比較結果輸出計數結果作為輸出資料。 The operation method of the time digital converter of the present invention is used to convert the enable time of a time signal into an output data, including the following steps. A count clock signal is provided by a digital phase locked loop according to a reference clock signal. A counting result is provided by counting by the counting unit according to the counting clock signal and the time signal. Comparing the enable time of the time signal with a minimum time through a comparison unit. When the enable time of the time signal is greater than the minimum time, the count result is output as the output data according to the comparison result.

基於上述，本發明實施例的時間數位轉換器及其運作方法，數位鎖相迴路依據一參考時脈信號提供一計數時脈信號，而計數單元依據計數時脈信號及時間信號進行計數而提供一計數結果，並且在時間信號的致能時間大於最小時間時，輸出計數結果作為輸出資料。藉此，可透過數位鎖相迴路調整輸出資料的解析度，以提高時間數位轉換器的通用性及適用性。 Based on the above, the time digit converter and the method for operating the same according to the embodiment of the present invention, the digital phase locked loop provides a count clock signal according to a reference clock signal, and the counting unit provides a count according to the count clock signal and the time signal. Counting knot If the enable time of the time signal is greater than the minimum time, the count result is output as the output data. Thereby, the resolution of the output data can be adjusted through the digital phase locked loop to improve the versatility and applicability of the time digital converter.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

100、200‧‧‧時間數位轉換器 100, 200‧‧‧ time digital converter

110、210‧‧‧比較單元 110, 210‧‧‧ comparison unit

120、220‧‧‧數位鎖相迴路 120, 220‧‧‧ digital phase-locked loop

130、230‧‧‧計數單元 130, 230‧‧‧counting unit

240‧‧‧多工器 240‧‧‧Multiplexer

CDIT‧‧‧區隔指定代碼 CDIT‧‧‧Division code

CKCT‧‧‧計數時脈信號 CKCT‧‧‧ count clock signal

CKR‧‧‧參考時脈信號 CKR‧‧‧ reference clock signal

CPR1、CPR2‧‧‧比較結果 Comparison of CPR1, CPR2‧‧‧

CTR1、CTR3‧‧‧計數結果 CTR1, CTR3‧‧‧ count results

CTR2‧‧‧參考計數結果 CTR2‧‧‧ reference count results

Dout‧‧‧輸出資料 Dout‧‧‧Output data

ECT‧‧‧計數致能信號 ECT‧‧‧counting enable signal

PE1、PE2‧‧‧致能時間 PE1, PE2‧‧‧Enable time

SCR‧‧‧比較參考信號 SCR‧‧‧ comparison reference signal

STE‧‧‧時間信號 STE‧‧‧ time signal

Tmin‧‧‧最小時間 Tmin‧‧‧Minimum time

VTM‧‧‧最小時間計數值 VTM‧‧‧minimum time count

S310、S320、S330、S340‧‧‧步驟 S310, S320, S330, S340‧‧‧ steps

圖1為依據本發明一實施例的時間數位轉換器的系統示意圖。 1 is a system diagram of a time digital converter in accordance with an embodiment of the present invention.

圖2為依據本發明另一實施例的時間數位轉換器的系統示意圖。 2 is a system diagram of a time digital converter in accordance with another embodiment of the present invention.

圖3為依據本發明一實施例的時間數位轉換器的運作方法的流程圖。 3 is a flow chart of a method of operating a time digital converter in accordance with an embodiment of the present invention.

圖1為依據本發明一實施例的時間數位轉換器的系統示意圖。請參照圖1，在本實施例中，時間數位轉換器100包括比較單元110、數位鎖相迴路120及計數單元130。比較單元100接收時間信號STE及表示最小時間Tmin的比較參考信號SCR，並且用以比較時間信號STE的致能時間PE1與最小時間Tmin以提供比較結果CPR1。在本實施例中，比較參考信號SCR的致能時間 PE2設定為等於最小時間Tmin，因此比較單元100可比較致能時間PE1是否大於PE2而決定比較結果CPR1的電壓準位。並且，比較單元100可將致能時間PE1及PE2轉換為對應的電壓準位或數位資料，以便於進行比對，但本發明實施例不以此為限。 1 is a system diagram of a time digital converter in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the present embodiment, the time digit converter 100 includes a comparison unit 110 , a digital phase locked loop 120 , and a counting unit 130 . The comparison unit 100 receives the time signal STE and the comparison reference signal SCR indicating the minimum time Tmin, and is used to compare the enable time PE1 of the time signal STE with the minimum time Tmin to provide a comparison result CPR1. In this embodiment, the enable time of the reference signal SCR is compared. PE2 is set equal to the minimum time Tmin, so the comparison unit 100 can compare whether the enable time PE1 is greater than PE2 and determine the voltage level of the comparison result CPR1. In addition, the comparison unit 100 can convert the enable times PE1 and PE2 into corresponding voltage levels or digital data to facilitate the comparison, but the embodiment of the present invention is not limited thereto.

當時間信號STE的致能時間PE2小於等於最小時間Tmin時，表示時間信號STE未傳送資料或傳送的資料可能是雜訊所引起的，因此比較單元110可輸出為禁能準位(例如為低電壓準位)的比較結果CPR1，以避免提供不正確的輸出資料Dout。當時間信號SET的致能時間PE2大於最小時間Tmin時，表示時間信號STE所傳送資料是有義意的，因此比較單元110會輸出時間信號STE作為比較結果CPR1，亦即比較結果CPR1的波形會相同於時間信號STE。 When the enable time PE2 of the time signal STE is less than or equal to the minimum time Tmin, it indicates that the data transmitted by the time signal STE or the transmitted data may be caused by noise, so the comparison unit 110 may output the disable level (for example, low). The comparison of the voltage levels) results in CPR1 to avoid providing incorrect output data Dout. When the enable time PE2 of the time signal SET is greater than the minimum time Tmin, it indicates that the data transmitted by the time signal STE is meaningful, so the comparison unit 110 outputs the time signal STE as the comparison result CPR1, that is, the waveform of the comparison result CPR1 Same as time signal STE.

數位鎖相迴路120耦接比較單元110以接收比較結果CPR1，且輸出比較結果CPR1作為計數致能信號ECT，亦即計數致能信號ECT的波形會相同於輸出比較結果CPR1。並且，數位鎖相迴路120接收參考時脈信號CKR以提供計數時脈信號CKCT，亦即計數時脈信號CKCT的頻率正比於參考時脈信號CKR的頻率。其中，參考時脈信號CKR的頻率可不同於計數時脈信號CKCT的頻率，並且計數時脈信號CKCT的頻率可高於參考時脈信號CKR的頻率，但本發明實施例不以此為限。 The digital phase-locked loop 120 is coupled to the comparison unit 110 to receive the comparison result CPR1, and outputs the comparison result CPR1 as the count enable signal ECT, that is, the waveform of the count enable signal ECT is the same as the output comparison result CPR1. Moreover, the digital phase locked loop 120 receives the reference clock signal CKR to provide the count clock signal CKCT, that is, the frequency of the count clock signal CKCT is proportional to the frequency of the reference clock signal CKR. The frequency of the reference clock signal CKR may be different from the frequency of the clock signal CKCT, and the frequency of the clock signal CKCT may be higher than the frequency of the reference clock signal CKR, but the embodiment of the present invention is not limited thereto.

計數單元130耦接數位鎖相迴路120，以接收計數致能信號ECT及計數時脈信號CKCT，並且依據計數致能信號ECT計數計數時脈信號CKCT的脈波數以產生計數結果CTR1。此時，由於計數致能信號ECT的波形會相同於時間信號STE，因此計數結果CTR1會對應時間信號STE的致能時間PE1。在本實施例中，由於計數單元130的計數結果CTR1已經是數位資料，因此計數單元130可直接輸出且鎖定計數結果CTR1作為輸出資料Dout。藉此，時間數位轉換器100可轉換時間信號STE的致能時間PE1為輸出資料Dout，並且可透過數位鎖相迴路120的頻率調整輸出資料Dout的解析度，以提高時間數位轉換器100的通用性及適用性。 The counting unit 130 is coupled to the digital phase locked loop 120 to receive the count enable signal ECT and the count clock signal CKCT, and is counted according to the count enable signal ECT. The number of pulses of the clock signal CKCT is counted to generate a count result CTR1. At this time, since the waveform of the count enable signal ECT will be the same as the time signal STE, the count result CTR1 will correspond to the enable time PE1 of the time signal STE. In the present embodiment, since the counting result CTR1 of the counting unit 130 is already digital data, the counting unit 130 can directly output and lock the counting result CTR1 as the output data Dout. Thereby, the enable time PE1 of the time digital converter 100 convertible time signal STE is the output data Dout, and the resolution of the output data Dout can be adjusted by the frequency of the digital phase locked loop 120 to improve the generality of the time digital converter 100. Sex and applicability.

綜合上述，在時間數位轉換器100中，比較單元110可比較時間信號STE的致能時間PE1與最小時間Tmin，以提供比較結果CPR1；數位鎖相迴路120可接收參考時脈信號CKR以提供計數時脈信號CKCT；計數單元130會接收計數時脈信號CKCT，以依據時間信號SET對計數時脈信號CKCT的時脈進行計數而提供計數結果CTR1。並且，當時間信號STE的致能時間PE1大於最小時間Tmin時，數位鎖相迴路120及計數單元130會依據比較結果CPR1進行計數而提供計數結果CTR1作為輸出資料Dout；當時間信號STE的致能時間PE1小於等於最小時間Tmin時，數位鎖相迴路120及計數單元130不會被啟動，亦即不會提供輸出資料Dout。 In summary, in the time digital converter 100, the comparison unit 110 can compare the enable time PE1 and the minimum time Tmin of the time signal STE to provide a comparison result CPR1; the digital phase locked loop 120 can receive the reference clock signal CKR to provide a count. The clock signal CKCT; the counting unit 130 receives the count clock signal CKCT to count the clock of the count clock signal CKCT according to the time signal SET to provide the count result CTR1. Moreover, when the enable time PE1 of the time signal STE is greater than the minimum time Tmin, the digital phase-locked loop 120 and the counting unit 130 perform counting according to the comparison result CPR1 to provide the counting result CTR1 as the output data Dout; when the time signal STE is enabled When the time PE1 is less than or equal to the minimum time Tmin, the digital phase locked loop 120 and the counting unit 130 are not activated, that is, the output data Dout is not provided.

在本實施例中，比較參考信號SCR例如是由數位鎖相迴路120所提供，亦即比較參考信號SCR可隨著參考時脈信號CKR而變動，但本發明實施例不以為限。 In the present embodiment, the comparison reference signal SCR is provided by the digital phase-locked loop 120, for example, the comparison reference signal SCR may vary with the reference clock signal CKR, but the embodiment of the present invention is not limited thereto.

圖2為依據本發明另一實施例的時間數位轉換器的系統示意圖。請參照圖2，在本實施例中，時間數位轉換器200包括比較單元210、數位鎖相迴路220、計數單元230及多工器240，其中比較單元210的比較結果CPR2預設為禁能準位(例如為低電壓準位)。 2 is a system diagram of a time digital converter in accordance with another embodiment of the present invention. Referring to FIG. 2, in the embodiment, the time digit converter 200 includes a comparison unit 210, a digital phase lock loop 220, a counting unit 230, and a multiplexer 240. The comparison result CPR2 of the comparison unit 210 is preset to be disabled. Bit (for example, low voltage level).

時間數位轉換器200預設為時間偵測模式(對應比較結果CPR2的禁能準位)，以偵測時間信號STE的致能時間PE1是否具有義意。當時間信號STE的致能時間PE1具有意義時(對應比較結果CPR2的致能準位，例如高電壓準位)，則時間數位轉換器200切換為資料轉換模式，以將時間信號STE的致能時間PE1轉換為輸出資料Dout。 The time digital converter 200 is preset to a time detection mode (corresponding to the disable level of the comparison result CPR2) to detect whether the enable time PE1 of the time signal STE has meaning. When the enable time PE1 of the time signal STE has a meaning (corresponding to the enable level of the comparison result CPR2, for example, a high voltage level), the time digital converter 200 switches to the data conversion mode to enable the time signal STE. The time PE1 is converted into the output data Dout.

數位鎖相迴路220接收參考時脈信號CKR及區隔指定代碼CDIT，以依據參考時脈信號CKR及產生計數時脈信號CKCT，亦即計數時脈信號CKCT的頻率相關於參考時脈信號CKR的頻率及區隔指定代碼CDIT。其中，區隔指定代碼CDIT用以設定數位鎖相迴路220的頻率增益值，亦即數位鎖相迴路220的頻率增益值越高，計數時脈信號CKCT的脈波的時間間隔越短，數位鎖相迴路220的頻率增益值越低，計數時脈信號CKCT的脈波的時間間隔越長，此可依據本領域通常知識者自行設定，本發明實施例不以此為限。 The digital phase locked loop 220 receives the reference clock signal CKR and the interval designation code CDIT to generate a count clock signal CKCT according to the reference clock signal CKR, that is, the frequency of the count clock signal CKCT is related to the reference clock signal CKR. The frequency and the specified code CDIT. The interval designation code CDIT is used to set the frequency gain value of the digital phase locked loop 220, that is, the higher the frequency gain value of the digital phase locked loop 220, the shorter the time interval of the pulse wave of the count clock signal CKCT, the digital lock The lower the frequency gain value of the phase loop 220, the longer the time interval of the pulse wave of the clock signal CKCT is counted, which can be set by a person skilled in the art, and the embodiment of the present invention is not limited thereto.

多工器240接收參考時脈信號CKR，並且耦接數位鎖相迴路220以接收計數時脈信號CKCT，多工器240依據比較單元 210的比較結果CPR2提供參考時脈信號CKR或計數時脈信號CKCT至計數單元230。 The multiplexer 240 receives the reference clock signal CKR, and is coupled to the digital phase locked loop 220 to receive the count clock signal CKCT, and the multiplexer 240 according to the comparison unit The comparison result CPR2 of 210 provides a reference clock signal CKR or a count clock signal CKCT to the counting unit 230.

在時間數位轉換器200為時間偵測模式時，多工器240受控於比較結果CPR2傳送參考時脈信號CKR至計數單元230，而計數單元230在接收參考時脈信號CKR及時間信號STE後，會依據參考時脈信號CKR及時間信號STE進行計數以提供參考計數結果CTR2。比較單元210耦接計數單元230且接收時間信號STE及參考計數結果CTR2，比較單元210比較參考計數結果CTR2與對應最小時間Tmin的最小時間計數值VTM以提供比較結果CPR2。 When the time digit converter 200 is in the time detection mode, the multiplexer 240 controls the comparison result CPR2 to transmit the reference clock signal CKR to the counting unit 230, and the counting unit 230 receives the reference clock signal CKR and the time signal STE. The count is based on the reference clock signal CKR and the time signal STE to provide a reference count result CTR2. The comparison unit 210 is coupled to the counting unit 230 and receives the time signal STE and the reference count result CTR2, and the comparison unit 210 compares the reference count result CTR2 with the minimum time count value VTM of the corresponding minimum time Tmin to provide a comparison result CPR2.

在參考計數結果CTR2小於等於最小時間計數值VTM時，比較結果CPR2保持於禁能準位，亦即時間數位轉換器200仍為時間偵測模式。在參考計數結果CTR2大於最小時間計數值時，比較結果CPR2切換為致能準位，而時間數位轉換器200對應地切換為資料轉換模式。 When the reference count result CTR2 is less than or equal to the minimum time count value VTM, the comparison result CPR2 is maintained at the disable level, that is, the time digit converter 200 is still in the time detection mode. When the reference count result CTR2 is greater than the minimum time count value, the comparison result CPR2 is switched to the enable level, and the time digit converter 200 is correspondingly switched to the data conversion mode.

在時間數位轉換器200切換為一資料轉換模式時，多工器240受控於比較結果CPR2傳送計數時脈信號CKCT至計數單元230，而計數單元230在接收計數時脈信號CKCT及時間信號STE後，會依據計數時脈信號CKCT及時間信號STE進行計數以提供計數結果CTR3。比較單元210在接收計數結果CTR3後，會輸出及鎖定計數結果CTR3作為輸出資料Dout。藉此，時間數位轉換器200可轉換時間信號STE的致能時間PE1為輸出資料 Dout，並且可透過區隔指定代碼CDIT調整輸出資料Dout的解析度，以提高時間數位轉換器200的通用性及適用性。 When the time digit converter 200 switches to a data conversion mode, the multiplexer 240 controls the comparison result CPR2 to transmit the count clock signal CKCT to the counting unit 230, and the counting unit 230 receives the count clock signal CKCT and the time signal STE. Thereafter, counting is performed according to the count clock signal CKCT and the time signal STE to provide the count result CTR3. After receiving the count result CTR3, the comparison unit 210 outputs and locks the count result CTR3 as the output data Dout. Thereby, the time digitizer 200 can convert the enable time PE1 of the time signal STE to the output data. Dout, and the resolution of the output data Dout can be adjusted by the interval designation code CDIT to improve the versatility and applicability of the time digital converter 200.

綜合上述，在時間數位轉換器200中，比較單元210可比較時間信號STE的致能時間PE1與最小時間Tmin，以提供比較結果CPR2；數位鎖相迴路220可接收參考時脈信號CKR以提供計數時脈信號CKCT；計數單元230會接收計數時脈信號CKCT，以依據時間信號SET對計數時脈信號CKCT的時脈進行計數而提供計數結果CTR3。並且，當時間信號STE的致能時間PE1大於最小時間Tmin時，數位鎖相迴路220及計數單元230會依據比較結果CPR2進行計數而提供計數結果CTR3，而比較單元210會輸出計數結果CTR3作為輸出資料Dout；當時間信號STE的致能時間PE1小於等於最小時間Tmin時，比較單元210不會提供輸出資料Dout。 In summary, in the time digit converter 200, the comparison unit 210 can compare the enable time PE1 and the minimum time Tmin of the time signal STE to provide a comparison result CPR2; the digital phase locked loop 220 can receive the reference clock signal CKR to provide a count. The clock signal CKCT; the counting unit 230 receives the count clock signal CKCT to count the clock of the count clock signal CKCT according to the time signal SET to provide the count result CTR3. Moreover, when the enable time PE1 of the time signal STE is greater than the minimum time Tmin, the digital phase locked loop 220 and the counting unit 230 provide a count result CTR3 according to the comparison result CPR2, and the comparison unit 210 outputs the count result CTR3 as an output. The data Dout; when the enable time PE1 of the time signal STE is less than or equal to the minimum time Tmin, the comparison unit 210 does not provide the output data Dout.

圖3為依據本發明一實施例的時間數位轉換器的運作方法的流程圖。請參照圖3，在本實施例中，時間數位轉換器用以轉換一時間信號的致能時間為一輸出資料，並且時間數位轉換器的運作方法包括下列步驟。透過一數位鎖相迴路依據一參考時脈信號提供一計數時脈信號(步驟S310)。透過一計數單元依據計數時脈信號及時間信號進行計數而提供一計數結果(步驟S320)。透過一比較單元比較時間信號的致能時間與一最小時間以提供一比較結果(步驟S330)。當時間信號的致能時間大於最小時間時，依據比較結果輸出計數結果作為輸出資料(步驟S340)。其中，上述步驟S310、S320、S330、S340的順序為用以說明，本發明實施例不以此為限。並且，上述步驟S310、S320、S330、S340的細節可參照圖1及圖2實施例所示，在此則不再贅述。 3 is a flow chart of a method of operating a time digital converter in accordance with an embodiment of the present invention. Referring to FIG. 3, in the embodiment, the time digital converter is used to convert the enable time of a time signal into an output data, and the operation method of the time digital converter includes the following steps. A count clock signal is provided according to a reference clock signal through a digital phase locked loop (step S310). A counting result is provided by counting by the counting unit according to the counting clock signal and the time signal (step S320). The enable time of the time signal is compared with a minimum time by a comparison unit to provide a comparison result (step S330). When the enable time of the time signal is greater than the minimum time, the count result is output as the output data according to the comparison result (step S340). Among them, the above steps The order of the steps S310, S320, S330, and S340 is for illustrative purposes, and the embodiment of the present invention is not limited thereto. The details of the above steps S310, S320, S330, and S340 can be referred to the embodiment of FIG. 1 and FIG. 2, and details are not described herein again.

綜上所述，本發明實施例的時間數位轉換器及其運作方法，數位鎖相迴路依據一參考時脈信號提供一計數時脈信號，而計數單元依據計數時脈信號及時間信號進行計數而提供一計數結果，並且在時間信號的致能時間大於最小時間時，輸出計數結果作為輸出資料。藉此，可透過參考時脈信號調整輸出資料的解析度，以提高時間數位轉換器的通用性及適用性。 In summary, the time-digit converter and the method for operating the same according to the embodiment of the present invention, the digital phase-locked loop provides a count clock signal according to a reference clock signal, and the counting unit counts according to the count clock signal and the time signal. A count result is provided, and when the enable time of the time signal is greater than the minimum time, the count result is output as the output data. Thereby, the resolution of the output data can be adjusted by referring to the clock signal to improve the versatility and applicability of the time digital converter.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S310、S320、S330、S340‧‧‧步驟 S310, S320, S330, S340‧‧‧ steps

Claims

一種時間數位轉換器，用以轉換一時間信號的致能時間為一輸出資料，包括：一比較單元，用以比較該時間信號的致能時間與一最小時間，以提供一比較結果；一數位鎖相迴路，接收一參考時脈信號以提供一計數時脈信號；以及一計數單元，接收該計數時脈信號，以依據該計數時脈信號及該時間信號進行計數而提供一計數結果；其中，當該時間信號的致能時間大於該最小時間時，依據該比較結果輸出該計數結果作為該輸出資料。 A time digital converter for converting an enable time of a time signal into an output data, comprising: a comparing unit for comparing an enable time of the time signal with a minimum time to provide a comparison result; a phase-locked loop, receiving a reference clock signal to provide a count clock signal; and a counting unit receiving the count clock signal to provide a count result according to the count clock signal and the time signal; When the enable time of the time signal is greater than the minimum time, the counting result is output as the output data according to the comparison result.

如申請專利範圍第1項所述的時間數位轉換器，其中該比較單元接收該時間信號及表示該最小時間的一比較參考信號，當該時間信號的致能時間大於該最小時間時，該比較單元輸出該時間信號作為該比較結果，當該時間信號的致能時間小於等於該最小時間時，該比較單元輸出為禁能準位的該比較結果，該數位鎖相迴路接收該比較結果，且輸出該比較結果作為一計數致能信號，該計數單元接收該計數時脈信號及該計數致能信號，以依據該計數時脈信號及該計數致能信號進行計數，並且該計數單元輸出且鎖定該計數結果作為該輸出資料。 The time digit converter of claim 1, wherein the comparing unit receives the time signal and a comparison reference signal indicating the minimum time, when the enabling time of the time signal is greater than the minimum time, the comparison The unit outputs the time signal as the comparison result. When the enable time of the time signal is less than or equal to the minimum time, the comparison unit outputs the comparison result of the disable level, and the digital phase locked loop receives the comparison result, and And outputting the comparison result as a count enable signal, the counting unit receiving the count clock signal and the count enable signal to count according to the count clock signal and the count enable signal, and the counting unit outputs and locks This count result is used as the output data.

如申請專利範圍第2項所述的時間數位轉換器，其中該數位鎖相迴路提供該比較參考信號。 a time digit converter as described in claim 2, wherein the number The bit phase locked loop provides the comparison reference signal.

如申請專利範圍第2項所述的時間數位轉換器，其中該比較參考信號的致能時間等於該最小時間。 The time digit converter of claim 2, wherein the enable time of the comparison reference signal is equal to the minimum time.

如申請專利範圍第1項所述的時間數位轉換器，其中在該時間數位轉換器為一時間偵測模式時，該計數單元接收該參考時脈信號及該時間信號以提供一參考計數結果，該比較單元比較該參考計數結果與對應該最小時間的一最小時間計數值以提供該比較結果，在該時間數位轉換器為一資料轉換模式時，該計數單元接收該計數時脈信號及該時間信號以提供該計數結果，該比較單元接收該計數結果，以輸出及鎖定該計數結果作為該輸出資料，其中，該時間數位轉換器依據該比較結果設定為該時間偵測模式或該資料轉換模式。 The time digital converter of claim 1, wherein the counting unit receives the reference clock signal and the time signal to provide a reference counting result when the time converter is in a time detecting mode. The comparing unit compares the reference counting result with a minimum time count value corresponding to the minimum time to provide the comparison result, and when the digital converter is in a data conversion mode, the counting unit receives the counting clock signal and the time a signal is provided to provide the counting result, and the comparing unit receives the counting result to output and lock the counting result as the output data, wherein the time digital converter is set to the time detecting mode or the data conversion mode according to the comparison result. .

如申請專利範圍第5項所述的時間數位轉換器，其中該時間數位轉換器預設為該時間偵測模式，並且在該參考計數結果大於該最小時間計數值時，該時間數位轉換器切換為該資料轉換模式。 The time digit converter of claim 5, wherein the time digit converter is preset to the time detection mode, and when the reference count result is greater than the minimum time count value, the time digit converter switches Convert the mode for this data.

如申請專利範圍第5項所述的時間數位轉換器，其中該數位鎖相迴路依據該參考時脈信號及一區隔指定代碼產生該計數時脈信號。 The time digital converter of claim 5, wherein the digital phase locked loop generates the count clock signal according to the reference clock signal and a designated code.

如申請專利範圍第5項所述的時間數位轉換器，更包括一多工器，接收該參考時脈信號及該計數時脈信號，以依據該比較結果提供該參考時脈信號或該計數時脈信號至該計數單元。 The time digital converter according to claim 5, further comprising a multiplexer, receiving the reference clock signal and the counting clock signal, according to the comparison As a result, the reference clock signal or the count clock signal is provided to the counting unit.

如申請專利範圍第1項所述的時間數位轉換器，其中該計數時脈信號的頻率高於該參考時脈信號。 The time digital converter of claim 1, wherein the frequency of the count clock signal is higher than the reference clock signal.

一種時間數位轉換器的運作方法，用以轉換一時間信號的致能時間為一輸出資料，包括：透過一數位鎖相迴路依據一參考時脈信號提供一計數時脈信號；透過一計數單元依據該計數時脈信號及該時間信號進行計數而提供一計數結果；透過一比較單元比較該時間信號的致能時間與一最小時間，以提供一比較結果；以及當該時間信號的致能時間大於該最小時間時，依據該比較結果輸出該計數結果作為該輸出資料。 A method for operating a time digital converter for converting an enable time of a time signal to an output data, comprising: providing a count clock signal according to a reference clock signal through a digital phase locked loop; The counting clock signal and the time signal are counted to provide a counting result; the enabling time of the time signal is compared with a minimum time by a comparing unit to provide a comparison result; and when the enabling time of the time signal is greater than At the minimum time, the count result is output as the output data based on the comparison result.

如申請專利範圍第10項所述的時間數位轉換器的運作方法，更包括：透過該比較單元比較該時間信號及表示該最小時間的一比較參考信號；當該時間信號的致能時間大於該最小時間時，透過該比較單元輸出該時間信號作為該比較結果；當該時間信號的致能時間小於等於該最小時間時，透過該比較單元輸出為禁能準位的該比較結果；透過該數位鎖相迴路傳送該比較結果作為一計數致能信號；以及透過該計數單元依據該計數時脈信號及該計數致能信號進行計數，並且透過該計數單元輸出且鎖定該計數結果作為該輸出資料。 The method for operating a time digital converter according to claim 10, further comprising: comparing, by the comparing unit, the time signal and a comparison reference signal indicating the minimum time; when the time of the time signal is greater than the At the minimum time, the comparison unit outputs the time signal as the comparison result; when the enable time of the time signal is less than or equal to the minimum time, the comparison result is outputted as the comparison result of the disable level through the comparison unit; The phase locked loop transmits the comparison result as a count enable signal; And counting by the counting unit according to the counting clock signal and the counting enable signal, and outputting through the counting unit and locking the counting result as the output data.

如申請專利範圍第11項所述的時間數位轉換器的運作方法，更包括透過該數位鎖相迴路提供該比較參考信號。 The method for operating a time digital converter according to claim 11, further comprising providing the comparison reference signal through the digital phase locked loop.

如申請專利範圍第11項所述的時間數位轉換器的運作方法，其中該比較參考信號的致能時間等於該最小時間。 The method of operating a time digital converter according to claim 11, wherein the comparison reference signal is enabled for the minimum time.

如申請專利範圍第10項所述的時間數位轉換器的運作方法，更包括：在該時間數位轉換器為一時間偵測模式時，透過該計數單元依據該參考時脈信號及該時間信號提供一參考計數結果，並且透過該比較單元比較該參考計數結果與對應該最小時間的一該最小時間計數值以提供該比較結果；在該時間數位轉換器為一資料轉換模式時，透過該計數單元依據該計數時脈信號及該時間信號提供該計數結果，透過該比較單元傳送及鎖定該計數結果作為該輸出資料；以及依據該比較結果設定該時間數位轉換器為該時間偵測模式或該資料轉換模式。 The method for operating a time digital converter according to claim 10, further comprising: when the digital converter is in a time detection mode, the counting unit provides the reference clock signal and the time signal through the counting unit Referring to the counting result, and comparing the reference counting result with a minimum time count value corresponding to the minimum time by the comparing unit to provide the comparison result; when the digital converter is in a data conversion mode, the counting unit is transmitted through the counting unit Providing the counting result according to the counting clock signal and the time signal, transmitting and locking the counting result as the output data through the comparing unit; and setting the time digit converter to the time detecting mode or the data according to the comparison result Conversion mode.

如申請專利範圍第14項所述的時間數位轉換器的運作方法，更包括：該時間數位轉換器預設為該時間偵測模式；以及在該參考計數結果大於該最小時間計數值時，將該時間數位轉換器切換為該資料轉換模式。 For example, the operation method of the time digital converter described in claim 14 of the patent scope further includes: The time digital converter is preset to the time detection mode; and when the reference count result is greater than the minimum time count value, the time digital converter is switched to the data conversion mode.

如申請專利範圍第14項所述的時間數位轉換器的運作方法，更包括：透過該數位鎖相迴路依據該參考時脈信號及一區隔指定代碼產生該計數時脈信號。 The method for operating a time digital converter according to claim 14, further comprising: generating, by the digital phase locked loop, the count clock signal according to the reference clock signal and a designated code.

如申請專利範圍第10項所述的時間數位轉換器的運作方法，其中該計數時脈信號的頻率高於該參考時脈信號。 The method of operating a time digital converter according to claim 10, wherein the frequency of the count clock signal is higher than the reference clock signal.