TWI533306B

TWI533306B - Structures and operational methods of non-volatile dynamic random access memory devices

Info

Publication number: TWI533306B
Application number: TW101147526A
Authority: TW
Inventors: 王立中
Original assignee: 閃矽公司
Priority date: 2012-12-14
Filing date: 2012-12-14
Publication date: 2016-05-11
Also published as: TW201423752A

Description

非揮發性動態隨機存取記憶體裝置之結構及操作方法 Non-volatile dynamic random access memory Device structure and operation method

本發明有關於非揮發性動態隨機存取記憶體(non-volatile dynamic random access memory，NVDRAM)之結構及其操作方法。特別地，係將一半導體非揮發性記憶體(non-volatile memory,NVM)單元(cell)與一習知動態隨機存取記憶體(dynamic random access memory，DRAM)單元結合而形成單一NVDRAM單元。本發明之NVDRAM單元的配置(configuration)可以隔離DRAM的低電壓操作和半導體NVDRAM單元的高電壓操作。因此，本發明之複數個NVDRAM單元的操作可被簡化，且可依據不同操作模式(mode)來導通(turn on)和切斷(turn off)不同的電壓源(voltage power)，以降低晶片(chip)功率消耗(power consumption)。本發明之NVDRAM單元兼具習知DRAM的讀/寫(read/write)速度及NVM的性能(capability)。 The invention relates to a structure of a non-volatile dynamic random access memory (NVDRAM) and an operation method thereof. In particular, a semiconductor non-volatile memory (NVM) cell is combined with a conventional dynamic random access memory (DRAM) cell to form a single NV DRAM cell. The configuration of the NV DRAM cell of the present invention can isolate low voltage operation of the DRAM and high voltage operation of the semiconductor NV DRAM cell. Therefore, the operation of the plurality of NV DRAM cells of the present invention can be simplified, and different voltage sources can be turned on and turned off according to different operation modes to lower the chip ( Chip) power consumption. The NVDRAM cell of the present invention combines the read/write speed of a conventional DRAM with the capability of NVM.

半導體記憶體已經廣泛地應用在電子系統。從控制基本功能至複雜運算過程，電子系統需要半導體記憶體來儲存指令和資料。半導體記憶體可分為揮發性記憶體和非揮發性記憶體二大類。在切斷記憶體電源後，揮發性記憶體包括靜態隨機存取記憶體(static random access memory，SRAM)和DRAM會遺失其儲存資料。然而，非揮發性記憶體，如唯讀記憶體(read only memory，ROM)、電子可抹除可程式唯讀記憶體(electrical erasable programmable read only memory，EEPROM)和快閃記憶體(flash)，在沒有電力的情況下，仍可以保留其儲存資料。 Semiconductor memory has been widely used in electronic systems. From controlling basic functions to complex computing processes, electronic systems require semiconductor memory to store instructions and data. Semiconductor memory can be divided into two categories: volatile memory and non-volatile memory. After the memory power is turned off, the volatile memory including static random access memory (SRAM) and DRAM will lose its stored data. However, non-volatile memory, such as read only memory (ROM), electronically smeared In addition to electrical erasable programmable read only memory (EEPROM) and flash memory, it can retain its stored data without power.

在諸多電子系統應用領域中，DRAM因其高讀/寫速度、高密度和低成本的特性，已變成儲存大量資料的最佳記憶體選擇。一主動式(active)電子系統應用從DRAM讀取的資料以執行指令和輸入資訊，並將更新資料儲存回DRAM以備進行後續的操作。此外，當一電子系統的電源被導通時，該系統需要有初始資料作為指令和資訊以進行操作。這些初始資料通常儲存於一NVM元件，在系統進行正常操作之前，該電子系統必須將初始指令和資料從該NVM元件搬移至一DRAM元件。而在該電子系統啟動(booting up)時，將該資料從該NVM元件搬移至該DRAM元件的動作，總是會佔用大部分等待時間(wait time)。另一方面，當切斷電子系統或電源因故障或突波而中斷時，在該DRAM元件中的一些關鍵性資料不能被遺失，而且需要被回存至該NVM元件，以作為下次開機之用。因此，對電子系統應用而言，亟需整合具有DRAM的功能與具有恢復(recall)及儲存非揮發性資料的功能之NVDRAM元件。 In many electronic system applications, DRAM has become the best memory choice for storing large amounts of data due to its high read/write speed, high density and low cost. An active electronic system applies data read from the DRAM to execute instructions and input information, and stores the updated data back to the DRAM for subsequent operations. In addition, when the power of an electronic system is turned on, the system needs to have initial data as instructions and information to operate. These initial data are typically stored in an NVM component that must be moved from the NVM component to a DRAM component before the system performs normal operation. When the electronic system is booting up, the movement of the material from the NVM component to the DRAM component always takes up most of the wait time. On the other hand, when the electronic system is cut off or the power supply is interrupted due to a fault or a surge, some key information in the DRAM component cannot be lost and needs to be saved back to the NVM component for the next boot. use. Therefore, for electronic system applications, there is an urgent need to integrate NVDRAM components having functions of DRAM and functions of recalling and storing non-volatile data.

在NVDRAM的發展中，在DRAM電容器的儲存節點(storage node)和半導體NVM的電荷儲存材質(charge storing material)之間轉移電荷已成主要的重點。例如，美國專利號碼3,916,390之專利文獻中，J.J.Chang等人揭露一種類似***閘(split-gate)氮氧金屬半導體(metal nitride oxide semiconductor)NVM的單元結構，一旦電源中斷時，可以備份動態記憶體的資料(如第1a圖所示)。美國專利號碼4,055,837之專利文獻中，K.U.Stein揭露一種電子可抹除可程式唯讀記憶體的結構(一P型存取電晶體(access transistor)和一非揮發性儲存節點之示意圖顯示於第1b圖)。美國專利號碼4,471,471之專利文獻中，D.J.DiMaria揭露一種多矽雙電子注入結構(silicon-rich double electron injection structure，DEIS)堆疊(stack)，在薄穿隧氧化層，(tunneling oxide)可使用之前，將電子注入浮動閘(floating gate)中以進行NVM程式化(programming)操作(如第1c圖所示)。美國專利號碼5,331,188之專利文獻中，Acovic等人利用三層多晶矽(poly-silicon)當作DEIS及利用介於第一層多晶矽和重摻雜(heavy doped)P-型擴散區(diffusion)間之薄穿隧氧化層作為單電子注入堆疊(single electron injection stack，SEIS)，用以在浮動閘和電容器儲存節點間轉移電荷(如第1d圖所示)。 In the development of NVDRAM, the transfer of charge between the storage node of the DRAM capacitor and the charge storage material of the semiconductor NVM has become a major focus. For example, in the patent document of U.S. Patent No. 3,916,390, J.J. Chang et al. A cell structure similar to a split-gate metal nitride oxide semiconductor (NVM) that backs up dynamic memory data (as shown in Figure 1a) once the power supply is interrupted. In the patent document of U.S. Patent No. 4,055,837, KU Stein discloses an electronically erasable programmable read only memory structure (a P-type access transistor and a non-volatile storage node are shown in Figure 1b). Figure). In the patent document of U.S. Patent No. 4,471,471, DJ DiMaria discloses a silicon-rich double electron injection structure (DEIS) stack, which can be used before a tunneling oxide layer can be used. The electrons are injected into a floating gate for NVM programming operations (as shown in Figure 1c). In U.S. Patent No. 5,331,188, Acovic et al. utilizes three layers of poly-silicon as DEIS and utilizes between a first layer of polycrystalline germanium and a heavily doped P-type diffusion. The thin tunnel oxide layer acts as a single electron injection stack (SEIS) for transferring charge between the floating gate and the capacitor storage node (as shown in Figure 1d).

因氧化物生長製程已大幅改善，對半導體NVM而言，當需要保持住儲存電荷而不揮發時，很容易地製造出轉移電荷(以進出電荷儲存材質)所需之可靠的薄穿隧氧化層。在近期的NVDRAM的發展中，美國專利號碼6,952,366、7,072,213和7,319,613之專利文獻中，Forbes揭露一種氮化物唯讀記憶體(nitride read only memory，NORM)單元作為存取電晶體，以及儲存電容器器(如第1e圖所示)。美國專利號碼6,996,007、7,054,201、7,099,181和7,244,609之專利文獻中，Ahn等人揭露一種氮化物薄膜和浮動閘NVM單元作為存取電晶體，以及儲存電容器(如第1f圖所示)。上述二者之NVDRAM的製程，皆達到1T1C(一電晶體和一電容器)結構的最大單元緊密度(compactness)，就如同習知DRAM元件的單元緊密度。雖然1T1C結構是NVDRAM單元的最緊密形式，但不同於習知DRAM單元的存取電晶體，非揮發性存取電晶體需要高電壓來運作以進行電荷轉移穿隧操作與存取電容器儲存節點。再者，因為非揮發性金氧半場效電晶體(metal-oxide-semiconductor field effect transistor，MOSFET)中，從控制閘(control gate)至通道(channel)之厚膜(thick film)堆疊包含耦合介電層(coupling dielectrics)、一電荷儲存材質(例如：浮動閘、氮化物介電層(nitride dielectrics)或奈米晶體(nano-crystals))以及一層厚度介於~100埃(angstrom)至~80埃的穿隧氧化層，所以該非揮發性MOSFET的驅動(driving)電晶體性能比應用於現代DRAM存取電晶體之MOSFET(氧化層厚度約30埃)的驅動電晶體性能差很多。在動態記憶體模式中，上述之1T1C NVDRAM會有較慢的讀/寫存取性能及需要施加一較高的閘極電壓以存取電容器儲存節點。相較於現代DRAM，高電壓存取亦導致較高的功率消耗和較長的切換時間(switching time)來導通(turn on)/切斷(turn off)該存取電晶體以執行動態記憶體的讀/寫操作。以非揮發性MOSFET來替代存取電晶體會犧牲現代DRAM在速度和功率消耗之性能。另外，為了程式化該1T1C NVDRAM，施加一高電壓於連接至一儲存電容器之非揮發性MOSFET的汲極電極，該高電壓有可能超過為現代DRAM低電壓操作而設計之該儲存電容器的最大介電場強度(dielectric filed strength)。此限制已導致較複雜和較低效冗長的程式化架構(scheme)，如Forbes和Ahn所揭露的前述架構。 Since the oxide growth process has been greatly improved, it is easy to manufacture a reliable thin tunneling oxide layer required for transferring charges (to enter and exit the charge storage material) when it is necessary to maintain the stored charge without volatilization. . In the recent development of NVDRAM, in the patent documents of U.S. Patent Nos. 6,952,366, 7,072,213 and 7,319,613, Forbes discloses a nitride read only memory (NORM) cell as an access transistor, and a storage capacitor device ( As shown in Figure 1e). United States In the patent documents No. 6,996,007, 7,054,201, 7,099,181 and 7,244,609, Ahn et al. disclose a nitride film and floating gate NVM unit as an access transistor, and a storage capacitor (as shown in Figure 1f). Both of the NVDRAM processes described above achieve the maximum cell compactness of the 1T1C (a transistor and a capacitor) structure, just like the cell tightness of conventional DRAM components. Although the 1T1C structure is the closest form of NVDRAM cells, unlike the access transistors of conventional DRAM cells, non-volatile access transistors require high voltages to operate for charge transfer tunneling operations and access capacitor storage nodes. Furthermore, because of the non-volatile metal-oxide-semiconductor field effect transistor (MOSFET), the thick film stack from the control gate to the channel contains a coupling medium. Coupling dielectrics, a charge storage material (eg, floating gates, nitride dielectrics or nano-crystals) and a thickness between ~100 angstroms to ~80 The tunneling oxide layer of Å, so the driving transistor performance of the non-volatile MOSFET is much worse than that of the MOSFET applied to the modern DRAM access transistor (the thickness of the oxide layer is about 30 angstroms). In the dynamic memory mode, the 1T1C NVDRAM described above has slower read/write access performance and requires a higher gate voltage to be applied to access the capacitor storage node. Compared to modern DRAM, high voltage access also results in higher power consumption and longer switching time to turn on/off the access transistor to perform dynamic memory. Read/write operation. Replacing access transistors with non-volatile MOSFETs sacrifices speed and power in modern DRAMs Rate of performance. In addition, in order to program the 1T1C NVDRAM, a high voltage is applied to the drain electrode of the non-volatile MOSFET connected to a storage capacitor, which may exceed the maximum of the storage capacitor designed for modern DRAM low voltage operation. Dielectric filed strength. This limitation has led to more complex and less efficient stylized schemas, such as those described by Forbes and Ahn.

為了簡化非揮發性記憶體的程式化/抹除(erase)操作，但又不損及低電壓操作的DRAM性能，本發明提供一種新的2T1C(一非揮發性電晶體+一存取電晶體+一儲存電容器)NVDRAM架構，在動態記憶體應用上可以和DRAM完全一樣地運作，並具有快速恢復及儲存非揮發性資料的功能。 In order to simplify the programming/erase operation of non-volatile memory without damaging the performance of DRAM operating at low voltage, the present invention provides a new 2T1C (a non-volatile transistor + an access transistor) + One storage capacitor) NVDRAM architecture, which can operate exactly the same as DRAM in dynamic memory applications, and has the function of quickly recovering and storing non-volatile data.

第2圖顯示一NVDRAM單元200的架構示意圖。該NVDRAM單元200由一DRAM元件(包括一存取電晶體201和一儲存電容器209)及一半導體非揮發性記憶體(NVM)元件205所構成。如同標準DRAM結構，該存取電晶體201為一個低電壓MOSFET，同時具有一閘極電極(gate electrode)203、一源極(source)電極202和一汲極(drain)電極204a；而該儲存電容器209具有一電容器電極204c和一共板電極(common plate electrode)210。該NVM記憶體元件205可以是一非揮發性MOSFET，此非揮發性記憶體元件205具有一控制閘極(control gate)電極208、一源極電極206、一基底(substrate)電極211、一汲極電極204b，以及一電荷儲存材質207(例如：夾在該控制閘極208和通道間的多晶矽(poly)浮動閘、氮化物介電層和奈米晶體等材質)。該存取電晶體201的汲極電極204a、該非揮發性記憶體元件205的汲極電極204b和該儲存電容器209的電容器電極204c連接在一起，形成一電荷儲存節點(node)204。當進行動態記憶體操作時，會施加一接地電壓(ground voltage)於該非揮發性記憶體元件205的控制閘極208，導致該非揮發性記憶體元件205被切斷(turn off)，所以該NVDRAM單元200的讀、寫和更新(refreshment)等操作都和習知DRAM元件一樣。如第3a圖所示，在儲存節點204之V_DD的“高(high)”電位(voltage potential)和V_SS的“低(low)”電位分別代表二種數位資料“1”和“0”，其中，V_DD和V_SS分別為DRAM操作電力軌(power rail)之正電壓和接地電壓。為了節省電力和薄電容介電層的可靠度，習知DRAM元件通常使用3伏(volt)以下之正電壓V_DD。大多數普通的DRAM使用的正電壓電力軌為1.8伏，且有往更低操作電壓發展的趨勢。因DRAM的操作已為業界所熟悉，所以不再贅述。請注意，如同習知DRAM元件之操作，取決於不同的DRAM讀取架構(read scheme)，該共板電極210可以連接至一接地電壓或是一半的低操作電壓(即V_DD/2)。 FIG. 2 shows a schematic diagram of the architecture of an NVDRAM cell 200. The NV DRAM cell 200 is comprised of a DRAM component (including an access transistor 201 and a storage capacitor 209) and a semiconductor non-volatile memory (NVM) component 205. Like the standard DRAM structure, the access transistor 201 is a low voltage MOSFET having a gate electrode 203, a source electrode 202, and a drain electrode 204a; and the storage The capacitor 209 has a capacitor electrode 204c and a common plate electrode 210. The NVM memory component 205 can be a non-volatile MOSFET having a control gate electrode 208, a source electrode 206, a substrate electrode 211, and a NMOS device. The electrode 206b and a charge storage material 207 (for example, a polysilicon floating gate, a nitride dielectric layer, and a nanocrystal sandwiched between the control gate 208 and the channel). The drain electrode 204a of the access transistor 201, the drain electrode 204b of the non-volatile memory element 205, and the capacitor electrode 204c of the storage capacitor 209 are connected together to form a charge storage node 204. When the dynamic memory operation is performed, a ground voltage is applied to the control gate 208 of the non-volatile memory element 205, causing the non-volatile memory element 205 to be turned off, so the NVDRAM The operations of reading, writing, and refreshing of unit 200 are the same as those of conventional DRAM elements. As shown in Figure 3a, the "high" potential of V _DD at storage node 204 and the "low" potential of V _SS represent two digital data "1" and "0", respectively. Where V _DD and V _SS are the positive voltage and the ground voltage of the DRAM operating power rail, respectively. In order to save power and reliability of the thin capacitor dielectric layer, conventional DRAM components typically use a positive voltage V _{DD of} 3 volts or less. Most common DRAMs use a positive voltage rail of 1.8 volts and have a tendency to move toward lower operating voltages. Since the operation of DRAM is already familiar to the industry, it will not be described again. Note that, as with the operation of conventional DRAM components, the common plate electrode 210 can be connected to a ground voltage or half of the low operating voltage (ie, V _DD /2) depending on the different DRAM read scheme.

藉由從通道注入電荷載子(charge carrier)至該電荷儲存材質207來調整(modulate)非揮發性記憶體元件205的臨界電壓(threshold voltage)，藉以儲存非揮發性資料。例如，將電子注入至該非揮發性記憶體元件205的電荷儲存材質207，該非揮發性記憶體元件205的臨界電壓便偏移(shift)至一較高的臨界電壓。當施加一閘極電壓V_g於多個非揮發性記憶體元件205的控制閘極208時，具高臨界電壓V_thh之非揮發性記憶體元件205會被切斷，而具低臨界電壓V_th1之非揮發性記憶體元件205會被導通，其中V_th1<V_g<V_thh。如第3b和3c圖所示，分別以“高”和“低”兩種臨界電壓(以該非揮發性記憶體元件205的V_thh和V_th1來代表)狀態來表示非揮發性資料“1”和“0”。因此，當施加一閘極電壓V_g於該非揮發性記憶體元件205的控制閘極208時，該非揮發性記憶體元件205的“導通”和“切斷”反應(response)分別決定了“0”和“1”的非揮發性資料。 The threshold voltage of the non-volatile memory element 205 is modulated by injecting a charge carrier from the channel to the charge storage material 207 to store non-volatile data. For example, electrons are injected into the charge storage material 207 of the non-volatile memory element 205, and the threshold voltage of the non-volatile memory element 205 is shifted to a higher threshold voltage. When a gate voltage V _{g is} applied to the control gates 208 of the plurality of non-volatile memory elements 205, the non-volatile memory element 205 having the high threshold voltage V _thh is cut off with a low threshold voltage V The non-volatile memory element 205 of _th1 will be turned on, where V _th1 <V _g <V _thh . As shown in FIG. 3c and second 3b, respectively, to "high" and "low" two kinds of threshold voltage (V _th1 and _V thh in the nonvolatile memory element 205 represented) to represent the non-volatile data state "1" And "0". Therefore, when a gate voltage V _{g is} applied to the control gate 208 of the non-volatile memory element 205, the "on" and "off" reactions of the non-volatile memory element 205 respectively determine "0. Non-volatile data for "and".

在該非揮發性記憶體元件205進行儲存資料之前，須先將該非揮發性記憶體元件205抹除至一較低臨界電壓V_th1。於該控制閘極208和該基底電極211間施加一高電壓場(voltage field)，藉由習知通道傅勒-諾德翰穿隧(Fowler-Nordheim tunneling)方法，使被儲存的電子自該電荷儲存材質207穿隧出去，以抹除該非揮發性記憶體元件205。或者，利用反向(reversed)源/極接面偏壓(voltage bias)促動能帶(band-to-band)熱電洞(hot hole)注入，以消滅(annihilate)儲存於該電荷儲存材質207中的電子。 Before the non-volatile memory component 205 stores the data, the non-volatile memory component 205 must be erased to a lower threshold voltage _Vth1 . A high voltage field is applied between the control gate 208 and the base electrode 211, and the stored electrons are stored by the conventional Fowler-Nordheim tunneling method. The charge storage material 207 is tunneled out to erase the non-volatile memory component 205. Alternatively, a reverse-sourced voltage-biased band-to-band hot hole implant is used to annihilate the charge storage material 207. Electronics.

於非揮發性儲存模式中，需要藉由程式化該非揮發性記憶體元件205來將DRAM元件(201和209)之資料回存至相對應的非揮發性記憶體元件205。美國專利公告號碼US 7,733,700 B2(上述專利的揭露內容在此被整體引用作為本說明書內容的一部份)之專利文獻中，Lee Wang揭露一種程式化架構(scheme)中，係分別施加一反向接面偏壓和V_DD至非揮發性MOSFET的源極電極和汲極電極。為產生程式化操作中的反向源極接面偏壓，分別施加一源極偏壓V_s和一負偏壓V_sub於在該非揮發性記憶體元件205的源極電極206和基底電極211上。藉由調整該負偏壓V_sub，該源極偏壓V_s可以是該接地電壓V_SS，以得到最佳程式化效能。該非揮發性記憶體元件205的汲極電極204b之偏壓為V_DD或接地電壓V_SS，分別對應DRAM元件之資料“1”或“0”。藉由施加一閘極電壓V_a於該存取電晶體201的閘電極203，讓該存取電晶體201導通，使該源極電極202的外部電壓V_DD或V_SS供應該儲存節點204的偏壓，而該源極電極202耦接至外部讀取/更新電路之金屬位元線(bit line)，如第4a和4b圖所示。在程式化期間，該外部電壓V_DD或V_SS可以維持該儲存節點204的偏壓，而程式化電流趨於下拉(pull down)該儲存節點204的電位。當施加歷時幾微秒(μs)且振幅為V_gh的一高電壓脈波(pulse)於該非揮發性記憶體元件205的控制閘極208時，具汲極偏壓V_DD之該非揮發性記憶體元件205產生之熱電子被注入至接近汲極空乏區(depletion region)之該電荷儲存材質207，如第4a圖所示，因此，具汲極偏壓V_DD之該非揮發性記憶體元件205從一抹除臨界電壓V_th1被程式化至一高臨界電壓V_thh。另一方面，當該非揮發性記憶體元件205的汲極偏壓V_SS等於源極偏壓V_SS時，該非揮發性記憶體元件205被導通於MOSFET的深線性模式區(deep linear mode region)，因為於MOSFET的深線性模式區無法產生熱電子，故導致沒有熱電子注入至該電荷儲存材質207，如第4b圖所示。因此，在該儲存節點204的電位為V_SS時，其相對應非揮發性記憶體元件205的臨界電壓仍維持在低抹除臨界電壓V_th1。只有在該儲存節點204具有V_DD的電位(代表DRAM元件儲存一數位資料“1”)時，其相對應非揮發性記憶體元件205才能被程式化至該高臨界電壓V_thh。在此亦請注意，相對於先前技術之概念，在程式化非揮發性MOSFET的整個過程中，在相對應非揮發性MOSFET內，絕不會發生儲存節點和電荷儲存材質間之電荷轉移。程式化非揮發性MOSFET的熱電子注入方式相同於程式化NVM的熱電子注入方式。 In the non-volatile storage mode, the non-volatile memory component 205 needs to be programmed to restore the data of the DRAM components (201 and 209) to the corresponding non-volatile memory component 205. In the patent document of US Pat. No. 7,733,700 B2, the disclosure of which is hereby incorporated by reference in its entirety in its entirety in the content of the content of the present disclosure, Lee Wang discloses a stylized architecture in which a reverse is applied Junction bias and V _DD to the source and drain electrodes of the non-volatile MOSFET. To generate a reverse biased source junction stylized operation, it is applied a bias voltage source V _s and a negative bias voltage V _sub to the source of the nonvolatile memory element 205 and the substrate electrode 206 electrode 211 on. By adjusting the negative bias voltage V _sub, the source bias voltage V _s may be the ground voltage V _SS, stylized to give the best performance. The bias voltage of the drain electrode 204b of the non-volatile memory element 205 is V _DD or ground voltage V _SS , which corresponds to the data "1" or "0" of the DRAM component, respectively. The access transistor 201 is turned on by applying a gate voltage V _a to the gate electrode 203 of the access transistor 201, and the external voltage V _DD or V _{SS of} the source electrode 202 is supplied to the storage node 204. The source electrode 202 is coupled to the metal bit line of the external read/update circuit as shown in Figures 4a and 4b. During programming, the external voltage V _DD or V _SS can maintain the bias voltage of the storage node 204, while the programmed current tends to pull down the potential of the storage node 204. The non-volatile memory with a buckling bias V _DD is applied when a high voltage pulse of a few microseconds (μs) and an amplitude of V _gh is applied to the control gate 208 of the non-volatile memory element 205. The hot electrons generated by the body element 205 are implanted into the charge storage material 207 near the depletion region, as shown in FIG. 4a, and thus the non-volatile memory element 205 having a drain bias voltage V _DD . It is programmed from a wipe-off threshold voltage V _th1 to a high threshold voltage V _thh . Meanwhile, when the drain of the nonvolatile memory element 205 is equal to the bias voltage source V _SS V _SS when the source bias, the non-volatile memory 205 is turned a deep region in the linear mode MOSFET element (deep linear mode region) Because the deep linear mode region of the MOSFET cannot generate hot electrons, no hot electrons are injected into the charge storage material 207, as shown in FIG. 4b. Therefore, when the potential of the storage node 204 is V _SS , the threshold voltage of the corresponding non-volatile memory element 205 is maintained at the low erase threshold voltage V _th1 . Only when the storage node 204 has a potential of V _DD (representing that the DRAM component stores a digital data "1"), its corresponding non-volatile memory component 205 can be programmed to the high threshold voltage V _thh . Note also here that, relative to the prior art concept, charge transfer between the storage node and the charge storage material never occurs in the corresponding non-volatile MOSFET throughout the staging of the non-volatile MOSFET. The hot electron injection method of a stylized non-volatile MOSFET is the same as Stylized NVM hot electron injection method.

為恢復(recall)非揮發性資料，該非揮發性記憶體元件205將其非揮發性資料載入(load)其相對應DRAM的儲存節點204。於此非揮發性資料之載入過程中，先將所有DRAM元件的儲存節點204充電至V_DD來完成所有DRAM元件被寫入資料“1”的動作。如業界所熟悉之DRAM操作，在切斷該存取電晶體201之後，儲存於該儲存節點204的電荷會經由所有可能的漏電流途徑(leakage current path)漸漸地放電(discharge)，因此，為防止記憶體資料永久喪失，必須做DRAM的更新(refreshment)。根據現代DRAM的規格，更新時間必須長於數十毫秒(millisecond)~數百毫秒。本發明僅在奈秒(nanosecond)時間等級(time order)內就完成下列資料載入程序，遠短於習知DRAM的更新時間。參考第5a圖，就在該儲存電容器209充完電以及該存取電晶體201被切斷之後，一控制閘極電壓V_g被施加於該非揮發性記憶體元件205的控制閘極208，其中V_th1<V_g<V_thh，同時該非揮發性記憶體元件205的源極電極206被偏壓至接地電壓。結果，具低臨界電壓V_th1之非揮發性MOSFET 205被導通，使儲存節點電位V_DD在奈秒的時間等級或更短的時間內，放電至接地電壓，而具高臨界電壓V_thh之非揮發性記憶體元件205仍維持在切斷狀態，並在放電期間內該儲存節點204仍維持在電壓電位V_DD。當儲存電容器209放電完畢時，該非揮發性記憶體元件205的控制閘極208被設定為接地電壓。可藉由斷接(disconnect)施加至該非揮發性記憶體元件205之源極電極206和控制閘極208的接地偏壓，來使該非揮發性記憶體元件205完全停止作動(deactivate)。在“載入”操作的最後階段，儲存在該些DRAM元件的資料就等於儲存在其相對應之非揮發性記憶體元件205之非揮發性資料的直接映像(direct image)，也就是高臨界電壓對應資料“1”，而低臨界電壓對應資料“0”。接著，NVDRAM 200回到DRAM的讀取操作，以讀取儲存在其相對應非揮發性MOSFET中之非揮發性資料。 To recall non-volatile data, the non-volatile memory component 205 loads its non-volatile data into the storage node 204 of its corresponding DRAM. During the loading of the non-volatile data, the storage node 204 of all DRAM elements is first charged to V _DD to complete the action of all DRAM elements being written to the data "1". As is well known in the art, after the access transistor 201 is turned off, the charge stored in the storage node 204 is gradually discharged through all possible leakage current paths, thus, To prevent permanent loss of memory data, DRAM refreshment must be done. According to modern DRAM specifications, the update time must be longer than tens of milliseconds (milliseconds) to hundreds of milliseconds. The present invention accomplishes the following data loading procedure only in the nanosecond time order, which is much shorter than the update time of the conventional DRAM. Referring to FIG. 5a, just after the storage capacitor 209 is completely charged and the access transistor 201 is cut off, a control gate voltage V _g is applied to the control gate 208 of the nonvolatile memory element 205, wherein V _th1 <V _g <V _thh , while the source electrode 206 of the non-volatile memory element 205 is biased to a ground voltage. As a result, the non-volatile MOSFET 205 having the low threshold voltage V _th1 is turned on, causing the storage node potential V _{DD to} discharge to the ground voltage in a time level of nanosecond or less, and having a high threshold voltage V _thh The volatile memory element 205 remains in the off state and the storage node 204 remains at the voltage potential V _DD during the discharge period. When the storage capacitor 209 is discharged, the control gate 208 of the non-volatile memory element 205 is set to the ground voltage. The non-volatile memory element 205 can be completely deactivated by disconnecting the ground bias applied to the source electrode 206 and the control gate 208 of the non-volatile memory element 205. In the final stage of the "loading" operation, the data stored in the DRAM components is equal to the direct image of the non-volatile data stored in its corresponding non-volatile memory component 205, that is, high critical. The voltage corresponds to the data "1", and the low threshold voltage corresponds to the data "0." Next, the NVDRAM 200 returns to the DRAM read operation to read the non-volatile data stored in its corresponding non-volatile MOSFET.

以下之說明將舉出本發明之數個較佳的示範實施例，熟悉本領域者應可理解，本發明可採用各種可能的方式實施，並不限於下列示範之實施例或實施例中的特徵。 The following description of the preferred embodiments of the present invention will be understood by those skilled in the art that the invention may be practiced in various possible ways and not limited to the features of the following exemplary embodiments or embodiments .

根據本發明NVDRAM的一實施例，結合複數個NVDRAM單元200(如第2圖所示)成為一非揮發性動態隨機存取記憶體單元陣列(memory cell array)600。請參考第6圖，沿著該M條位元線(bit line)，M×N個NVDRAM單元200被配置形成複數個交錯偶奇配對單元(staggered odd-even paired cell)之電路組態，並可被2N條字元線(word line)所存取，如同一般常見之折曲(folded)DRAM單元陣列架構。一列(row)M/2個低電壓存取電晶體201的閘極在水平方向相連接而形成一條字元線，而一行(column)N個低電壓存取電晶體201的源極電極皆連接至一條垂直位元線。對於一反或型(NOR-type)快閃記憶體單元陣列(flash memory cell array)而言，一列M/2個非揮發性記憶體元件205的控制閘相連接而形成一控制閘極線CG。成對的二列各有M/2個非揮發性MOSFET的源極電極相接形成一共源極線(common source line)CS。如同習知DRAM，該些NVDRAM單元200中該些儲存電容器209的該些共板電極210連接在一起形成陣列中之單一共板(common plate)。該共板可以是位於堆疊電容結構(stacked capacitor structure)之單一導電板(single conducting plate)或是位於深溝槽電容結構(deep trench capacitor structure)之導電矽基底 (conducting silicon substrate)。取決於不同的DRAM讀取架構，如習知DRAM元件操作一般，該些共板電極210可被連接至一接地電壓或是低操作電壓的一半(即V_DD/2)。第2圖之NVDRAM單元之儲存節點204係位於記憶體單元的內側、唯一的內部節點。最後，每一個M行和2N列之非揮發性動態隨機存取記憶體單元陣列600包含M×N個NVDRAM單元200、2N條字元線、2N條控制閘極線(CG)、M條位元線和N條共源極線(CS)，如第6圖所示。請注意，第6圖之M行和2N列之非揮發性動態隨機存取記憶體單元陣列僅作為示例，並非本發明之限制。 In accordance with an embodiment of the NVDRAM of the present invention, a plurality of NV DRAM cells 200 (as shown in FIG. 2) are incorporated into a non-volatile dynamic random access memory cell array 600. Referring to FIG. 6, along the M bit lines, M×N NVDRAM cells 200 are configured to form a circuit configuration of a plurality of staggered odd-even paired cells, and It is accessed by 2N word lines, like the commonly used folded DRAM cell array architecture. The gates of one row of M/2 low voltage access transistors 201 are connected in the horizontal direction to form one word line, and the source electrodes of one column of N low voltage access transistors 201 are connected. To a vertical bit line. For a NOR-type flash memory cell array, the control gates of a column of M/2 non-volatile memory elements 205 are connected to form a control gate line CG. . The source electrodes of the paired two columns each having M/2 non-volatile MOSFETs are connected to form a common source line CS. As with conventional DRAMs, the common plate electrodes 210 of the storage capacitors 209 in the NV DRAM cells 200 are connected together to form a single common plate in the array. The common plate may be a single conducting plate located in a stacked capacitor structure or a conducting silicon substrate in a deep trench capacitor structure. Depending on the DRAM read architecture, as is conventional DRAM device operation, the common plate electrodes 210 can be connected to a ground voltage or half of the low operating voltage (ie, V _DD /2). The storage node 204 of the NVDRAM cell of Fig. 2 is located inside the memory cell and is the only internal node. Finally, each of the M rows and 2N columns of the non-volatile DRAM cell array 600 includes M×N NVDRAM cells 200, 2N word lines, 2N control gate lines (CG), and M bits. The meta-line and the N common source line (CS) are shown in Figure 6. Please note that the non-volatile DRAM cell array of M rows and 2N columns of FIG. 6 is only an example and is not a limitation of the present invention.

該非揮發性動態隨機存取記憶體單元陣列600可操作於一動態記憶體模式和一非揮發性記憶體模式。該非揮發性動態隨機存取記憶體單元陣列600在動態記憶體模式的操作和習知DRAM的讀、寫和更新操作都一樣。因DRAM的標準操作已為業界所熟悉，所以不再贅述。本發明之非揮發性記憶體模式包含“載入”和“儲存”模式。“載入”模式是將非揮發性資料從該非揮發性記憶體元件205載入至DRAM元件之操作，而“儲存”模式是將資料從DRAM元件儲存至該非揮發性記憶體元件205之操作。在該非揮發性動態隨機存取記憶體單元陣列600準備儲存非揮發性資料之前，該非揮發性動態隨機存取記憶體單元陣列600之非揮發性記憶體元件205必須先被抹除至一低臨界電壓，如利用快閃記憶體陣列最常用的傅勒-諾德翰穿隧效應，來抹除該非揮發性動態隨機存取記憶體單元陣列600。為了要進行傅勒-諾德翰穿隧效應，係施加一個小於或等於零伏特的偏壓V_g於2N條控制閘極線以及施加一個大於零伏特的偏壓V_sub於該陣列基底電極211，使得施加的電場可以將電子自該電荷儲存材質207穿隧出去到基底，陣列中之該些非揮發性記憶體元件205的臨界電壓便被抹除至一低臨界電壓分佈，如第7圖所示。施加一控制閘極電壓V_g於2N條控制閘極線時，該控制閘極電壓V_g係大於一群(group)非揮發性記憶體元件205所具有之抹除臨界電壓和小於一群非揮發性記憶體元件205所具有之程式化臨界電壓，可分別”導通”和“切斷”陣列中之該些非揮發性記憶體元件205。 The non-volatile DRAM cell array 600 is operable in a dynamic memory mode and a non-volatile memory mode. The operation of the non-volatile DRAM cell array 600 in the dynamic memory mode is the same as the read, write, and update operations of the conventional DRAM. Since the standard operation of DRAM is already familiar to the industry, it will not be described again. The non-volatile memory modes of the present invention include "load" and "storage" modes. The "load" mode is the operation of loading non-volatile data from the non-volatile memory element 205 to the DRAM element, and the "storage" mode is the operation of storing data from the DRAM element to the non-volatile memory element 205. Before the non-volatile DRAM cell array 600 is ready to store non-volatile data, the non-volatile memory component 205 of the non-volatile DRAM cell array 600 must be erased to a low threshold. The voltage, such as the most commonly used Fuller-Nodheim tunneling effect of a flash memory array, is used to erase the non-volatile DRAM cell array 600. In order to perform the Fuller-Nodheim tunneling effect, a bias voltage V _{g of} less than or equal to zero volts is applied to the 2N control gate lines and a bias voltage V _sub greater than zero volts is applied to the array substrate electrode 211, The applied electric field can tunnel electrons from the charge storage material 207 to the substrate, and the threshold voltages of the non-volatile memory elements 205 in the array are erased to a low threshold voltage distribution, as shown in FIG. Show. When a control gate voltage V _g is applied to 2N control gate lines, the control gate voltage V _g is greater than a erase threshold voltage of a group of non-volatile memory elements 205 and less than a group of non-volatile The memory element 205 has a programmed threshold voltage that can "turn on" and "cut" the non-volatile memory elements 205 in the array, respectively.

在“儲存”模式中，於DRAM元件中的資料會被儲存至其相對應之非揮發性記憶體元件205。於非揮發性動態隨機存取記憶體單元陣列600中，選擇一列NVDRAM單元來進行操作。第8圖顯示被選擇的字元線、位元線、控制閘極線(CG)、共源極線(CS)和基底之施加電壓時序圖。為維持該儲存節點204的電壓V_DD或V_SS以程式化該被選擇列NVDRAM單元，透過導通(用以更新之)DRAM寫入驅動器(write driver)以對相對應的位元線進行偏壓，同時施加一偏壓V_a至被選擇的字元線以啟動(activate)該被選擇的字元線。當施加歷時幾微秒(μs)且振幅為V_gh的高電壓脈衝(pulse)於該控制閘極線時，便開始進行程式化過程。對於被選擇列中具儲存電壓V_DD(具資料”1”)之DRAM元件而言，程式化過程會注入電子至該電荷儲存材質207，以使其相對應非揮發性記憶體元件205的臨界電壓被偏移至較高的臨界電壓。對於被選擇列中具儲存電壓V_SS(具資料”0”)之DRAM元件而言，不會發生程式化過程，因此其相對應非揮發性記憶體元件205也沒有產生臨界電壓偏移，故具資料“0”DRAM元件之相對應非揮發性記憶體元件205仍維持在抹除臨界電壓。該些非揮發性記憶體元件205的“高”和“低”臨界電壓的狀態分別表示“1”和“0”的非揮發性資料。藉由改變該些非揮發性記憶體元件205的“高”和“低”臨界電壓的兩個狀態，該些DRAM資料可直接被儲存至其相對應非揮發性記憶體元件205。 In the "storage" mode, the data in the DRAM component is stored to its corresponding non-volatile memory component 205. In the non-volatile DRAM cell array 600, a column of NVDRAM cells is selected for operation. Figure 8 shows a timing diagram of applied voltages for selected word lines, bit lines, control gate lines (CG), common source lines (CS), and substrate. To maintain the voltage V _DD or V _{SS of} the storage node 204 to program the selected column NVDRAM cell, the corresponding bit line is biased by turning on (for updating) the DRAM write driver. Simultaneously applying a bias voltage V _a to the selected word line to activate the selected word line. The stylization process begins when a high voltage pulse of a few microseconds (μs) and an amplitude of V _gh is applied to the control gate line. For a DRAM component with a stored voltage V _DD (with data "1") in the selected column, the stylization process injects electrons into the charge storage material 207 to correspond to the criticality of the non-volatile memory component 205. The voltage is shifted to a higher threshold voltage. For the DRAM device with the storage voltage V _SS (with data "0") in the selected column, the stylization process does not occur, so the corresponding non-volatile memory device 205 does not generate a threshold voltage offset. The corresponding non-volatile memory component 205 with the "0" DRAM component remains at the erase threshold voltage. The states of the "high" and "low" threshold voltages of the non-volatile memory elements 205 represent non-volatile data of "1" and "0", respectively. By varying the two states of the "high" and "low" threshold voltages of the non-volatile memory elements 205, the DRAM data can be directly stored to its corresponding non-volatile memory element 205.

在“載入”模式中，儲存於該些非揮發性記憶體元件205的非揮發性資料會被載回到(load back)該些DRAM元件中。於非揮發性動態隨機存取記憶體單元陣列600中，選擇一列NVDRAM單元來進行“載入”操作。第9圖顯示被選擇的字元線、位元線、控制閘極線(CG)、共源極線(CS)和該儲存節點204的電位之施加電壓時序。於該時序中，如同習知DRAM寫入的過程，被選擇列的NVDRAM單元的DRAM元件被寫入資料“1”，因此該些儲存節點204的電位被充電至V_DD。在施加一個接近接地電壓的電壓於被選擇的字元線以切斷被選擇的該些DRAM元件之後，再施加一閘極電壓V_g於相對應控制閘極線，以導通被選擇列的非揮發性記憶體元件205，其中V_th1<v_g<V_thh。該共源極線(CS)被連接至接地電壓。對於被選擇列中具低臨界電壓的該些非揮發性記憶體元件205(儲存非揮發性資料“0”)而言，當該些非揮發性記憶體元件205被導通而使該儲存電容器209放電時，儲存節點電壓便降至接地電壓。然而，對於被選擇列中具高臨界電壓的該些非揮發性記憶體元件205(儲存非揮發性資料“1”)而言，因為該些非揮發性記憶體元件205被“切斷”，故儲存節點電壓仍維持不變。於載入程序之後，在被選擇列的該些DRAM元件中的資料係完全拷貝(identical copy)儲存於其相對應之該些非揮發性記憶體元件205中的非揮發性資料。之後，可利用平常DRAM讀取操作，來讀取將該些非揮發性資料。 In the "load" mode, the non-volatile data stored in the non-volatile memory elements 205 is loaded back into the DRAM elements. In the non-volatile DRAM cell array 600, a column of NVDRAM cells is selected for the "loading" operation. Figure 9 shows the applied voltage timing of the selected word line, bit line, control gate line (CG), common source line (CS), and potential of the storage node 204. In this timing, as in the conventional DRAM write process, the DRAM elements of the selected column of NVDRAM cells are written with data "1", so the potential of the storage nodes 204 is charged to V _DD . After applying a voltage close to the ground voltage to the selected word line to cut off the selected DRAM elements, a gate voltage V _g is applied to the corresponding control gate line to turn on the selected column. Volatile memory element 205, where V _th1 <v _g <V _thh . The common source line (CS) is connected to a ground voltage. For the non-volatile memory elements 205 (stored non-volatile data "0") having a low threshold voltage in the selected column, when the non-volatile memory elements 205 are turned on, the storage capacitor 209 is turned on. When discharged, the storage node voltage drops to ground. However, for the non-volatile memory elements 205 having a high threshold voltage in the selected column (storing the non-volatile data "1"), since the non-volatile memory elements 205 are "cut", Therefore, the storage node voltage remains unchanged. After the loading process, the data in the selected DRAM elements of the selected column is an identical copy of the non-volatile data stored in the corresponding non-volatile memory elements 205. The non-volatile data can then be read using a normal DRAM read operation.

在該非揮發性動態隨機存取記憶體單元陣列600中，不需要放大(amplification)和緩衝中間資料(buffering)，可直接將該些非揮發性記憶體元件205中的非揮發性資料載入至其相對應之DRAM元件，達到高速度存取非揮發性資料的功效。本發明在一NVDRAM單元中，提供兼具動態記憶體之快速讀/寫功能和非揮發性記憶體之儲存性能。 In the non-volatile DRAM cell array 600, the non-volatile data in the non-volatile memory elements 205 can be directly loaded into the non-volatile memory element 205 without the need for amplification and buffering. Its corresponding DRAM components achieve high-speed access to non-volatile data. The present invention provides a fast read/write function of both dynamic memory and storage performance of non-volatile memory in an NV DRAM cell.

綜而言之，本發明非揮發性動態隨機存取記憶體及其操作方法已被揭示。本發明非揮發性動態隨機存取記憶體單元具有與動態隨機存取記憶體一樣的讀/寫功能及快速載入/儲存之非揮發性記憶體性能。 In summary, the non-volatile dynamic random access memory of the present invention and its method of operation have been disclosed. The non-volatile dynamic random access memory cell of the present invention has the same read/write function as the dynamic random access memory and non-volatile memory performance of fast loading/storing.

以上雖以實施例說明本發明，但並不因此限定本發明之範圍，只要不脫離本發明之要旨，該行業者可進行各種變形或變更，均應落入本發明之申請專利範圍。 The present invention has been described above by way of examples, and the scope of the present invention is not limited thereto, and various modifications and changes may be made by those skilled in the art without departing from the scope of the invention.

200‧‧‧非揮發性動態隨機存取記憶體單元 200‧‧‧Non-volatile DRAM cell

201‧‧‧存取電晶體 201‧‧‧Access transistor

202‧‧‧存取電晶體的源極電極 202‧‧‧Access to the source electrode of the transistor

203‧‧‧存取電晶體的閘極電極 203‧‧‧Access gate electrode of transistor

204‧‧‧儲存節點 204‧‧‧ Storage node

204a‧‧‧汲極電極 204a‧‧‧汲electrode

204b‧‧‧非揮發性記憶體元件的汲極電極 204b‧‧‧The electrode of the non-volatile memory element

204c‧‧‧電容器電極 204c‧‧‧Capacitor electrode

205‧‧‧非揮發性記憶體元件 205‧‧‧ Non-volatile memory components

206‧‧‧非揮發性記憶體元件的源極電極 206‧‧‧Source electrode of non-volatile memory components

207‧‧‧非揮發性記憶體元件的電荷儲存材質 207‧‧‧Charge storage material for non-volatile memory components

208‧‧‧非揮發性記憶體元件的控制閘極 208‧‧‧Control gates for non-volatile memory components

209‧‧‧儲存電容器 209‧‧‧Storage capacitor

210‧‧‧共板電極 210‧‧‧ Common plate electrode

211‧‧‧基底電極 211‧‧‧Base electrode

600‧‧‧非揮發性動態隨機存取記憶體單元陣列 600‧‧‧Non-volatile DRAM cell array

第1(a)~1(f)圖係根據先前技術，顯示不同的NVDRAM示意圖。 The 1(a) to 1(f) diagrams show different NVDRAM schematics according to the prior art.

第2圖係根據本發明之一實施例，顯示NVDRAM單元的架構示意圖 2 is a schematic diagram showing the architecture of an NVDRAM cell according to an embodiment of the present invention.

第3a圖係根據本發明之一實施例，顯示NVDRAM單元之DRAM訊號的數位定義。 Figure 3a shows a digital definition of a DRAM signal for an NV DRAM cell in accordance with an embodiment of the present invention.

第3b及3c圖係根據本發明之一實施例，顯示NVDRAM單元之非揮發性記憶體元件的非揮發性資料定義。 Figures 3b and 3c show non-volatile data definitions for non-volatile memory elements of NV DRAM cells in accordance with an embodiment of the present invention.

第4a及4b圖係根據本發明之一實施例，說明在儲存模式下，當NVDRAM單元之DRAM元件分別儲存資料“1”和資料“0”時，對應非揮發性記憶體元件的程式化操作。 4a and 4b illustrate a stylized operation of a non-volatile memory component when the DRAM component of the NVDRAM cell stores data "1" and data "0", respectively, in the storage mode, according to an embodiment of the present invention. .

第5圖是根據第2圖，說明非揮發性記憶體元件的非揮發性資料被載入至DRAM元件。 Figure 5 is a diagram showing the non-volatile data of a non-volatile memory element being loaded into a DRAM element according to Figure 2.

第6圖是根據本發明之一實施例，顯示一非揮發性動態隨機存取記憶體單元陣列的示意圖。 Figure 6 is a schematic diagram showing an array of non-volatile DRAM cells in accordance with an embodiment of the present invention.

第7圖是根據本發明之一實施例，顯示一陣列中非揮發性記憶體元件在進行程式化/抹除運作後之一典型臨界電壓分佈圖。 Figure 7 is a diagram showing a typical threshold voltage distribution of a non-volatile memory component in an array after a stylization/erasing operation, in accordance with an embodiment of the present invention.

第8圖是根據本發明之一實施例，顯示在一非揮發性動態隨機存取記憶體單元陣列中，將DRAM元件資料儲存至相對應的非揮發性記憶體元件之施加電壓時序圖。 Figure 8 is a timing diagram showing applied voltages for storing DRAM device data to corresponding non-volatile memory devices in a non-volatile DRAM cell array in accordance with an embodiment of the present invention.

第9圖是根據本發明之一實施例，顯示在一非揮發性動態隨機存取記憶體單元陣列中，將非揮發性記憶體元件資料載入至DRAM元件並以DRAM讀取感測電路(read sensing circuitry)來讀取之施加電壓時序圖。 Figure 9 is a diagram showing the loading of non-volatile memory component data into a DRAM component and reading the sensing circuit in DRAM in a non-volatile DRAM cell array according to an embodiment of the present invention ( Read Sensing circuitry) to read the applied voltage timing diagram.

201‧‧‧存取電晶體 201‧‧‧Access transistor

204‧‧‧儲存節點 204‧‧‧ Storage node

204a‧‧‧存取電晶體的汲極電極 204a‧‧‧ access to the gate electrode of the transistor

204c‧‧‧電容器電極 204c‧‧‧Capacitor electrode

209‧‧‧儲存電容器 209‧‧‧Storage capacitor

210‧‧‧共板電極 210‧‧‧ Common plate electrode

211‧‧‧基底電極 211‧‧‧Base electrode

Claims

一種非揮發性動態隨機存取記憶體單元(NVDRAM cell)，包含：單一非揮發性記憶體(NVM)元件，包含一電荷儲存材質、一控制閘極電極、一第一源極電極、一第一汲極電極以及一基底電極；以及單一動態隨機存取記憶體(DRAM)元件，包含：一存取電晶體，包含一閘極電極、一第二源極電極以及一第二汲極電極；以及一儲存電容器，包含一第一板狀電極以及一第二板狀電極；其中，該第一板狀電極、該第一汲極電極以及該第二汲極電極形成一儲存節點；其中，施加於該第一源極電極的電壓係小於或等於該第一汲極電極的電壓；以及其中，該單一非揮發性記憶體元件僅包含有四個電極。 A non-volatile dynamic random access memory cell (NVDRAM cell) comprising: a single non-volatile memory (NVM) device, including a charge storage material, a control gate electrode, a first source electrode, and a first a drain electrode and a base electrode; and a single dynamic random access memory (DRAM) component, comprising: an access transistor comprising a gate electrode, a second source electrode, and a second drain electrode; And a storage capacitor comprising a first plate electrode and a second plate electrode; wherein the first plate electrode, the first drain electrode and the second electrode form a storage node; wherein The voltage of the first source electrode is less than or equal to the voltage of the first drain electrode; and wherein the single non-volatile memory element includes only four electrodes.

如申請專利範圍第1項所記載之非揮發性動態隨機存取記憶體單元，其中當該非揮發性記憶體元件被切斷(turn off)時，該非揮發性動態隨機存取記憶體單元的運作就如同習知動態隨機存取記憶體元件。 The non-volatile dynamic random access memory unit according to claim 1, wherein the operation of the non-volatile dynamic random access memory unit when the non-volatile memory element is turned off Just like the conventional dynamic random access memory component.

如申請專利範圍第1項所記載之非揮發性動態隨機存取記憶體單元，其中當該非揮發性記憶體元件在一低臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為0；以及，其中當該非揮發性記憶體元件在一高臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為1。 The non-volatile dynamic random access memory unit according to claim 1, wherein when the non-volatile memory element is in a low threshold voltage state, the non-volatile memory element is stored. The data bit is 0; and wherein when the non-volatile memory element is in a high threshold voltage state, the non-volatile memory element stores a data bit of one.

如申請專利範圍第1項所記載之非揮發性動態隨機存取記憶體單元，其中當該儲存節點具一低操作電壓時，表示該動態隨機存取記憶體元件儲存一資料位元為1；以及其中當該儲存節點具一接地電壓時，表示該動態隨機存取記憶體元件儲存一資料位元為0。 The non-volatile dynamic random access memory unit of claim 1, wherein when the storage node has a low operating voltage, the dynamic random access memory device stores a data bit of 1; And when the storage node has a ground voltage, indicating that the DRAM element stores a data bit of zero.

如申請專利範圍第1項所記載之非揮發性動態隨機存取記憶體單元，其中該第二板狀電極被偏壓至一接地電壓或一低操作電壓的一半。 The non-volatile dynamic random access memory cell according to claim 1, wherein the second plate electrode is biased to a ground voltage or a half of a low operating voltage.

如申請專利範圍第1項所記載之非揮發性動態隨機存取記憶體單元，其中該非揮發性動態隨機存取記憶體單元形成一非揮發性動態隨機存取記憶體單元陣列(cell array)的一單元。 The non-volatile dynamic random access memory unit according to claim 1, wherein the non-volatile DRAM unit forms a non-volatile DRAM cell array. One unit.

一種非揮發性動態隨機存取記憶體單元的操作方法，用以將儲存於單一非揮發性記憶體元件的資料位元載入至單一動態隨機存取記憶體元件，該單一非揮發性記憶體元件包含一電荷儲存材質、一控制閘極電極、一源極電極、一汲極電極以及一基底電極，該動態隨機存取記憶體元件包含一存取電晶體以及一儲存電容器，該儲存電容器包含一第一板狀電極以及一第二板狀電極，該存取電晶體的汲極電極、該非揮發性記憶體元件的汲極電極以及該第一板狀電極形成一儲存節點，該第二板狀電極被偏壓至一參考電壓，該方法包含以下循序步驟：將該儲存電容器充電至一低操作電壓；切斷該存取電晶體；將該非揮發性記憶體元件的源極電極耦接至一接地端；以及施加一偏壓V_g至該非揮發性記憶體元件的控制閘極電極；其中，V_th1<V_g<V_thh，以及V_th1和V_thh分別代表該非揮發性記憶體元件的低臨界電壓和高臨界電壓；其中，該單一非揮發性記憶體元件僅包含有四個電極。 A method for operating a non-volatile DRAM cell for loading data bits stored in a single non-volatile memory device into a single DRAM device, the single non-volatile memory The device includes a charge storage material, a control gate electrode, a source electrode, a drain electrode, and a base electrode, the dynamic random access memory device includes an access transistor and a storage capacitor, the storage capacitor includes a first plate electrode and a second plate electrode, the drain electrode of the access transistor, the drain electrode of the non-volatile memory element, and the first plate electrode form a storage node, the second plate The electrode is biased to a reference voltage, the method comprising the steps of: charging the storage capacitor to a low operating voltage; cutting the access transistor; coupling the source electrode of the non-volatile memory element to a ground terminal; and a bias voltage V _g applied to the control gate electrode of the non-volatile memory element; wherein V _th1 <V _g <V _thh , and V _th1 and V _thh respectively Representing a low threshold voltage and a high threshold voltage of the non-volatile memory component; wherein the single non-volatile memory component contains only four electrodes.

如申請專利範圍第7項之方法，其中當該非揮發性記憶體元件在該低臨界電壓狀態時，該非揮發性記憶體元件被導通，而使得該儲存電容器放電，導致該儲存節點在施加該偏壓V_g的步驟期間內具有一接地電壓。 The method of claim 7, wherein when the non-volatile memory element is in the low threshold voltage state, the non-volatile memory element is turned on, causing the storage capacitor to discharge, causing the storage node to apply the bias There is a ground voltage during the step of pressing V _g .

如申請專利範圍第7項之方法，其中當該非揮發性記憶體元件在該高臨界電壓狀態時，該非揮發性記憶體元件被切斷，而使得該儲存節點在施加該偏壓V_g至該控制閘極電極的步驟期間內，保持在該低操作電壓。 The method according to Claim 7 patentable scope, wherein the non-volatile memory when the element is in the high threshold voltage state, the non-volatile memory element is cut, so that the storage node and the bias voltage V _g applied to the The low operating voltage is maintained during the step of controlling the gate electrode.

如申請專利範圍第7項之方法，更包含：在施加該電壓偏壓V_g至該控制閘極電極的步驟之後，施加一接地電壓至該非揮發性記憶體元件的控制閘極電極。 The method according to Claim 7 patentable scope, further comprising: after the step of applying the voltage V bias to the control electrode _g to the gate, a ground voltage is applied to the control gate of the nonvolatile memory element electrode.

如申請專利範圍第10項之方法，更包含：在施加該接地電壓的步驟之後，將該接地電壓隔離開該非揮發性記憶體元件的控制閘極電極和源極電極。 The method of claim 10, further comprising: after the step of applying the ground voltage, isolating the ground voltage from the control gate electrode and the source electrode of the non-volatile memory element.

如申請專利範圍第7項之方法，其中該充電步驟包含：導通該存取電晶體以及提供該低操作電壓至該存取電晶體的源極電極，藉以將該儲存電容器充電至該低操作電壓。 The method of claim 7, wherein the charging step comprises: turning on the access transistor and providing the low operating voltage to a source electrode of the access transistor, thereby charging the storage capacitor to the low operating voltage .

如申請專利範圍第7項之方法，其中該參考電壓係一接地電壓或該低操作電壓的一半。 The method of claim 7, wherein the reference voltage is a ground voltage or half of the low operating voltage.

一種非揮發性動態隨機存取記憶體單元的操作方法，用以將單一動態隨機存取記憶體元件的資料位元儲存至單一非揮發性記憶體元件，該單一非揮發性記憶體元件包含一電荷儲存材質、一控制閘極電極、一源極電極、一汲極電極以及一基底電極，該動態隨機存取記憶體元件包含一存取電晶體以及一儲存電容器，該儲存電容器包含一第一板狀電極以及一第二板狀電極，該存取電晶體的汲極電極、該非揮發性記憶體元件的汲極電極以及該第一板狀電極形成一儲存節點，該第二板狀電極被偏壓至一參考電壓，該方法包含以下循序步驟：將該非揮發性記憶體元件抹除至一低臨界電壓狀態；提供一接地電壓以及一低操作電壓之其一給該儲存節點；以及分別施加一高電壓偏壓、該接地電壓和一負電壓至該非揮發性記憶體元件的控制閘極電極、源極電極和基底電極，使得該非揮發性記憶體元件根據該儲存節點之電壓具有對應的臨界電壓；其中，該單一非揮發性記憶體元件僅包含有四個電極。 A method for operating a non-volatile DRAM memory unit for storing data bits of a single DRAM device to a single non-volatile memory device, the single non-volatile memory device including a charge storage material, a control gate electrode, a source electrode, a drain electrode, and a base electrode, the dynamic random access memory device includes an access transistor and a storage capacitor, the storage capacitor includes a first a plate electrode and a second plate electrode, the drain electrode of the access transistor, the drain electrode of the non-volatile memory element, and the first plate electrode form a storage node, and the second plate electrode is Biasing to a reference voltage, the method comprising the steps of: erasing the non-volatile memory component to a low threshold voltage state; providing a ground voltage and a low operating voltage to the storage node; Applying a high voltage bias, the ground voltage, and a negative voltage to the control gate electrode, the source electrode, and the base electrode of the non-volatile memory element, respectively, such that the non-volatile memory element has a corresponding voltage according to the storage node The threshold voltage; wherein the single non-volatile memory element contains only four electrodes.

如申請專利範圍第14項之方法，其中在分別施加該高電壓偏壓、該接地電壓和該負電壓的步驟之後，當該儲存節點具該低操作電壓時，該非揮發性記憶體元件被程式化至一高臨界電壓狀態；以及其中，當該儲存節點具該接地電壓時，該非揮發性記憶體元件係維持在該低臨界電壓狀態。 The method of claim 14, wherein the non-volatile memory component is programmed when the storage node has the low operating voltage after the step of applying the high voltage bias, the ground voltage, and the negative voltage, respectively. And a high threshold voltage state; and wherein the non-volatile memory component is maintained at the low threshold voltage state when the storage node has the ground voltage.

如申請專利範圍第15項之方法，其中當該非揮發性記憶體元件在該低臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為0；以及，其中當該非揮發性記憶體元件在該高臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為1。 The method of claim 15, wherein when the non-volatile memory element is in the low threshold voltage state, the non-volatile memory element stores a data bit of 0; and wherein the non-volatile memory When the component is in the high threshold voltage state, it indicates that the non-volatile memory component stores a data bit of one.

如申請專利範圍第14項之方法，其中該參考電壓係一接地電壓或該低操作電壓的一半。 The method of claim 14, wherein the reference voltage is a ground voltage or half of the low operating voltage.

一種記憶體單元陣列，包含：複數個非揮發性動態隨機存取記憶體(NVDRAM)單元，被配置為具有行(column)與列(row)之電路組態，沿著一個行之方向，每隔一列配置一個非揮發性動態隨機存取記憶體單元，以及沿著一個列之方向，每隔一行配置一個非揮發性動態隨機存取記憶體單元，各該非揮發性動態隨機存取記憶體單元，包含：單一非揮發性記憶體元件，包含一電荷儲存材質、一控制閘極電極、一第一源極電極、一第一汲極電極以及一基底電極；以及單一動態隨機存取記憶體元件，包含：一存取電晶體，包含一閘極電極、一第二源極電極以及一第二汲極電極；以及一儲存電容器，包含一第一板狀電極以及一第二板狀電極，其中該第一板狀電極、該第一汲極電極以及該第二汲極電極形成一儲存節點；複數條位元線，用以連接該記憶體單元陣列中各行非揮發性動態隨機存取記憶體單元的第二源極電極；複數條字元線，用以連接該記憶體單元陣列的各列非揮發性動態隨機存取記憶體單元的閘極電極；複數條控制閘極線，用以連接該記憶體單元陣列中各列非揮發性動態隨機存取記憶體單元的控制閘極電極；以及複數條共源極線，每一條共源極線連接該記憶體單元陣列的兩相鄰列的非揮發性動態隨機存取記憶體單元的第一源極電極，使得該兩相鄰列的非揮發性動態隨機存取記憶體單元分享一條共源極線；其中，該些共源極線連接至一接地端；其中，該單一非揮發性記憶體元件僅包含有四個電極；以及其中，施加於該第一源極電極的電壓係小於或等於該第一汲極電極的電壓。 A memory cell array comprising: a plurality of non-volatile dynamic random access memory (NVDRAM) cells configured to have a circuit configuration of columns and rows, along a row direction, each Configuring a non-volatile DRAM cell in a column, along the direction of a column, every Configuring a non-volatile DRAM cell in a row, each non-volatile DRAM cell comprising: a single non-volatile memory component, including a charge storage material, a control gate electrode, and a first a source electrode, a first drain electrode and a base electrode; and a single dynamic random access memory device, comprising: an access transistor comprising a gate electrode, a second source electrode, and a second a drain electrode; and a storage capacitor comprising a first plate electrode and a second plate electrode, wherein the first plate electrode, the first drain electrode and the second electrode form a storage node; a plurality of bit lines for connecting the second source electrodes of each row of non-volatile DRAM cells in the memory cell array; a plurality of word lines for connecting the columns of the memory cell array a gate electrode of a non-volatile dynamic random access memory cell; a plurality of control gate lines for connecting each column of the non-volatile dynamic random access memory in the memory cell array a control gate electrode of the cell; and a plurality of common source lines, each of the common source lines connecting the first source electrodes of the two adjacent columns of the non-volatile DRAM cells of the memory cell array, Having the two adjacent columns of non-volatile DRAM cells share a common source line; wherein the common source lines are connected to a ground terminal; wherein the single non-volatile memory component only includes There are four electricity And a voltage applied to the first source electrode is less than or equal to a voltage of the first drain electrode.

如申請專利範圍第18項所記載之記憶體單元陣列，其中當該些非揮發性記憶體元件被切斷時，該記憶體單元陣列的運作如同習知動態隨機存取記憶體單元陣列。 The memory cell array of claim 18, wherein the memory cell array operates as a conventional dynamic random access memory cell array when the non-volatile memory components are turned off.

如申請專利範圍第18項所記載之記憶體單元陣列，其中當一非揮發性記憶體元件在一低臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為0；以及，其中當一非揮發性記憶體元件在一高臨界電壓狀態時，表示該非揮發性記憶體元件儲存一資料位元為1。 The memory cell array of claim 18, wherein when a non-volatile memory component is in a low threshold voltage state, the non-volatile memory component stores a data bit of 0; When a non-volatile memory component is in a high threshold voltage state, it indicates that the non-volatile memory component stores a data bit of one.

如申請專利範圍第18項所記載之記憶體單元陣列，其中在一儲存模式的開始階段時，與一條被選擇字元線相關的複數個被選擇的非揮發性記憶體元件最初是在一低臨界電壓狀態。 The memory cell array of claim 18, wherein at the beginning of a storage mode, a plurality of selected non-volatile memory elements associated with a selected word line are initially at a low level Threshold voltage state.

如申請專利範圍第21項所記載之記憶體單元陣列，其中在該儲存模式結束階段，當一個被選擇的儲存節點具一低操作電壓時，其相對應之非揮發性記憶體元件被程式化至一高臨界電壓狀態，以及，其中當一個被選擇的儲存節點具一接地電壓時，其相對應之非揮發性記憶體元件仍維持在該低臨界電壓狀態。 The memory cell array of claim 21, wherein at the end of the storage mode, when a selected storage node has a low operating voltage, the corresponding non-volatile memory component is programmed To a high threshold voltage state, and wherein when a selected storage node has a ground voltage, its corresponding non-volatile memory component remains in the low threshold voltage state.

如申請專利範圍第18項所記載之記憶體單元陣列，其中在一載入模式的開始階段時，與一條被選擇字元線相關的複數個被選擇的存取電晶體被導通，以及與該條被選擇字元線相關的複數個被選擇的儲存電容器最初被充電至一低操作電壓。 The memory cell array of claim 18, wherein a plurality of selected access transistors associated with a selected word line are turned on at the beginning of a load mode, and A plurality of selected storage capacitors associated with the selected word line are initially charged to a low operating voltage.

如申請專利範圍第23項所記載之記憶體單元陣列，其中，於該載入模式中，在該些被選擇的儲存電容器最初被充電至該低操作電壓以及在該些被選擇的存取電晶體被切斷之後，具該低臨界電壓狀態的相對應被選擇的非揮發性記憶體元件被導通，使其相對應之儲存電容器放電，導致相對應之儲存節點具有一接地電壓。 The memory cell array of claim 23, wherein in the loading mode, the selected storage capacitors are initially charged to the low operating voltage and the selected access powers After the crystal is turned off, the corresponding selected non-volatile memory element having the low threshold voltage state is turned on to discharge the corresponding storage capacitor, resulting in a corresponding ground node having a ground voltage.

如申請專利範圍第23項所記載之記憶體單元陣列，其中，於該載入模式中，在該些被選擇的儲存電容器最初被充電至該低操作電壓以及在該些被選擇的存取電晶體被切斷之後，具該高臨界電壓狀態的相對應被選擇的非揮發性記憶體元件被切斷，使相對應之儲存節點保持該低操作電壓。 The memory cell array of claim 23, wherein in the loading mode, the selected storage capacitors are initially charged to the low operating voltage and the selected access powers After the crystal is severed, the corresponding selected non-volatile memory component having the high threshold voltage state is turned off, causing the corresponding storage node to maintain the low operating voltage.

如申請專利範圍第18項所記載之記憶體單元陣列，其中於記憶體單元陣列中，所有非揮發性動態隨機存取記憶體單元之儲存電容器的第二板狀電極形成單一共板。 The memory cell array according to claim 18, wherein in the memory cell array, the second plate electrodes of the storage capacitors of all the non-volatile DRAM cells form a single common plate.

如申請專利範圍第18項所記載之記憶體單元陣列，其中所有非揮發性動態隨機存取記憶體單元之儲存電容器的第二板狀電極被偏壓至一接地電壓或一低操作電壓的一半。 The memory cell array of claim 18, wherein the second plate electrode of the storage capacitor of all the non-volatile DRAM cells is biased to a ground voltage or a low operating voltage .