TWI530992B - Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same - Google Patents
Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same Download PDFInfo
- Publication number
- TWI530992B TWI530992B TW102135356A TW102135356A TWI530992B TW I530992 B TWI530992 B TW I530992B TW 102135356 A TW102135356 A TW 102135356A TW 102135356 A TW102135356 A TW 102135356A TW I530992 B TWI530992 B TW I530992B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor substrate
- bit line
- mask
- structures
- trench
- Prior art date
Links
Description
本發明涉及一種半導體製程技術，特別是指一種可應用在記憶體元件上的以免光罩方式定義位元線溝槽之半導體基底及其製造方法。 The present invention relates to a semiconductor process technology, and more particularly to a semiconductor substrate that can be applied to a memory device to define a bit line trench in a reticle-free manner and a method of fabricating the same.
記憶體，顧名思義是用來儲存資料/數據的半導體元件，一般在數位資料的儲存上習慣以位元(Bit)表示記憶體的容量，而記憶體內每個用於儲存資料的單元則是稱為記憶胞(cell)。隨著電腦微處理器的功能愈來愈複雜，軟體程式所進行的運算也愈來愈龐大，故記憶體的製作技術已成為半導體產業所不可忽略的重要技術之一。動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)係屬於一種揮發性記憶體，其為多個記憶胞所組成，每一個記憶胞包含一個電晶體與一個電容器，且每一個記憶胞係藉由字元線(Word Line,WL)與位元線(Bit Line,BL)彼此電性連接。 Memory, as the name suggests, is a semiconductor component used to store data/data. Generally, in the storage of digital data, it is customary to use Bit to represent the capacity of the memory, and each unit in the memory for storing data is called Memory cell. As the functions of computer microprocessors become more and more complex, the computing operations of software programs are becoming more and more large. Therefore, the memory technology has become one of the important technologies that the semiconductor industry cannot ignore. Dynamic Random Access Memory (DRAM) is a kind of volatile memory, which is composed of multiple memory cells. Each memory cell contains a transistor and a capacitor, and each memory cell borrows It is electrically connected to each other by a word line (WL line) and a bit line (Bit Line, BL).
隨著半導體結構設計規則的複雜化，光學微影蝕刻技術勢必會朝向更小的線寬發展。對現今微影製程而言，在相同晶圓面積中元件密度提高(圖案的複雜度提高)以及線寬、線距大幅縮減的前提下，對準精確度的要求也變的越來越高。習知微影製程係在待蝕刻材料層上形成一層光阻層，之後再以投影曝光方式 (Projection)，將光罩(Photo mask)上的圖案(Pattern)以重複且步進(Step and repeat)或步進且掃描(Step and scan)方式轉移到晶圓上。 With the complication of semiconductor structure design rules, optical micro-etching technology is bound to develop toward smaller line widths. For today's lithography processes, the alignment accuracy is becoming higher and higher with the increase in component density (increased pattern complexity) and the sharp reduction in line width and line pitch in the same wafer area. The conventional lithography process forms a photoresist layer on the material layer to be etched, and then uses a projection exposure method. (Projection), the pattern on the photo mask is transferred to the wafer in a step and repeat or step and scan manner.
惟，基於上述製程所形成的圖案雖具有較佳的解析度，但此微影製程的複雜度高，且會受制於光罩對準位置、放大倍數(Magnification)誤差、步進機(stepper)和掃描機(Scanner)的對準正確性以及機械裝置間之搭配等問題，導致製程的裕度(Process window)變得更加緊縮，從而增加了對準上的困難度，甚至在製程上有可能造成缺陷(Defect)。 However, although the pattern formed by the above process has better resolution, the lithography process has high complexity and is subject to the reticle alignment position, Magnification error, stepper. The correct alignment of the scanner and the matching between the mechanical devices have caused the process window to become tighter, which increases the difficulty of alignment and even the process. Defect.
此外，金屬-絕緣物-金屬(metal-insulator-metal,MIM)電容器係眾多類型的電容器中常用的一種，但製作MIM電容器通常需要三層以上的光罩以及繁複的製程，因而容易對製程良率有不良影響(因為繁複的製程是良率降低的潛在性原因之一)。因此，對MIM電容器的製程而言，在減少光罩的使用上有著迫切的需求。 In addition, metal-insulator-metal (MIM) capacitors are commonly used in many types of capacitors, but MIM capacitors usually require more than three layers of masks and complicated processes, making it easy to process. Rates have an adverse effect (because complex processes are one of the potential causes of yield reduction). Therefore, there is an urgent need for reducing the use of the mask for the process of the MIM capacitor.
本發明針對現有技術存在之缺失，提出一種以免光罩方式定義位元線溝槽之半導體基底及其製造方法，可降低對光罩的需求數量，以及可避免因光罩未對準(Mis-alignment)造成電容器的預定成型區域面積過小或位置偏移。 The present invention is directed to the absence of the prior art, and proposes a semiconductor substrate for defining a bit line trench in a mask-free manner and a method of fabricating the same, which can reduce the number of required masks and avoid misalignment of the mask (Mis- Alignment) causes the area of the predetermined molding area of the capacitor to be too small or offset.
為達成上述目的及功效，本發明採用以下技術方案：一種以免光罩方式定義位元線溝槽之半導體基底的製造方法，包括以下步驟：首先，提供一半導體基材，具有複數個深溝槽；接著，形成複數個絕緣結構於該半導體基材上，每一絕緣結構具有一隔離部及一突出部，該些隔離部位於該些深溝槽內，該些突出部位於該些隔離部上且溢出部分覆蓋該半導體基材，其中相鄰的兩突出部之間定義出一位元線區域；然後，形成一犧牲層於該些突出部及該些位元線區域上，該犧牲層具有複數個開口；之後，形成複 數個遮蔽結構於該些開口內；最後，以該些遮蔽結構為自對準罩幕，選擇性地移除部分該犧牲層及該半導體基材，以於每一位元線區域內形成兩位元線溝槽。 In order to achieve the above object and effect, the present invention adopts the following technical solution: a method for manufacturing a semiconductor substrate for defining a bit line trench in a mask-free manner, comprising the steps of: firstly, providing a semiconductor substrate having a plurality of deep trenches; Then, a plurality of insulating structures are formed on the semiconductor substrate, each of the insulating structures has a partition portion and a protrusion portion, and the partition portions are located in the deep trenches, and the protrusion portions are located on the plurality of isolation portions and overflow Partially covering the semiconductor substrate, wherein a single-element region is defined between two adjacent protrusions; then, a sacrificial layer is formed on the protrusions and the bit line regions, and the sacrificial layer has a plurality of Opening; afterwards, forming a complex a plurality of shielding structures are disposed in the openings; and finally, the shielding structures are self-aligned masks, and a portion of the sacrificial layer and the semiconductor substrate are selectively removed to form two in each bit line region Bit line groove.
基於上述方法，本發明還提供一種以免光罩方式定義位元線溝槽之半導體基底，其包括一半導體基材、複數個絕緣結構、一犧牲層及複數個遮蔽結構。其中該半導體基材具有複數個深溝槽；該些絕緣結構係平行間隔設置於該半導體基材上，每一絕緣結構具有一隔離部及一突出部，該些隔離部位於該些深溝槽內，該些突出部位於該些隔離部上且溢出部分覆蓋該半導體基材，其中相鄰的兩突出部之間定義出一位元線區域；該犧牲層係覆蓋該些突出部及該些位元線區域，該犧牲層具有複數個開口；該些遮蔽結構係位於該些開口內。 Based on the above method, the present invention also provides a semiconductor substrate for defining a bit line trench in a mask-free manner, comprising a semiconductor substrate, a plurality of insulating structures, a sacrificial layer and a plurality of shielding structures. The semiconductor substrate has a plurality of deep trenches; the insulating structures are disposed on the semiconductor substrate in parallel, each insulating structure has a partition and a protrusion, and the spacers are located in the deep trenches. The protrusions are located on the spacers and the overflow portion covers the semiconductor substrate, wherein a bit line region is defined between the adjacent two protrusions; the sacrificial layer covers the protrusions and the bits In the line region, the sacrificial layer has a plurality of openings; the shielding structures are located within the openings.
採用的製造方法，不需要使用光罩即可準確定義出主動區及其中之位元線溝槽、電容器及位元線接觸窗預定成型區域，因此可降低對光罩的需求以節省製程成本。再者，由於絕緣結構之突出部與遮蔽結構可共同當作自對準罩幕，因此可進一步防止電容器、位元線接觸窗等預定成型區域因為光罩未對準而造成位置偏移、面積過小，進而可有效提升製程良率，且有助於記憶體元件之微型化。 The manufacturing method can accurately define the active region and the bit line trenches, capacitors and bit line contact window predetermined molding areas without using a mask, thereby reducing the need for the mask to save process cost. Furthermore, since the protruding portion of the insulating structure and the shielding structure can be used together as a self-aligning mask, it is possible to further prevent a predetermined molding area such as a capacitor or a bit line contact window from being displaced due to misalignment of the mask. Too small, which can effectively improve the process yield and contribute to the miniaturization of memory components.
以上關於本發明內容的說明以及以下實施方式的說明係用以舉例並解釋本創作的原理，並且提供本發明之專利申請範圍進一步的解釋。 The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the principles of the present invention, and provide further explanation of the scope of the patent application of the present invention.
10‧‧‧半導體基材 10‧‧‧Semiconductor substrate
DT‧‧‧深溝槽 DT‧‧ deep trench
11‧‧‧基底 11‧‧‧Base
12‧‧‧氧化層 12‧‧‧Oxide layer
13‧‧‧硬遮罩層 13‧‧‧hard mask layer
ST‧‧‧淺溝槽 ST‧‧‧ shallow trench
14‧‧‧圖案化光阻層 14‧‧‧ patterned photoresist layer
20‧‧‧絕緣結構 20‧‧‧Insulation structure
21‧‧‧隔離部 21‧‧‧Isolation Department
22‧‧‧突出部 22‧‧‧Protruding
22a‧‧‧內端部 22a‧‧‧Inside
22b‧‧‧外端部 22b‧‧‧Outside
220b‧‧‧緩坡結構 220b‧‧‧Slope structure
23‧‧‧位元線區域 23‧‧‧ bit line area
30‧‧‧犧牲層 30‧‧‧sacrificial layer
31‧‧‧開口 31‧‧‧ openings
40‧‧‧遮蔽結構 40‧‧‧Shielding structure
50‧‧‧位元線溝槽 50‧‧‧ bit line trench
AA‧‧‧主動區域 AA‧‧‧active area
C‧‧‧電容器預定成型區域 C‧‧‧Capacitor intended molding area
BLC‧‧‧位元線接觸窗預定成型區域 BLC‧‧‧ bit line contact window intended molding area
圖1為本發明之以免光罩方式定義位元線溝槽之半導體基底的製造方法之流程示意圖。 1 is a schematic flow chart of a method for fabricating a semiconductor substrate in which a bit line trench is defined in a mask-free manner according to the present invention.
圖2至8為本發明之以免光罩方式定義位元線溝槽之半導體基底的製造方法之製程示意圖。 2 to 8 are schematic diagrams showing the process of fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner according to the present invention.
本揭露書提出一種以免光罩方式定義位元線溝槽之半導體基底的製造方法，其通過特殊製程設計，可利用自對準機制在半導體基材上形成沿相同方向延伸之複數隔離結構及位元線溝槽而不需使用光罩。值得一提的是，本發明之方法在形成位元線溝槽的同時，可進一步定義出電容器(Capacitor)及位元線接觸窗(BL contact)預定成型區域，因此能夠防止預定成型區域因為光罩未對準而造成位置偏移、面積過小。 The present disclosure proposes a method for fabricating a semiconductor substrate in which a bit line trench is defined in a mask-free manner, which can form a plurality of isolation structures and bits extending in the same direction on a semiconductor substrate by a self-alignment mechanism through a special process design. The element line trenches do not require the use of a reticle. It is worth mentioning that the method of the present invention can further define a predetermined molding area of a capacitor (capacitor) and a bit line contact window (BL contact) while forming a bit line trench, thereby preventing a predetermined molding area from being blocked. The cover is misaligned and the position is shifted and the area is too small.
請參考圖1，係為本發明之以免光罩方式定義位元線溝槽之半導體基底的製造方法之流程示意圖，並請配合參考圖2至7，係分別為對應該製造方法之各步驟之製程示意圖。下文特舉一較佳實施例並配合所附圖式對本發明之製造方法作詳細說明如下。 Please refer to FIG. 1 , which is a schematic flow chart of a method for manufacturing a semiconductor substrate for defining a bit line trench in a mask-free manner according to the present invention, and referring to FIG. 2 to FIG. 7 respectively, which are respectively corresponding to the steps of the manufacturing method. Process schematic. The manufacturing method of the present invention will be described in detail below with reference to a preferred embodiment and the accompanying drawings.
首先，執行步驟S10，提供一半導體基材10，其具有複數個深溝槽DT(如圖2所示)，其中相鄰之兩深溝槽DT相隔一預定距離，提供後續步驟定義出主動區域AA(active area)。在本實施例中，預定距離約介於1000至1500Å之間，但本發明並不以此為限，所述之預定距離可根據製程需求而有所調整。 First, step S10 is performed to provide a semiconductor substrate 10 having a plurality of deep trenches DT (shown in FIG. 2), wherein the adjacent two deep trenches DT are separated by a predetermined distance, providing a subsequent step to define the active region AA ( Active area). In the present embodiment, the predetermined distance is between about 1000 and 1500 Å, but the invention is not limited thereto, and the predetermined distance may be adjusted according to the process requirements.
具體地說，半導體基材10依序為一基底11、一墊層12、一硬遮罩層13及一圖案化光阻層14堆疊所構成，而形成深溝槽DT的方法包括以下步驟：首先提供基底11，接著在基底11上形成墊層12，在墊層12上形成硬遮罩層13，並在硬遮罩層13上形成圖案化光阻層14，然後移除未被圖案化光阻層14遮蔽的部分。在本實施例中，基底11例如是一多晶矽基底，墊層12例如是墊氧化層(pad oxide)或墊氮化層(pad nitride)，硬遮罩層13的材質可包括氧化矽、氮化矽或其組合，但本發明並不以此為限，所述之堆疊結構之各層材質可根據蝕刻選擇比(Selectivity)而有所調整。 Specifically, the semiconductor substrate 10 is sequentially formed by stacking a substrate 11, a pad layer 12, a hard mask layer 13, and a patterned photoresist layer 14. The method for forming the deep trench DT includes the following steps: A substrate 11 is provided, then a pad layer 12 is formed on the substrate 11, a hard mask layer 13 is formed on the pad layer 12, and a patterned photoresist layer 14 is formed on the hard mask layer 13, and then unpatterned light is removed. The portion of the resist layer 14 that is shielded. In this embodiment, the substrate 11 is, for example, a polysilicon substrate, and the pad layer 12 is, for example, a pad oxide or a pad nitride. The material of the hard mask layer 13 may include ruthenium oxide and nitridation.矽 or a combination thereof, but the invention is not limited thereto, and the material of each layer of the stacked structure can be adjusted according to the etching selectivity.
接著，執行步驟S12，在半導體基材10上形成複數個絕緣結構20(如圖5所示)，每一個絕緣結構20具有一隔離部21及一突 出部22，其中該些隔離部21係位於該些深溝槽DT內，該些突出部22係位於該些隔離部21上，且溢出部分覆蓋半導體基材10；值得說明的是，相鄰之兩突出部22之間可定義出一位元線區域23，以便於在後續步驟中以免光罩方式製作位元線溝槽(未繪示)。 Next, step S12 is performed to form a plurality of insulating structures 20 (shown in FIG. 5) on the semiconductor substrate 10. Each of the insulating structures 20 has a partition 21 and a protrusion. The portion 22, wherein the spacers 21 are located in the deep trenches DT, the protrusions 22 are located on the spacers 21, and the overflow portion covers the semiconductor substrate 10; it is worth noting that adjacent A one-dimensional line region 23 may be defined between the two protrusions 22 to facilitate the fabrication of bit line trenches (not shown) in a mask-free manner in a subsequent step.
具體地說，該些絕緣結構20係利用自對準方式形成，所採用的方法包括以下步驟：首先移除步驟S10殘留之圖案化光阻層14，接著以選擇性蝕刻方式對硬遮罩層13進行圖案化(如圖3所示)以形成複數個淺溝槽ST，該些淺溝槽ST係分別與該些深溝槽DT相對應且淺溝槽ST之內徑大於深溝槽DT之內徑，然後填充絕緣材料於每一深溝槽DT及其相對應之深溝槽DT內(如圖4所示)，最後再移除圖案化之硬遮罩層13(如圖5所示)。在本實施例中，絕緣材料例如是氧化物或氮氧化物，但本發明並不以此為限。 Specifically, the insulating structures 20 are formed by a self-aligned method, and the method includes the steps of first removing the patterned photoresist layer 14 remaining in step S10, and then selectively etching the hard mask layer. 13 is patterned (as shown in FIG. 3) to form a plurality of shallow trenches ST corresponding to the deep trenches DT, respectively, and the inner diameter of the shallow trenches ST is larger than the inner deep trenches DT The via is then filled with an insulating material in each deep trench DT and its corresponding deep trench DT (as shown in FIG. 4), and finally the patterned hard mask layer 13 is removed (as shown in FIG. 5). In the present embodiment, the insulating material is, for example, an oxide or an oxynitride, but the invention is not limited thereto.
更詳細地說，每一個絕緣結構20之突出部22可進一步區分成一內端部22a及至少一外端部22b，其中內端部22a係由隔離部21朝遠離半導體基材10的方向延伸成型，外端部22b係位於內端部22a之至少一側，以覆蓋隔離部21之至少一側的部分半導體基材10。藉此，本發明在利用自對準方式形成絕緣結構20的同時，也定義出了電容器預定成型區域C(landing area)。 In more detail, the protruding portion 22 of each of the insulating structures 20 can be further divided into an inner end portion 22a and at least one outer end portion 22b, wherein the inner end portion 22a is formed by the partition portion 21 extending away from the semiconductor substrate 10 The outer end portion 22b is located on at least one side of the inner end portion 22a to cover a portion of the semiconductor substrate 10 on at least one side of the partition portion 21. Thereby, the present invention also defines a predetermined molding area C of the capacitor while forming the insulating structure 20 by self-alignment.
然後，執行步驟S14及S16，係先在該些絕緣結構20及位元線區域23上沉積一層犧牲層30，且所述之犧牲層30可界定出複數個暴露於該些絕緣結構20之間的開口31(如圖6所示)，再形成複數個遮蔽結構40於該些開口31內(如圖7所示)。具體地說，犧牲層30係經由原子沉積製程(Atomic layer deposition,ALD)所形成，其優點在於，犧牲層30的厚度可控制在Å等級且均勻性極佳。進一步地，為使犧牲層30可共形地覆蓋在絕緣結構20之外表面，以確保開口31呈立方狀，每一個絕緣結構20之外端部22b上可形成一緩坡結構220b(如圖6a所示)。 Then, steps S14 and S16 are performed to deposit a sacrificial layer 30 on the insulating structures 20 and the bit line regions 23, and the sacrificial layer 30 can define a plurality of exposures between the insulating structures 20. The opening 31 (shown in FIG. 6) further forms a plurality of shielding structures 40 in the openings 31 (as shown in FIG. 7). Specifically, the sacrificial layer 30 is formed by Atomic layer deposition (ALD), which has an advantage in that the thickness of the sacrificial layer 30 can be controlled at Å level and the uniformity is excellent. Further, in order to make the sacrificial layer 30 conformally cover the outer surface of the insulating structure 20 to ensure that the opening 31 has a cubic shape, a gentle slope structure 220b may be formed on the outer end portion 22b of each insulating structure 20 (as shown in FIG. 6a). Shown).
在本實施例中，犧牲層30的材質例如是氮化矽，但本發明並不以此為限；需要注意的是，犧牲層30必須和基底11同時選擇為富含矽的材質，以利在同一蝕刻步驟中將兩者同時移除，並且遮蔽結構40必須和絕緣結構20同時選擇為富含氧化物的材質，以利在該蝕刻步驟中起到阻擋作用。但是在一變化實施例中，犧牲層30也可以和基底11同時選擇為富含氧化物的材質，遮蔽結構40則可以和絕緣結構20同時選擇為富含矽的材質。 In this embodiment, the material of the sacrificial layer 30 is, for example, tantalum nitride, but the invention is not limited thereto; it should be noted that the sacrificial layer 30 must be selected as a material rich in germanium at the same time as the substrate 11 to facilitate Both are removed simultaneously in the same etching step, and the shielding structure 40 must be selected as an oxide-rich material simultaneously with the insulating structure 20 to facilitate blocking in the etching step. However, in a variant embodiment, the sacrificial layer 30 can also be selected as an oxide-rich material simultaneously with the substrate 11, and the shielding structure 40 can be selected as a germanium-rich material simultaneously with the insulating structure 20.
最後，執行步驟S18，以該些絕緣結構20及遮蔽結構40共同作為自行對準罩幕進行蝕刻(如圖8所示)，以形成複數個位元線溝槽50。具體地說，此步驟所採用的蝕刻方式係為非等向性蝕刻，例如是電漿蝕刻(Plasma etching)或反應性離子蝕刻(Reactive ion etching)，但本發明並不以此為限。 Finally, step S18 is performed to etch the insulating structures 20 and the shielding structures 40 together as a self-aligning mask (as shown in FIG. 8) to form a plurality of bit line trenches 50. Specifically, the etching method used in this step is an anisotropic etching, such as plasma etching or reactive ion etching, but the invention is not limited thereto.
再者，蝕刻反應氣體可選擇使用含溴化氫(HBr)氣體與含氧(O2)氣體之混合氣體。原因在於，含溴化氫氣體對多晶矽材質之基底11與氮化矽材質之犧牲層30具有良好的選擇性，因而可減少蝕刻過程中對其他層的影響。據此，可依序將未被絕緣結構20及遮蔽結構40所遮蔽的犧牲層30及基底11移除，以免光罩方式在每一個位元線區域23內形成兩位元線溝槽50。 Further, the etching reaction gas may be selected from a mixed gas containing hydrogen bromide (HBr) gas and oxygen-containing (O 2 ) gas. The reason is that the hydrogen bromide-containing gas has a good selectivity to the polycrystalline germanium substrate 11 and the tantalum nitride-based sacrificial layer 30, thereby reducing the influence on other layers during the etching process. Accordingly, the sacrificial layer 30 and the substrate 11 not covered by the insulating structure 20 and the shielding structure 40 can be sequentially removed to form the two-dimensional line trench 50 in each of the bit line regions 23 in a reticle manner.
請復參考圖2、5及8，本發明以免光罩方式定義位元線溝槽之半導體基底的製造方法之技術特徵已詳述如上，基於此製造方法可以製作出一種可應用在記憶體元件上之半導體基底，其包括一半導體基材10、複數個絕緣結構20、一犧牲層30及複數個遮蔽結構40(如圖7所示)。 Referring to FIGS. 2, 5 and 8, the technical features of the method for fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner are as described above. Based on the manufacturing method, a memory element can be fabricated. The semiconductor substrate includes a semiconductor substrate 10, a plurality of insulating structures 20, a sacrificial layer 30, and a plurality of shielding structures 40 (shown in FIG. 7).
具體而言，半導體基材10具有複數個深溝槽DT，該些絕緣結構20係平行間隔設置於半導體基材10上，且每一絕緣結構20具有一隔離部21及一突出部22。特別的是，該些隔離部21係分別位於該些深溝槽DT內，可在半導體基材10上定義出複數個主動區預AA；該些突出部22係分別位於該些隔離部21上，溢出部 分則覆蓋部分半導體基材10，如此相鄰之兩突出部22之間定可義出一位元線區域23，且溢出部分可義出複數個電容器預定成型區域C；犧牲層30位於(覆蓋)該些突出部22與該些位元線區域23，且犧牲層30可界定出複數個位於位元線區域23上方的開口31，而該些遮蔽結構40係分別位於該些開口31內。 Specifically, the semiconductor substrate 10 has a plurality of deep trenches DT, and the insulating structures 20 are disposed on the semiconductor substrate 10 in parallel, and each of the insulating structures 20 has a partition portion 21 and a protruding portion 22. In particular, the spacers 21 are respectively located in the deep trenches DT, and a plurality of active regions pre-AA are defined on the semiconductor substrate 10; the protrusions 22 are respectively located on the spacers 21, Overflow The portion covers a portion of the semiconductor substrate 10 such that a single line region 23 is defined between the adjacent two protrusions 22, and the overflow portion can define a plurality of capacitors to form a predetermined molding region C; the sacrificial layer 30 is located (covered) The protrusions 22 and the bit line regions 23, and the sacrificial layer 30 can define a plurality of openings 31 above the bit line regions 23, and the shielding structures 40 are respectively located in the openings 31.
非常明顯地，採用本發明之半導體基底，由於絕緣結構20之突出部22與遮蔽結構40可當作蝕刻過程中的自對準罩幕，因此不需要使用光罩便可準確定義出主動區預AA及其中之兩位元線溝槽50、兩位元線溝槽50間之位元線接觸窗預定成型區域BLC、位元線溝槽50與隔離部21間之電容器預定成型區域C。 Obviously, with the semiconductor substrate of the present invention, since the protruding portion 22 of the insulating structure 20 and the shielding structure 40 can be used as a self-aligning mask in the etching process, the active region can be accurately defined without using a mask. The bit line contact window between the AA and the two-element trench 50 and the two-element trench 50 is intended to form a molding region BLC between the bit line trench 50 and the spacer trench portion 50 and the isolation portion 21.
進一步值得說明的是，本發明的製造方法除了能以免光罩方式定義出位元線溝槽50、位元線接觸窗預定成型區域BLC和電容器預定成型區域C外，還可調整藉由自對準罩幕以調整該等區域的尺寸(dimension)及/或深度(depth)；具體地說，位元線接觸窗預定成型區域BLC的尺寸可經由遮蔽結構40的寬度進行調整，電容器預定成型區域C的尺寸可經由突出部22之外端部22b的寬度進行調整，位元線溝槽50的尺寸則可同時經由遮蔽結構40的寬度與外端部22b的寬度進行調整，並且所有位元線溝槽50的深度均相等。藉此，可以大大提升製程效率及可靠度。 It should be further noted that the manufacturing method of the present invention can be adjusted by the self-alignment except that the bit line trench 50, the bit line contact window predetermined forming area BLC and the capacitor predetermined forming area C can be defined in a mask-free manner. a mask to adjust the dimensions and/or depth of the regions; specifically, the size of the predetermined line forming region BLC of the bit line contact window can be adjusted via the width of the shielding structure 40, the predetermined molding area of the capacitor The size of C can be adjusted via the width of the outer end 22b of the protrusion 22, and the size of the bit line groove 50 can be simultaneously adjusted by the width of the shielding structure 40 and the width of the outer end 22b, and all the bit lines The depths of the grooves 50 are all equal. Thereby, the process efficiency and reliability can be greatly improved.
是以，相較於傳統利用光罩定義出位元線溝槽的製程，本發明之以免光罩方式定義位元線溝槽之半導體基底的製造方法至少具有下列優點： Therefore, the manufacturing method of the semiconductor substrate of the present invention for defining the bit line trenches in a mask-free manner has at least the following advantages compared to the conventional process of defining a bit line trench by using a photomask:
1.本發明所提出之製造方法不需要使用光罩即可準確定義出主動區及其中之位元線溝槽、電容器及位元線接觸窗預定成型區域，可降低對光罩的需求以節省製程成本。 1. The manufacturing method of the present invention can accurately define the active region and the bit line trenches, capacitors and bit line contact window predetermined forming regions without using a mask, thereby reducing the need for the mask to save Process cost.
2.本發明所提出之製造方法可藉絕緣結構之突出部與遮蔽結構共同當作自對準罩幕，因此除了製程簡單外，還可防止電容器、位元線接觸窗等預定成型區域因為光罩未對準而造成位置偏 移、面積過小，進而可有效提升製程良率，且有助於記憶體元件之微型化。 2. The manufacturing method proposed by the invention can be regarded as a self-aligning mask by the protruding portion of the insulating structure and the shielding structure, so that in addition to the simple process, the predetermined molding area such as the capacitor and the bit line contact window can be prevented because of the light. The cover is misaligned and the position is biased The shift and the area are too small, which can effectively improve the process yield and contribute to the miniaturization of the memory components.
3.承上，本發明之半導體基底因為藉由絕緣結構之突出部與遮蔽結構共同當作自對準罩幕，因此很容易透過調整製程參數以控制電容器、位元線接觸窗等預定成型區域的面積，進而由後續步驟所製成之電容器、位元線接觸窗等元件具有良好的一致性。 3. The semiconductor substrate of the present invention is used as a self-aligned mask by the protruding portion of the insulating structure and the shielding structure, so that it is easy to adjust the process parameters to control a predetermined molding region such as a capacitor and a bit line contact window. The area, and thus the capacitors, bit line contact windows and the like made by the subsequent steps have good consistency.
綜上所述，本發明實已符合新型專利之要件，依法提出申請。惟以上所揭露者，僅為本發明較佳實施例而已，自不能以此限定本案的權利範圍，因此依本案申請範圍所做的均等變化或修飾，仍屬本案所涵蓋的範圍。 In summary, the present invention has met the requirements of the new patent and has applied for it according to law. However, the above disclosure is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus the equivalent changes or modifications made in the scope of the present application are still covered by the present application.
10‧‧‧半導體基材 10‧‧‧Semiconductor substrate
30‧‧‧犧牲層 30‧‧‧sacrificial layer
31‧‧‧開口 31‧‧‧ openings
40‧‧‧遮蔽結構 40‧‧‧Shielding structure
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135356A TWI530992B (en) | 2013-09-30 | 2013-09-30 | Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same |
| CN201310487796.3A CN104517955B (en) | 2013-09-30 | 2013-10-17 | Semiconductor substrate and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135356A TWI530992B (en) | 2013-09-30 | 2013-09-30 | Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201513185A TW201513185A (en) | 2015-04-01 |
| TWI530992B true TWI530992B (en) | 2016-04-21 |
Family
ID=52793023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102135356A TWI530992B (en) | 2013-09-30 | 2013-09-30 | Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104517955B (en) |
| TW (1) | TWI530992B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11063051B2 (en) * | 2019-08-07 | 2021-07-13 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
| DE102020119738B4 (en) | 2020-07-27 | 2022-02-03 | Infineon Technologies Dresden GmbH & Co. KG | Process for manufacturing a semiconductor device and semiconductor device with deep trenches |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1107347C (en) * | 1997-08-22 | 2003-04-30 | 世界先进积体电路股份有限公司 | Dynamic random-access storage device structure and mfg. method therefor |
| US7411246B2 (en) * | 2002-04-01 | 2008-08-12 | Silicon Storage Technology, Inc. | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby |
| US7476933B2 (en) * | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
| US8143121B2 (en) * | 2009-10-01 | 2012-03-27 | Nanya Technology Corp. | DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof |
| KR20130005120A (en) * | 2011-07-05 | 2013-01-15 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device with vertical gate |
| JP2013058676A (en) * | 2011-09-09 | 2013-03-28 | Elpida Memory Inc | Semiconductor device and method of manufacturing the same, and data processing system |
-
2013
- 2013-09-30 TW TW102135356A patent/TWI530992B/en active
- 2013-10-17 CN CN201310487796.3A patent/CN104517955B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201513185A (en) | 2015-04-01 |
| CN104517955A (en) | 2015-04-15 |
| CN104517955B (en) | 2017-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9230853B2 (en) | Semiconductor devices having bit line contact plugs and methods of manufacturing the same | |
| US8465908B2 (en) | Method for forming fine patterns of semiconductor device | |
| US8120103B2 (en) | Semiconductor device with vertical gate and method for fabricating the same | |
| TWI477999B (en) | Method for fabricating semiconductor device using spacer patterning technique | |
| TW201814829A (en) | Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines | |
| TWI571915B (en) | Method for manufacturing lower electrode of capacitor and semiconducor device | |
| JP2016033968A (en) | Method of manufacturing semiconductor device | |
| CN113675146A (en) | Semiconductor structure, forming method thereof and memory | |
| CN112447603B (en) | Method for forming semiconductor memory | |
| WO2022205701A1 (en) | Semiconductor structure preparation method and semiconductor structure | |
| WO2021175157A1 (en) | Method for forming active region array, and semiconductor structure | |
| TWI530992B (en) | Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same | |
| JP2016021463A (en) | Semiconductor device manufacturing method | |
| TWI396261B (en) | Low parasitic capacitance bit line process for stack dram | |
| TWI520265B (en) | Method for forming self-aligned trench isolation in semiconductor substrate and semiconductor device | |
| US11862513B2 (en) | Manufacturing method of semiconductor structure | |
| CN112447582B (en) | Method for forming trench isolation structure in substrate | |
| CN114823295A (en) | Method for manufacturing semiconductor device | |
| US20200203176A1 (en) | Manufacturing method for semiconductor pattern | |
| WO2014148423A1 (en) | Semiconductor device and method for producing same | |
| WO2022205730A1 (en) | Fabrication method for semiconductor structure | |
| CN111025845A (en) | Mask plate, capacitor array, semiconductor device and preparation method thereof | |
| US20230056584A1 (en) | Manufacturing method of semiconductor structure | |
| WO2022088734A1 (en) | Method for preparing semiconductor structure, and semiconductor structure | |
| WO2022100131A1 (en) | Semiconductor structure and forming method therefor |