TWI528156B - Computing system having wake-up circuit - Google Patents
Computing system having wake-up circuit Download PDFInfo
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- TWI528156B TWI528156B TW103142783A TW103142783A TWI528156B TW I528156 B TWI528156 B TW I528156B TW 103142783 A TW103142783 A TW 103142783A TW 103142783 A TW103142783 A TW 103142783A TW I528156 B TWI528156 B TW I528156B
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Description
本發明係有關於一種具有喚醒電路的計算機系統,尤指一種計算機系統經延遲時間區間自喚醒狀態轉換至上電狀態之具有喚醒電路的計算機系統。 The present invention relates to a computer system having a wake-up circuit, and more particularly to a computer system having a wake-up circuit that transitions from a wake-up state to a power-up state in a delay time interval.
隨著科技日新月異的進步,網路的發達已使各種電子裝置充斥著人們的生活,而建構網路所需的設備為如計算機系統之伺服器,其中,現有之計算機系統自睡眠狀態轉換至喚醒狀態後,待喚醒裝置需喚醒才可使計算機系統確實上電工作,然而,喚醒待喚醒裝置之必備條件係需要經一延遲時間,當計算機系統內設計之電路未達該延遲時間而觸發喚醒待喚醒裝置時,待喚醒裝置會無法被喚醒而致使計算機系統無法正常上電工作,而現有之計算機系統內所設計之電路一般都無法確保可達延遲時間之此一喚醒條件,因此,現有技術仍具有改善之空間。 With the rapid advancement of technology, the development of the Internet has made various electronic devices full of people's lives, and the devices needed to construct the network are servers such as computer systems, in which the existing computer system switches from sleep state to wake-up. After the state, the wake-up device needs to wake up to enable the computer system to be powered on. However, the necessary condition for waking up the device to be awakened requires a delay time, and when the circuit designed in the computer system fails to reach the delay time, the wake-up is triggered. When the device is woken up, the device to be woken up cannot be woken up, and the computer system cannot be powered on normally. However, the circuit designed in the existing computer system generally cannot ensure the wake-up condition of the delay time. Therefore, the prior art still There is room for improvement.
有鑒於計算機系統中之電路無法確保可達延遲時間而 喚醒待喚醒裝置,普遍具有無法穩定上電工作之問題。緣此,本發明主要係提供一種具有喚醒電路的計算機系統,主要係藉由喚醒電路內之延遲電路確保計算機系統經延遲時間區間喚醒待喚醒裝置,以解決上述之問題。 In view of the fact that circuits in computer systems cannot guarantee reachable delay time Awakening the device to be awakened generally has the problem of not being able to stabilize the power-on work. Accordingly, the present invention mainly provides a computer system having a wake-up circuit, which mainly solves the above problem by ensuring that the computer system wakes up the device to be awakened by a delay time interval by a delay circuit in the wake-up circuit.
基於上述目的,本發明所採用之主要技術手段係提供一種具有喚醒電路的計算機系統,係包含一重置裝置、一喚醒電路以及一待喚醒裝置,重置裝置係發送出一喚醒信號,喚醒電路包含一第一反相邏輯電路、一延遲電路、一與門電路以及一第二反相邏輯電路。第一反相邏輯電路係電性連接於重置裝置,延遲電路係電性連接於第一反相邏輯電路,與門電路係電性連接於第一反相邏輯電路與延遲電路,第二反相邏輯電路係電性連接於與門電路,待喚醒裝置係電性連接於第二反相邏輯電路。其中,第一反相邏輯電路接收重置裝置發出的喚醒信號,並產生一反相喚醒信號,延遲電路接收反相喚醒信號並於一第一延遲時間區間傳送出一反相延遲喚醒信號,與門電路接收喚醒信號與反相延遲喚醒信號進行邏輯與功能處理後傳送出一與門喚醒信號,第二反相邏輯電路接收與門喚醒信號進行反相後傳送出一終端喚醒信號,待喚醒裝置接收終端喚醒信號進行喚醒動作。其中,計算機系統自一睡眠狀態轉換至一喚醒狀態時,重置裝置傳送出處於一第一電平狀態的喚醒信號,經過一第二延遲時間區間後,計算機系統進入一系統上電狀態並且喚醒信號從第一電平狀態轉換至一第二電平狀態。 Based on the above objective, the main technical means adopted by the present invention is to provide a computer system with a wake-up circuit, comprising a reset device, a wake-up circuit and a wake-up device, and the reset device sends a wake-up signal to wake up the circuit. A first inverting logic circuit, a delay circuit, an AND gate circuit and a second inverting logic circuit are included. The first inverting logic circuit is electrically connected to the reset device, the delay circuit is electrically connected to the first inverting logic circuit, and the AND circuit is electrically connected to the first inverting logic circuit and the delay circuit, and the second The phase logic circuit is electrically connected to the AND circuit, and the device to be awakened is electrically connected to the second inverter logic circuit. The first inverting logic circuit receives the wake-up signal sent by the reset device, and generates an inverted wake-up signal, and the delay circuit receives the inverted wake-up signal and transmits an inverted delayed wake-up signal in a first delay time interval, and The gate circuit receives the wake-up signal and the inverted delay wake-up signal for logical and functional processing, and then sends an AND gate wake-up signal, and the second inverted logic circuit receives the AND gate wake-up signal to invert and transmits a terminal wake-up signal, and the wake-up device is to be awakened. The terminal wake-up signal is received to perform a wake-up action. Wherein, when the computer system transitions from a sleep state to an awake state, the reset device transmits a wake-up signal at a first level state, and after a second delay time interval, the computer system enters a system power-on state and wakes up. The signal transitions from a first level state to a second level state.
其中,上述具有喚醒電路的計算機系統之附屬技術手段 之較佳實施例中,在喚醒狀態中,第一反相邏輯電路係接收並反相處於第一電平狀態的喚醒信號,藉以產生並傳送出處於第二電平狀態的反相喚醒信號,延遲電路係接收處於第二電平狀態的反相喚醒信號,並於一第三延遲時間區間傳送出處於第二電平狀態的反相延遲喚醒信號,與門電路接收處於第一電平狀態的喚醒信號與處於第二電平狀態的反相延遲喚醒信號並傳送出處於第一電平狀態的與門喚醒信號,第二反相邏輯電路接收處於第一電平狀態的與門喚醒信號進行反相後輸出處於第二電平狀態的終端喚醒信號至待喚醒裝置。此外,計算機系統進入系統上電狀態並且喚醒信號從第一電平狀態轉換至第二電平狀態時,第一反相邏輯電路接收並反相處於第二電平狀態的喚醒信號,藉以產生並傳送出處於第一電平狀態的反相喚醒信號,延遲電路係接收處於第一電平狀態的反相喚醒信號,並於一第四延遲時間區間傳送出處於第二電平狀態的反相延遲喚醒信號,與門電路接收處於第二電平狀態的喚醒信號與處於第二電平狀態的反相延遲喚醒信號並傳送出一處於第二電平狀態的與門喚醒信號,第二反相邏輯電路接收處於第二電平狀態的與門喚醒信號進行反相後輸出處於第一電平狀態的終端喚醒信號至待喚醒裝置。 Among them, the above-mentioned technical means of the computer system with the wake-up circuit In a preferred embodiment, in the awake state, the first inverting logic circuit receives and inverts the wake-up signal in the first level state, thereby generating and transmitting the inverted wake-up signal in the second level state, The delay circuit receives the inverted wake-up signal in the second level state, and transmits the inverted delayed wake-up signal in the second level state in a third delay time interval, and the AND gate receives the first level state. A wake-up signal and an inverted delay wake-up signal in a second level state and transmitting an AND gate wake-up signal in a first level state, the second inverting logic circuit receiving an AND gate wake-up signal in a first level state The phase wake-up signal of the terminal in the second level state is output to the device to be woken up. In addition, when the computer system enters the system power-on state and the wake-up signal transitions from the first level state to the second level state, the first inverting logic circuit receives and inverts the wake-up signal in the second level state, thereby generating and Transmitting an inverted wake-up signal in a first level state, the delay circuit receiving an inverted wake-up signal in a first level state, and transmitting an inverted delay in a second level state in a fourth delay time interval Wake-up signal, the AND circuit receives the wake-up signal in the second level state and the inverted delayed wake-up signal in the second level state and transmits an AND gate wake-up signal in the second level state, the second inversion logic The circuit receives the terminal wake-up signal in a first level state after receiving the inversion of the gate wake-up signal in the second level state to the device to be woken up.
其中,上述具有喚醒電路的計算機系統之附屬技術手段之較佳實施例中,喚醒裝置係一南橋晶片、一北橋晶片、一處理器與一基板管理控制器(baseboard management controller,BMC)中之一者,第一反相邏輯 電路與第二反相邏輯電路為一非門(NOT GATE),待喚醒裝置為一具有外設互聯標準(Peripheral Component Interconnect,PCI)介面之晶片與一具有高速外設互聯標準(Peripheral Component Interconnect Express,PCIE)介面之晶片中之一者,第一電平狀態為邏輯低電平,第二電平狀態為邏輯高電平,延遲電路為一阻容延時電路(RC delay),待喚醒裝置為一處理器、一記憶體與一存儲裝置中之一者。 In a preferred embodiment of the above-mentioned auxiliary technical means for a computer system having a wake-up circuit, the wake-up device is one of a south bridge chip, a north bridge chip, a processor, and a baseboard management controller (BMC). First reverse logic The circuit and the second inverting logic circuit are NOT GATE, and the device to be woken up is a chip with a Peripheral Component Interconnect (PCI) interface and a high-speed peripheral interconnect standard (Peripheral Component Interconnect Express). One of the chips of the PCIE) interface, the first level state is a logic low level, the second level state is a logic high level, and the delay circuit is a RC delay circuit, and the wake-up device is One of a processor, a memory, and a storage device.
藉由本發明所採用之具有喚醒電路的計算機系統之主要技術手段後,由於係藉由喚醒電路內之延遲電路確保計算機系統經延遲時間區間喚醒待喚醒裝置,因此計算機系統可確實自喚醒狀態進入系統上電狀態,因而可確實工作而有效解決現有技術之問題。 After the main technical means of the computer system with the wake-up circuit used in the present invention, the computer system can surely wake up from the wake-up state by the delay circuit in the wake-up circuit to ensure that the computer system wakes up the device to be awakened through the delay time interval. It is powered on, so it can work effectively and effectively solve the problems of the prior art.
本發明所採用的具體實施例,將藉由以下之實施例及圖式作進一步之說明。 The specific embodiments of the present invention will be further described by the following examples and drawings.
1‧‧‧具有喚醒電路的計算機系統 1‧‧‧Computer system with wake-up circuit
11‧‧‧重置裝置 11‧‧‧Reset device
12‧‧‧喚醒電路 12‧‧‧Wake-up circuit
121‧‧‧第一反相邏輯電路 121‧‧‧First Inverting Logic Circuit
122‧‧‧延遲電路 122‧‧‧Delay circuit
1221‧‧‧電阻 1221‧‧‧resistance
1222‧‧‧電容 1222‧‧‧ Capacitance
12221‧‧‧第一端 12221‧‧‧ first end
12222‧‧‧第二端 12222‧‧‧ second end
123‧‧‧與門電路 123‧‧‧With gate
124‧‧‧第二反相邏輯電路 124‧‧‧Second inverting logic circuit
13‧‧‧待喚醒裝置 13‧‧‧Awaiting device
S1‧‧‧喚醒信號 S1‧‧‧ wake up signal
S2‧‧‧反相喚醒信號 S2‧‧‧ reverse wake-up signal
S3‧‧‧反相延遲喚醒信號 S3‧‧‧Inverse delayed wake-up signal
S4‧‧‧與門喚醒信號 S4‧‧‧With door wake-up signal
S5‧‧‧終端喚醒信號 S5‧‧‧ terminal wake-up signal
T1‧‧‧第一延遲時間區間 T1‧‧‧First delay time interval
T2‧‧‧第二延遲時間區間 T2‧‧‧second delay time interval
T3‧‧‧第三延遲時間區間 T3‧‧‧ third delay time interval
T4‧‧‧第四延遲時間區間 T4‧‧‧4th delay time interval
t1、t2、t3、t4‧‧‧時間 T1, t2, t3, t4‧‧‧ time
第一圖係顯示本發明較佳實施例之具有喚醒電路的計算機系統之方塊示意圖;第二圖係顯示本發明較佳實施例之計算機系統之狀態之波形示意圖;以及第三圖係顯示本發明較佳實施例之延遲時間區間之波形示意圖。 1 is a block diagram showing a computer system having a wake-up circuit in accordance with a preferred embodiment of the present invention; a second diagram showing a waveform of a state of a computer system in accordance with a preferred embodiment of the present invention; and a third diagram showing the present invention. A schematic diagram of the waveform of the delay time interval of the preferred embodiment.
由於本發明所提供之具有喚醒電路的計算機系統中,其組合實施方式不勝枚舉,故在此不再一一贅述,僅列舉一較佳實施例加以具體說明。 In the computer system with the wake-up circuit provided by the present invention, the combined implementation manners are numerous, and therefore will not be further described herein, and only a preferred embodiment will be specifically described.
請參閱第一圖,第一圖係顯示本發明較佳實施例之具有喚醒電路的計算機系統之方塊示意圖。如圖所示,本發明較佳實施例之具有喚醒電路的計算機系統1係包含一重置裝置11、一喚醒電路12以及一待喚醒裝置13。重置裝置11係一南橋晶片、一北橋晶片、一處理器與一基板管理控制器(baseboard management controller,BMC)中之一者,但其他實施例中不限於此。 Please refer to the first figure, which is a block diagram showing a computer system with a wake-up circuit in accordance with a preferred embodiment of the present invention. As shown in the figure, a computer system 1 having a wake-up circuit according to a preferred embodiment of the present invention includes a reset device 11, a wake-up circuit 12, and a wake-up device 13. The reset device 11 is one of a south bridge chip, a north bridge chip, a processor, and a baseboard management controller (BMC), but other embodiments are not limited thereto.
喚醒電路12包含一第一反相邏輯電路121、一延遲電路122、一與門電路123以及一第二反相邏輯電路124。第一反相邏輯電路121係電性連接於重置裝置11(電性連接點標記為A),並為一非門(非閘;NOT GATE),延遲電路122係電性連接於第一反相邏輯電路121(電性連接點標記為B),且延遲電路122為一阻容延時電路(RC delay),具體來說,延遲電路122包含一電阻1221以及一電容1222,電阻1221係電性連接於第一反相邏輯電路121,電容1222之一第一端12221係電性連接於電阻1221以及與門電路123(電性連接點標記為C),電容1222之一第二端12222係接地。 The wake-up circuit 12 includes a first inverting logic circuit 121, a delay circuit 122, an AND circuit 123, and a second inverting logic circuit 124. The first inverting logic circuit 121 is electrically connected to the reset device 11 (the electrical connection point is labeled as A), and is a NOT gate (NOT gate), and the delay circuit 122 is electrically connected to the first counter. The phase logic circuit 121 (the electrical connection point is labeled as B), and the delay circuit 122 is a RC delay. Specifically, the delay circuit 122 includes a resistor 1221 and a capacitor 1222. The resistor 1221 is electrically connected. Connected to the first inverting logic circuit 121, one of the first ends 12221 of the capacitor 1222 is electrically connected to the resistor 1221 and the AND circuit 123 (the electrical connection point is labeled C), and the second end 12222 of the capacitor 1222 is grounded. .
與門電路123係電性連接於第一反相邏輯電路121(電性連接點標記為A),並電性連接於延遲電路122之電容1222之第一端12221(電性連接點標記為C),且與門電路123即為及閘(AND GATE)。第二反相邏輯電 路124係電性連接於與門電路123(電性連接點標記為D),並為一非門(非閘;NOT GATE)。 The gate circuit 123 is electrically connected to the first inverting logic circuit 121 (the electrical connection point is labeled as A), and is electrically connected to the first end 12221 of the capacitor 1222 of the delay circuit 122 (the electrical connection point is marked as C). And the AND gate circuit 123 is an AND gate. Second inverted logic The circuit 124 is electrically connected to the AND circuit 123 (the electrical connection point is marked as D) and is a NOT gate (NOT gate).
待喚醒裝置13係電性連接於第二反相邏輯電路124(電性連接點標記為E),並為一具有外設互聯標準(Peripheral Component Interconnect,PCI)介面之晶片與一具有高速外設互聯標準(Peripheral Component Interconnect Express,PCIE)介面之晶片中之一者,或是為一處理器、一記憶體與一存儲裝置中之一者,而上述之處理器例如為中央處理器(Central Processing Unit,CPU)或圖形處理器(Graphic Processing Unit,GPU)或加速處理器(Accelerated Processing Unit,APU),而記憶體(內存)例如為非揮發性記憶體(Non-Volatile Memory)或揮發性記憶體(Volatile Memory),而存儲裝置例如為硬碟(HDD)。 The wake-up device 13 is electrically connected to the second inverting logic circuit 124 (the electrical connection point is marked as E), and is a chip with a Peripheral Component Interconnect (PCI) interface and a high-speed peripheral device. One of the chips of the Peripheral Component Interconnect Express (PCIE) interface, or one of a processor, a memory and a storage device, and the above processor is, for example, a central processing unit (Central Processing) Unit, CPU) or Graphic Processing Unit (GPU) or Accelerated Processing Unit (APU), and memory (memory) such as non-volatile memory (Non-Volatile Memory) or volatile memory Volatile Memory, and the storage device is, for example, a hard disk (HDD).
請一併參閱第一圖至第三圖,第二圖係顯示本發明較佳實施例之計算機系統之狀態之波形示意圖,第三圖係顯示本發明較佳實施例之延遲時間區間之波形示意圖。 Please refer to the first to third figures. The second figure shows the waveform diagram of the state of the computer system of the preferred embodiment of the present invention. The third figure shows the waveform diagram of the delay time interval of the preferred embodiment of the present invention. .
如圖所示,上述計算機系統1之運作中,重置裝置11係發送出一喚醒信號S1,第一反相邏輯電路121接收重置裝置11發出的喚醒信號S1後產生一反相喚醒信號S2,延遲電路122接收反相喚醒信號S2並於一第一延遲時間區間T1傳送出一反相延遲喚醒信號S3,與門電路123接收喚醒信號S1與反相延遲喚醒信號S3進行邏輯與功能處理後傳送出一與門喚醒信號S4,第二反相邏輯電路124接收與門喚醒信號S4進行反相後傳送出 一終端喚醒信號S5,而待喚醒裝置13接收終端喚醒信號S5後被觸發進行喚醒動作。 As shown in the figure, in the operation of the computer system 1, the reset device 11 sends a wake-up signal S1, and the first inverting logic circuit 121 receives the wake-up signal S1 from the reset device 11 to generate a reverse wake-up signal S2. The delay circuit 122 receives the inverted wake-up signal S2 and transmits an inverted delayed wake-up signal S3 in a first delay time interval T1, and the AND circuit 123 receives the wake-up signal S1 and the inverted delayed wake-up signal S3 for logical AND functional processing. An AND gate wake-up signal S4 is transmitted, and the second inverting logic circuit 124 receives the AND gate wake-up signal S4 to invert and transmit A terminal wakes up signal S5, and the wake-up device 13 is triggered to perform a wake-up action after receiving the terminal wake-up signal S5.
其中,在此需要一提的是,以下說明中,第一電平狀態為邏輯低電平(亦即數位信號中的「0」,可稱低電位),第二電平狀態為邏輯高電平(亦即數位信號中的「1」,可稱高電位)。當計算機系統1自一睡眠狀態(sleep status)轉換至一喚醒狀態(wake-up status)時(如第二圖與第三圖所示的時間t1),重置裝置11係傳送出處於一第一電平狀態的喚醒信號S1,經過一第二延遲時間區間T2(如第二圖所示)後,計算機系統1進入一系統上電狀態(system power on)並且喚醒信號S1從第一電平狀態轉換至第二電平狀態,也就是說,上述的第一延遲時間區間T1係與第二延遲時間區間T2相等。 Here, it should be noted that, in the following description, the first level state is a logic low level (that is, "0" in the digital signal, which can be called a low potential), and the second level state is a logic high power. Flat (that is, "1" in the digital signal, can be called high potential). When the computer system 1 transitions from a sleep status to a wake-up status (as shown in the second and third times, t1), the reset device 11 transmits the first After the wake-up signal S1 of a level state passes through a second delay time interval T2 (as shown in the second figure), the computer system 1 enters a system power on state and wakes up the signal S1 from the first level. The state transitions to the second level state, that is, the first delay time interval T1 described above is equal to the second delay time interval T2.
具體來說,在喚醒狀態中(亦即在第一延遲時間區間T1中),第一反相邏輯電路121係接收並反相處於第一電平狀態的喚醒信號S1,藉以產生並傳送出處於第二電平狀態的反相喚醒信號S2(請參閱第三圖電性連接點B之波形),延遲電路122係接收處於第二電平狀態的反相喚醒信號S2,並於一第三延遲時間區間T3傳送出處於第二電平狀態的反相延遲喚醒信號S3(請參閱第三圖電性連接點C之波形)。其中,在此需要說明的是,由於延遲電路122中包含有電容1222,因此當接收第二電平狀態的反相喚醒信號S2後電容1222會持續充電,並在達到所設定的第一電壓閾值時觸發傳送出處於第二電平狀態的反相延遲喚醒信號S3,而本發明較佳 實施例中係在時間t2才傳送出處於第二電平狀態的反相延遲喚醒信號S3,也就是說,上述充電的時間係t2-t1,且本發明較佳實施例中,在第三延遲時間區間T3中都是傳送出處於第二電平狀態的反相延遲喚醒信號S3,特此敘明。 Specifically, in the awake state (that is, in the first delay time interval T1), the first inverting logic circuit 121 receives and inverts the wake-up signal S1 in the first level state, thereby generating and transmitting The inverted wake-up signal S2 of the second level state (refer to the waveform of the electrical connection point B in the third figure), the delay circuit 122 receives the inverted wake-up signal S2 in the second level state, and at a third delay The time interval T3 transmits the inverted delayed wake-up signal S3 in the second level state (refer to the waveform of the electrical connection point C in the third figure). It should be noted that, since the delay circuit 122 includes the capacitor 1222, the capacitor 1222 continues to be charged after receiving the inverted wake-up signal S2 of the second level state, and reaches the set first voltage threshold. When triggered, the inverted delayed wake-up signal S3 in the second level state is transmitted, and the present invention preferably In the embodiment, the inverted delayed wake-up signal S3 in the second level state is transmitted at time t2, that is, the charging time is t2-t1, and in the preferred embodiment of the present invention, the third delay In the time interval T3, the inverted delayed wake-up signal S3 in the second level state is transmitted, which is hereby described.
另外,與門電路123接收處於第一電平狀態的喚醒信號S1與處於第二電平狀態的反相延遲喚醒信號S3並傳送出處於第一電平狀態的與門喚醒信號S4(請參閱第三圖電性連接點D之波形),第二反相邏輯電路124接收處於第一電平狀態的與門喚醒信號S4進行反相後輸出處於第二電平狀態的終端喚醒信號S5(請參閱第三圖電性連接點E之波形)至待喚醒裝置13。 In addition, the AND circuit 123 receives the wake-up signal S1 in the first level state and the inverted delayed wake-up signal S3 in the second level state and transmits the AND gate wake-up signal S4 in the first level state (see The three-phase electrical connection point D waveform), the second inverting logic circuit 124 receives the terminal wake-up signal S5 in the second level state after the inversion of the gate wake-up signal S4 in the first level state (see The third figure is electrically connected to the waveform of the point E) to the device 13 to be awakened.
另外,當計算機系統1進入系統上電狀態並且喚醒信號S1從第一電平狀態轉換至第二電平狀態時(如第二圖與第三圖所示的時間t3),第一反相邏輯電路121接收並反相處於第二電平狀態的喚醒信號S1,藉以產生並傳送出處於第一電平狀態的反相喚醒信號S2(請參閱第三圖電性連接點B之波形),延遲電路122係接收處於第一電平狀態的反相喚醒信號S2,並於一第四延遲時間區間T4傳送出處於第二電平狀態的反相延遲喚醒信號S3(請參閱第三圖電性連接點C之波形)。其中,在此需要說明的是,由於延遲電路122中包含有電容1222,因此當接收第一電平狀態的反相喚醒信號S2後電容1222會持續放電,並在達到所設定的第二電壓閾值(例如為0V)時觸發傳送出處於第一電平狀態的反 相延遲喚醒信號S3,而本發明較佳實施例中係在時間t4才傳送出處於第一電平狀態的反相延遲喚醒信號S3,也就是說,上述放電的時間係t4-t3(亦可為T4=t4-t3),因此事實上第四延遲時間區間T4中都是傳送出處於第二電平狀態的反相延遲喚醒信號S3,並在時間t4後才傳送出處於第一電平狀態的反相延遲喚醒信號S3,特此敘明 In addition, when the computer system 1 enters the system power-on state and the wake-up signal S1 transitions from the first level state to the second level state (as shown in the second and third times, time t3), the first inversion logic The circuit 121 receives and inverts the wake-up signal S1 in the second level state, thereby generating and transmitting the inverted wake-up signal S2 in the first level state (refer to the waveform of the electrical connection point B in the third figure), the delay The circuit 122 receives the inverted wake-up signal S2 in the first level state, and transmits the inverted delayed wake-up signal S3 in the second level state in a fourth delay time interval T4 (refer to the third figure electrical connection) Point C waveform). It should be noted that, since the delay circuit 122 includes the capacitor 1222, the capacitor 1222 continues to discharge after receiving the inverted wake-up signal S2 of the first level state, and reaches the set second voltage threshold. (for example, 0V) triggers the transmission of the opposite state at the first level The phase delay wake-up signal S3, and in the preferred embodiment of the present invention, the inverted delay wake-up signal S3 in the first level state is transmitted at time t4, that is, the time of the discharge is t4-t3 (may also It is T4=t4-t3), so in fact, the fourth delay time interval T4 transmits the inverted delay wake-up signal S3 in the second level state, and transmits the first level state after the time t4. Inverted delay wake-up signal S3, hereby stated
在與門電路123接收處於第二電平狀態的喚醒信號S1與處於第二電平狀態的反相延遲喚醒信號S3後,係傳送出一處於第二電平狀態的與門喚醒信號S4(請參閱第三圖電性連接點D之波形),第二反相邏輯電路124接收處於第二電平狀態的與門喚醒信號S4進行反相後輸出處於第一電平狀態的終端喚醒信號S5至待喚醒裝置13。其中,一般來說,T1=T3+T4,且T1=T2,而T4約為10ms,也就是說,t2-t1也約為10ms,但在其他實施例中不限於此,可視實務設計而定。 After the AND circuit 123 receives the wake-up signal S1 in the second level state and the inverted delay wake-up signal S3 in the second level state, the AND gate wake-up signal S4 in the second level state is transmitted (please Referring to the waveform of the electrical connection point D in the third figure, the second inverting logic circuit 124 receives the terminal wake-up signal S5 in the first level state after the inversion of the gate wake-up signal S4 in the second level state. The device 13 is to be awakened. In general, T1=T3+T4, and T1=T2, and T4 is about 10ms, that is, t2-t1 is also about 10ms, but it is not limited to this in other embodiments, depending on the practical design. .
綜合以上所述,在採用本發明所提供之具有喚醒電路的計算機系統後,由於係藉由喚醒電路內之延遲電路以及與門電路來確保計算機系統經延遲時間區間喚醒待喚醒裝置,因此計算機系統可確實自喚醒狀態進入系統上電狀態,因而可確實工作而有效解決現有技術之問題。 In summary, after the computer system with the wake-up circuit provided by the present invention is used, the computer system ensures that the computer system wakes up the device to be awakened by the delay time interval by using the delay circuit and the AND gate circuit in the wake-up circuit. It can be sure to enter the system power-on state from the awake state, so that it can work effectively and effectively solve the problems of the prior art.
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所 欲申請之專利範圍的範疇內。 The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. Rather, its purpose is to accommodate various changes and equivalence arrangements in the present invention. Within the scope of the patent scope to be applied for.
1‧‧‧具有喚醒電路的計算機系統 1‧‧‧Computer system with wake-up circuit
11‧‧‧重置裝置 11‧‧‧Reset device
12‧‧‧喚醒電路 12‧‧‧Wake-up circuit
121‧‧‧第一反相邏輯電路 121‧‧‧First Inverting Logic Circuit
122‧‧‧延遲電路 122‧‧‧Delay circuit
1221‧‧‧電阻 1221‧‧‧resistance
1222‧‧‧電容 1222‧‧‧ Capacitance
12221‧‧‧第一端 12221‧‧‧ first end
12222‧‧‧第二端 12222‧‧‧ second end
123‧‧‧與門電路 123‧‧‧With gate
124‧‧‧第二反相邏輯電路 124‧‧‧Second inverting logic circuit
13‧‧‧待喚醒裝置 13‧‧‧Awaiting device
S1‧‧‧喚醒信號 S1‧‧‧ wake up signal
S2‧‧‧反相喚醒信號 S2‧‧‧ reverse wake-up signal
S3‧‧‧反相延遲喚醒信號 S3‧‧‧Inverse delayed wake-up signal
S4‧‧‧與門喚醒信號 S4‧‧‧With door wake-up signal
S5‧‧‧終端喚醒信號 S5‧‧‧ terminal wake-up signal
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Cited By (4)
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TWI655546B (en) * | 2017-10-12 | 2019-04-01 | 光寶科技股份有限公司 | Reset circuit of solid state drive and reset method thereof |
US10642328B2 (en) | 2017-10-12 | 2020-05-05 | Solid State Storage Technology Corporation | Solid state drive with reset circuit and reset method thereof |
CN114691221A (en) * | 2020-12-31 | 2022-07-01 | 新唐科技股份有限公司 | Control circuit and operating system |
US11784635B1 (en) | 2022-08-23 | 2023-10-10 | Nuvoton Technology Corporation | Control circuit and operation system |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI655546B (en) * | 2017-10-12 | 2019-04-01 | 光寶科技股份有限公司 | Reset circuit of solid state drive and reset method thereof |
US10642328B2 (en) | 2017-10-12 | 2020-05-05 | Solid State Storage Technology Corporation | Solid state drive with reset circuit and reset method thereof |
CN114691221A (en) * | 2020-12-31 | 2022-07-01 | 新唐科技股份有限公司 | Control circuit and operating system |
CN114691221B (en) * | 2020-12-31 | 2023-12-15 | 新唐科技股份有限公司 | Control circuit and operating system |
US11784635B1 (en) | 2022-08-23 | 2023-10-10 | Nuvoton Technology Corporation | Control circuit and operation system |
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