TWI528094B - Electrochromic multi-layer devices with spatially coordinated switching - Google Patents

Description

空間協調切換之電致變色多層裝置 Space-coordinated switching electrochromic multilayer device

本發明大致係關於能夠在大致其等之整個面積或其等之整個面積之所選擇之子區域內協調切換之可切換電致變色裝置，諸如建築窗。更特定言之，且在一較佳實施例中，本發明係關於可切換電致變色多層裝置，尤其以空間協調方式在大致其等之整個面積或其等之整個面積之所選擇之子區域內切換之建築應用之大面積矩形窗；視需要此等係不均勻形狀，視需要其等在大致其等之整個面積或其等之整個面積之所選擇之子區域內同步(即一致)切換或以協調但非同步方式(例如，從側面至側面或從頂部至底部)從第一光學狀態(例如，透明狀態)切換為第二光學狀態(例如，反射狀態或有色狀態)。 The present invention is generally directed to a switchable electrochromic device, such as a building window, that is capable of coordinated switching within a selected sub-area of substantially the entire area or its entire area. More particularly, and in a preferred embodiment, the present invention relates to a switchable electrochromic multi-layer device, particularly in a spatially coordinated manner over a selected sub-area of substantially the entire area of its area or its entire area. Switching a large-area rectangular window for architectural applications; if desired, such a non-uniform shape, as needed, may be synchronized (ie, consistently) switched or selected within a selected sub-area of substantially the entire area or its entire area The coordinated but non-synchronous manner (eg, from side to side or from top to bottom) switches from a first optical state (eg, a transparent state) to a second optical state (eg, a reflective state or a colored state).

眾所周知用作汽車之鏡、車窗、飛機窗總成、天窗、建築窗之商業可切換玻璃裝置。此等裝置可包括舉例而言，無機電致變色裝置、有機電致變色裝置、可切換鏡及此等之混合物，其等具有兩個導電層，在導電層之間具有一或多個活性層。當跨此等導電層施加電壓時，其間之一層或諸層之光學性質改變。此等光學性質改變通常係電磁光譜之可見光或太陽光子部分之透射率之調變。為方便起見，在下文討論中，兩種光學狀態可稱作亮狀態及暗狀態，但是應瞭解此等僅為實例及相對術語 (即，該兩個狀態之一者比另一狀態「更亮」或更透光)且可能存在針對特定電致變色裝置可達成之極值之間之一組亮狀態及暗狀態；舉例而言，在此一組中在中間亮狀態與暗狀態之間切換可行。 It is well known as a commercial switchable glass device for mirrors, windows, aircraft window assemblies, skylights, and architectural windows of automobiles. Such devices may include, by way of example, inorganic electrochromic devices, organic electrochromic devices, switchable mirrors, and mixtures thereof, having two conductive layers with one or more active layers between the conductive layers . When a voltage is applied across the conductive layers, the optical properties of one of the layers or layers therebetween change. Such changes in optical properties are typically the modulation of the transmission of visible light or solar photonic portions of the electromagnetic spectrum. For convenience, in the following discussion, the two optical states may be referred to as bright and dark states, but it should be understood that these are merely examples and relative terms. (ie, one of the two states is "brighter" or lighter than the other state) and there may be a group of bright and dark states between the extreme values achievable for a particular electrochromic device; for example In this group, switching between the middle bright state and the dark state is feasible.

相對較小電致變色裝置(諸如電致變色後視鏡總成)中亮狀態與暗狀態之間之切換通常快速且一致，而大面積電致變色裝置中亮狀態與暗狀態之間之切換可能慢且在空間上不一致。逐漸、不一致顯色或切換係與大面積電致變色裝置相關之常見問題。此問題(通常稱作「虹膜效應」)通常係穿透提供電接觸至裝置之一側或兩側之透明導電塗層之電壓降之結果。舉例而言，當最初將電壓施加至裝置時，電位通常在裝置之邊緣(施加電壓之處)附近最大且在裝置之中心最小；因此，在裝置之邊緣附近之透射率與裝置之中心處之透射率可能存在明顯差異。但是，隨時間過去，中心與邊緣之間之所施加之電壓之差異減小且因此裝置之中心處與邊緣上之透射率之差異減小。在此等情況中，電致變色介質通常藉由最初改變所施加之電位附近之裝置之透射率而顯示不一致之透射率，隨著切換進行透射率逐漸且逐進朝向裝置之中心改變。雖然最常在相對較大裝置中觀察到虹膜效應，但是其亦存在於具有相應較高電阻率導電層之較小裝置中。 Switching between bright and dark states in relatively small electrochromic devices, such as electrochromic rearview mirror assemblies, is generally fast and consistent, while switching between bright and dark states in large area electrochromic devices May be slow and inconsistent in space. Gradual, inconsistent color development or switching problems are common problems associated with large area electrochromic devices. This problem (commonly referred to as the "iris effect") is typically the result of a voltage drop that penetrates the transparent conductive coating that provides electrical contact to one or both sides of the device. For example, when a voltage is initially applied to the device, the potential is typically greatest near the edge of the device (where the voltage is applied) and at the center of the device; therefore, the transmittance near the edge of the device is at the center of the device There may be significant differences in transmittance. However, over time, the difference in applied voltage between the center and the edge is reduced and thus the difference in transmittance at the center and edge of the device is reduced. In such cases, the electrochromic medium typically exhibits an inconsistent transmittance by initially changing the transmittance of the device in the vicinity of the applied potential, with the transmittance gradually changing and progressively changing toward the center of the device. Although the iris effect is most often observed in relatively large devices, it is also present in smaller devices having correspondingly higher resistivity conductive layers.

在本發明之各種態樣中，提供可容易地製作之能夠跨大致其整個面積協調切換及顯色之相對較大面積電致變色多層裝置。 In various aspects of the invention, a relatively large area electrochromic multilayer device that can be readily fabricated that can coordinately switch and develop color across substantially the entire area is provided.

簡言之，因此，本發明係關於包括第一基板及其表面上之第一導電層之多層裝置。第一導電層透射具有在紅外光至紫外光之範圍中之波長之電磁輻射且具有以在第一導電層中之位置為函數而變化之針對穿過第一導電層之電流之流動之薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少2。 Briefly, therefore, the present invention is directed to a multilayer device including a first substrate and a first conductive layer on its surface. The first conductive layer transmits electromagnetic radiation having a wavelength in the range of infrared light to ultraviolet light and has a thin layer of current flowing through the first conductive layer as a function of position in the first conductive layer resistance R _s, wherein the first conductive layer, the sheet resistance of the maximum value R _max ratio of the minimum value R _min of the sheet resistance is at least 2.

本發明之另一態樣係包括第一基板及其表面上之第一導電層之多層裝置。第一導電層具有以在第一導電層中之位置為函數而變化之針對穿過第一導電層之電流之流動之空間變化薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少大約1.25。 Another aspect of the invention is a multilayer device comprising a first substrate and a first conductive layer on its surface. The first conductive layer has at the position of the first conductive layer varies as a function of change in the sheet resistance R _s of the current flowing through the space for the first conductive layers, wherein the maximum sheet resistance of the first conductive layer The ratio of the value _Rmax to the minimum sheet resistance value _Rmin is at least about 1.25.

本發明之另一態樣係包括第一基板、該基板之表面上之第一導電層及第一導電層之表面上之第一電極層之多層裝置。第一導電層具有以在第一導電層中之位置為函數而變化之空間變化薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少大約1.25。 Another aspect of the invention includes a first substrate, a first conductive layer on a surface of the substrate, and a multilayer device of a first electrode layer on a surface of the first conductive layer. A first conductive layer having a first conductive layer, the position varies as a function of the spatial variation of the sheet resistance R _s, wherein the first conductive layer, the sheet resistance of the maximum value to the minimum value R _max of the sheet resistance R The ratio of _min is at least about 1.25.

本發明之另一態樣係包括第一基板及基板之表面上之第一導電層之多層裝置。第一導電層具有以在第一導電 層中之位置為函數而變化之空間變化薄層電阻R_s，其中以在第一導電層內之位置為函數之薄層電阻R_s之等高線圖含有一組等電阻線及垂直於等電阻線之一組電阻梯度線。該組中沿著梯度線之薄層電阻大致增大、大致減小、大致增大直至其達到最大值且隨後大致減小或大致減小直至其達到最小值且隨後大致增大。在一實施例中，舉例而言，薄層電阻之梯度為常數。進一步舉例而言，在一實施例中，薄層電阻之梯度為常數且基板之形狀為矩形。 Another aspect of the invention is a multilayer device comprising a first substrate and a first conductive layer on the surface of the substrate. The first conductive layer has a spatially varying sheet resistance R _s that varies as a function of position in the first conductive layer, wherein the contour map of the sheet resistance R _s as a function of position within the first conductive layer contains a A set of equal resistance lines and a set of resistance gradient lines perpendicular to one of the equal resistance lines. The sheet resistance along the gradient line in the set generally increases, substantially decreases, generally increases until it reaches a maximum and then decreases substantially or substantially decreases until it reaches a minimum and then increases substantially. In one embodiment, for example, the gradient of the sheet resistance is constant. By way of further example, in one embodiment, the gradient of the sheet resistance is constant and the shape of the substrate is rectangular.

本發明之另一態樣係包括第一基板、該基板之表面上之第一導電層及第一導電層之表面上之第一電極層之多層裝置。第一導電層具有以在第一導電層中之位置為函數而變化之空間變化薄層電阻R_s，其中以在第一導電層內之位置為函數之薄層電阻R_s之等高線圖含有一組等電阻線及垂直於等電阻線之一組電阻梯度線。該組中沿著梯度線之薄層電阻大致增大、大致減小、大致增大直至其達到最大值且隨後大致減小或大致減小直至其達到最小值且隨後大致增大。在一實施例中，舉例而言，薄層電阻之梯度為常數。進一步舉例而言，在一實施例中，薄層電阻之梯度為常數且基板之形狀為矩形。 Another aspect of the invention includes a first substrate, a first conductive layer on a surface of the substrate, and a multilayer device of a first electrode layer on a surface of the first conductive layer. The first conductive layer has a spatially varying sheet resistance R _s that varies as a function of position in the first conductive layer, wherein the contour map of the sheet resistance R _s as a function of position within the first conductive layer contains a A set of equal resistance lines and a set of resistance gradient lines perpendicular to one of the equal resistance lines. The sheet resistance along the gradient line in the set generally increases, substantially decreases, generally increases until it reaches a maximum and then decreases substantially or substantially decreases until it reaches a minimum and then increases substantially. In one embodiment, for example, the gradient of the sheet resistance is constant. By way of further example, in one embodiment, the gradient of the sheet resistance is constant and the shape of the substrate is rectangular.

本發明之另一態樣係包括介於第一導電層與第二導電層之間且與第一導電層及第二導電層電接觸之電致變色層之電致變色多層裝置。第一導電層及/或第二導電層具有以在第一導電層及/或第二導電層中之位置為函數而 變化之空間變化薄層電阻R_s，其中以在第一導電層及/或第二導電層內之位置為函數之薄層電阻R_s之等高線圖含有一組等電阻線及垂直於等電阻線之一組電阻梯度線。在第一導電層及/或第二導電層中沿著梯度線之薄層電阻大致增大、大致減小、大致增大直至其達到最大值且隨後大致減小或大致減小直至其達到最小值且隨後大致增大。在一實施例中，舉例而言，薄層電阻之梯度為常數。進一步舉例而言，在一實施例中，薄層電阻之梯度為常數且基板之形狀為矩形。 Another aspect of the invention is an electrochromic multilayer device comprising an electrochromic layer between a first conductive layer and a second conductive layer and in electrical contact with the first conductive layer and the second conductive layer. The first conductive layer and/or the second conductive layer have a spatially varying sheet resistance R _s that varies as a function of position in the first conductive layer and/or the second conductive layer, wherein the first conductive layer and/or Or the contour map of the sheet resistance R _s of the position in the second conductive layer is a set of equal resistance lines and a set of resistance gradient lines perpendicular to the equal resistance lines. The sheet resistance along the gradient line in the first conductive layer and/or the second conductive layer increases substantially, substantially decreases, substantially increases until it reaches a maximum value and then substantially decreases or substantially decreases until it reaches a minimum The value then increases substantially. In one embodiment, for example, the gradient of the sheet resistance is constant. By way of further example, in one embodiment, the gradient of the sheet resistance is constant and the shape of the substrate is rectangular.

本發明之又一態樣係包括第一基板、第一導電層、第一電極層、第二導電層及第二基板之電致變色裝置。第一導電層及第二導電層各具有以在第一導電層及第二導電層中之位置為函數而變化之分別針對穿過第一導電層及第二導電層之電流之流動之薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少2且在第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少2。第一基板及第一導電層透射具有在紅外光至紫外光之範圍中之波長。舉例而言，在一實施例中，第一基板及第一導電層對具有在紅外光至紫外光之範圍中之波長之電磁輻射透明。 Still another aspect of the present invention includes an electrochromic device of a first substrate, a first conductive layer, a first electrode layer, a second conductive layer, and a second substrate. The first conductive layer and the second conductive layer each have a thin layer respectively for a flow of current through the first conductive layer and the second conductive layer as a function of a position in the first conductive layer and the second conductive layer a resistance R _s , wherein a ratio of a maximum sheet resistance value R _max to a minimum sheet resistance value R _min in the first conductive layer is at least 2 and a maximum sheet resistance value R _max to a minimum in the second conductive layer The ratio of the value of the sheet resistance R _min is at least 2. The first substrate and the first conductive layer transmit wavelengths having a range from infrared light to ultraviolet light. For example, in one embodiment, the first substrate and the first conductive layer are transparent to electromagnetic radiation having a wavelength in the range of infrared light to ultraviolet light.

本發明之又一態樣係用於調變電致變色多層裝置之透射率之製程，多層裝置包括介於第一導電層與第二導電層之間且與第一導電層及第二導電層電接觸之電致變色 層。製程包括在第一導電層與第二導電層之間施加電壓脈衝，電壓脈衝具有至少大約2伏之量值。電壓脈衝引致電致變色層從第一光學狀態切換至第二光學狀態，其中第一光學狀態或第二光學狀態相對於另一光學狀態具有針對具有在紫外光波長至紅外光波長之範圍中之波長之電磁輻射之更大透射率，且第二光學狀態在脈衝後及在無施加於導電層之間之電壓之情況下持續至少1秒。 Still another aspect of the present invention is a process for modulating transmittance of an electrochromic multilayer device, the multilayer device comprising between the first conductive layer and the second conductive layer and with the first conductive layer and the second conductive layer Electrochromic electrical contact Floor. The process includes applying a voltage pulse between the first conductive layer and the second conductive layer, the voltage pulse having a magnitude of at least about 2 volts. The voltage pulse directs the photochromic layer to switch from the first optical state to the second optical state, wherein the first optical state or the second optical state has a range from ultraviolet wavelength to infrared wavelength relative to the other optical state The greater the transmission of electromagnetic radiation of the wavelength, and the second optical state lasts for at least one second after the pulse and without the voltage applied between the conductive layers.

本發明之又一態樣係用於製備多層裝置之製程，製程包括在第一基板之表面上形成第一導電層。第一導電透射包括透明導體且具有以在第一導電層中之位置為函數而變化之針對穿過第一導電層之電流之流動之空間變化薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少大約1.25。 Yet another aspect of the invention is a process for making a multilayer device comprising forming a first conductive layer on a surface of a first substrate. The first conductive transmission includes a transparent conductor and has a spatially varying sheet resistance R _{s for a} flow of current through the first conductive layer as a function of position in the first conductive layer, wherein in the first conductive layer The ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin is at least about 1.25.

本發明之又一態樣係用於製備多層裝置之製程。製程包括形成包括電致變色層、導電層及基板之多層結構，導電層介於第一電極層與基板之間。第一導電層具有以在第一導電層中之位置為函數而變化之針對穿過第一導電層之電流之流動之空間變化薄層電阻R_s，其中在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少大約1.25。 Yet another aspect of the invention is a process for making a multilayer device. The process includes forming a multilayer structure including an electrochromic layer, a conductive layer, and a substrate, the conductive layer being interposed between the first electrode layer and the substrate. The first conductive layer has at the position of the first conductive layer varies as a function of change in the sheet resistance R _s of the current flowing through the space for the first conductive layers, wherein the maximum sheet resistance of the first conductive layer The ratio of the value _Rmax to the minimum sheet resistance value _Rmin is at least about 1.25.

本發明之又一態樣係關於用於製備多層裝置之製程。製程包括形成包括介於第一導電層與第二導電層之間且與第一導電層及第二導電層電接觸之電致變色層之多層層結構。第一導電層及/或第二導電層具有以在第一導電 層及/或第二導電層中之位置為函數而變化之分別針對穿過第一導電層及/或第二導電層之電流之流動之空間變化薄層電阻R_s，其中在第一導電層及/或第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率分別為至少大約1.25。 Yet another aspect of the invention pertains to a process for making a multilayer device. The process includes forming a multi-layer structure comprising an electrochromic layer between the first conductive layer and the second conductive layer and in electrical contact with the first conductive layer and the second conductive layer. The first conductive layer and/or the second conductive layer have a current that varies across the first conductive layer and/or the second conductive layer as a function of position in the first conductive layer and/or the second conductive layer The spatial variation of the sheet resistance R _s , wherein the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in the first conductive layer and/or the second conductive layer is at least about 1.25, respectively.

下文中可部分瞭解及部分指出其他目標及特徵。 Some of the other objectives and features can be partially understood and partially noted below.

縮寫及定義 Abbreviations and definitions

提供下列定義及方法以更好地定義本發明及在本發明之實踐中指導本領域一般技術者。除非另有說明，否則術語應根據相關領域之一般技術者之習知用法進行理解。 The following definitions and methods are provided to better define the present invention and to guide those of ordinary skill in the art in the practice of the invention. Unless otherwise stated, the terms should be understood according to the well-known usage of one of ordinary skill in the relevant art.

術語「陽極電致變色層」指的是在離子移除時從更透光狀態改變為較不透光狀態之電極層。 The term "anode electrochromic layer" refers to an electrode layer that changes from a more transparent state to a less opaque state upon ion removal.

術語「陰極電致變色層」指的是在離子***時從更透光狀態改變為較不透光狀態之電極層。 The term "cathode electrochromic layer" refers to an electrode layer that changes from a more transparent state to a less opaque state upon ion insertion.

術語「導電」及「電阻」指的是材料之導電率及電阻率。 The terms "conducting" and "resistance" refer to the electrical conductivity and electrical resistivity of a material.

術語「凸多邊形」指的是簡單多邊形，其中各內角小於或等於180度且兩個頂角之間之各線段保留在多邊形之邊界內或多邊形之邊界上。例示性凸多邊形包含三角形、矩形、五邊形、六邊形等，其中各內角小於或等於180度且兩個頂角之間之各線段保留在多邊形之邊界內 或多邊形之邊界上。 The term "convex polygon" refers to a simple polygon in which each inner angle is less than or equal to 180 degrees and each line segment between the two apex angles remains within the boundary of the polygon or on the boundary of the polygon. An exemplary convex polygon includes a triangle, a rectangle, a pentagon, a hexagon, etc., wherein each inner angle is less than or equal to 180 degrees and each line segment between the two apex angles remains within the boundary of the polygon Or on the border of a polygon.

術語「電致變色層」指的是包括電致變色材料之層。 The term "electrochromic layer" refers to a layer comprising an electrochromic material.

術語「電致變色材料」指的是能夠因離子及電子之***或引出可逆地改變其等之光學性質之材料。舉例而言，電致變色材料可在有色、半透明狀態與透明狀態之間改變。 The term "electrochromic material" refers to a material that is capable of reversibly changing the optical properties of ions and electrons due to the insertion or extraction of ions and electrons. For example, the electrochromic material can change between a colored, translucent state, and a transparent state.

術語「電極層」指的是能夠傳導離子以及電子之層。電極層含有可在將離子***材料中時氧化之物質且含有能夠在將離子從層中引出時還原之物質。電極層中物質之氧化狀態之此改變導致裝置之光學性質之改變。 The term "electrode layer" refers to a layer that is capable of conducting ions as well as electrons. The electrode layer contains a substance which can be oxidized when ions are inserted into the material and contains a substance which can be reduced when the ions are taken out of the layer. This change in the oxidation state of the material in the electrode layer results in a change in the optical properties of the device.

術語「電學電位」或簡稱「電位」指的是跨包括電極/離子導體/電極堆疊之裝置而產生之電壓。 The term "electrical potential" or simply "potential" refers to the voltage generated across a device comprising an electrode/ion conductor/electrode stack.

術語「透射」用於表示電磁輻射透射穿過材料。 The term "transmission" is used to mean that electromagnetic radiation is transmitted through the material.

術語「透明」用於表示電磁輻射實質透射穿過材料使得舉例而言可使用適當影像感測技術使位於材料另一邊或材料背後之主體被清楚地看見或成像。 The term "transparent" is used to mean that electromagnetic radiation is substantially transmitted through the material such that, for example, the subject located on the other side of the material or behind the material can be clearly seen or imaged using appropriate image sensing techniques.

第1圖描繪根據本發明之第一實施例之電致變色裝置1之橫截面結構圖。從中心向外移動，電致變色裝置1包括離子傳導層10。第一電極層20位於離子傳導層10之一側上並與離子傳導層10之一第一表面接觸，且第二電極層21位於離子傳導層10之另一側上並與離子傳導層10之一第二表面接觸。此外，第一電極層20及第二電極層21之至少一者包括電致變色材料；在一實施例中，第一電極層20及第二電極層21各包括電致變色材料。 中心結構(即，層20、10、21)安置於第一導電層22與第二導電層23之間，該等第一導電層22及第二導電層23接著抵靠外基板24、25而配置。元件22、20、10、21及23統稱為電致變色堆疊28。 Fig. 1 is a cross-sectional structural view showing an electrochromic device 1 according to a first embodiment of the present invention. Moving outward from the center, the electrochromic device 1 includes an ion conducting layer 10. The first electrode layer 20 is located on one side of the ion conductive layer 10 and is in contact with one of the first surfaces of the ion conductive layer 10, and the second electrode layer 21 is located on the other side of the ion conductive layer 10 and with the ion conductive layer 10 A second surface contact. Furthermore, at least one of the first electrode layer 20 and the second electrode layer 21 comprises an electrochromic material; in one embodiment, the first electrode layer 20 and the second electrode layer 21 each comprise an electrochromic material. The central structure (ie, layers 20, 10, 21) is disposed between the first conductive layer 22 and the second conductive layer 23, and the first conductive layer 22 and the second conductive layer 23 then abut the outer substrates 24, 25. Configuration. Elements 22, 20, 10, 21 and 23 are collectively referred to as electrochromic stack 28.

導電層22經由匯流排條26與一電源(未繪示)之一端子電接觸且導電層23經由匯流排條27與電源(未繪示)之另一端子電接觸，藉此可藉由施加一電壓脈衝至導電層22及23而改變電致變色裝置10之透射率。脈衝導致電子及離子在第一電極層20與第二電極層21之間移動，且因此，(若干)第一電極層及/或第二電極層中之電致變色材料改變光學狀態，藉此將電致變色裝置1從較透光狀態切換至較不透光狀態，或從較不透光狀態切換至較透光狀態。在一實施例中，電致變色裝置1在電壓脈衝之前透明且在電壓脈衝之後為較不透光(例如，更具反射性或有色)或反之亦然。 The conductive layer 22 is in electrical contact with one of the terminals of a power source (not shown) via the bus bar 26 and the conductive layer 23 is in electrical contact with the other terminal of the power source (not shown) via the bus bar 27, whereby A voltage pulse is applied to the conductive layers 22 and 23 to change the transmittance of the electrochromic device 10. The pulse causes electrons and ions to move between the first electrode layer 20 and the second electrode layer 21, and thus, the electrochromic material in the first electrode layer and/or the second electrode layer changes optical state, thereby The electrochromic device 1 is switched from a light transmissive state to a less opaque state, or from a less opaque state to a lighter opaque state. In an embodiment, the electrochromic device 1 is transparent prior to the voltage pulse and less opaque (eg, more reflective or colored) after the voltage pulse or vice versa.

應瞭解，提及較不透光狀態與較透光狀態之間之過渡非限制且旨在描述電致變色材料針對電磁輻射之透射率可達成之整個過渡範圍。舉例而言，透射率之改變可為從一第一光學狀態至一第二光學狀態之改變，該第二光學狀態(i)比第一狀態相對更具吸收性(即，較不透光)，(ii)比第一狀態相對更不具吸收性(即，較透光)，(iii)比第一狀態相對更具反射性(即，較不透光)，(iv)比第一狀態相對更不具反射性(即，較透光)，(v)比第一狀態相對更具反射性及更具吸收性(即，較不透光)或(vi) 比第一狀態相對更不具反射性及更不具吸收性(即，較透光)。此外，改變可介於電致變色裝置可達成之兩個極端光學狀態之間，例如介於第一透明狀態與第二狀態之間，該第二狀態不透明或反射(鏡射)。或者，改變可介於兩個光學狀態之間，該兩個光學狀態之至少一者係在沿著針對特定電致變色裝置可達成之兩個極端狀態(例如，透明與不透明或透明與鏡射)之間之光譜中間。除非本文另有規定，否則每當提及較不透光及較透光，或甚至漂白色過渡時，相應裝置或製程涵蓋其他光學狀態過渡，諸如不反射-反射、透明-不透明等。此外，術語「漂白」指的是光學中性狀態，例如無色、透明或半透明。更進一步，除非本文另有規定，否則電致變色過渡之「色彩」並不限於任何特定波長或波長範圍。如熟悉此項技術者所知，適當之電致變色及反電極材料之選擇管控相關光學過渡。 It should be understood that the transition between the less opaque state and the more opaque state is not limiting and is intended to describe the entire transition range that the electrochromic material can achieve for the transmission of electromagnetic radiation. For example, the change in transmittance may be a change from a first optical state to a second optical state, the second optical state (i) being relatively more absorbent (ie, less opaque) than the first state. (ii) is relatively less absorbent (ie, lighter) than the first state, (iii) relatively more reflective (ie, less opaque) than the first state, and (iv) is relatively more reflective than the first state Less reflective (ie, lighter), (v) relatively more reflective and more absorbent than the first state (ie, less opaque) or (vi) It is relatively less reflective and less absorbent (ie, lighter) than the first state. Moreover, the change can be between two extreme optical states achievable by the electrochromic device, such as between a first transparent state and a second state, the second state being opaque or reflective (mirror). Alternatively, the change may be between two optical states, at least one of which is achievable along two extreme states (eg, transparent and opaque or transparent and mirrored) for a particular electrochromic device. ) between the middle of the spectrum. Unless otherwise specified herein, the respective apparatus or process encompasses other optical state transitions, such as non-reflective-reflective, transparent-opaque, etc., whenever reference is made to less opaque and lighter, or even bleached white transitions. Further, the term "bleaching" refers to an optically neutral state such as colorless, transparent or translucent. Furthermore, the "color" of the electrochromic transition is not limited to any particular wavelength or range of wavelengths unless otherwise specified herein. As is known to those skilled in the art, the selection of appropriate electrochromic and counter electrode materials governs the associated optical transition.

通常，透射率之改變較佳地包括針對具有在紅外光至紫外光輻射之範圍中之波長之電磁輻射之透射率之改變。例如，在一實施例中，透射率之改變主要針對紅外光光譜中之電磁輻射之透射率之改變。在第二實施例中，透射率之改變針對具有主要在可見光光譜中之波長之電磁輻射。在第三實施例中，透射率之改變針對具有主要在紫外光光譜中之波長之電磁輻射。在第四實施例中，透射率之改變針對具有主要在紫外光光譜及可見光光譜中之波長之電磁輻射。在第五實施例中，透射率之改變 針對具有主要在紅外光光譜及可見光光譜中之波長之電磁輻射。在第六實施例中，透射率之改變係針對具有主要在紫外光光譜、可見光光譜及紅外光光譜中之波長之電磁輻射。 Generally, the change in transmittance preferably includes a change in transmittance for electromagnetic radiation having a wavelength in the range of infrared light to ultraviolet light radiation. For example, in one embodiment, the change in transmittance is primarily directed to the change in transmittance of electromagnetic radiation in the infrared spectrum. In a second embodiment, the change in transmittance is for electromagnetic radiation having a wavelength primarily in the visible light spectrum. In a third embodiment, the change in transmittance is for electromagnetic radiation having a wavelength predominantly in the ultraviolet spectrum. In the fourth embodiment, the change in transmittance is directed to electromagnetic radiation having a wavelength mainly in the ultraviolet light spectrum and the visible light spectrum. In the fifth embodiment, the change in transmittance For electromagnetic radiation having wavelengths primarily in the infrared and visible spectra. In the sixth embodiment, the change in transmittance is for electromagnetic radiation having wavelengths mainly in the ultraviolet light spectrum, the visible light spectrum, and the infrared light spectrum.

組成電致變色堆疊28之材料可包括有機材料或無機材料，且其等可為固體或液體。舉例而言，在特定實施例中，電致變色堆疊28包括為無機、固體(即，處於固態中)或無機且固體二者之材料。無機材料在建築應用方面已展現更好之可靠性。固態材料亦可提供無如液態材料通常出現之抑制及泄漏問題之優點。應瞭解，堆疊中之層之任意一者或多者可含有一些量之有機材料，但是在許多實施方案中，層之一者或多者含有些許或不含有機物。可能少量存在於一個或多個層中之液體亦為如此。在特定的其他實施例中，組成電致變色堆疊28之材料之一些或所有係有機。有機離子導體可提供更高之遷移率且因此可能提供更好之裝置切換效能。有機電致變色層可提供更高之對比率及更多樣的色彩選項。下文詳細討論電致變色裝置中之層之每一者。應瞭解，可藉由採用液體組分之製程(諸如採用溶膠-凝膠或化學氣相沈積之特定製程)沈積或另外形成固態材料。 The materials constituting the electrochromic stack 28 may include organic materials or inorganic materials, and the like may be solid or liquid. For example, in a particular embodiment, the electrochromic stack 28 comprises a material that is inorganic, solid (ie, in a solid state) or both inorganic and solid. Inorganic materials have shown better reliability in architectural applications. Solid materials can also provide advantages such as the suppression and leakage problems typically found in liquid materials. It will be appreciated that any one or more of the layers in the stack may contain some amount of organic material, but in many embodiments, one or more of the layers contain little or no organics. This is also the case for liquids that may be present in small amounts in one or more layers. In certain other embodiments, some or all of the materials that make up the electrochromic stack 28 are organic. Organic ion conductors provide higher mobility and therefore may provide better device switching performance. Organic electrochromic layers offer higher contrast ratios and a wider range of color options. Each of the layers in the electrochromic device is discussed in detail below. It will be appreciated that the solid state material may be deposited or otherwise formed by a process employing a liquid component, such as a particular process employing sol-gel or chemical vapor deposition.

再次參考第1圖，連接至匯流排條26、27之電源(未繪示)通常係具有視需要之電流限制或電流控制特徵之一電壓源且可經組態以結合局部熱、光敏或其他環境感測器運作。電壓源亦可經組態以與根據諸如年、日及量 測之環境條件之因素控制電致變色裝置之能量管理系統(諸如電腦系統)介接。此能量管理系統結合大面積電致變色裝置(例如，電致變色建築窗)可大大降低建築物之能耗。 Referring again to Figure 1, the power source (not shown) connected to the bus bars 26, 27 is typically a voltage source having one of the desired current limiting or current control features and can be configured to incorporate local heat, light or other The environmental sensor operates. The voltage source can also be configured to be based on, for example, year, day and quantity The factors of the environmental conditions are measured to control the energy management system (such as a computer system) of the electrochromic device. This energy management system combined with large area electrochromic devices (eg, electrochromic building windows) can greatly reduce the energy consumption of buildings.

基板24、25之至少一者較佳透明以向周圍環境顯露堆疊28之電致變色性質。具有適當光學、電、熱及機械性質之任何材料可用作第一基板24或第二基板25。此等基板包含(舉例而言)玻璃、塑膠、金屬及金屬塗覆之玻璃或塑膠。可行塑膠基板之非排他性實例係聚碳酸酯、聚丙烯酸類、聚氨基甲酸脂、氨基甲酸酯碳酸鹽共聚物、聚碸類、聚醯亞胺、聚丙烯酸酯、聚醚、聚酯、聚乙烯、聚烯烴、聚醯亞胺、多硫化物、聚醋酸乙烯酯及基於纖維素之聚合物。若使用塑膠基板，則其可使用(諸如)塑膠玻璃技術中總所周知之(舉例而言)類金剛石保護塗層、矽石/矽酮抗磨損塗層或類似塗層之堅硬塗層而受障壁保護及磨損保護。適當之玻璃包含透明或有色鈉鈣玻璃，包含鈉鈣浮式玻璃。玻璃可經回火或未回火。在具有用作第一基板24及/或第二基板25之玻璃(例如，鈉鈣玻璃)之電致變色裝置1之一些實施例中，在第一基板24與第一導電層22之間及/或第二基板25與第二導電層23之間存在一鈉擴散障壁層(未繪示)以防止鈉離子從玻璃擴散至第一導電層及/或第二導電層23中。在一些實施例中，第二基板25省略。 At least one of the substrates 24, 25 is preferably transparent to reveal the electrochromic properties of the stack 28 to the surrounding environment. Any material having suitable optical, electrical, thermal, and mechanical properties can be used as the first substrate 24 or the second substrate 25. Such substrates comprise, for example, glass, plastic, metal and metal coated glass or plastic. Non-exclusive examples of viable plastic substrates are polycarbonate, polyacrylic acid, polyurethane, urethane carbonate copolymer, polyfluorene, polyimine, polyacrylate, polyether, polyester, poly Ethylene, polyolefin, polyimine, polysulfide, polyvinyl acetate and cellulose based polymers. If a plastic substrate is used, it can be used, for example, by a well-known (for example) diamond-like protective coating, a vermiculite/fluorenone anti-wear coating or a hard coating of a similar coating in plastic glass technology. Barrier protection and wear protection. Suitable glasses comprise clear or colored soda lime glass, including soda lime floating glass. The glass can be tempered or not tempered. In some embodiments of the electrochromic device 1 having glass (eg, soda lime glass) used as the first substrate 24 and/or the second substrate 25, between the first substrate 24 and the first conductive layer 22, There is a sodium diffusion barrier layer (not shown) between the second substrate 25 and the second conductive layer 23 to prevent sodium ions from diffusing from the glass into the first conductive layer and/or the second conductive layer 23. In some embodiments, the second substrate 25 is omitted.

在本發明之一較佳實施例中，第一基板24及第二基板 25各為浮式玻璃。在建築應用之特定實施例中，此玻璃係至少0.5米乘0.5米，且可大得多，例如大至約3米乘4米。在此等應用中，此玻璃通常為至少約2 mm厚且更常見為4 mm至6 mm厚。 In a preferred embodiment of the present invention, the first substrate 24 and the second substrate 25 are each floating glass. In a particular embodiment of the architectural application, the glass is at least 0.5 meters by 0.5 meters and can be much larger, for example up to about 3 meters by 4 meters. In such applications, the glass is typically at least about 2 mm thick and more commonly 4 mm to 6 mm thick.

不限於應用，本發明之電致變色裝置可具有大範圍之大小。通常，較佳的是電致變色裝置包括具有至少0.001平方米之表面積之表面之一基板。舉例而言，在特定實施例中，電致變色裝置包括具有至少0.01平方米之表面積之表面一基板。進一步舉例而言，在特定實施例中，電致變色裝置包括具有至少0.1平方米之表面積之表面之一基板。進一步舉例而言，在特定實施例中，電致變色裝置包括具有至少1平方米之表面積之表面之一基板。進一步舉例而言，在特定實施例中，電致變色裝置包括具有至少5平方米之表面積之表面之一基板。進一步舉例而言，在特定實施例中，電致變色裝置包括具有至少10平方米之表面積之表面之一基板。 Without limitation, the electrochromic device of the present invention can have a wide range of sizes. Generally, it is preferred that the electrochromic device comprises a substrate having a surface having a surface area of at least 0.001 square meters. For example, in a particular embodiment, the electrochromic device comprises a surface-substrate having a surface area of at least 0.01 square meters. By way of further example, in a particular embodiment, the electrochromic device comprises a substrate having a surface having a surface area of at least 0.1 square meters. By way of further example, in a particular embodiment, the electrochromic device comprises a substrate having a surface having a surface area of at least 1 square meter. By way of further example, in a particular embodiment, the electrochromic device comprises a substrate having a surface having a surface area of at least 5 square meters. By way of further example, in a particular embodiment, the electrochromic device comprises a substrate having a surface having a surface area of at least 10 square meters.

兩個導電層22、23之至少一者較佳亦透明以向周圍環境顯露堆疊28之電致變色性質。在一實施例中，導電層23係透明。在另一實施例中，導電層22、23各係透明。在特定實施例中，導電層22、23之一者或兩者係無機及/或固體。導電層22及23可由許多不同透明材料製成，包含透明導電氧化物、薄金屬塗層、導電奈米粒子之網狀物(例如，桿、管、點)、導電金屬氮化物及複合導體。透明導電氧化物包含金屬氧化物及摻雜有一種或多種金 屬之金屬氧化物。此等金屬氧化物及摻雜之金屬氧化物之實例包含氧化銦、氧化銦錫、摻雜之氧化銦、氧化錫、摻雜之氧化錫、氧化鋅、氧化鋁鋅、摻雜之氧化鋅、氧化釕、摻雜之氧化釕及類似物。透明導電氧化物有時稱作(TCO)層。亦可使用大致透明之薄金屬塗層。用作此等薄金屬塗層之金屬之實例包含金、鉑、銀、鋁、鎳及此等之合金。透明導電氮化物之實例包含氮化鈦、氮化鉭、氮氧化鈦及氮氧化鉭。導電層22及23亦可為透明複合導體。可藉由將高導電陶瓷及金屬線或導電層圖案放置於基板之面之一者上且接著用透明導電材料(諸如摻雜之氧化錫或氧化銦錫)外塗而製作此等複合導體。理想地，此等線應為足夠薄至為肉眼所看不見(例如，約100 μm或更薄)。對可見光透明之電子導體22及23之非排他性實例係氧化銦錫(ITO)、氧化錫、氧化鋅、氧化鈦、n或p摻雜之氧化鋅及氟氧化鋅之薄膜。最近亦已發開基於金屬之層(諸如ZnS/Ag/ZnS)及碳奈米管層。取決於特定應用，一或兩個導電層22及23可由金屬格柵製成或包含金屬格柵。 At least one of the two conductive layers 22, 23 is preferably also transparent to reveal the electrochromic properties of the stack 28 to the surrounding environment. In an embodiment, the conductive layer 23 is transparent. In another embodiment, the conductive layers 22, 23 are each transparent. In a particular embodiment, one or both of the electrically conductive layers 22, 23 are inorganic and/or solid. Conductive layers 22 and 23 can be made from a variety of different transparent materials, including transparent conductive oxides, thin metal coatings, meshes of conductive nanoparticles (eg, rods, tubes, dots), conductive metal nitrides, and composite conductors. The transparent conductive oxide comprises a metal oxide and is doped with one or more gold Metal oxides. Examples of such metal oxides and doped metal oxides include indium oxide, indium tin oxide, doped indium oxide, tin oxide, doped tin oxide, zinc oxide, aluminum zinc oxide, doped zinc oxide, Cerium oxide, doped cerium oxide and the like. Transparent conductive oxides are sometimes referred to as (TCO) layers. A substantially transparent thin metal coating can also be used. Examples of metals used as such thin metal coatings include gold, platinum, silver, aluminum, nickel, and alloys thereof. Examples of the transparent conductive nitride include titanium nitride, tantalum nitride, titanium oxynitride, and hafnium oxynitride. Conductive layers 22 and 23 can also be transparent composite conductors. The composite conductors can be fabricated by placing highly conductive ceramic and metal wire or conductive layer patterns on one of the faces of the substrate and then overcoating with a transparent conductive material such as doped tin oxide or indium tin oxide. Ideally, the lines should be sufficiently thin to be invisible to the naked eye (eg, about 100 μm or less). Non-exclusive examples of electronic conductors 22 and 23 that are transparent to visible light are thin films of indium tin oxide (ITO), tin oxide, zinc oxide, titanium oxide, n or p-doped zinc oxide, and zinc oxyfluoride. Metal-based layers (such as ZnS/Ag/ZnS) and carbon nanotube layers have also recently been developed. Depending on the particular application, one or both of the conductive layers 22 and 23 may be made of or comprise a metal grid.

可藉由包括於層內之材料之組合物及其透明特徵影響導電層之厚度。在一些實施例中，導電層22及23係透明且各具有介於約1000 nm與約50 nm之間之一厚度。在一些實施例中，導電層22及23之厚度介於約500 nm與約100 nm之間。在其他實施例中，導電層22及23各具有介於約400 nm與約200 nm之間之一厚度。通常， 只要較厚或較薄層提供所需之電性質(例如，導電率)及光學性質(例如，透射率)，便可採用該等較厚或較薄層。對於特定應用，通常較佳導電層22及23儘可能薄以增加透明度及降低成本。 The thickness of the conductive layer can be affected by the composition of the material included in the layer and its transparent characteristics. In some embodiments, conductive layers 22 and 23 are transparent and each have a thickness between about 1000 nm and about 50 nm. In some embodiments, the conductive layers 22 and 23 have a thickness between about 500 nm and about 100 nm. In other embodiments, conductive layers 22 and 23 each have a thickness between about 400 nm and about 200 nm. usually, These thicker or thinner layers can be used as long as the thicker or thinner layer provides the desired electrical properties (e.g., electrical conductivity) and optical properties (e.g., transmittance). For certain applications, it is generally preferred that the conductive layers 22 and 23 be as thin as possible to increase transparency and reduce cost.

再次參考第1圖，導電層之功能係將由電源在電致變色堆疊28之整個表面上提供之電位施加至堆疊之內部區域。電位透過至導電層之電連接而轉移至導電層。在一些實施例中，一者與第一導電層22接觸且一者與第二導電層23接觸之匯流排條提供電壓源與導電層22及23之間之電連接。 Referring again to Figure 1, the function of the conductive layer is to apply the potential provided by the power supply over the entire surface of the electrochromic stack 28 to the interior region of the stack. The potential is transferred to the conductive layer through electrical connection to the conductive layer. In some embodiments, a bus bar that is in contact with the first conductive layer 22 and that is in contact with the second conductive layer 23 provides an electrical connection between the voltage source and the conductive layers 22 and 23.

在一實施例中，第一導電層22及第二導電層23之薄層電阻R_s為約500Ω/□至1Ω/□。在一些實施例中，第一導電層22及第二導電層23之薄層電阻為約100Ω/□至5Ω/□。通常，需要第一導電層22及第二導電層23之各者之薄層電阻大約相同。在一實施例中，第一導電層22及第二導電層23各具有約20Ω/□至約8Ω/□之薄層電阻。 In one embodiment, the sheet resistance R _s of the first conductive layer 22 and the second conductive layer 23 is about 500 Ω/□ to 1 Ω/□. In some embodiments, the first conductive layer 22 and the second conductive layer 23 have a sheet resistance of about 100 Ω/□ to 5 Ω/□. Generally, the sheet resistance of each of the first conductive layer 22 and the second conductive layer 23 is required to be about the same. In one embodiment, the first conductive layer 22 and the second conductive layer 23 each have a sheet resistance of about 20 Ω/□ to about 8 Ω/□.

為了促進電致變色裝置1更快速地從較大透射率狀態切換至較小透射率狀態或反之亦然，導電層22、23之至少一者較佳具有針對穿過層之電子之流動之不均勻薄層電阻R_s。舉例而言，在一實施例中，僅第一導電層22及第二導電層23之一者具有針對穿過該層之電子之流動之不均勻薄層電阻。或者且通常更佳，第一導電層22及第二導電層23各具有針對穿過各自層之電子之流動之不均 勻薄層電阻。在未受任何特定理論約束之情況下，目前據信空間上改變導電層22之薄層電阻、空間上改變導電層23之薄層電阻或空間上改變導電層22及導電層23之薄層電阻藉由控制導電層中之電壓降以在裝置之區域內提供跨裝置之均勻電位降或所要不均勻電位降來改進裝置之切換效能。 In order to facilitate the faster switching of the electrochromic device 1 from a larger transmittance state to a lower transmittance state or vice versa, at least one of the conductive layers 22, 23 preferably has a flow for electrons passing through the layer. Uniform sheet resistance R _s . For example, in one embodiment, only one of the first conductive layer 22 and the second conductive layer 23 has an uneven sheet resistance for the flow of electrons through the layer. Alternatively and generally better, the first conductive layer 22 and the second conductive layer 23 each have an uneven sheet resistance for the flow of electrons through the respective layers. Without being bound by any particular theory, it is presently believed to spatially change the sheet resistance of the conductive layer 22, spatially change the sheet resistance of the conductive layer 23, or spatially change the sheet resistance of the conductive layer 22 and the conductive layer 23. The switching efficiency of the device is improved by controlling the voltage drop in the conductive layer to provide a uniform potential drop across the device or a desired uneven potential drop in the region of the device.

通常，電路模型化可用於考慮電致變色裝置之類型，裝置形狀及尺寸，電極特性及至電壓源之電連接(例如，匯流排條)之放置來決定提供所要切換效能之薄層電阻分佈。接著可至少部分藉由使(諸)第一導電層及/或第二導電層之厚度成梯度；使(諸)第一導電層及/或第二導電層之組合物成梯度或使(諸)第一導電層及/或第二導電層圖案化或此等之一些組合來控制薄層電阻分佈。 In general, circuit modeling can be used to consider the type of electrochromic device, the shape and size of the device, the characteristics of the electrodes, and the placement of electrical connections to the voltage source (e.g., bus bars) to determine the sheet resistance distribution that provides the desired switching performance. The composition of the first conductive layer and/or the second conductive layer may be graded or graded at least in part by gradients of the thickness of the first conductive layer(s) and/or the second conductive layer(s) The first conductive layer and/or the second conductive layer are patterned or some combination thereof to control the sheet resistance distribution.

在一例示性實施例中，電致變色裝置係矩形電致變色窗。再次參考第1圖，在此實施例中，第一基板24及第二基板25係矩形玻璃面板或其他透明基板且電致變色裝置1具有分別定位於第一電極層20及第二電極層21之相對側上之兩個匯流排條26、27。當以此方式組態時，通常較佳針對第一導電層22中之電子之流動之電阻隨與匯流排條26相距之距離增大而增加且針對第二導電層23中之電子之流動之電阻隨與匯流排條27相距之距離增大而增加。此接著可(舉例而言)藉由根據與匯流排條26相距之距離之增大而減小第一導電層22之厚度及根據與匯流排條27相距之距離之減小而減小第二導電層 23之厚度而實現。 In an exemplary embodiment, the electrochromic device is a rectangular electrochromic window. Referring again to FIG. 1 , in this embodiment, the first substrate 24 and the second substrate 25 are rectangular glass panels or other transparent substrates and the electrochromic device 1 has a first electrode layer 20 and a second electrode layer 21 respectively. Two bus bars 26, 27 on opposite sides. When configured in this manner, it is generally preferred that the resistance to the flow of electrons in the first conductive layer 22 increases as the distance from the bus bar 26 increases and for the flow of electrons in the second conductive layer 23. The resistance increases as the distance from the bus bar 27 increases. This can then, by way of example, reduce the thickness of the first conductive layer 22 by an increase in the distance from the bus bar 26 and reduce the second according to the decrease in the distance from the bus bar 27 Conductive layer 23 thickness is achieved.

本發明之多層裝置可具有除了矩形之外之形狀；可具有多於兩個匯流排條及/或在裝置之相對層上可以不具有匯流排條。例如，多層裝置可具有更通常為四邊形之周邊或具有比(例如)四個更多或更少之邊之形狀，多層裝置在形狀上可為三角形、五邊形、六邊形等。進一步舉例而言，多層裝置可具有彎曲但缺少頂點之周邊，例如圓形、橢圓形等。進一步舉例而言，多層裝置可包括將多層裝置連接至電壓源之三個、四個或更多個匯流排條或無數量限制之匯流排條可定位於非相對側上。在此等實例之各者中，(諸)導電層中之較佳電阻分佈可與針對矩形、兩個匯流排條組態之描述不同。 The multilayer device of the present invention may have a shape other than a rectangular shape; may have more than two bus bars and/or may have no bus bars on the opposite layer of the device. For example, the multilayer device can have a shape that is more generally a quadrilateral perimeter or has a shape that is more than, for example, four or fewer sides, and the multilayer device can be triangular, pentagonal, hexagonal, etc. in shape. By way of further example, a multi-layer device can have a perimeter that is curved but lacks vertices, such as a circle, an ellipse, or the like. By way of further example, the multi-layer device can include three, four or more bus bars or a limitless bus bar connecting the multilayer device to a voltage source that can be positioned on a non-opposite side. In each of these examples, the preferred resistance distribution in the conductive layer(s) may be different than the description for the rectangular, two bus bar configurations.

但是，通常不限於多層裝置是否具有除了矩形之外之形狀，存在多於兩個電連接(例如，匯流排條)，及/或電連接(例如，匯流排條)位於裝置之相對側上，第一導電層22中、第二導電層23中或第一導電層22及第二導電層23中之薄層電阻R_s可被繪製成接合以在第一導電層及/或第二導電層內之(二維)位置為函數之相等薄層電阻之點(即，等電阻線)。此一般性質之曲線圖(有時稱作等高線圖)常在製圖中用於接合等高之點。在本發明之背景內容中，以在第一導電層及/或第二導電層內之(二維)位置為函數之第一導電層及/或第二導電層中之薄層電阻R_s之等高線圖較佳含有一系列等電阻線(有時亦稱作等高線)及電阻梯度線(垂直於等電阻線之線)。 沿著(諸)第一導電層及/或第二導電層中之梯度線之薄層電阻大致增大、大致減小、大致增大直至其達到最大值且隨後大致減小或大致減小直至其達到最小值且隨後大致增大。 However, it is generally not limited to whether the multilayer device has a shape other than a rectangle, there are more than two electrical connections (eg, bus bars), and/or electrical connections (eg, bus bars) are on opposite sides of the device, The sheet resistance R _{s of the} first conductive layer 22, the second conductive layer 23 or the first conductive layer 22 and the second conductive layer 23 may be drawn to be bonded to the first conductive layer and/or the second conductive layer The inner (two-dimensional) position is the point of the equivalent sheet resistance of the function (ie, the equal resistance line). This general nature graph (sometimes referred to as a contour map) is often used in drawing to join contours. In the context of the present invention, the sheet resistance R _s in the first conductive layer and/or the second conductive layer as a function of the (two-dimensional) position within the first conductive layer and/or the second conductive layer The contour map preferably contains a series of equal-resistance lines (sometimes referred to as contour lines) and resistive gradient lines (perpendicular to the lines of the equal-resistance lines). The sheet resistance along the gradient lines in the first conductive layer and/or the second conductive layer increases substantially, substantially decreases, substantially increases until it reaches a maximum value and then decreases or substantially decreases until It reaches a minimum and then increases substantially.

第2A圖至第2E圖描繪以在根據本發明之電致變色堆疊之若干例示性實施例之導電層內之(二維)位置為函數之一導電層(即，第一導電層、第二導電層或第一導電層及第二導電層之各者)中之薄層電阻R_s之等高線圖。在第2A圖至第2E圖之各者中，等高線圖50描繪由具有正方形(第2A圖、第2B圖及第2C圖)或圓形(第2D圖及第2E圖)之周邊及與電致變色堆疊之第一導電層及第二導電層(未標注)接觸之變化數量及位置之匯流排條226及227之電致變色堆疊所得之一組薄層等電阻曲線52(即，薄層電阻R_s沿其具有恆定值之曲線)及垂直於等電阻曲線52之一組電阻梯度曲線54。在第2A圖中，該組梯度54之方向指示導電層內之薄層電阻R_s沿著該組梯度54及在與匯流排條227接觸之導電層之西側55與東側56之間逐進增加。在第2B圖中，梯度54A之方向指示與匯流排條227接觸之導電層內之薄層電阻R_s從西南角57至形心59逐進減小且隨後從形心59至東北角58減小。在第2C圖中，該組梯度54之方向指示與匯流排條227接觸之導電層內之薄層電阻R_s從西側60及東側61至形心59逐進減小且從頂側58及底側57至形心59逐進增加；換言之，薄層電阻R_s形成以形心59為中心之鞍狀 形式。在第2D圖中，梯度54a及54b之方向指示與匯流排條227接觸之導電層內之薄層電阻R_s從位置64及65之各者至形心59逐進減小且從位置63及62之各者至形心59逐進增加；換言之，薄層電阻R_s形成以形心59為中心之鞍狀形式。在第2E圖中，該組梯度54之方向指示與匯流排條227接觸之導電層內之薄層電阻R_s從西側55至東側56逐進減小。舉例而言，在一實施例中，薄層電阻中之梯度係常數。進一步舉例而言，在一實施例中，薄層電阻中之梯度係常數且基板在形狀上為矩形。 2A through 2E depict one conductive layer (ie, first conductive layer, second) as a function of (two-dimensional) position within a conductive layer of several exemplary embodiments of an electrochromic stack in accordance with the present invention. A contour plot of the sheet resistance R _s of the conductive layer or each of the first conductive layer and the second conductive layer. In each of FIGS. 2A to 2E, the contour map 50 depicts the periphery and the electric power having squares (2A, 2B, and 2C) or circles (2D and 2E). A set of thin layer isoelectric resistance curves 52 (ie, thin layers) obtained by electrochromic stacking of the first conductive layer and the second conductive layer (not labeled) of the color-changing stack and the electrochromic stack of the bus bars 226 and 227 A resistance R _s along its curve having a constant value and a set of resistance gradient curves 54 perpendicular to the isoelectric resistance curve 52 . In FIG. 2A, the direction of the set of gradient 54 indicates a sheet resistance R _s of the inner conductive layer 54 and the set of gradient by gradual increases in the west between the conductive layers 227 and contacts the bus bar 55 and the east side 56 . In Figure 2B, the direction of the gradient indicates the bus bar 54A of the sheet resistance R _s of electrically conductive inner layer 227 of the contact 57 from the southwest corner to a centroid 59 and then gradually decreases from the inlet 59 to the northeast corner of the centroid Save 58 small. In the FIG. 2C, the direction of the set of gradient bus bar 54 indicative of the sheet resistance R _s of electrically conductive inner layer 227 of the contact 61 from the west side to the east side 60 and centroid 59 and reduced by feeding from the top side 58 and the bottom The side 57 to the centroid 59 are progressively increased; in other words, the sheet resistance R _s forms a saddle-like form centered on the centroid 59. In FIG. 2D, the direction of the gradient indicated 54a and 54b of the bus bar and sheet resistance R _s of electrically conductive inner layer 227 of the contact persons from the respective positions 64 and 65 to the feed by reducing the centroid 59 and 63 and from the position Each of the 62 to centroids is progressively increased; in other words, the sheet resistance R _s forms a saddle-like form centered on the centroid 59. In the FIG. 2E, the direction of the gradient set 54 of bus bar indicating the sheet resistance R _s of electrically conductive inner layer 227 in contact with the feed is reduced by 55 from the west to the east side 56. For example, in one embodiment, the gradient in the sheet resistance is constant. By way of further example, in one embodiment, the gradient in the sheet resistance is constant and the substrate is rectangular in shape.

在目前較佳之實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約1.25。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約1.5。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約2。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約3。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約4。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值Rmin之比率為至少約5。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約6。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻 之值R_min之比率為至少約7。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約8。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約9。在一例示性實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約10。 In a presently preferred embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 1.25. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 1.5. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 2. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 3. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 4. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value Rmin in the first conductive layer is at least about 5. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 6. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 7. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 8. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 9. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer is at least about 10.

第21圖繪示多層電致變色裝置1之第一導電層22之薄層電阻之不均勻。第一導電層22包括薄層電阻梯度曲線(該線包括線段X₁-Y₁，其如結合圖2所述，指示導電層22內之薄層電阻R_s逐進增加)。在X₁與Y₁之間，第一導電層22之薄層電阻大致增大，大致減小或大致增大且隨後減小。在一實施例中，線段X₁-Y₁具有至少1 cm之一長度。舉例而言，線段X₁-Y₁可具有2.5 cm、5 cm、10 cm或25 cm之一長度。此外，線段X₁-Y₁可為筆直或彎曲。 FIG. 21 illustrates the unevenness of the sheet resistance of the first conductive layer 22 of the multilayer electrochromic device 1. A first conductive layer 22 comprises a sheet resistance gradients (including the line segment X ₁ -Y _1, which as in connection with Figure 2, indicating the sheet resistance R _s of the conductive layer 22 by gradual increase). Between X ₁ and Y ₁ , the sheet resistance of the first conductive layer 22 increases substantially, substantially decreasing or substantially increasing and then decreasing. In an embodiment, the line segment X ₁ -Y ₁ has a length of at least 1 cm. For example, the line segment X ₁ -Y ₁ may have a length of 2.5 cm, 5 cm, 10 cm or 25 cm. Further, the line segments X ₁ -Y ₁ may be straight or curved.

在一實施例中，可藉由將第一導電層之兩個不同區域中之平均薄層電阻R_avg之比率作比較來觀察第一導電層之薄層電阻之不均勻，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25，其中第一區域及第二區域之各者由凸多邊形限定且各包括第一導電層之表面積之至少25%。此可參考第21圖繪示。第一導電層22 包括凸多邊形A₁及凸多邊形B₁且各限定包括第一導電層22之表面積之至少25%之一區域；在一實施例中，以凸多邊形A₁為界限之第一導電層之第一區域中之平均薄層電阻R¹ _avg對以凸多邊形B₁為界限之第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25。如所示，僅為例證之目的，凸多邊形A₁為三角形且凸多邊形B₁為正方形；實踐中，第一區域可以任何凸多邊形為界限且第二區域可以任何凸多邊形為界限。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少3，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少4，其中第一區域及第二區域各由凸多邊形限定且 各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少5，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少6，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少7，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少8，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少9，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中 之平均薄層電阻R² _avg之比率為至少10，其中第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%。在前述實例之各者中之一實施例中，第一區域及第二區域係互不相交區域。 In one embodiment, the sheet resistance of the first conductive layer can be observed by comparing the ratio of the average sheet resistance R _avg in two different regions of the first conductive layer, wherein the first region and The second regions are each defined by a convex polygon and each comprise at least 25% of the surface area of the first conductive layer. For example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _avg in the second region of the first conductive layer is at least 1.25, wherein each of the first region and the second region is defined by a convex polygon and each includes at least 25% of a surface area of the first conductive layer. This can be seen in Figure 21. The first conductive layer 22 includes a convex polygon A ₁ and a convex polygon B ₁ and each defines a region including at least 25% of the surface area of the first conductive layer 22; in one embodiment, the first is bounded by the convex polygon A ₁ a first conductive layer of the region of sheet resistance R ¹ _avg average of convex polygons B ₁ is a first region of a second conductive layer in the limit of the sheet resistance R ² _avg average ratio of at least 1.25. As shown, for illustrative purposes only, the convex polygon A ₁ is a triangle and the convex polygon B ₁ is a square; in practice, the first region may be bounded by any convex polygon and the second region may be bounded by any convex polygon. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 1.5, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of the surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 2, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 3, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 4, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 5, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 6, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 7, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 8, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. Further example, in one embodiment of this embodiment, the first region of the first conductive layer in the average sheet resistance R ¹ _avg second region of the first conductive layer of the sheet resistance R of the average of the ratio is ² _avg At least 9, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 10, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the first conductive layer. In one of the foregoing embodiments, the first region and the second region are mutually disjoint regions.

在一實施例中，可藉由將第一導電層之四個不同區域中之平均薄層電阻R_avg作比較來觀察第一導電層之薄層電阻之不均勻，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第一導電層之表面積之至少10%。舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25，第一導電層之第二區域中之平均薄層電阻R² _avg對第一導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少1.25，第一導電層之第三區域中之平均薄層電阻R³ _avg對第一導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.25，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第一導電層之表面積之至少10%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5，第一導電層之第二區域中之平均薄層電阻R² _avg對第一導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少1.5，第一導電層之第三區 域中之平均薄層電阻R³ _avg對第一導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.5，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第一導電層之表面積之至少10%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2，第一導電層之第二區域中之平均薄層電阻R² _avg對第一導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少2，第一導電層之第三區域中之平均薄層電阻R³ _avg對第一導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少2，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第一導電層之表面積之至少10%。在前述實例之各者中之一實施例中，第一區域、第二區域、第三區域及第四區域係互不相交區域。 In one embodiment, the sheet resistance of the first conductive layer can be observed by comparing the average sheet resistance R _avg of the four different regions of the first conductive layer, wherein the first region and the second region The regions are contiguous, the second region is contiguous with the third region, and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the first conductive layer. For example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _avg in the second region of the first conductive layer is at least 1.25, the ratio of the average sheet resistance R ² _avg in the second region of the first conductive layer to the average sheet resistance R ³ _avg in the third region of the first conductive layer is at least 1.25, the third of the first conductive layer The ratio of the average sheet resistance R ³ _avg in the region to the average sheet resistance R ⁴ _avg in the fourth region of the first conductive layer is at least 1.25, wherein the first region is adjacent to the second region, and the second region is third The regions are contiguous and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 1.5, the ratio of the average sheet resistance R ² _avg in the second region of the first conductive layer to the average sheet resistance R ³ _avg in the third region of the first conductive layer is at least 1.5, the first conductive layer three in the area of the average sheet resistance R ³ _avg fourth region of the first conductive layer of the sheet resistance R in the average rate of ⁴ _avg of at least 1.5, wherein the first region and the second region adjoins the second region and the second The three regions are contiguous and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the first conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 2, the ratio of the average sheet resistance R ² _avg in the second region of the first conductive layer to the average sheet resistance R ³ _avg in the third region of the first conductive layer is at least 2, the first conductive layer three in the area of the average sheet resistance R ³ _avg fourth region of the first conductive layer of the sheet resistance R in the average rate of ⁴ _avg of at least 2, wherein the first region and the second region adjoins the second region and the second The three regions are contiguous and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the first conductive layer. In one of the foregoing embodiments, the first region, the second region, the third region, and the fourth region are mutually disjoint regions.

在目前較佳之實施例中，第二導電層具有以在第二導電層中之位置為函數而變化之針對穿過第二導電層之電流之流動之薄層電阻R_s。在一此實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約1.25。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約1.5。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至 少約2。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約3。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約4。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約5。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約6。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約7。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約8。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約9。在一例示性實施例中，第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約10。 In the presently preferred embodiment, the second conductive layer has at the position of the second conductive layer is changed for the flow of current through the thin layer of the second conductive layer of the resistor R _s represents a function. In one embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 1.25. In an exemplary embodiment, the ratio of the value of the maximum sheet resistance _Rmax in the second conductive layer to the value _Rmin of the minimum sheet resistance is at least about 1.5. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 2. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 3. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _{Rmin in} the second conductive layer is at least about 4. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 5. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 6. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 7. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 8. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _{Rmin in} the second conductive layer is at least about 9. In an exemplary embodiment, the ratio of the maximum sheet resistance value _Rmax in the second conductive layer to the minimum sheet resistance value _Rmin is at least about 10.

第21圖繪示多層電致變色裝置1之第二導電層23之薄層電阻之不均勻。導電層22包括薄層電阻梯度曲線54，該薄層電阻梯度曲線54包含線段X-Y；在X與Y之間，第二導電層23之薄層電阻大致增大、大致減小或大致增大且隨後減小。在一實施例中，線段X₁-Y₁具有至少1 cm之一長度。舉例而言，線段X-Y可具有2.5 cm、5 cm、10 cm或25 cm之一長度。此外，線段X-Y可為筆直或彎曲。 Fig. 21 is a view showing the unevenness of the sheet resistance of the second conductive layer 23 of the multilayer electrochromic device 1. The conductive layer 22 includes a thin layer resistance gradient curve 54 comprising a line segment XY; between X and Y, the sheet resistance of the second conductive layer 23 is substantially increased, substantially reduced or substantially increased and Then decrease. In an embodiment, the line segment X ₁ -Y ₁ has a length of at least 1 cm. For example, the line segment XY may have a length of 2.5 cm, 5 cm, 10 cm, or 25 cm. In addition, the line segment XY can be straight or curved.

在一實施例中，可藉由將第二導電層之兩個不同區域 中之平均薄層電阻R_avg之比率作比較來觀察第二導電層之薄層電阻之不均勻，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。此可參考第21圖繪示。第二導電層23包括凸多邊形A及凸多邊形B且各限定包括第二導電層23之表面積之至少25%之一區域；在一實施例中，以凸多邊形A為界限之第二導電層之第一區域中之平均薄層電阻R¹ _avg對以凸多邊形B為界限之第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25。如所示，僅為例證之目的，凸多邊形A為三角形且凸多邊形B為正方形；實踐中，第一區域可以任何凸多邊形為界限且第二區域可以任何凸多邊形為界限。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2，其中第一區域及第二區域之各由凸多邊形限定且各包括第二導電層之表面積之至 少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少3，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少4，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少5，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少6，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少7，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為 至少8，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少9，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少10，其中第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。在前述實例之各者中之一實施例中，第一區域及第二區域係互不相交區域。 In one embodiment, the sheet resistance of the second conductive layer can be observed by comparing the ratio of the average sheet resistance R _avg in two different regions of the second conductive layer, wherein the first region and The second regions are each defined by convex polygons and each include at least 25% of the surface area of the second conductive layer. For example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _avg in the second region of the second conductive layer is at least 1.25, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. This can be seen in Figure 21. The second conductive layer 23 includes a convex polygon A and a convex polygon B and each defines a region including at least 25% of the surface area of the second conductive layer 23; in one embodiment, the second conductive layer is bounded by the convex polygon A The ratio of the average sheet resistance R ¹ _avg in the first region to the average sheet resistance R ² _avg in the second region of the second conductive layer bounded by the convex polygon B is at least 1.25. As shown, for illustrative purposes only, the convex polygon A is a triangle and the convex polygon B is a square; in practice, the first region may be bounded by any convex polygon and the second region may be bounded by any convex polygon. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 1.5, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 2, wherein each of the first region and the second region is defined by a convex polygon and each includes at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 3, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 4, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. Of further example, in the embodiment, the first region of the second conductive layers in the average sheet resistance R ¹ _avg this embodiment a second region of the second conductive layer of the sheet resistance R of the average of the ratio is ² _avg At least 5, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 6, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 7, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 8, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 9, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 10, wherein the first region and the second region are each defined by a convex polygon and each comprise at least 25% of a surface area of the second conductive layer. In one of the foregoing embodiments, the first region and the second region are mutually disjoint regions.

在一實施例中，可藉由將第二導電層之四個不同區域中之平均薄層電阻R_avg作比較來觀察第二導電層之薄層電阻之不均勻，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第二導電層之表面積之至少10%。例如，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25，第二導電層之第二區域中之平均薄層電阻R² _avg對第二導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少1.25，第二導電層之第三區域中之平均薄層電阻R³ _avg對第二導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.25，其中第 一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第二導電層之表面積之至少10%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5，第二導電層之第二區域中之平均薄層電阻R² _avg對第二導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少1.5，第二導電層之第三區域中之平均薄層電阻R³ _avg對第二導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.5，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第二導電層之表面積之至少10%。進一步舉例而言，在一此實施例中，第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2，第二導電層之第二區域中之平均薄層電阻R² _avg對第二導電層之第三區域中之平均薄層電阻R³ _avg之比率為至少2，第二導電層之第三區域中之平均薄層電阻R³ _avg對第二導電層之第四區域中之平均薄層電阻R⁴ _avg之比率為至少2，其中第一區域與第二區域鄰接，第二區域與第三區域鄰接，第三區域與第四區域鄰接，區域之各者由凸多邊形限定且各包括第二導電層之表面積之至少10%。在前述實例之各者中之一實施例中，第一區域、第二區域、第三區域及第四區域係互不相交區域。 In one embodiment, the sheet resistance of the second conductive layer can be observed by comparing the average sheet resistance R _avg of the four different regions of the second conductive layer, wherein the first region and the second region The regions are contiguous, the second region is contiguous with the third region, and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the second conductive layer. For example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _avg in the second region of the second conductive layer is at least 1.25. a ratio of an average sheet resistance R ² _avg in a second region of the second conductive layer to an average sheet resistance R ³ _avg in a third region of the second conductive layer of at least 1.25, in a third region of the second conductive layer the average sheet resistance R ³ _avg fourth region of the second conductive layer of the sheet resistance R in the average rate of ⁴ _avg of at least 1.25, wherein the first region and a second region adjacent to the second and third regions adjacent to The third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 1.5, the ratio of the average sheet resistance R ² _avg in the second region of the second conductive layer to the average sheet resistance R ³ _avg in the third region of the second conductive layer is at least 1.5, and the second conductive layer three in the area of the average sheet resistance R ³ _avg fourth region of the second conductive layer of the sheet resistance R in the average rate of ⁴ _avg of at least 1.5, wherein the first region and the second region adjoins the second region and the second The three regions are contiguous and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the second conductive layer. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the second conductive layer to the average sheet resistance R ² _{avg in} the second region of the second conductive layer is At least 2, the ratio of the average sheet resistance R ² _avg in the second region of the second conductive layer to the average sheet resistance R ³ _avg in the third region of the second conductive layer is at least 2, and the second conductive layer three in the area of the average sheet resistance R ³ _avg fourth region of the second conductive layer of the sheet resistance R in the average rate of ⁴ _avg of at least 2, wherein the first region and the second region adjoins the second region and the second The three regions are contiguous and the third region is contiguous with the fourth region, each of the regions being defined by the convex polygons and each comprising at least 10% of the surface area of the second conductive layer. In one of the foregoing embodiments, the first region, the second region, the third region, and the fourth region are mutually disjoint regions.

在目前較佳之實施例中，第一導電層22及第二導電層23具有以在第一導電層及第二導電層中之位置為函數而變化之針對穿過第二導電層之電流之流動之薄層電阻R_s。雖然在此實施例中通常較佳在第一導電層及第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為大約相同，但是其等可具有不同值。例如，在一此實施例中，在第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率具有為第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率之至少兩倍之多之一值。但是，更通常而言，在第一導電層及第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率將大約相同且各為至少約1.25。在一例示性實施例中，在第一導電層及第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率將大約相同且各為至少約1.5。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約2。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約3。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比 率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約4。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約5。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約6。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約7。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約8。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約9。在一例示性實施例中，在第一導電層及第二導電層之各者中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率，最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約10。 In a presently preferred embodiment, the first conductive layer 22 and the second conductive layer 23 have a flow of current through the second conductive layer as a function of position in the first conductive layer and the second conductive layer. Sheet resistance R _s . Although it is generally preferred in this embodiment that the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in the first conductive layer and the second conductive layer is about the same, they may have different values. . For example, in one embodiment of this embodiment, the first conductive layer, the sheet resistance of the maximum value R _max has a value of a second conductive layer of the maximum sheet resistance R _max R _min pairs of the minimum value of the ratio of sheet resistance One of at least twice the ratio of the value of the minimum sheet resistance, _Rmin . More generally, however, the ratio of the maximum sheet resistance value _Rmax to the minimum sheet resistance value _Rmin in the first conductive layer and the second conductive layer will be about the same and each will be at least about 1.25. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in the first conductive layer and the second conductive layer, the maximum sheet resistance value R _{max is} the smallest thin The ratio of the layer resistance values _Rmin will be about the same and each will be at least about 1.5. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 2. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 3. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 4. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 5. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 6. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 7. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 8. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 9. In an exemplary embodiment, the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in each of the first conductive layer and the second conductive layer, the maximum sheet resistance value R _max The ratio of the value of the minimum sheet resistance, _Rmin , is at least about 10.

在一實施例中，可藉由分別將第一導電層及第二導電層之兩個不同區域中之平均薄層電阻R_avg之比率作比較 來觀察第一導電層及第二導電層之薄層電阻之不均勻，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。例如，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.25，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少1.5，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2且第二導 電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少2，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少3且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少3，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少4且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少4，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區 域中之平均薄層電阻R² _avg之比率為至少5且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少5，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少6且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少6，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少7且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少7，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區 域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少8且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少8，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少9且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少9，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。進一步舉例而言，在一此實施例中，第一導電層之第一區域中之平均薄層電阻R¹ _avg對第一導電層之第二區域中之平均薄層電阻R² _avg之比率為至少10且第二導電層之第一區域中之平均薄層電阻R¹ _avg對第二導電層之第二區域中之平均薄層電阻R² _avg之比率為至少10，其中第一導電層之第一區域及第二區域各由凸多邊形限定且各包括第一導電層之表面積之至少25%及第二導電層之第一區域及第二區域各由凸多邊形限定且各包括第二導電層之表面積之至少25%。在前 述實例之各者中之一實施例中，第一區域及第二區域係互不相交區域。 In one embodiment, the first conductive layer and the second conductive layer can be observed by comparing the ratios of the average sheet resistances R _avg in the two different regions of the first conductive layer and the second conductive layer, respectively. The layer resistance is uneven, wherein the first region and the second region of the first conductive layer are each defined by the convex polygon and each includes at least 25% of the surface area of the first conductive layer and the first region and the second region of the second conductive layer Each is defined by a convex polygon and each includes at least 25% of the surface area of the second conductive layer. For example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _avg in the second region of the first conductive layer is at least 1.25 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer of at least 1.25, wherein the first region of the first conductive layer And the second regions are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by the convex polygons and each includes a surface area of the second conductive layer At least 25%. Further example, in one embodiment of this embodiment, the first region of the first conductive layer in the average sheet resistance R ¹ _avg second region of the first conductive layer of the sheet resistance R of the average of the ratio is ² _avg a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer of at least 1.5 and at least 1.5, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 2 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 2, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 3 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 3, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 4 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 4, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 5 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 5, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. Further example, in one embodiment of this embodiment, the first region of the first conductive layer in the average sheet resistance R ¹ _avg second region of the first conductive layer of the sheet resistance R of the average of the ratio is ² _avg At least 6 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 6, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 7 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 7, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 8 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 8, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 9 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 9, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. By way of further example, in one embodiment, the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _{avg in} the second region of the first conductive layer is At least 10 and a ratio of an average sheet resistance R ¹ _avg in the first region of the second conductive layer to an average sheet resistance R ² _avg in the second region of the second conductive layer is at least 10, wherein the first conductive layer The first region and the second region are each defined by the convex polygons and each includes at least 25% of the surface area of the first conductive layer and the first and second regions of the second conductive layer are each defined by a convex polygon and each includes a second conductive layer At least 25% of the surface area. In one of the foregoing embodiments, the first region and the second region are mutually disjoint regions.

再次參考第21圖，根據本發明之一態樣，第一導電層及第二導電層之薄層電阻之空間不均勻可相關。舉例而言，第一導電層22中之線段X₁-Y₁可穿過第二電極層21、離子傳導層10及第一電極層20投影，且投影至第二導電層23上，該投影界定線段X-Y。通常，若薄層電阻在第一導電層22中沿著線段X₁-Y₁大致增大(即，薄層電阻沿著薄層電阻梯度曲線移動而在從點X₁至點Y₁之方向上大致增大)，則該薄層電阻在第二導電層23中沿著線段X-Y大致減小(即，薄層電阻沿著薄層電阻梯度曲線54且在從點X至點Y之方向上大致減小)。如上所述，線段X-Y及X₁-Y₁具有至少1 cm之長度。舉例而言，線段X-Y及X₁-Y₁可具有2.5 cm、5 cm、10 cm或25 cm之長度。此外，線段X-Y及X₁-Y₁可為筆直或彎曲。在一實施例中，舉例而言，導電層22、23中之薄層電阻梯度係非零常數，且符號相反(例如，該薄層電阻在第一導電層中沿著從點X₁至點Y₁之方向大致線性增大，且沿著薄層電阻梯度曲線54在從點X至點Y之方向上大致線性減小)。進一步舉例而言，在一實施例中，基板24、25係矩形，且導電層22、23中之薄層電阻梯度係非零常數，且符號相反(例如，該薄層電阻在第二導電層23中沿著梯度54在從點X至點Y之方向上大致線性增大，且在第一導電層22中沿著含有線段X₁-Y₁之線在從點X₁至點Y₂之方向上大致線性減 小)。 Referring again to Figure 21, in accordance with one aspect of the present invention, the spatial non-uniformity of the sheet resistance of the first conductive layer and the second conductive layer can be correlated. For example, the line segment X ₁ -Y ₁ in the first conductive layer 22 can be projected through the second electrode layer 21, the ion conductive layer 10 and the first electrode layer 20, and projected onto the second conductive layer 23, the projection Define the line segment XY. Generally, if the sheet resistance is substantially increased along the line segment X ₁ -Y ₁ in the first conductive layer 22 (ie, the sheet resistance moves along the sheet resistance gradient curve from the point X ₁ to the point Y ₁ The upper layer is substantially increased), the sheet resistance is substantially reduced along the line segment XY in the second conductive layer 23 (ie, the sheet resistance is along the sheet resistance gradient curve 54 and in the direction from point X to point Y Roughly reduced). As described above, the line segments XY and X ₁ -Y ₁ have a length of at least 1 cm. For example, the line segments XY and X ₁ -Y ₁ may have a length of 2.5 cm, 5 cm, 10 cm, or 25 cm. Further, the line segments XY and X ₁ -Y ₁ may be straight or curved. In one embodiment, for example, conductive layers 22, 23 in the sheet resistance of the gradient-based nonzero constant, and the opposite sign (e.g., sheet resistance of the conductive layer in the first direction from the point X ₁ to the point The direction of Y ₁ increases substantially linearly and decreases substantially linearly along the sheet resistance gradient curve 54 from the point X to the point Y. By way of further example, in one embodiment, the substrates 24, 25 are rectangular, and the sheet resistance gradients in the conductive layers 22, 23 are non-zero constant and opposite in sign (eg, the sheet resistance is in the second conductive layer) 23 increases substantially linearly along the gradient 54 from the point X to the point Y, and in the first conductive layer 22 along the line containing the line segment X ₁ -Y ₁ from the point X ₁ to the point Y ₂ The direction is roughly linearly reduced).

在另一實施例中，且仍然參考第21圖，第一導電層及第二導電層之薄層電阻之空間不均勻之特徵可涉及將該第一導電層中之第一區域及第二區域與其等至該第二導電層上之投影分離以在該第二導電層中定義互補的第一區域及第二區域，其中該第一導電層之第一區域及第二區域各以凸多邊形為界限，各含有該第一導電層之表面積之至少25%，且係互不相交之區域。通常，該第一導電層在該第一導電層之第一區域及第二區域中具有平均薄層電阻，且該第二導電層在該第二導電層之互補第一區域及第二區域中具有平均薄層電阻，其中：(a)(i)第一導電層在該第一區域中之平均薄層電阻對第一導電層在該第二區域中之平均薄層電阻之比率為至少1.5，或(ii)第二導電層在該互補第一區域中之平均薄層電阻對第二導電層在該互補第二區域中之平均薄層電阻之比率大於1.5，及(b)第一導電層在該第一區域中之平均薄層電阻對第二導電層在該互補第一區域(即，該第一導電層之第一區域至該第二導電層上之投影)中之平均薄層電阻之比率係第一導電層在該第二區域中之平均薄層電阻對第二導電層在該互補第二區域(即，該第一導電層之第二區域至該第二導電層上之投影)中之平均薄層電阻之比率之至少150%。 In another embodiment, and still referring to FIG. 21, the spatial non-uniformity of the sheet resistance of the first conductive layer and the second conductive layer may involve the first region and the second region in the first conductive layer. And dividing the projection on the second conductive layer to define a complementary first region and a second region in the second conductive layer, wherein the first region and the second region of the first conductive layer are each a convex polygon The boundaries each containing at least 25% of the surface area of the first conductive layer and are regions that do not intersect each other. Generally, the first conductive layer has an average sheet resistance in the first region and the second region of the first conductive layer, and the second conductive layer is in the complementary first region and the second region of the second conductive layer. Having an average sheet resistance, wherein: (a) (i) the ratio of the average sheet resistance of the first conductive layer in the first region to the average sheet resistance of the first conductive layer in the second region is at least 1.5 Or (ii) a ratio of an average sheet resistance of the second conductive layer in the complementary first region to an average sheet resistance of the second conductive layer in the complementary second region of greater than 1.5, and (b) a first conductive An average thin layer of the layer in the first region versus an average thin layer of the second conductive layer in the complementary first region (ie, the projection of the first region of the first conductive layer onto the second conductive layer) The ratio of the resistance is the average sheet resistance of the first conductive layer in the second region to the second conductive layer in the complementary second region (ie, the second region of the first conductive layer to the second conductive layer) At least 150% of the ratio of the average sheet resistance in the projection).

再次參考第21圖，第一導電層22包括區域A₁及區域B₁，其中區域A₁及區域B₁各包括該第一導電層之表面積 之至少25%，且各由凸多邊形限定，且為互不相交之區域。區域A₁至第二導電層23上之投影界定該第二導電層中由一凸多邊形限定之包括該第二導電層之表面積之至少25%之區域A。區域B₁至第二導電層上之投影界定該第二導電層中由一凸多邊形限定之包括該第二導電層之表面積之至少25%之區域B。第一導電層22在區域A₁中具有對應於R^A1 _avg之平均薄層電阻，且在區域B₁中具有對應於R^B1 _avg之平均薄層電阻。第二導電層23在區域A中具有對應於R^A _avg之平均薄層電阻，且在區域B中具有對應於R^B _avg之平均薄層電阻。根據一實施例，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少1.5，及(ii)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少1.5。舉例而言，在一實施例中，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少1.75，及(ii)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少1.75。進一步舉例而言，在一實施例中，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少2，及(ii)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少2。進一步舉例而言，在一實施例中，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少3，及(ii)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少3。進一步舉例而言，在一實施例中，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少5，及(ii)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少5。進一步舉例而言，在一實施例中，(i)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少10，及(ii) (R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少10。 Referring again to FIG. 21, the first conductive layer 22 includes a region A ₁ and a region B ₁ , wherein each of the regions A ₁ and B ₁ includes at least 25% of the surface area of the first conductive layer, and each is defined by a convex polygon, and For areas that do not intersect each other. The projections on region A ₁ to second conductive layer 23 define a region A of the second conductive layer defined by a convex polygon that includes at least 25% of the surface area of the second conductive layer. Regions B _{1 and} the projection of the second conductive layer on the second conductive layer defining a polygonal region defined to include at least 25% of the surface area of the second conductive layer is composed of a convex B. The first conductive layer 22 has an average sheet resistance corresponding to R ^A1 _avg in the region A ₁ and an average sheet resistance corresponding to R ^B1 _avg in the region B ₁ . The second conductive layer 23 has an average sheet resistance corresponding to R ^A _avg in the region A and an average sheet resistance corresponding to R ^B _avg in the region B. According to an embodiment, (i) R ^A1 _avg ratio R ^B1 _avg in or R ^B _avg ratio R ^A _avg is at least 1.5, and _{^{(ii) (R A1 avg /}} R A avg) of (R ^B1 _avg / The ratio of R ^B _avg ) is at least 1.5. For example, in one embodiment, (i) the ratio of R ^A1 _avg to R ^B1 _avg or the ratio of R ^B _avg to R ^A _avg is at least 1.75, and (ii) (R ^A1 _avg /R ^A _avg ) The ratio of (R ^B1 _avg /R ^B _avg ) is at least 1.75. By way of further example, in one embodiment, (i) the ratio of R ^A1 _avg to R ^B1 _avg or the ratio of R ^B _avg to R ^A _avg is at least 2, and (ii) (R ^A1 _avg /R ^A _avg ) The ratio of (R ^B1 _avg /R ^B _avg ) is at least 2. By way of further example, in one embodiment, (i) the ratio of R ^A1 _avg to R ^B1 _avg or the ratio of R ^B _avg to R ^A _avg is at least 3, and (ii) (R ^A1 _avg /R ^A _avg ) The ratio of (R ^B1 _avg /R ^B _avg ) is at least 3. By way of further example, in one embodiment, (i) the ratio of R ^A1 _avg to R ^B1 _avg or the ratio of R ^B _avg to R ^A _avg is at least 5, and (ii) (R ^A1 _avg /R ^A _avg ) The ratio of (R ^B1 _avg /R ^B _avg ) is at least 5. Further example, in one embodiment, (i) R ^A1 _avg ratio of R or R ^B _avg ^B1 _avg ratio of R ^A _avg is at least 10, and _{^{(ii) (R A1 avg /}} R A avg) The ratio of (R ^B1 _avg /R ^B _avg ) is at least 10.

不期望受任何特定理論約束，且基於最新獲得之特定實驗證據，在特定實施例中，電極薄層電阻可表達為以在一大面積電致變色裝置(其提供跨電致變色堆疊之大致恆定的局部電壓降)中之位置為函數。對於第1圖中展示之簡單幾何形，其中對頂部電極進行之接觸(匯流排條27)係在x=0，且對底部電極進行之接觸(匯流排條26)係在x=xt，關係簡單地為R'(x)=R(x)*(xt/x-1)； 其中R(x)係以位置為函數之頂部電極之薄層電阻，且R'(x)係以位置為函數之底部電極之薄層電阻。此關係之簡單數學實例為，對於該頂部電極之薄層電阻中之線性改變，R(x)=a*x，該底部電極之薄層電阻必須為R'(x)=a*(xt-x)。另一簡單實例係針對R(x)=1/(xt-a*x)，則R'(x)=1/(a*x)。此關係在數學意義上對於任何函數R(x)成立。可藉由沿著垂直於等電阻線之梯度曲線從一接觸點(z=0)至另一者(z=L)之薄層電阻R(z)與相應相反電極薄層電阻分佈R'(z)之間之以下關係將此關係一般化至平滑變化之任何電極薄層電阻分佈及任何接觸組態。 Without wishing to be bound by any particular theory, and based on the particular experimental evidence obtained so far, in particular embodiments, the electrode sheet resistance can be expressed as being substantially constant across a large area electrochromic device that provides a cross-electrochromic stack. The position in the local voltage drop is a function. For the simple geometry shown in Figure 1, where the contact to the top electrode (bus bar 27) is at x = 0, and the contact to the bottom electrode (bus bar 26) is at x = xt, relationship Simply R'(x)=R(x)*(xt/x-1); Where R(x) is the sheet resistance of the top electrode as a function of position and R'(x) is the sheet resistance of the bottom electrode as a function of position. A simple mathematical example of this relationship is that for a linear change in the sheet resistance of the top electrode, R(x) = a*x, the sheet resistance of the bottom electrode must be R'(x) = a*(xt- x). Another simple example is for R(x) = 1/(xt-a*x), then R'(x) = 1/(a*x). This relationship holds in mathematical terms for any function R(x). The sheet resistance R' (with a sheet resistance R(z) from a contact point (z=0) to the other (z=L) along a gradient curve perpendicular to the isoelectric resistance line and the corresponding opposite electrode sheet resistance R' ( The following relationship between z) generalizes this relationship to any electrode sheet resistance distribution and any contact configuration that varies smoothly.

R'(z)=R(z)*(L/z-1)；作為實踐事項，裝置無需精確地遵循此關係以實現本發明之優點。例如，在上文R'(x)=1/(a*x)之情況中，R'(0)=無窮大。雖然吾人可實際上建立非常大之量值之電阻，然而具有R'(x)=1/(a*x+b)之膜(其中b相對於a較小)可 展現比包括均勻薄層電阻之電極之裝置明顯改良之切換一致性。 R'(z)=R(z)*(L/z-1); As a matter of practice, the device does not need to accurately follow this relationship to achieve the advantages of the present invention. For example, in the case of R'(x) = 1/(a*x) above, R'(0) = infinity. Although we can actually create a very large amount of resistance, a film with R'(x) = 1/(a*x+b) (where b is smaller relative to a) can Significantly improved switching consistency is demonstrated for devices that include electrodes with uniform sheet resistance.

具有不均勻薄層電阻之導電層可藉由一系列方法製備。在一實施例中，不均勻薄層電阻係層中組合物變動之結果；組合物變動可例如藉由在以相對於基板之位置為函數變化至各目標之功率的同時從不同材料之兩個圓柱形目標濺鍍塗佈；藉由在以相對於基板之位置為函數變化氣體分壓及/或組合物的同時從一圓柱形目標反應性濺鍍塗佈；藉由用以相對於基板之位置為函數的變化之組合物或製程噴塗；或藉由離子植入、擴散或反應而將摻雜物變動引入均勻組合物及厚度膜而形成。在另一實施例中，不均勻薄層電阻係層中之厚度變動的結果；厚度變動可例如藉由在以相對於基板之位置為函數變化至該目標之功率的同時從一圓柱形目標濺鍍塗佈；在恆定功率下從一目標濺鍍塗佈，且以相對於基板之位置為函數變化目標下方之基板之速度而形成，具有均勻TCO膜222a至222r之沈積堆疊位於基板224上，其中各膜具有如第3圖中繪示之有限空間範圍。或者，厚度梯度可藉由以均勻厚度導電層開始，且隨後以空間不均勻方式蝕刻該層而形成，諸如跨該層按不一致速率用蝕刻劑浸漬蝕刻或噴塗。在另一實施例中，該不均勻薄層電阻係圖案化之結果；梯度可例如藉由將一系列刻線雷射圖案化成恆定厚度及恆定電阻率膜而引入，以建立所要之空間變化電阻率。除雷射圖案化之外，可用使用(如半 導體裝置製造領域已知之)光阻劑之機械刻線及微影圖案化以建立所要之空間變化電阻率。在另一實施例中，不均勻薄層電阻係缺陷變動之結果；缺陷變動可例如藉由經由離子植入引入空間變化缺陷，或經由應用至具有先前均勻缺陷密度之一層的空間變化退火製程建立一空間變化缺陷密度而引入。 A conductive layer having an uneven sheet resistance can be prepared by a series of methods. In one embodiment, the result of composition variation in the uneven sheet resistance layer; composition variation can be from two different materials, for example, by varying the power to each target as a function of position relative to the substrate Cylindrical target sputter coating; reactive sputtering from a cylindrical target while varying the gas partial pressure and/or composition as a function of position relative to the substrate; by means of a substrate relative to the substrate The composition is a functionally varying composition or process spray; or a dopant composition is introduced into the uniform composition and the thickness film by ion implantation, diffusion or reaction. In another embodiment, the thickness variation in the uneven sheet resistance layer; the thickness variation can be splashed from a cylindrical target, for example, by varying the power to the target as a function of position relative to the substrate. Plating; forming at a constant power from a target sputter coating and varying the speed of the substrate below the target as a function of the position of the substrate, the deposition stack having uniform TCO films 222a through 222r on the substrate 224, Each of the membranes has a limited spatial extent as depicted in Figure 3. Alternatively, the thickness gradient can be formed by starting with a uniform thickness of conductive layer and then etching the layer in a spatially non-uniform manner, such as by dip etching or spraying with an etchant at an inconsistent rate across the layer. In another embodiment, the uneven sheet resistance is the result of patterning; the gradient can be introduced, for example, by patterning a series of reticle lasers into a constant thickness and constant resistivity film to establish the desired spatially varying resistance rate. In addition to laser patterning, it can be used (such as half Mechanical scribe and lithography of photoresists are known in the art of conductor fabrication to establish the desired spatially varying resistivity. In another embodiment, the uneven sheet resistance is a result of a variation in defect; the defect variation can be established, for example, by introducing a spatially varying defect via ion implantation, or via a spatially varying annealing process applied to one of the layers having a previously uniform defect density Introduced by a spatially varying defect density.

再次參考第1圖，第一電極層20及第二電極層21之至少一者係電致變色，第一電極層及第二電極層之一者係另一者之反電極，且第一電極層20及第二電極層21係無機及/或固體。電致變色電極層20及21之非排他性實例係基於鎢、鉬、鈮、鈦、鉛及/或鉍之氧化物之陰極顯色薄膜，或基於鎳、銥、鐵、鉻、鈷及/或銠之氧化物、氫氧化物及/或氧氫化物之陽極顯色薄膜。 Referring again to FIG. 1 , at least one of the first electrode layer 20 and the second electrode layer 21 is electrochromic, and one of the first electrode layer and the second electrode layer is the other of the counter electrodes, and the first electrode The layer 20 and the second electrode layer 21 are inorganic and/or solid. Non-exclusive examples of electrochromic electrode layers 20 and 21 are cathode chromogenic films based on oxides of tungsten, molybdenum, niobium, titanium, lead and/or bismuth, or based on nickel, ruthenium, iron, chromium, cobalt and/or An anodized film of an oxide, hydroxide and/or oxyhydride of ruthenium.

在一實施例中，第一電極層20含有許多不同電致變色材料之任何一種或多種，包含金屬氧化物。此等金屬氧化物包含氧化鎢(WO₃)、氧化鉬(MoO₃)、氧化鈮(Nb₂O₅)、氧化鈦(TiO₂)、氧化銅(CuO)、氧化銥(Ir₂O₃)、氧化鉻(Cr₂O₃)、氧化錳(Mn₂O₃)、氧化釩(V₂O₃)、氧化鎳(Ni₂O₃)、氧化鈷(Co₂O₃)及類似物。在一些實施例中，金屬氧化物用一種或多種摻雜物摻雜，諸如鋰、鈉、鉀、鉬、釩、鈦及/或其他適當金屬或含有金屬之化合物。混合氧化物(例如，W-Mo氧化物、W-V氧化物)亦使用於特定實施例中。 In one embodiment, the first electrode layer 20 contains any one or more of a number of different electrochromic materials, including metal oxides. These metal oxides include tungsten oxide (WO ₃ ), molybdenum oxide (MoO ₃ ), niobium oxide (Nb ₂ O ₅ ), titanium oxide (TiO ₂ ), copper oxide (CuO), and cerium oxide (Ir ₂ O ₃ ). Chromium oxide (Cr ₂ O ₃ ), manganese oxide (Mn ₂ O ₃ ), vanadium oxide (V ₂ O ₃ ), nickel oxide (Ni ₂ O ₃ ), cobalt oxide (Co ₂ O ₃ ), and the like. In some embodiments, the metal oxide is doped with one or more dopants such as lithium, sodium, potassium, molybdenum, vanadium, titanium, and/or other suitable metals or metal-containing compounds. Mixed oxides (e.g., W-Mo oxides, WV oxides) are also used in certain embodiments.

在一些實施例中，將氧化鎢或經摻雜之氧化鎢用於第 一電極層20。在一實施例中，第一電極層20係電致變色，且大致由WO_x製成，其中「x」指該電致變色層中之氧對鎢之原子比率，且x介於約2.7與3.5之間。已建議僅亞化學計量氧化鎢展現電致變色性；即，化學計量WO₃不展現電致變色性。在更特定之實施例中，將WO_x用於第一電極層20，其中x小於3.0且至少約2.7。在另一實施例中，第一電極層20係WO_x，其中x介於約2.7與約2.9之間。諸如拉塞福背向散射譜學(RBS)之技術可識別氧原子之總數目，其包含與鎢鍵合之氧原子及未與鎢鍵合之氧原子。在一些實例中，x為3或更大之氧化鎢層推測歸因於過多未鍵合之氧連同亞化學計量氧化鎢而展現電致變色性。在另一實施例中，該氧化鎢層具有化學計量氧或更多氧，其中x為3.0至約3.5。 In some embodiments, tungsten oxide or doped tungsten oxide is used for the first electrode layer 20. In one embodiment, the first electrode layer 20 is electrochromic and is substantially made of WO _x , wherein "x" refers to the atomic ratio of oxygen to tungsten in the electrochromic layer, and x is between about 2.7 and Between 3.5. It has been suggested that only substoichiometric tungsten oxide exhibits electrochromic properties; that is, stoichiometric WO ₃ does not exhibit electrochromism. In a more specific embodiment, WO _{x is} used for the first electrode layer 20, where x is less than 3.0 and at least about 2.7. In another embodiment, the first electrode layer 20 is WO _x , wherein x is between about 2.7 and about 2.9. Techniques such as Rutherford Backscatter Spectroscopy (RBS) can identify the total number of oxygen atoms comprising oxygen atoms bonded to tungsten and oxygen atoms not bonded to tungsten. In some examples, a tungsten oxide layer with x of 3 or greater is presumably attributed to electrochromism due to excessive unbonded oxygen along with substoichiometric tungsten oxide. In another embodiment, the tungsten oxide layer has a stoichiometric oxygen or more oxygen, wherein x is from 3.0 to about 3.5.

在特定實施例中，電致變色混合金屬氧化物係晶體、奈米晶或非晶質。在一些實施例中，氧化鎢大致係奈米晶，具有如由穿透式電子顯微鏡(TEM)特徵化之平均從約5 nm至50 nm(或從約5 nm至20 nm)之粒徑大小。氧化鎢形態亦可使用x射線繞射(XRD)特徵化為奈米晶。舉例而言，奈米晶電致變色氧化鎢之特徵可藉由以下XRD特徵特徵化：約10 nm至100 nm之晶體大小(例如，約55 nm)。此外，奈米晶氧化鎢可展現有限長範圍數量級，例如，以若干(約5至20個)氧化鎢單位晶胞之數量級。 In a particular embodiment, the electrochromic mixed metal oxide is crystalline, nanocrystalline or amorphous. In some embodiments, the tungsten oxide is predominantly nanocrystalline having an average particle size of from about 5 nm to 50 nm (or from about 5 nm to 20 nm) as characterized by a transmission electron microscope (TEM). . The tungsten oxide form can also be characterized as nanocrystals using x-ray diffraction (XRD). For example, the characteristics of nanocrystalline electrochromic tungsten oxide can be characterized by the following XRD features: a crystal size of about 10 nm to 100 nm (eg, about 55 nm). In addition, nanocrystalline tungsten oxide can exhibit a finite length range of magnitude, for example, on the order of a few (about 5 to 20) tungsten oxide unit cells.

第一電極層20之厚度取決於針對電致變色層所選擇之電致變色材料。在一些實施例中，第一電極層20係約50 nm至2,000 nm，或約100 nm至700 nm。在一些實施例中，該第一電極層20係約250 nm至約500 nm。 The thickness of the first electrode layer 20 depends on the electrochromic material selected for the electrochromic layer. In some embodiments, the first electrode layer 20 is about 50 Nm to 2,000 nm, or about 100 nm to 700 nm. In some embodiments, the first electrode layer 20 is between about 250 nm and about 500 nm.

第二電極層21用作第一電極層20之反電極，且如同第一電極層20，第二電極層21可包括電致變色材料以及非電致變色材料。第二電極層21之非排他性實例係基於鎢、鉬、鈮、鈦、鉛及/或鉍之氧化物之陰極顯色電致變色薄膜，基於鎳、銥、鐵、鉻、鈷及/或銠之氧化物、氫氧化物及/或氧氫化物之陽極顯色電致變色薄膜，或例如基於釩及/或鈰以及活性碳之氧化物之非電致變色薄膜。此外，此等材料之組合可使用為第二電極層21。 The second electrode layer 21 serves as a counter electrode of the first electrode layer 20, and like the first electrode layer 20, the second electrode layer 21 may include an electrochromic material and a non-electrochromic material. A non-exclusive example of the second electrode layer 21 is a cathodic color electrochromic film based on oxides of tungsten, molybdenum, niobium, titanium, lead and/or niobium based on nickel, ruthenium, iron, chromium, cobalt and/or rhenium. Anodically colored electrochromic thin films of oxides, hydroxides and/or oxyhydrides, or non-electrochromic thin films based on, for example, vanadium and/or antimony and oxides of activated carbon. Further, a combination of these materials may be used as the second electrode layer 21.

在一些實施例中，第二電極層21可包括在電致變色裝置處於漂白狀態時能夠用作離子儲體之許多不同材料之一種或多種。在例如藉由施加適當電位啟動電致變色過渡期間，反電極層將其保持之離子之一些或所有轉移至電致變色第一電極層20，將該電致變色第一電極層20改變為有色狀態。 In some embodiments, the second electrode layer 21 can include one or more of a number of different materials that can be used as ion reservoirs when the electrochromic device is in a bleached state. The counter electrode layer transfers some or all of the ions it retains to the electrochromic first electrode layer 20 during the transition of the electrochromic transition, for example by applying an appropriate potential, changing the electrochromic first electrode layer 20 to colored status.

在一些實施例中，與WO₃互補之反電極之適當材料包含氧化鎳(NiO)、氧化鎳鎢(NiWO)、氧化鎳釩、氧化鎳鉻、氧化鎳鋁、氧化鎳錳、氧化鎳鎂、氧化鉻(Cr₂O₃)、氧化錳(MnO₂)及普魯士藍。光學被動反電極包括氧化鈰鈦(CeO₂-TiO₂₎、氧化鈰鋯(CeO₂-ZrO₂)、氧化鎳(NiO)、氧化鎳鎢(NiWO)、氧化釩(V₂O₅)及氧化物之混合物(例如，Ni₂O₃與WO₃之混合物)。亦可使用此等氧化物之經摻雜配方，包含例如鉭及鎢之摻雜物。因為第一電極層20含有 在電致變色材料處於漂白狀態時用於在該電致變色材料中產生電致變色現象之離子，所以當該反電極保持大量此等離子時，其較佳具有高透射率及中性色彩。 In some embodiments, suitable materials for the counter electrode complementary to WO ₃ include nickel oxide (NiO), nickel tungsten oxide (NiWO), nickel vanadium oxide, nickel chromium oxide, nickel aluminum oxide, nickel manganese oxide, nickel magnesium oxide, Chromium oxide (Cr ₂ O ₃ ), manganese oxide (MnO ₂ ), and Prussian blue. The optical passive counter electrode includes cerium oxide titanium oxide (CeO ₂ -TiO _{2 )} , cerium oxide zirconium oxide (CeO ₂ -ZrO ₂ ), nickel oxide (NiO), nickel tungsten oxide (NiWO), vanadium oxide (V ₂ O ₅ ) and oxidation. the mixture (e.g., Ni ₂ O ₃ and WO ₃ of a mixture) of the product. Doped formulations of such oxides can also be used, including dopants such as tantalum and tungsten. Since the first electrode layer 20 contains ions for generating an electrochromic phenomenon in the electrochromic material when the electrochromic material is in a bleaching state, it preferably has a high transmission when the counter electrode holds a large amount of the plasma. Rate and neutral color.

在一些實施例中，將氧化鎳鎢(NiWO)用於反電極層中。在特定實施例中，該氧化鎳鎢中存在之鎳的量可多達約90%重量比之氧化鎳鎢。在一特定實施例中，該氧化鎳鎢中之鎳對鎢的質量比介於約4：6與6：4之間(例如，約1：1)。在一實施例中，該NiWO介於約15%(原子)Ni與約60%Ni之間；介於約10%W與約40%W之間；及介於約30%O與約75%O之間。在另一實施例中，該NiWO介於約30%(原子)Ni與約45%Ni之間；介於約10%W與約25%W之間；及介於約35%O與約50%O之間。在一實施例中，該NiWO係約42%(原子)Ni，約14%W及約44%O。 In some embodiments, nickel tungsten oxide (NiWO) is used in the counter electrode layer. In a particular embodiment, the amount of nickel present in the nickel tungsten oxide can be up to about 90% by weight nickel oxide tungsten. In a particular embodiment, the nickel to tungsten mass ratio of tungsten to tungsten is between about 4:6 and 6:4 (eg, about 1:1). In one embodiment, the NiWO is between about 15% (atomic) Ni and about 60% Ni; between about 10% W and about 40% W; and between about 30% O and about 75%. Between O. In another embodiment, the NiWO is between about 30% (atomic) Ni and about 45% Ni; between about 10% W and about 25% W; and between about 35% O and about 50. Between %O. In one embodiment, the NiWO is about 42% (atomic) Ni, about 14% W, and about 44% O.

在一些實施例中，第二電極層21之厚度係約50 nm至約650 nm。在一些實施例中，第二電極層21之厚度係約100 nm至約400 mn，較佳在約200 nm至300 nm之範圍內。 In some embodiments, the thickness of the second electrode layer 21 is from about 50 nm to about 650 nm. In some embodiments, the thickness of the second electrode layer 21 is from about 100 nm to about 400 mn, preferably from about 200 nm to 300 nm.

離子傳導層10用作一介質，當電致變色裝置在漂白狀態與有色狀態之間變換時，離子(以電解質之方式)被運輸穿過該介質。離子傳導層10包括離子傳導材料。其取決於應用可為透明或不透明，有色或無色。較佳地，離子傳導層10對於第一電極層20及第二電極層21之相關離子高度傳導。取決於材料之選擇，此等離子包含鋰 離子(Li⁺)及氫離子(H⁺)(即，質子)。特定實施例中亦可利用其他離子。此等包含氘離子(D⁺)、鈉離子(Na⁺)、鉀離子(K⁺)、鈣離子(Ca⁺⁺)、鋇離子(Ba⁺⁺)、鍶離子(Sr⁺⁺)及鎂離子(Mg⁺⁺)。較佳地，離子傳導層10亦具有在正常運作期間發生可忽略之電子轉移的足夠低電子導電性。在各種實施例中，該離子傳導材料具有介於約10^-5 S/cm與10^-3 S/cm之間之離子導電性。 The ion conducting layer 10 acts as a medium through which ions (as electrolytes) are transported as the electrochromic device changes between a bleached state and a colored state. The ion conducting layer 10 includes an ion conducting material. It may be transparent or opaque, colored or colorless depending on the application. Preferably, the ion conducting layer 10 is highly conductive to the associated ions of the first electrode layer 20 and the second electrode layer 21. Depending on the choice of material, the plasma contains lithium ions (Li ⁺ ) and hydrogen ions (H ⁺ ) (ie, protons). Other ions may also be utilized in certain embodiments. These include strontium ions (D ⁺ ), sodium ions (Na ⁺ ), potassium ions (K ⁺ ), calcium ions (Ca ⁺⁺ ), barium ions (Ba ⁺⁺ ), barium ions (Sr ⁺⁺ ), and magnesium ions. (Mg ⁺⁺ ). Preferably, ion conducting layer 10 also has sufficiently low electronic conductivity to cause negligible electron transfer during normal operation. In various embodiments, the ion conducting material has an ionic conductivity of between about 10 ^-5 S/cm and 10 ^-3 S/cm.

電解質類型之一些非排他性實例係：固體聚合物電解質(SPE)，諸如具有溶解之鋰鹽的聚(環氧乙烷)；凝膠聚合物電解質(GPE)，諸如具有鋰鹽之聚(甲基丙烯酸甲酯)及碳酸丙烯酯之混合物；複合凝膠聚合物電解質(GPE)，其類似於GPE但添加第二聚合物，諸如聚(環氧乙烷)，及液體電解質(LE)，諸如具有鋰鹽之碳酸伸乙酯/碳酸二乙酯之溶劑混合物；及複合有機-無機電解質(CE)，包括添加氧化鈦、矽石或其他氧化物之LE。所使用之鋰鹽之一些非排他性實例係LiTFSI(雙三氟甲烷磺醯亞胺鋰)、LiBF₄(四氟硼酸鋰)、LiAsF₆(六氟砷酸鋰)、LiCF₃SO₃(三氟甲磺酸鋰)及LiClO₄(高氯酸鋰)。適當離子傳導層之額外實例包含矽酸鹽、氧化矽、氧化鎢、氧化鉭、氧化鈮及硼酸鹽。氧化矽包含氧化矽鋁。此等材料可用不同摻雜物摻雜，包含鋰。摻雜鋰之氧化矽包含氧化鋰矽鋁。在一些實施例中，該離子傳導層包括基於矽酸鹽之結構。在其他實施例中，適當離子導體特別適於鋰離子運輸，包含但不限於矽酸鋰、矽酸鋰鋁、硼酸鋰鋁、 氟化鋰鋁、硼酸鋰、氮化鋰、矽酸鋰鋯、鈮酸鋰、硼矽酸鋰、磷矽酸鋰及其他此等基於鋰之陶瓷材料、矽石或氧化矽，包含氧化鋰矽。 Some non-exclusive examples of electrolyte types are: solid polymer electrolytes (SPE), such as poly(ethylene oxide) with dissolved lithium salts; gel polymer electrolytes (GPE), such as poly(methyl) with lithium salts a mixture of methyl acrylate) and propylene carbonate; a composite gel polymer electrolyte (GPE) similar to GPE but with a second polymer such as poly(ethylene oxide), and a liquid electrolyte (LE), such as a solvent mixture of a lithium salt of ethyl carbonate/diethyl carbonate; and a composite organic-inorganic electrolyte (CE) comprising LE added with titanium oxide, vermiculite or other oxides. Some non-exclusive examples of lithium salts used are LiTFSI (lithium bistrifluoromethanesulfonimide), LiBF ₄ (lithium tetrafluoroborate), LiAsF ₆ (lithium hexafluoroarsenate), LiCF ₃ SO ₃ (trifluoro Lithium methanesulfonate) and LiClO ₄ (lithium perchlorate). Additional examples of suitable ion conducting layers include decanoate, cerium oxide, tungsten oxide, cerium oxide, cerium oxide, and borate. Cerium oxide contains yttrium aluminum oxide. These materials may be doped with different dopants, including lithium. The lithium doped cerium oxide comprises lithium cerium oxide. In some embodiments, the ion conducting layer comprises a citrate based structure. In other embodiments, suitable ionic conductors are particularly suitable for lithium ion transport, including but not limited to lithium niobate, lithium aluminum niobate, lithium aluminum borate, lithium aluminum fluoride, lithium borate, lithium nitride, lithium zirconium niobate, Lithium niobate, lithium borohydride, lithium phosphite, and other such lithium-based ceramic materials, vermiculite or cerium oxide, including lithium cerium oxide.

離子傳導層10之厚度將取決於材料而變化。在使用無機離子導體之一些實施例中，該離子傳導層10係約250 nm至1 nm厚，較佳地約50 nm至5 nm厚。在使用有機離子導體之一些實施例中，該離子傳導層係約100000 nm至1000 nm厚，或約25000 nm至10000 nm厚。該離子傳導層之厚度亦大致均勻。在一實施例中，大致均勻離子傳導層在上述厚度範圍之各者中變化不大於約+/-10%。在另一實施例中，大致均勻離子傳導層在上述厚度範圍之各者中變化不大於約+/-5%。在另一實施例中，大致均勻離子傳導層在上述厚度範圍之各者中變化不大於約+/-3%。 The thickness of the ion conducting layer 10 will vary depending on the material. In some embodiments using an inorganic ionic conductor, the ion conducting layer 10 is about 250 nm to 1 nm thick, preferably about 50 nm to 5 nm thick. In some embodiments using an organic ionic conductor, the ion conducting layer is about 100000 nm to 1000 nm thick, or about 25000 nm to 10000 nm thick. The thickness of the ion conducting layer is also substantially uniform. In one embodiment, the substantially uniform ion conducting layer varies by no more than about +/- 10% in each of the thickness ranges described above. In another embodiment, the substantially uniform ion conducting layer varies by no more than about +/- 5% in each of the thickness ranges described above. In another embodiment, the substantially uniform ion conducting layer varies by no more than about +/- 3% in each of the thickness ranges described above.

再次參考第1圖，基板24及25具有平坦表面。即，其等具有在各點上與切平面重合之一表面。儘管電致變色建築窗及許多其他電致變色裝置通常利用具有平坦表面之基板，然而預期本發明之多層裝置可具有單個或甚至雙重彎曲表面。換言之，預期堆疊28之層之各者具有相應曲率半徑。舉例而言見美國專利第7,808,692號，其關於單個及雙重彎曲表面之界定及其製備方法，其全文以引用之方式併入本文中。 Referring again to Figure 1, the substrates 24 and 25 have a flat surface. That is, they have one surface that coincides with the tangent plane at each point. While electrochromic building windows and many other electrochromic devices typically utilize substrates having a flat surface, it is contemplated that the multilayer device of the present invention can have a single or even double curved surface. In other words, each of the layers of stack 28 is expected to have a corresponding radius of curvature. See, for example, U.S. Pat.

第4圖描繪根據本發明之一第二實施例之一電致變色裝置之一截面結構圖。從中心向外移動，電致變色裝置 101包括電致變色電極層120。在電致變色電極層120之任一側上係第一導電層122及第二導電層123，其等接著抵靠外基板124、125配置。元件122、120及123統稱為一電致變色堆疊128。導電層122經由匯流排條126與一電壓源電接觸，且導電層123經由匯流排條127與一電壓源電接觸，藉此可藉由施加一電壓脈衝至導電層122、123而改變電致變色裝置120之透射率。該脈衝導致電致變色電極層120中之陰極化合物經歷可逆化學還原，且電致變色電極層120中之陽極化合物經歷可逆化學氧化。陰極化合物或陽極化合物之任一者將展現電致變色表現，使得電致變色電極層120在該脈衝之後變得較不透光或較透光；在一實施例中，電致變色裝置101在電壓脈衝之前具有相對較大透射率及在電壓脈衝之後具有較小透射率，或反之亦然。 Figure 4 is a cross-sectional structural view showing an electrochromic device according to a second embodiment of the present invention. Moving outward from the center, electrochromic device 101 includes an electrochromic electrode layer 120. On either side of the electrochromic electrode layer 120, a first conductive layer 122 and a second conductive layer 123 are formed, which are then disposed against the outer substrates 124, 125. Elements 122, 120, and 123 are collectively referred to as an electrochromic stack 128. The conductive layer 122 is in electrical contact with a voltage source via the bus bar 126, and the conductive layer 123 is in electrical contact with a voltage source via the bus bar 127, whereby the electro-optic can be changed by applying a voltage pulse to the conductive layers 122, 123. Transmittance of the color changing device 120. This pulse causes the cathode compound in the electrochromic electrode layer 120 to undergo reversible chemical reduction, and the anode compound in the electrochromic electrode layer 120 undergoes reversible chemical oxidation. Either the cathode compound or the anode compound will exhibit an electrochromic appearance such that the electrochromic electrode layer 120 becomes less opaque or lighter after the pulse; in one embodiment, the electrochromic device 101 is The voltage pulse has a relatively large transmittance before and a small transmittance after the voltage pulse, or vice versa.

第20圖描繪根據本發明之一第三實施例之一電致變色裝置之一截面結構圖。從中間向外移動，電致變色裝置301包括離子傳導層310。電致變色電極層320位於離子傳導層310之一第一表面之一側上，且與離子傳導層310之第一表面接觸。一第一導電層322與電致變色層320接觸。一第二導電層323位於離子傳導層310之一第二表面上，離子傳導層310之第一表面及第二表面係相反表面。第一導電層322及第二導電層323抵靠外基板324、325而配置。元件310、320、322及323統稱為電致變色堆疊328。導電層322經由匯流排條326與一電壓 源(未繪示)電接觸，且導電層323經由匯流排條327與一電壓源(未繪示)電接觸，藉此可藉由施加一電壓脈衝至導電層322、323而改變電致變色層320之透射率。離子傳導層310包括能夠在電子或離子***或引出時可逆地氧化或還原之物質，且此物質亦可具電致變色活性。電壓脈衝導致電子及離子在第一電極層320與離子傳導層310之間移動，且因此，該電極層320中之電致變色材料改變色彩，藉此使得電致變色裝置301較不透光或較透光。在一實施例中，電致變色裝置301在電壓脈衝之前具有相對較大透射率及在電壓脈衝之後具有相對較小透射率，或反之亦然。 Figure 20 is a cross-sectional structural view showing an electrochromic device according to a third embodiment of the present invention. Moving from the middle outward, the electrochromic device 301 includes an ion conducting layer 310. The electrochromic electrode layer 320 is located on one side of one of the first surfaces of the ion conducting layer 310 and is in contact with the first surface of the ion conducting layer 310. A first conductive layer 322 is in contact with the electrochromic layer 320. A second conductive layer 323 is located on a second surface of the ion conductive layer 310, and the first surface and the second surface of the ion conductive layer 310 are opposite surfaces. The first conductive layer 322 and the second conductive layer 323 are disposed to abut against the outer substrates 324 and 325. Elements 310, 320, 322, and 323 are collectively referred to as an electrochromic stack 328. Conductive layer 322 via bus bar 326 and a voltage The source (not shown) is in electrical contact, and the conductive layer 323 is in electrical contact with a voltage source (not shown) via the bus bar 327, whereby the electrochromic can be changed by applying a voltage pulse to the conductive layers 322, 323. Transmittance of layer 320. The ion conductive layer 310 includes a substance capable of reversibly oxidizing or reducing upon insertion or extraction of electrons or ions, and the substance may also have electrochromic activity. The voltage pulse causes electrons and ions to move between the first electrode layer 320 and the ion conducting layer 310, and thus, the electrochromic material in the electrode layer 320 changes color, thereby making the electrochromic device 301 less opaque or More light. In an embodiment, electrochromic device 301 has a relatively large transmission before the voltage pulse and a relatively small transmittance after the voltage pulse, or vice versa.

通常，第一導電層122、322及第二導電層123、323之組合物及薄層電阻分佈如前文結合第1圖所描述。電致變色電極層120及320可舉例而言含有作為固體膜或分佈於電解質中之一電致變色材料，該電致變色材料從無機金屬氧化物(諸如三氧化鎢(WO₃)、氧化鎳(NiO)及二氧化鈦(TiO₂))及有機電致變色材料(包含聯吡啶鹽(紫精)衍生物、N,N'-雙(p-苯腈)4,4'-雙吡啶(CPQ)、醌類衍生物(諸如蒽醌)及吖嗪衍生物(諸如吩噻嗪)之間選擇。 Generally, the composition of the first conductive layers 122, 322 and the second conductive layers 123, 323 and the sheet resistance distribution are as described above in connection with FIG. The electrochromic electrode layers 120 and 320 may, for example, contain an electrochromic material as a solid film or distributed in an electrolyte, such as an inorganic metal oxide such as tungsten trioxide (WO ₃ ), nickel oxide. (NiO) and titanium dioxide (TiO ₂ )) and organic electrochromic materials (including bipyridyl salt (viologen) derivatives, N, N'-bis(p-benzonitrile) 4,4'-bipyridine (CPQ) A choice between a quinone derivative such as hydrazine and a pyridazine derivative such as phenothiazine.

在運作中，為將本發明之一電致變色裝置從第一光學狀態切換至具有不同透射率之第二光學狀態，即，從相對較大透射率之狀態切換至較小透射率之狀態，或反之亦然，將施加一電壓脈衝至該裝置上之電接觸件/匯流排條。一旦切換，該第二光學狀態將在該電壓脈衝結束之 後以及甚至在無任何所施加之電壓之情況下持續一定時間；舉例而言，該第二光學狀態將在電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1秒。進一步舉例而言，該第二光學狀態可在電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少5秒。進一步舉例而言，該第二光學狀態可在電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1分鐘。進一步舉例而言，該第二光學狀態可在電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1小時。裝置可隨後藉由顛倒極性及施加一第二電壓脈衝而從該第二光學狀態返回第一光學狀態，且在切換返回時，該第一光學狀態將在該第二脈衝結束之後，甚至在無任何所施加之電壓之情況下持續一定時間；舉例而言，該第一光學狀態將在該電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1秒。進一步舉例而言，該第一光學狀態可在該電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1分鐘。進一步舉例而言，該第一光學狀態可在該電壓脈衝結束之後以及甚至在無任何所施加之電壓之情況下持續至少1小時。從一第一持續光學狀態可逆地切換至第二持續光學狀態且隨後再次返回之此過程可重複許多次，且實踐中可無限次。 In operation, in order to switch an electrochromic device of the present invention from a first optical state to a second optical state having a different transmittance, that is, a state of switching from a state of relatively large transmittance to a state of lesser transmittance, Or vice versa, a voltage pulse will be applied to the electrical contacts/bus bars on the device. Once switched, the second optical state will end at the voltage pulse After a certain period of time and even without any applied voltage; for example, the second optical state will last for at least 1 second after the end of the voltage pulse and even without any applied voltage. By way of further example, the second optical state can last for at least 5 seconds after the end of the voltage pulse and even without any applied voltage. By way of further example, the second optical state can last for at least one minute after the end of the voltage pulse and even without any applied voltage. By way of further example, the second optical state can last for at least one hour after the end of the voltage pulse and even without any applied voltage. The device can then return to the first optical state from the second optical state by reversing the polarity and applying a second voltage pulse, and upon switching back, the first optical state will be after the end of the second pulse, even in the absence of Any applied voltage continues for a certain period of time; for example, the first optical state will continue for at least 1 second after the end of the voltage pulse and even without any applied voltage. By way of further example, the first optical state can last for at least one minute after the end of the voltage pulse and even without any applied voltage. By way of further example, the first optical state can last for at least one hour after the end of the voltage pulse and even without any applied voltage. This process of reversibly switching from a first continuous optical state to a second continuous optical state and then returning again can be repeated many times, and in practice can be infinite.

在一些實施例中，電壓脈衝之波形可經設計使得跨該電致變色堆疊之局部電壓從不超過一預定位準；此在舉 例而言在跨電致變色堆疊之過電壓可能損壞裝置及/或引致電致變色材料之非所要之改變之特定電致變色裝置中可為較佳。 In some embodiments, the waveform of the voltage pulse can be designed such that the local voltage across the electrochromic stack never exceeds a predetermined level; For example, it may be preferred in a particular electrochromic device that over-voltages across the electrochromic stack may damage the device and/or introduce undesirable changes in the photochromic material.

有利地，本發明之多層裝置之第一導電層及/或第二導電層之不均勻薄層電阻可容許有關電壓脈衝之量值及/或持續時間之更大容限。因此，由於該(該等)導電層中之電壓降，跨電致變色堆疊之局部電壓可明顯小於跨整個裝置所施加之電壓。舉例而言，在一實施例中，跨該電致變色堆疊所施加之電位具有至少2伏特之量值。進一步舉例而言，該電壓脈衝可具有至少3伏特之量值。進一步舉例而言，該電壓脈衝可具有至少4伏特之量值。進一步舉例而言，該電壓脈衝可具有至少5伏特之量值。進一步舉例而言，該電壓脈衝可具有至少6伏特之量值。進一步舉例而言，該電壓脈衝可具有至少7伏特之量值。進一步舉例而言，該電壓脈衝可具有至少8伏特之量值。進一步舉例而言，該電壓脈衝可具有至少9伏特之量值。進一步舉例而言，該電壓脈衝可具有至少10伏特之量值。進一步舉例而言，該電壓脈衝可具有至少11伏特之量值。進一步舉例而言，該電壓脈衝可具有至少12伏特之量值。進一步舉例而言，該電壓脈衝可具有至少13伏特之量值。進一步舉例而言，該電壓脈衝可具有至少14伏特之量值。進一步舉例而言，該電壓脈衝可具有至少15伏特之量值。進一步舉例而言，該電壓脈衝可具有至少16伏特之量值。進一步舉例而言，該電壓脈衝可具有 至少18伏特之量值。進一步舉例而言，該電壓脈衝可具有至少20伏特之量值。進一步舉例而言，該電壓脈衝可具有至少22伏特之量值。進一步舉例而言，該電壓脈衝可具有至少24伏特之量值。通常，此等電位可施加達相對較長時間週期。舉例而言，具有此等值之任何者之量值之一電位可施加達至少1秒之週期。進一步舉例而言，具有此等值之任何者之量值之一電位可施加達至少10秒之週期。進一步舉例而言，具有此等值之任何者之量值之一電位可施加達至少20秒之週期。進一步舉例而言，具有此等值之任何者之量值之一電位可施加達至少40秒之週期。 Advantageously, the uneven sheet resistance of the first conductive layer and/or the second conductive layer of the multilayer device of the present invention can tolerate greater tolerances regarding the magnitude and/or duration of the voltage pulses. Thus, due to the voltage drop in the (the) conductive layers, the local voltage across the electrochromic stack can be significantly less than the voltage applied across the entire device. For example, in one embodiment, the potential applied across the electrochromic stack has a magnitude of at least 2 volts. By way of further example, the voltage pulse can have a magnitude of at least 3 volts. By way of further example, the voltage pulse can have a magnitude of at least 4 volts. By way of further example, the voltage pulse can have a magnitude of at least 5 volts. By way of further example, the voltage pulse can have a magnitude of at least 6 volts. By way of further example, the voltage pulse can have a magnitude of at least 7 volts. By way of further example, the voltage pulse can have a magnitude of at least 8 volts. By way of further example, the voltage pulse can have a magnitude of at least 9 volts. By way of further example, the voltage pulse can have a magnitude of at least 10 volts. By way of further example, the voltage pulse can have a magnitude of at least 11 volts. By way of further example, the voltage pulse can have a magnitude of at least 12 volts. By way of further example, the voltage pulse can have a magnitude of at least 13 volts. By way of further example, the voltage pulse can have a magnitude of at least 14 volts. By way of further example, the voltage pulse can have a magnitude of at least 15 volts. By way of further example, the voltage pulse can have a magnitude of at least 16 volts. By way of further example, the voltage pulse can have At least 18 volts. By way of further example, the voltage pulse can have a magnitude of at least 20 volts. By way of further example, the voltage pulse can have a magnitude of at least 22 volts. By way of further example, the voltage pulse can have a magnitude of at least 24 volts. Typically, this equipotential can be applied for a relatively long period of time. For example, one of the magnitudes of any of these values can be applied for a period of at least 1 second. By way of further example, one of the magnitudes of any of these values can be applied for a period of at least 10 seconds. By way of further example, one of the magnitudes of any of these values can be applied for a period of at least 20 seconds. By way of further example, one of the magnitudes of any of these values can be applied for a period of at least 40 seconds.

為繪示一特定例示性實施例，可跨併入具有不均勻薄層電阻之兩個TCO導電層及定位在整個裝置之相對周邊邊緣上之匯流排條之一電致變色堆疊施加16伏特之電壓脈衝。該電壓脈衝快速上升以允許跨該等層之局部電壓降快速升高至1.0伏特，並維持該電壓直到該裝置之切換進行完全，此時該等裝置層開始充電，且電流下降。由於導電層中之梯度及薄層電阻，跨該裝置之電壓降跨裝置恆定，且此外，跨該裝置之導電層之各者存在一電壓降。透過不均勻電阻率之導電層的電壓降使得明顯大於該裝置堆疊之最大操作電壓的電壓跨整個總成施加，且維持跨該裝置堆疊之局部電壓低於所要值。隨著裝置充電發生，所施加之電壓下降以將跨該等裝置層之局部電壓保持在1.0伏特。若期望跨局部裝置厚度保持穩定狀態 之1.0伏特，則電壓脈衝將降至接近1伏特之穩定狀態值，或或者，若期望在穩定狀態中跨該局部裝置厚度保持無電壓，則該電壓脈衝將降至零伏特。 To illustrate a particular exemplary embodiment, 16 volts can be applied across an electrochromic stack incorporating two TCO conductive layers having uneven sheet resistance and one of the bus bars positioned on opposite peripheral edges of the entire device. Voltage pulse. The voltage pulse rises rapidly to allow the local voltage drop across the layers to rise rapidly to 1.0 volts and maintains the voltage until the switching of the device is complete, at which point the device layers begin to charge and the current drops. Due to the gradient in the conductive layer and the sheet resistance, the voltage drop across the device is constant across the device and, in addition, there is a voltage drop across each of the conductive layers of the device. The voltage drop across the conductive layer of non-uniform resistivity causes a voltage that is significantly greater than the maximum operating voltage of the device stack to be applied across the entire assembly and maintains the local voltage across the stack of devices below a desired value. As device charging occurs, the applied voltage drops to maintain the local voltage across the device layers at 1.0 volts. If it is desired to maintain a stable state across the thickness of the local device At 1.0 volts, the voltage pulse will drop to a steady state value close to 1 volt, or alternatively, if it is desired to remain voltage-free across the local device thickness in a steady state, the voltage pulse will drop to zero volts.

為將多層裝置之光學狀態改變為一中間狀態，施加一電壓脈衝至該裝置上之電接觸件/匯流排條。此電壓脈衝之此形狀通常將為裝置專有，且取決於所要之中間狀態。該中間狀態可按照移動之總電荷、裝置之充電狀態或裝置之光學量測而界定。藉由使用不均勻電子傳導層以跨該等裝置層施加均勻局部電壓，這提供針對使用光學狀態回饋之快速大面積中間狀態控制之獨特優點，因為邊緣附近之裝置狀態之局部光學量測將總是代表整個裝置(沒有虹膜效應)。另外，藉由使用不均勻電子傳導層以跨該等裝置層施加均勻局部電壓，此提供針對使用電壓回饋之快速大面積中間狀態控制之獨特優點，因為匯流排條上之電壓狀態將代表整個裝置，而非跨不均勻有色裝置之平均值(還是無虹膜效應)。在一特定實例中，跨併入兩個梯度TCO層及定位在整個裝置之相反周邊邊緣上之一匯流排條之一電致變色裝置施加32伏特之一電壓脈衝。該電壓脈衝快速上升以允許跨該等層之局部電壓降快速升高至1.0伏特，且維持該電壓直到該裝置到達用一適當光學感測器量測之期望光學狀態，此時該電壓脈衝快速下降至零或至一所要穩定狀態電壓。 To change the optical state of the multilayer device to an intermediate state, a voltage pulse is applied to the electrical contacts/bus bars on the device. This shape of this voltage pulse will typically be device specific and will depend on the desired intermediate state. The intermediate state can be defined by the total charge of the movement, the state of charge of the device, or the optical measurement of the device. By using a non-uniform electron conducting layer to apply a uniform local voltage across the device layers, this provides a unique advantage for fast large-area intermediate state control using optical state feedback, since local optical measurements of device states near the edges will total It is representative of the entire device (no iris effect). In addition, by using a non-uniform electron conducting layer to apply a uniform local voltage across the device layers, this provides a unique advantage for fast large-area intermediate state control using voltage feedback because the voltage state on the bus bar will represent the entire device Instead of the average across the uneven colored device (still no iris effect). In a specific example, one of the 32 volts of voltage pulses is applied across one of the electrochromic devices incorporating one of the two gradient TCO layers and one of the bus bars positioned on the opposite peripheral edge of the entire device. The voltage pulse rises rapidly to allow the local voltage drop across the layers to rise rapidly to 1.0 volts and maintains the voltage until the device reaches a desired optical state measured with a suitable optical sensor, at which point the voltage pulse is fast Drop to zero or to a steady state voltage.

已詳細描述本發明，顯然修改及變動可行而不脫離隨附申請專利範圍中界定之本發明之範疇。此外，應瞭解， 本揭示內容中所有實例提供作為非限制性實例。 The present invention has been described in detail, and it is obvious that modifications and variations may be made without departing from the scope of the invention as defined in the appended claims. In addition, you should understand that All examples in this disclosure are provided as non-limiting examples.

實例 Instance

提供以下非限制性實例以進一步說明本發明。熟習此項技術者應瞭解，以下實例中揭示之技術代表發明者發現在實踐本發明時運行正常的途徑，且因此可視作組成其實踐之模式實例。然而，按照本揭示內容，熟習此項技術者應瞭解，在所揭示之特定實施例中可作出許多變化且仍然獲得相似或類似結果而不脫離本發明之精神及範疇。 The following non-limiting examples are provided to further illustrate the invention. It will be appreciated by those skilled in the art that the techniques disclosed in the examples below represent a way for the inventors to find that they operate normally when practicing the invention, and thus may be considered as examples of the modes that constitute their practice. However, it will be apparent to those skilled in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

實例1：虹膜效應切換 Example 1: Iris effect switching

已使用1-D集總元件電路模型模擬使用適於捕獲大面積裝置之切換動態之組件值的電致變色型裝置之動態表現。第5圖中所示之集總元件模型10係基於Skrayabin等人之論文(Electrochimica Acta 44(1999)3203-3209)。該電致變色裝置由並聯電阻器及非線性電容器局部地模型化，且導電層局部模型化為一電阻器。如第5圖所示之此等裝置之網路模型化大面積電致變色裝置之表現。該裝置與電源之間之低電阻電阻器模擬該電源與該裝置之間之接觸電阻。第6圖繪示所施加之電壓，1.1伏特之階梯函數。所得電流繪示於第7圖中；其快速上升至一最大值，且隨後隨著裝置切換發生而減小。第8圖繪示裝置之邊緣附近(一半處朝向中間)，及從裝置兩側至該裝置之中間附近的跨該電致變色裝置之電壓降(總共六條軌跡)。所見係該裝置之邊緣相對緩慢地切換且朝該裝 置之中間移動，該切換之發生更為緩慢。該裝置之中間相對於邊緣之更緩慢切換係稱作虹膜效應之大面積裝置之眾所周知的特性。 The 1-D lumped element circuit model has been used to simulate the dynamic performance of electrochromic devices using component values suitable for capturing switching dynamics of large area devices. The lumped element model 10 shown in Fig. 5 is based on the paper by Skrayabin et al. (Electrochimica Acta 44 (1999) 3203-3209). The electrochromic device is locally modeled by a parallel resistor and a non-linear capacitor, and the conductive layer is locally modeled as a resistor. The performance of the network modeled large area electrochromic device of such devices as shown in Figure 5. A low resistance resistor between the device and the power supply simulates the contact resistance between the power supply and the device. Figure 6 shows the applied voltage, a step function of 1.1 volts. The resulting current is depicted in Figure 7; it rises rapidly to a maximum and then decreases as device switching occurs. Figure 8 shows the vicinity of the edge of the device (half towards the middle) and the voltage drop across the electrochromic device from both sides of the device to the middle of the device (a total of six tracks). It is seen that the edge of the device is switched relatively slowly and towards the loading With the middle move, the switch occurs more slowly. The slower switching of the device relative to the edge is a well known characteristic of large area devices known as iris effects.

可藉由施加更複雜之電壓波形而增大此整個裝置之切換速度。此一波形連同其對電流之影響及對切換動態之影響繪示於第9圖至第11圖中。所施加之電壓脈衝經選擇以使邊緣附近之電壓升高至最大值，不超過1.0伏特。此要求電壓波形快速升高，且隨後根據需要及時降低電壓以將跨該裝置之電壓保持低於1.0伏特。此波形繪示於第9圖中。從電源流出之電流繪示於第10圖中，且繪示最初電流急劇增大，隨後隨所施加之電壓的減小，電流隨時間減小。第11圖繪示裝置之邊緣附近、一半處朝向裝置之中間及從兩個接觸件至裝置中間附近之跨該裝置之電壓降(總共6條軌跡)。可見在此情況中該裝置在該裝置邊緣附近比所施加之電壓係階梯函數的先前實例中切換更快。該裝置之中間附近切換仍然緩慢，且同時整個裝置比先前情況切換更快，虹膜效應可能加劇，因為在切換之部分期間邊緣與中間之間的電壓差更大。注意，該切換係對稱使得對應於對稱地相對定位在該裝置上之點的曲線相同地切換及重疊。如下一實例中所示，可藉由調整該多層裝置之電子傳導層中之薄層電阻分佈而減少或消除此虹膜效應。 The switching speed of the entire device can be increased by applying a more complex voltage waveform. This waveform, along with its effect on current and its effect on switching dynamics, is shown in Figures 9 through 11. The applied voltage pulse is selected to raise the voltage near the edge to a maximum of no more than 1.0 volts. This requires a rapid rise in the voltage waveform and subsequent voltage reduction as needed to keep the voltage across the device below 1.0 volts. This waveform is shown in Figure 9. The current flowing from the power supply is shown in Figure 10 and shows that the initial current increases sharply, and then the current decreases with time as the applied voltage decreases. Figure 11 shows the voltage drop across the edge of the device, halfway toward the middle of the device, and from the two contacts to the vicinity of the device (a total of six tracks). It can be seen that in this case the device switches faster near the edge of the device than in the previous example of the applied voltage system step function. Switching near the middle of the device is still slow, and at the same time the entire device switches faster than in the previous case, the iris effect may be exacerbated because the voltage difference between the edge and the middle is greater during the switching portion. Note that the switching is symmetrical such that the curves corresponding to the points symmetrically positioned relative to the device are switched and overlap identically. As shown in the following example, this iris effect can be reduced or eliminated by adjusting the sheet resistance distribution in the electron conducting layer of the multilayer device.

實例2：一致切換 Example 2: Consistent switching

第12圖中所示之1-D電路模型體現導電層之各者中之 薄層電阻之恆定梯度。此等經配置使得薄層電阻在與電源之連接處附近最低，且在該裝置之相對末端上最高。該電源之一極性施加至一導電層，且該電源之另一極性施加至相對導電層及該裝置之相對側上。使用此配置，不存在虹膜效應，且切換表現在品質上不同-提供跨整個裝置之一致切換及整個裝置之更快切換兩者。此切換表現繪示於第13圖至第15圖中。第13圖繪示所施加之電壓波形。此波形經選擇以將跨該裝置之電壓限制於總是低於所要臨限值(在此實例中為1.0伏特)。所得波形係具有快速上升前沿及更緩慢下降沿之電壓脈衝，其經選擇以使跨該裝置之電壓保持低於但接近所要臨限電壓。第14圖繪示以時間為函數之流動穿過裝置之電流，該電流快速升高，且具有形狀上類似於所施加之電壓脈衝之波形的波形。第15圖繪示電源接觸件附近之裝置邊緣處及裝置之中間附近的跨該電致變色裝置之電壓降。如在此曲線圖中可見，跨該裝置之電壓分佈在所有位置上相同。結果係，可在相對較短時間期限內將大電流驅動穿過該裝置，而跨該裝置之電壓較低且各處相同。導電層中之此不均勻薄層電阻可允許大面積電致變色裝置以類似於小面積裝置之動態切換。 The 1-D circuit model shown in Figure 12 represents each of the conductive layers. A constant gradient of sheet resistance. These are configured such that the sheet resistance is lowest near the junction with the power source and highest at the opposite end of the device. One polarity of the power source is applied to a conductive layer, and another polarity of the power source is applied to the opposite conductive layer and the opposite side of the device. With this configuration, there is no iris effect and the switching performance is qualitatively different - providing both consistent switching across the entire device and faster switching of the entire device. This switching performance is shown in Figures 13 through 15. Figure 13 shows the applied voltage waveform. This waveform is selected to limit the voltage across the device to always below the desired threshold (1.0 volts in this example). The resulting waveform is a voltage pulse having a fast rising leading edge and a slower falling edge that is selected such that the voltage across the device remains below but close to the desired threshold voltage. Figure 14 depicts the current flowing through the device as a function of time, which current rises rapidly and has a waveform that is similar in shape to the waveform of the applied voltage pulse. Figure 15 illustrates the voltage drop across the electrochromic device at the edge of the device near the power contact and near the middle of the device. As can be seen in this graph, the voltage distribution across the device is the same at all locations. As a result, a large current can be driven through the device over a relatively short period of time, while the voltage across the device is low and the same everywhere. This uneven sheet resistance in the conductive layer can allow for large area electrochromic devices to be dynamically switched similar to small area devices.

實例3：定向切換 Example 3: Directional Switching

第16圖中之集總元件模型係在一電致變色裝置中提供受控切換分佈之一組態之一實例。在此情況中，該裝置將從左切換至右。導電層係不對稱。頂部導電層係在左 側上具有5 Ω/□之薄層電阻的一層，且在此層之右側上線性增大至50 Ω/□。底部導電層係在左側上具有30 Ω/□之薄層電阻的一層，且在該層之右側上線性減小至3 Ω/□。第17圖繪示所施加之電壓波形，以在該裝置之左側上產生快速上升之電壓，同時將跨該裝置之此電壓保持低於1.0伏特。第18圖繪示穿過該裝置之相應電流，其最初快速增大，隨後隨裝置切換而快速下降。第19圖繪示從左至右之六個位置上之跨該裝置之電壓。如可看見，該電壓在最左側最快增大並接近1.0 V，且在更右邊之各點上，跨該裝置之電壓更緩慢地增大並接近1.0 V。此將導致裝置將以一預定方式從左切換至右。此表現可按窗大小控制，其可以導電層中之給定恆定薄層電阻展現虹膜效應。此外，從左至右發生切換之視速度之速率可由該等導電層中之薄層電阻分佈之間之差異控制。舉例而言，若實例3中之下導電層係在左側上具有40 Ω/□之薄層電阻，且在該層之右側線性地減小至4 Ω/□的一層，則在此情況中該裝置之切換從左至右會快得多。在薄層電阻分佈在相反方向上係線性且相同之限制情況中，則該裝置將如實例2中所展現般一致地切換。 The lumped element model of Figure 16 provides an example of one of the configurations of a controlled switching profile in an electrochromic device. In this case, the device will switch from left to right. The conductive layer is asymmetrical. The top conductive layer is on the left A layer with a sheet resistance of 5 Ω/□ on the side and linearly increases to 50 Ω/□ on the right side of this layer. The bottom conductive layer is a layer having a sheet resistance of 30 Ω/□ on the left side and linearly reduced to 3 Ω/□ on the right side of the layer. Figure 17 depicts the applied voltage waveform to produce a rapidly rising voltage on the left side of the device while maintaining this voltage across the device below 1.0 volts. Figure 18 depicts the corresponding current through the device, which initially increases rapidly and then drops rapidly as the device switches. Figure 19 shows the voltage across the device at six locations from left to right. As can be seen, this voltage increases fastest on the leftmost side and approaches 1.0 V, and at the more right points, the voltage across the device increases more slowly and approaches 1.0 V. This will cause the device to switch from left to right in a predetermined manner. This performance can be controlled by window size, which can exhibit an iris effect for a given constant sheet resistance in the conductive layer. Moreover, the rate of viewing speed from left to right can be controlled by the difference between the sheet resistance distributions in the conductive layers. For example, if the lower conductive layer in Example 3 has a sheet resistance of 40 Ω/□ on the left side and linearly decreases to a level of 4 Ω/□ on the right side of the layer, then in this case The switching of the device is much faster from left to right. In the case where the sheet resistance distribution is linear and identical in the opposite direction, then the device will switch consistently as demonstrated in Example 2.

實例4及比較實例4A Example 4 and Comparative Example 4A

實例4及比較實例4A(及實例5至7及比較實例)之所有基板之尺寸係9 cmx13.7 cm且厚度介於2.3 mm與4 mm之間。 The dimensions of all of the substrates of Example 4 and Comparative Example 4A (and Examples 5 to 7 and Comparative Examples) were 9 cm x 13.7 cm and the thickness was between 2.3 mm and 4 mm.

針對該實例及比較實例製備含有單個電致變色電極層 及單個離子傳導層之裝置，該單個電致變色電極層及該單個離子傳導層安置於定位在兩個玻璃外基板之間之兩個導電層之間。導電層係濺鍍塗佈於浮式玻璃基板上之摻雜錫之氧化銦(ITO)透明導電氧化物(TCO)層。比較實例4A使用具有65 Ω/□之均勻薄層電阻之塗佈ITO的基板。實例4使用具有從70 Ω/□至400 Ω/□線性增大之薄層電阻之塗佈ITO的基板。薄層電阻在13.7 cm方向上線性增大(即，恆定薄層電阻梯度)，且在9 cm方向上近似均勻。該等ITO基板針對藉由濺鍍至裸浮式玻璃基板上之工作而專門製備。裝置之製作程序在下文中詳細描述。 Preparation of a single electrochromic electrode layer for this and comparative examples And a device for a single ion-conducting layer disposed between the two conductive layers positioned between the two outer glass substrates. The conductive layer is a tin-doped indium oxide (ITO) transparent conductive oxide (TCO) layer that is sputter coated on a floating glass substrate. Comparative Example 4A used a substrate coated with ITO having a uniform sheet resistance of 65 Ω/□. Example 4 used a coated ITO substrate having a sheet resistance that increased linearly from 70 Ω/□ to 400 Ω/□. The sheet resistance increases linearly in the 13.7 cm direction (ie, a constant sheet resistance gradient) and is approximately uniform in the 9 cm direction. These ITO substrates are specifically prepared for the work by sputtering onto a bare floating glass substrate. The production process of the device is described in detail below.

塗佈ITO之基板之薄層電阻使用4點探針量測工具量測。有關梯度電阻ITO基板之薄層電阻量測在放置在直線上之至少五個相等間隔之位置上進行，該線垂直於基板之9 cm側延伸，且量測之位置覆蓋薄層電阻梯度之大部分。 The sheet resistance of the substrate coated with ITO was measured using a 4-point probe measuring tool. The sheet resistance measurement of the gradient resistance ITO substrate is performed at at least five equally spaced positions placed on the line, the line extending perpendicular to the 9 cm side of the substrate, and the measured position covers the thickness of the sheet resistance gradient section.

氧化鎢前軀體製備如下。在0℃冰浴中，2 L燒瓶裝入40 mL水，且配有攪拌棒。隨後添加800 mL水性過氧化氫(30 wt.% H₂O₂)及冰醋酸之50：50溶液，且攪拌30分鐘以平衡至冰浴溫度。將65 g鎢金屬添加至該冷混合物，並攪拌以反應24小時。所得溶液經粗糙濾紙(Whatman 54)及隨後精細濾紙(Whatman 42)過濾以產生透明、微黃濾液。該濾液隨後在55℃下迴流18小時，且經精細(Whatman 42)濾紙重新過濾，隨後在真空下以65℃(使 用吸水器)乾燥，以回收粉末狀鎢過氧酸酯產物。 The tungsten oxide precursor was prepared as follows. The 2 L flask was charged with 40 mL of water in a 0 ° C ice bath with a stir bar. A solution of 800 mL of aqueous hydrogen peroxide (30 wt.% H ₂ O ₂ ) and glacial acetic acid in 50:50 was then added and stirred for 30 minutes to equilibrate to ice bath temperature. 65 g of tungsten metal was added to the cold mixture and stirred for 24 hours. The resulting solution was filtered through a coarse filter paper (Whatman 54) followed by fine filter paper (Whatman 42) to give a clear, slightly yellow filtrate. The filtrate was then refluxed at 55 ° C for 18 hours and re-filtered through fine (Whatman 42) filter paper, followed by drying at 65 ° C (using a water aspirator) under vacuum to recover the powdered tungsten peroxy ester product.

藉由在手套箱中之氬氛圍下，在60 mL無水乙醇中溶解18 g固體鎢過氧酸前軀體、0.668 g鋰甲醇及2.367 g草酸而製備塗層溶液。 A coating solution was prepared by dissolving 18 g of solid tungsten peroxyacid precursor, 0.668 g of lithium methanol, and 2.367 g of oxalic acid in 60 mL of absolute ethanol under an argon atmosphere in a glove box.

塗層溶液旋塗於兩個TCO類型上(均勻薄層電阻及梯度薄層電阻)。 The coating solution was spin coated onto two TCO types (uniform sheet resistance and gradient sheet resistance).

在塗佈之後，使用水從基板之所有側上移除一條塗佈之膜。此使下伏TCO暴露以用於電接觸及更好的黏附。該等膜在一潮濕腔室中用以下程序處理。 After coating, a coated film was removed from all sides of the substrate using water. This exposes the underlying TCO for electrical contact and better adhesion. The membranes were treated in a humid chamber using the following procedure.

在從該潮濕腔室移除之後，該等膜在空氣中在烤爐中用以下程序處理，以產生氧化鎢膜。 After removal from the wet chamber, the films were processed in air in an oven using the following procedure to produce a tungsten oxide film.

最終厚度藉由一接觸表面輪廓儀量測為大約300 nm。 The final thickness was measured to be approximately 300 nm by a contact surface profiler.

在一組ITO基板(一個均勻薄層電阻ITO及一個梯度薄層電阻ITO)之相對角上鑽入直徑4 mm之兩個孔。隨後藉由圍繞外部邊緣使用熱固環氧樹脂而將匹配基板密閉性地密封在一起(導電表面朝內)，從而構造該等裝置(例如，在單個裝置中使用兩個均勻薄層電阻ITO基板，而在另一裝置中使用兩個梯度薄層電阻ITO基板)。藉由將具有已知直徑之玻璃珠粒混合成環氧樹脂而設定210 μm之固定間隙寬度。基板相對於彼此移位，以在所有方向上產生大約0.5 cm之重疊以容許電連接及電量測。用於電接觸之匯流排條焊接於該裝置之較短側(即，9 cm側)上之重疊區段上。梯度ITO裝置組裝有彼此相對之梯度，且其等之低薄層電阻側用作接觸件之匯流排條區(即，各基板之低薄層電阻側對準為面向另一基板之高薄層電阻側，且兩個低薄層電阻側安置為暴露)。 Two holes of 4 mm in diameter were drilled at opposite corners of a set of ITO substrates (a uniform sheet resistance ITO and a gradient sheet resistance ITO). The devices are then hermetically sealed by using a thermoset epoxy around the outer edge to seal the mating substrates together (the conductive surfaces are facing inward) (eg, using two uniform sheet resistance ITO substrates in a single device) While using two gradient sheet resistance ITO substrates in another device). A fixed gap width of 210 μm was set by mixing glass beads having a known diameter into an epoxy resin. The substrates are displaced relative to each other to create an overlap of approximately 0.5 cm in all directions to allow electrical connection and electrical measurements. The bus bars for electrical contact are soldered to overlapping sections on the shorter side of the device (i.e., the 9 cm side). The gradient ITO devices are assembled with gradients opposite each other, and the lower sheet resistance side of the substrate is used as the bus bar region of the contacts (ie, the low sheet resistance side of each substrate is aligned to a high thin layer facing the other substrate) The resistance side, and the two low-profile resistor sides are placed to be exposed).

所製備之裝置透過鑽入之孔填充離子傳導溶液(無水碳酸丙烯酯中之0.5 M的三氟甲磺酸鋰及0.05 M的二茂鐵)。隨後密封該等孔。在此等裝置中，該離子傳導層中之二茂鐵用作能夠在***及引出電子時可逆地氧化及還原之一物質。 The prepared apparatus was filled with an ion-conducting solution (0.5 M lithium trifluoromethanesulfonate and 0.05 M ferrocene in anhydrous propylene carbonate) through a drilled hole. The holes are then sealed. In such devices, the ferrocene in the ion-conducting layer serves as a substance capable of reversibly oxidizing and reducing upon insertion and extraction of electrons.

所完成之裝置之分析及特徵化使用定製實驗儀器實行。該儀器容許同時控制電壓源、量測在裝置中之多個 點上之跨電磁光譜之透射及多個點上之跨電化學堆疊之電位。此允許該裝置之完全特徵化，且將該裝置中之一特定點上之電致變色堆疊中之電壓電位與相同點上之電磁透射關聯。例如，一裝置可用具有預設電壓脈衝分佈，及電壓及光學資料之簡單量測而特徵化。此外，該裝置可用調整以維持該電致變色堆疊中之目標電壓電位之電壓脈衝而特徵化。 Analysis and characterization of the completed device was performed using custom experimental instruments. The instrument allows simultaneous control of the voltage source and measurement of multiple devices in the device The transmission across the electromagnetic spectrum at the point and the potential across the electrochemical stack at multiple points. This allows for full characterization of the device and correlates the voltage potential in the electrochromic stack at a particular point in the device to electromagnetic transmission at the same point. For example, a device can be characterized by a simple measurement with a predetermined voltage pulse distribution, and voltage and optical data. Additionally, the device can be characterized by voltage pulses that are adjusted to maintain a target voltage potential in the electrochromic stack.

比較實例4A及實例4中之裝置被特徵化。展示電壓及透射值上之變動之資料在下文中提出。「虹膜」值係以550 nm在裝置從漂白狀態切換至有色狀態時量測之該裝置邊緣附近與中間附近之區域之間的最大透射差異。最大電壓△係在裝置從漂白狀態切換至有色狀態時在該裝置之邊緣附近與中間附近之跨該電致變色堆疊之最大電位差。自動調整源電壓以在該裝置之邊緣上跨該電致變色堆疊維持1.2伏特。至穩定狀態之總時間在各情況中為約150秒。 The devices in Comparative Examples 4A and 4 were characterized. Information showing changes in voltage and transmission values is presented below. The "Iris" value is the maximum transmission difference between the vicinity of the device edge and the vicinity of the vicinity of the device measured at 550 nm as the device switches from bleaching to colored. The maximum voltage Δ is the maximum potential difference across the electrochromic stack near the edge of the device near the edge of the device when the device is switched from the bleached state to the colored state. The source voltage is automatically adjusted to maintain 1.2 volts across the electrochromic stack on the edge of the device. The total time to steady state is about 150 seconds in each case.

實例5及比較實例5A Example 5 and Comparative Example 5A

針對實例及比較實例製備安置於單個離子傳導層之各側上之包括兩個電致變色電極層之裝置，各電致變色電極層抵靠一導電TCO層而安置，且各TCO層抵靠玻璃外基板而配置。比較實例5A使用具有大約220 Ω/□之均 勻薄層電阻之塗佈ITO之基板。實例5使用具有從大約100 Ω/□至500 Ω/□之恆定梯度薄層電阻之塗佈ITO之基板。梯度裝置構造有如實例4中之定向之基板。針對該方案專門濺射沈積ITO，且隨後熱處理以增大其薄層電阻。在熱處理之後及在***最終裝置中之前對沈積之電極膜進行薄層電阻量測。 A device comprising two electrochromic electrode layers disposed on each side of a single ion conducting layer is prepared for the examples and comparative examples, each electrochromic electrode layer being disposed against a conductive TCO layer, and each TCO layer resting against the glass The outer substrate is arranged. Comparative Example 5A uses a mean of approximately 220 Ω/□ The ITO substrate coated with a uniform sheet resistance. Example 5 used a substrate coated with ITO having a constant gradient sheet resistance of from about 100 Ω/□ to 500 Ω/□. The gradient device was constructed with a substrate oriented as in Example 4. The ITO was sputter deposited specifically for this scheme and then heat treated to increase its sheet resistance. The deposited electrode film was subjected to sheet resistance measurement after the heat treatment and before being inserted into the final device.

塗佈ITO之基板之薄層電阻使用4點探針量測工具量測。對均勻塗佈ITO之基板之薄層電阻量測在膜上之若干點上進行。對梯度薄層電阻ITO基板之薄層電阻量測在直線上之至少五個相等間隔之位置上進行，該線垂直該基板之兩個9 cm側，且在該基板之兩個9 cm側之間延伸。據觀察，由於電極膜之熱處理及應用，ITO之薄層電阻會改變。在一電極膜熱處理或施加之後，將一校正因數應用於薄層電阻量測。藉由量測放置在各9 cm側之中點與與邊緣偏移約0.5 cm之兩點之間之基板的總體薄層電阻，及確保對暴露之TCO之量測而計算該校正因數。該校正因數隨後為在處理前與處理後之該基板之此總體薄層電阻之比率。舉例而言，若此薄層電阻由於熱處理而從100 Ω增大至150 Ω，且原以Ω/□量測之薄層電阻係200 Ω/□，則在熱處理之後報告之以Ω/sq計之薄層電阻係300 Ω/□。 The sheet resistance of the substrate coated with ITO was measured using a 4-point probe measuring tool. The sheet resistance measurement of the substrate uniformly coated with ITO was performed at several points on the film. The sheet resistance measurement of the gradient sheet resistance ITO substrate is performed at at least five equally spaced locations on the line that are perpendicular to the two 9 cm sides of the substrate and on the two 9 cm sides of the substrate Extended between. It has been observed that the sheet resistance of ITO changes due to the heat treatment and application of the electrode film. A correction factor is applied to the sheet resistance measurement after heat treatment or application of an electrode film. The correction factor is calculated by measuring the overall sheet resistance of the substrate placed between the midpoint of each 9 cm side and the point offset by about 0.5 cm from the edge, and by ensuring the measurement of the exposed TCO. The correction factor is then the ratio of this overall sheet resistance of the substrate before and after processing. For example, if the sheet resistance is increased from 100 Ω to 150 Ω due to heat treatment, and the sheet resistance measured by Ω/□ is 200 Ω/□, it is reported as Ω/sq after heat treatment. The sheet resistance is 300 Ω/□.

如實例4中在兩個基板類型(即，一個均勻薄層電阻及一個梯度薄層電阻基板)上製備氧化鎢膜。該等氧化鎢膜用作第一電極層。 A tungsten oxide film was prepared as in Example 4 on two substrate types (i.e., a uniform sheet resistance and a gradient sheet resistance substrate). These tungsten oxide films are used as the first electrode layer.

在該兩個基板類型上製備互補氧化釩乾凝膠膜。在塗佈之前在此組之相對邊角中鑽入直徑4 mm之兩個孔。該等氧化釩膜用作第二電極層。 A complementary vanadium oxide xerogel film was prepared on the two substrate types. Two holes of 4 mm diameter were drilled into the opposite corners of this set prior to coating. These vanadium oxide films are used as the second electrode layer.

藉由陽離子交換而酸化LiVO₃，緊接著在所得釩酸可能出現凝膠作用之前旋塗而進行氧化釩乾凝膠塗佈。塗層溶液之程序如下。 The vanadium oxide xerogel coating is carried out by acidifying LiVO ₃ by cation exchange followed by spin coating before the resulting vanaic acid may gel. The procedure for the coating solution is as follows.

藉由在60℃下攪拌1小時而在34 mL之40%vol之水性乙醇中溶解8.08 g的LiVO₃，從而製備2 M之LiVO₃前軀體溶液。過濾(Whatman 40)渾濁溶液，且過濾器用40%乙醇清洗。濾液稀釋至40 mL，且搖晃以混合產生微黃、黏性之2 M之LiVO₃溶液。 A 2 M LiVO ₃ precursor solution was prepared by dissolving 8.08 g of LiVO ₃ in 34 mL of 40% vol of aqueous ethanol by stirring at 60 ° C for 1 hour. The turbid solution was filtered (Whatman 40) and the filter was washed with 40% ethanol. The filtrate was diluted to 40 mL and shaken to mix to produce a yellowish, viscous 2 M LiVO ₃ solution.

藉由將2 mL(3.4 meq)Dowex WX8 100-200網狀陽離子交換樹脂(質子形式)填充入配有0.2微米PTFE Acrodisk過濾器之3 mL針筒中而製備急驟離子交換管柱，以保留樹脂珠粒。該等管柱用水沖洗兩次，且隨後排水。一毫升LiVO₃溶液添加至填充之針筒，該溶液搖晃十秒以與樹脂混合。藉由按壓針筒活塞而洗脫該「管柱」，且亮橙色釩酸溶液立即重新過濾(0.2微米PTFE Acrodisk)至基板上並旋轉以形成塗層。在塗佈之後，使用水處理從基板之所有側上移除一條塗佈之膜。此使下伏TCO暴露以用於電接觸及更好的黏附。 Prepare a flash ion exchange column to retain resin beads by filling 2 mL (3.4 meq) Dowex WX8 100-200 reticulated cation exchange resin (proton form) into a 3 mL syringe equipped with a 0.2 micron PTFE Acrodisk filter grain. The columns were rinsed twice with water and then drained. One milliliter of LiVO ₃ solution was added to the filled syringe, and the solution was shaken for ten seconds to be mixed with the resin. The "column" was eluted by pressing the syringe piston, and the bright orange vanadic acid solution was immediately re-filtered (0.2 micron PTFE Acrodisk) onto the substrate and rotated to form a coating. After coating, a coated film was removed from all sides of the substrate using water treatment. This exposes the underlying TCO for electrical contact and better adhesion.

所得膜使用以下配方熱處理以產生氧化釩膜。 The resulting film was heat treated using the following formulation to produce a vanadium oxide film.

最終厚度藉由一接觸表面輪廓儀量測為大約100 nm。 The final thickness was measured to be approximately 100 nm by a contact surface profiler.

在一手套工具箱中使用鋰金屬反電極及溶液(碳酸丙烯酯中之1 M高氯酸鋰)鋰化該等氧化釩膜。用針對參考鋰金屬引用之電壓執行涉及氧化至3.8 V，隨後在2.4 V下還原之兩步驟程序。執行鋰化以使該氧化釩進入還原狀態，該還原狀態允許氧化釩用作氧化鎢膜之反電極。 The vanadium oxide film is lithiated in a glove kit using a lithium metal counter electrode and a solution (1 M lithium perchlorate in propylene carbonate). A two-step procedure involving oxidation to 3.8 V followed by reduction at 2.4 V was performed with a voltage referenced to the reference lithium metal. Lithiation is performed to bring the vanadium oxide into a reduced state, which allows the vanadium oxide to be used as a counter electrode of the tungsten oxide film.

隨後藉由使用丙烯酸膠帶將匹配基板密閉性地密封在一起(導電表面朝內)而構造該等裝置。藉由該膠帶設定500 μm之固定間隙寬度。丙烯酸膠帶用於快速建立裝置。基板相對於彼此移位，以在所有方向上產生大約0.5 cm之重疊以容許電連接及量測。梯度裝置如實例4組裝，暴露低薄層電阻側用於電接觸。 The devices are then constructed by hermetically sealing the mating substrates together (the conductive surfaces are facing inward) using acrylic tape. A fixed gap width of 500 μm was set by the tape. Acrylic tape is used to quickly build the device. The substrates are displaced relative to each other to create an overlap of approximately 0.5 cm in all directions to allow electrical connection and measurement. The gradient device was assembled as in Example 4, exposing the low sheet resistance side for electrical contact.

所製備之裝置透過鑽孔填充電解質溶液(無水碳酸丙烯酯中之1.5 M的雙三氟甲烷磺醯亞胺鋰)。隨後密封該等孔。 The prepared apparatus was filled with an electrolyte solution (1.5 M of lithium bistrifluoromethanesulfonimide in anhydrous propylene carbonate) through a drilled hole. The holes are then sealed.

實例5及比較實例5A裝置用實例4中描述之專門設置分析。結果示於下文 Example 5 and Comparative Example 5A apparatus were analyzed using the special settings described in Example 4. The results are shown below

如由結果所表明，與比較實例5A之裝置相比，，實例5之裝置明顯減小虹膜值，同時達成更快之切換速度。 As indicated by the results, the device of Example 5 significantly reduced the iris value compared to the device of Comparative Example 5A while achieving a faster switching speed.

實例6 Example 6

製備含有安置於單個離子傳導層之各側上的兩個電致變色電極層之裝置，各電致變色電極層抵靠一導電TCO層而安置，且各TCO層抵靠玻璃外基板而配置。此實例6之裝置使用具有兩個雷射刻線之圖案之TEC 70基板(Pilkington)。TEC玻璃為市售摻雜氟之氧化錫(FTO)，其中名稱中之數字以Ω/□指示薄層電阻。FTO係TCO。雷射刻線之圖案增大及調變該TCO之薄層電阻。第一TEC基板具有模擬250 Ω/□之均勻薄層電阻之一雷射圖案。第二TEC基板具有模擬從170 Ω/□至1500 Ω/□之基板薄層電阻之線性增大之一雷射刻線圖案。 Apparatus is provided for containing two electrochromic electrode layers disposed on each side of a single ion conducting layer, each electrochromic electrode layer being disposed against a conductive TCO layer, and each TCO layer disposed against the outer glass substrate. The device of Example 6 used a TEC 70 substrate (Pilkington) having a pattern of two laser scribe lines. TEC glass is a commercially available fluorine-doped tin oxide (FTO) in which the number in the name indicates the sheet resistance in Ω/□. FTO is a TCO. The pattern of the laser reticle increases and modulates the sheet resistance of the TCO. The first TEC substrate has a laser pattern that mimics a uniform sheet resistance of 250 Ω/□. The second TEC substrate has a laser reticle pattern that simulates a linear increase in substrate sheet resistance from 170 Ω/□ to 1500 Ω/□.

刻線TEC玻璃基板之薄層電阻藉由量測該基板上間隔開1 cm之兩點之間之薄層電阻而計算。對具有以Ω/□計之已知薄層電阻之值的一組不刻線TEC玻璃執行相同量測。從該等不刻線TEC量測中，計算將Ω/□與2點薄層電阻值相關之校準曲線。隨後針對對該等刻線TEC玻 璃基板之各量測計算以Ω/□計之薄層電阻值。藉由在該基板之兩個9 cm側之間且垂直於該基板之兩個9 cm側之直線上按1 cm間隔進行個別量測而量測第二TEC玻璃基板薄層電阻分佈。 The sheet resistance of the reticle TEC glass substrate was calculated by measuring the sheet resistance between the two points spaced apart by 1 cm on the substrate. The same measurement was performed on a set of un-scored TEC glasses having values of known sheet resistance in Ω/□. From these non-marked TEC measurements, a calibration curve relating Ω/□ to the 2-point sheet resistance value was calculated. Subsequently for the reticle The measurement of the sheet resistance in Ω/□ was calculated for each measurement of the glass substrate. The second TEC glass substrate sheet resistance distribution was measured by individual measurements at 1 cm intervals on the line between the two 9 cm sides of the substrate and perpendicular to the two 9 cm sides of the substrate.

該裝置應與實例3對比。實例3描述具有定向切換之電致變色裝置之集總元件模型。在實例3中此定向切換藉由導電層(例如，TCO)中之不對稱性而達成。實例6之裝置在兩個導電層中具有不對稱性，且預期展示該裝置在該第二TEC基板之低薄層電阻側上切換較快，且在該第二TEC基板之高薄層電阻側上切換較慢之一定向切換。 The device should be compared to Example 3. Example 3 describes a lumped element model of an electrochromic device with directional switching. This directional switching is achieved in Example 3 by the asymmetry in the conductive layer (e.g., TCO). The device of Example 6 has asymmetry in the two conductive layers, and it is expected that the device will switch faster on the low sheet resistance side of the second TEC substrate and on the high sheet resistance side of the second TEC substrate One of the slower switching is directional switching.

該裝置使用下述程序構造。 The device was constructed using the following procedure.

在該第二TEC基板(具有梯度薄層電阻)上製備如實例4中之氧化鎢膜。該氧化鎢膜用作第一電極層。 A tungsten oxide film as in Example 4 was prepared on the second TEC substrate (having a gradient sheet resistance). This tungsten oxide film is used as the first electrode layer.

在該第一TEC基板(均勻薄層電阻)上製備互補氧化釩膜。該氧化釩膜用作第二電極層。在塗佈之前在該均勻薄層電阻基板之相對邊角中鑽入直徑大約4 mm之兩個孔。根據以下配方製備塗層溶液。 A complementary vanadium oxide film is prepared on the first TEC substrate (uniform sheet resistance). This vanadium oxide film is used as the second electrode layer. Two holes having a diameter of about 4 mm were drilled into the opposite corners of the uniform sheet resistance substrate prior to coating. A coating solution was prepared according to the following formulation.

藉由在60℃下將固體溶解在水中，形成5%wt溶液，接著經Whatman 40紙過濾而製備LiVO₃溶液。藉由將LiVO₃之此5%wt溶液透過填充有至少20等份H⁺形式之Dowex Monosphere 650C之離子交換管柱逐滴流動，用額外去離子水洗脫直到淺黃色終點而將釩酸鹽物質質子化為「釩酸」。允許經洗脫之釩酸保持整晚，其後其被超聲降解以 分散所形成之任何固體。 A LiVO ₃ solution was prepared by dissolving the solid in water at 60 ° C to form a 5% wt solution followed by filtration through Whatman 40 paper. The vanadate is eluted by passing the 5% wt solution of LiVO ₃ through a column of ion exchange tubes filled with at least 20 aliquots of H ⁺ form of Dowex Monosphere 650C, eluting with additional deionized water until a pale yellow end point The protonation of matter is "vanadic acid". The eluted vanadic acid was allowed to remain overnight, after which it was sonicated to disperse any solid formed.

將六等份三乙胺添加至該釩酸，且該混合物在40℃至50℃下超聲降解一小時，以形成無色、輕微渾濁。此溶液在高至55℃下於減小之壓力下蒸發以產生黃色黏性液體。此在乙醇或2-甲氧基乙醇中溶解為介於0.4 M釩與1.2 M釩之間以產生最終塗層溶液。 Six aliquots of triethylamine were added to the vanadic acid, and the mixture was sonicated at 40 ° C to 50 ° C for one hour to form a colorless, slightly turbid. This solution was evaporated under reduced pressure at up to 55 ° C to produce a yellow viscous liquid. This dissolves between 0.4 M vanadium and 1.2 M vanadium in ethanol or 2-methoxyethanol to produce the final coating solution.

該塗層溶液旋塗於基板上。在塗佈之後，使用水處理從基板之所有側上移除一條塗佈之膜。此使下伏TCO暴露以用於電接觸及更好的黏附。該膜使用以下配方在空氣中熱處理以產生氧化釩膜。 The coating solution is spin coated onto the substrate. After coating, a coated film was removed from all sides of the substrate using water treatment. This exposes the underlying TCO for electrical contact and better adhesion. The film was heat treated in air using the following formulation to produce a vanadium oxide film.

最終厚度藉由一接觸表面輪廓儀量測為大約200 nm。 The final thickness was measured to be approximately 200 nm by a contact surface profiler.

該氧化釩膜在一手套工具箱中使用鋰金屬反電極及1 M溶液(碳酸丙烯酯中之高氯酸鋰)而鋰化。鋰化期間針對鋰金屬之電壓為2.7至2.9伏特。執行鋰化以使該氧化釩進入還原狀態，該還原狀態允許氧化釩用作氧化鎢膜之反電極。 The vanadium oxide film was lithiated in a glove kit using a lithium metal counter electrode and a 1 M solution (lithium perchlorate in propylene carbonate). The voltage for lithium metal during lithiation is 2.7 to 2.9 volts. Lithiation is performed to bring the vanadium oxide into a reduced state, which allows the vanadium oxide to be used as a counter electrode of the tungsten oxide film.

隨後藉由圍繞外部邊緣使用熱固環氧樹脂而將匹配基板密閉性地密封在一起(導電表面朝內)，從而構造該等裝置。藉由將已知直徑之玻璃珠粒與該環氧樹脂混合而設定210 μm之固定間隙寬度。基板相對於彼此移位以 在所有方向上產生約0.5 cm之重疊，以容許電連接及量測。該裝置構造有梯度基板，該梯度基板定向為低薄層電阻側暴露用於電連接。 The devices are then constructed by hermetically sealing the mating substrates together with the thermosetting epoxy around the outer edges (the conductive surfaces are facing inward). A fixed gap width of 210 μm was set by mixing glass beads of known diameter with the epoxy resin. The substrates are displaced relative to each other to An overlap of about 0.5 cm is produced in all directions to allow electrical connection and measurement. The device is constructed with a gradient substrate oriented with a low sheet resistance side exposed for electrical connection.

所製備之裝置在25℃下於25%相對濕度下在潮濕腔室中水合2小時。所製備之裝置隨後透過鑽孔填充電解質溶液(無水碳酸丙烯酯中之1.5 M的双三氟甲烷磺酰亚胺锂)。隨後密封該等孔。 The prepared device was hydrated in a humid chamber at 25 ° C for 2 hours at 25% relative humidity. The prepared apparatus was then filled with an electrolyte solution (1.5 M of bistrifluoromethanesulfonimide lithium in anhydrous propylene carbonate) through a drilled hole. The holes are then sealed.

實例6之裝置特徵化為並展現顯著的定向改變效應，其中該裝置從漂白狀態切換至有色狀態在第二TEC基板之低薄層電阻側上明顯比在第二TEC基板之高薄層電阻側上快。在著色期間透射之差異超過25%。此定向改變在質上與實例3中進行之預測一致。 The device of Example 6 was characterized as and exhibited significant orientation change effects, wherein switching the device from a bleached state to a colored state was significantly higher on the low sheet resistance side of the second TEC substrate than on the high sheet resistance side of the second TEC substrate. Fast up. The difference in transmission during coloring exceeds 25%. This orientation change is qualitatively consistent with the predictions made in Example 3.

實例7及比較實例7A Example 7 and Comparative Example 7A

製造含有安置於單個離子傳導層之各側上之兩個電極之裝置(其一者係電致變色，各電極層抵靠一導電TCO層安置，且各TCO層抵靠玻璃外基板配置。比較實例7A之裝置使用具有雷射刻線圖案之TEC 70基板(Pilkington)以模擬250 Ω/□之薄層電阻。雷射刻線圖案增大及調變該TCO之薄層電阻。實例7之裝置使用具有雷射刻線圖案之TEC 70基板，其模擬70 Ω/□至250 Ω/□之基板。薄層電阻值如實例6中所計算。該裝置構造有基板，該基板定向為具有與實例4相反之薄層電阻梯度。所有裝置使用下文描述之程序構造。 A device comprising two electrodes disposed on each side of a single ion conducting layer (one of which is electrochromic, each electrode layer disposed against a conductive TCO layer, and each TCO layer disposed against the outer glass substrate) is fabricated. The apparatus of Example 7A used a TEC 70 substrate (Pilkington) with a laser reticle pattern to simulate a sheet resistance of 250 Ω/□. The laser reticle pattern increases and modulates the sheet resistance of the TCO. A TEC 70 substrate with a laser reticle pattern was used, which simulates a substrate from 70 Ω/□ to 250 Ω/□. The sheet resistance values were calculated as in Example 6. The device was constructed with a substrate oriented with and with examples 4 The opposite sheet resistance gradient. All devices were constructed using the procedure described below.

將水性溶液(Alfa Aesar)中20 wt%膠態分散之氧化鈰塗 層溶液旋塗於一組雷射刻線之FTO基板上。在旋塗之後，使用醋酸溶液(aq.,2.5wt%)從所有側上移除一條氧化鈰膜。該膜在空氣中在240℃下熱處理一小時。 20 wt% colloidally dispersed cerium oxide coating in aqueous solution (Alfa Aesar) The layer solution is spin coated onto a set of laser reticle FTO substrates. After spin coating, a cerium oxide film was removed from all sides using an acetic acid solution (aq., 2.5 wt%). The film was heat treated in air at 240 ° C for one hour.

最終厚度藉由表面輪廓儀量測為約350 nm。 The final thickness was measured by a surface profiler to be approximately 350 nm.

該等氧化鈰膜用作第一電極層。 These ruthenium oxide films are used as the first electrode layer.

在相同基板組上製備互補氧化釩膜。該等氧化釩膜用作第二電極層，且係電致變色。在塗佈之前，在此組之邊角中鑽入直徑4 mm之兩個孔。根據以下程序製備釩溶液。 A complementary vanadium oxide film was prepared on the same substrate group. These vanadium oxide films are used as the second electrode layer and are electrochromic. Prior to coating, two holes of 4 mm diameter were drilled into the corners of this set. A vanadium solution was prepared according to the following procedure.

藉由在60℃下攪拌1小時而在34 mL 40%vol之水性乙醇中溶解8.08 g LiVO₃，從而製備2 M的LiVO₃前軀體溶液。過濾(Whatman 40)渾濁溶液，且過濾器用40%之乙醇清洗。濾液稀釋至40 mL，且搖晃以混合產生微黃、黏性的2 M的LiVO₃溶液。 A 2 M LiVO ₃ precursor solution was prepared by dissolving 8.08 g of LiVO ₃ in 34 mL of 40% vol of aqueous ethanol by stirring at 60 ° C for 1 hour. The turbid solution was filtered (Whatman 40) and the filter was rinsed with 40% ethanol. The filtrate was diluted to 40 mL and shaken to mix to produce a yellowish, viscous 2 M LiVO ₃ solution.

藉由在用力攪拌下添加介於4.5 g與6 g之間之Dowex Monosphere 650C陽離子交換樹脂(質子形式)而將二十毫升之此LiVO₃溶液酸化。所得亮橙色混合物經濾紙(Whatman 40)過濾，且隨後用6.6 mL水稀釋以產生最終塗層溶液。 Twenty milliliters of this LiVO ₃ solution was acidified by the addition of between 4.5 g and 6 g of Dowex Monosphere 650C cation exchange resin (proton form) with vigorous stirring. The resulting bright orange mixture was filtered through a filter paper (Whatman 40) and then diluted with 6.6 mL water to give a final coating solution.

所塗佈之膜在空氣中在240℃下熱處理一小時以產生氧化釩膜。最終厚度藉由一接觸表面輪廓儀量測為約150 nm。 The coated film was heat-treated at 240 ° C for one hour in the air to produce a vanadium oxide film. The final thickness was measured to be about 150 nm by a contact surface profiler.

該等氧化釩膜在一手套工具箱中使用鋰金屬反電極及溶液(碳酸丙烯酯中之1 M高氯酸鋰)而被鋰化。用針 對參考鋰金屬引用之電壓執行涉及3.8 V至氧化，隨後在2.4 V下還原之兩步驟程序。執行鋰化以使該氧化釩進入還原狀態，該還原狀態允許氧化釩用作氧化鈰膜之反電極。 The vanadium oxide films were lithiated in a glove kit using a lithium metal counter electrode and a solution (1 M lithium perchlorate in propylene carbonate). Needle A two-step procedure involving 3.8 V to oxidation followed by a reduction at 2.4 V is performed on the voltage referenced by the reference lithium metal. Lithiation is performed to bring the vanadium oxide into a reduced state, which allows the vanadium oxide to be used as a counter electrode of the hafnium oxide film.

隨後藉由圍繞外部邊緣使用丙烯酸膠帶而將匹配基板密閉性地密封在一起(導電表面朝內)，從而構造該等裝置。由該膠帶設定500 μm之固定間隙寬度。基板相對於彼此移位，以產生在所有方向上約0.5 cm之重疊，以容許電連接及量測。梯度裝置如實例4中所組裝，暴露低薄層電阻側用於電接觸。 The devices are then constructed by hermetically sealing the mating substrates together with the acrylic tape around the outer edges (the conductive surfaces are facing inward). A fixed gap width of 500 μm was set by the tape. The substrates are displaced relative to one another to create an overlap of about 0.5 cm in all directions to allow for electrical connection and measurement. The gradient device was assembled as in Example 4, exposing the low sheet resistance side for electrical contact.

所製備之裝置隨後透過鑽孔填充電解質溶液(無水碳酸丙烯酯中之1.5 M的双三氟甲烷磺酰亚胺锂)。隨後密封該等孔。 The prepared apparatus was then filled with an electrolyte solution (1.5 M of bistrifluoromethanesulfonimide lithium in anhydrous propylene carbonate) through a drilled hole. The holes are then sealed.

此等裝置之虹膜值在450 nm下量測。使用此波長，因為其與550 nm相比在漂白狀態與有色狀態之間展示更大透射率改變。 The iris values of these devices were measured at 450 nm. This wavelength is used because it exhibits a greater transmission change between the bleached state and the colored state than 550 nm.

該梯度裝置達成更一致切換及明顯更快之切換速度。 The gradient device achieves a more consistent switching and a significantly faster switching speed.

1‧‧‧多層電致變色裝置 1‧‧‧Multilayer electrochromic device

10‧‧‧離子傳導層 10‧‧‧Ion Conductive Layer

20‧‧‧第一電極層 20‧‧‧First electrode layer

21‧‧‧第二電極層 21‧‧‧Second electrode layer

22‧‧‧第一導電層 22‧‧‧First conductive layer

23‧‧‧第二導電層 23‧‧‧Second conductive layer

24‧‧‧第一基板 24‧‧‧First substrate

25‧‧‧第二基板 25‧‧‧second substrate

26‧‧‧匯流排條 26‧‧‧ Bus bar

27‧‧‧匯流排條 27‧‧‧ Bus bar

28‧‧‧電致變色堆疊 28‧‧‧Electrochromic stacking

50‧‧‧等高線圖 50‧‧‧ contour map

52‧‧‧等電阻曲線 52‧‧‧etc. resistance curve

54‧‧‧電阻梯度曲線 54‧‧‧resistance gradient curve

54A‧‧‧梯度 54A‧‧‧ gradient

54B‧‧‧梯度 54B‧‧‧ Gradient

55‧‧‧導電層之西側 55‧‧‧West side of the conductive layer

56‧‧‧導電層之東側 56‧‧‧ east side of the conductive layer

57‧‧‧導電層之西南角 57‧‧‧Southwest corner of the conductive layer

58‧‧‧導電層之東北角 58‧‧‧Northeast corner of the conductive layer

57‧‧‧導電層之底側 57‧‧‧Bottom side of the conductive layer

58‧‧‧導電層之頂側 58‧‧‧Top side of the conductive layer

59‧‧‧導電層之形心 59‧‧‧The centroid of the conductive layer

60‧‧‧導電層之西側 60‧‧‧West side of the conductive layer

61‧‧‧導電層之東側 61‧‧‧ east side of the conductive layer

62‧‧‧導電層之位置 62‧‧‧Location of the conductive layer

63‧‧‧導電層之位置 63‧‧‧Location of the conductive layer

64‧‧‧導電層之位置 64‧‧‧Location of the conductive layer

65‧‧‧導電層之位置 65‧‧‧Location of the conductive layer

101‧‧‧電致變色裝置 101‧‧‧Electrochromic device

120‧‧‧電致變色電極層 120‧‧‧Electrochromic electrode layer

122‧‧‧第一導電層 122‧‧‧First conductive layer

123‧‧‧第二導電層 123‧‧‧Second conductive layer

124‧‧‧外基板 124‧‧‧External substrate

125‧‧‧外基板 125‧‧‧External substrate

126‧‧‧匯流排條 126‧‧‧ bus bar

127‧‧‧匯流排條 127‧‧‧ bus bar

128‧‧‧電致變色堆疊 128‧‧‧Electrochromic stacking

222A-222R‧‧‧TCO膜 222A-222R‧‧‧TCO film

226‧‧‧匯流排條 226‧‧‧ bus bar

227‧‧‧匯流排條 227‧‧‧ bus bar

301‧‧‧電致變色裝置 301‧‧‧Electrochromic device

310‧‧‧離子傳導層 310‧‧‧Ion Conductive Layer

320‧‧‧電致變色電極層 320‧‧‧Electrochromic electrode layer

322‧‧‧第一導電層 322‧‧‧First conductive layer

323‧‧‧第二導電層 323‧‧‧Second conductive layer

324‧‧‧外基板 324‧‧‧External substrate

325‧‧‧外基板 325‧‧‧External substrate

326‧‧‧匯流排條 326‧‧‧ bus bar

327‧‧‧匯流排條 327‧‧‧ bus bar

328‧‧‧電致變色堆疊 328‧‧‧Electrochromic stacking

X-Y‧‧‧線段 X-Y‧‧‧ line segment

X₁-Y₁‧‧‧線段 X ₁ -Y ₁ ‧‧‧ segments

A‧‧‧凸多邊形 A‧‧‧ convex polygon

A₁‧‧‧凸多邊形 A ₁ ‧‧‧ convex polygon

B‧‧‧凸多邊形 B‧‧‧ convex polygon

B₁‧‧‧凸多邊形 B ₁ ‧‧‧ convex polygon

圖1係本發明之多層電致變色裝置之示意截面。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross section of a multilayer electrochromic device of the present invention.

圖2A至圖2E係第一導電層及/或第二導電層中以在第一導電層及/或第二導電層內之(二維)位置為函數之薄層電阻R_s之一系列等高線圖，其等繪示由針對具有正方形及圓形周邊之裝置之匯流排條之各種替代配置產生之等電阻線(有時亦稱作等高線)及電阻梯度線(垂直於等電阻線之線)。 2A to 2E are a series of contour lines of the sheet resistance R _s in the first conductive layer and/or the second conductive layer as a function of the (two-dimensional) position in the first conductive layer and/or the second conductive layer. Figure, which shows equal resistance lines (sometimes referred to as contour lines) and resistance gradient lines (perpendicular to the line of equal resistance lines) produced by various alternative configurations for bus bars having a square and circular perimeter. .

圖3係在基板上具有梯度厚度之導電層之示意截面。 Figure 3 is a schematic cross section of a conductive layer having a gradient thickness on a substrate.

圖4係本發明之多層電致變色裝置之替代實施例之示意截面。 4 is a schematic cross section of an alternate embodiment of the multilayer electrochromic device of the present invention.

圖5係如實例1所述之用於模擬電致變色裝置之動態表現之1-D集總元件電路模型圖。 Figure 5 is a circuit diagram of a 1-D lumped element circuit for simulating the dynamic performance of an electrochromic device as described in Example 1.

圖6係如實例1所述之施加至匯流排之電壓波形之曲線圖。 Figure 6 is a graph of the voltage waveform applied to the busbar as described in Example 1.

圖7係如實例1所述之流動至裝置中之電流對時間之曲線圖。 Figure 7 is a graph of current versus time as flowed into the apparatus as described in Example 1.

圖8係如實例1所述之在三個位置上(邊緣附近、中心附近及此二者之間)之跨電致變色膜之電壓之曲線圖。 Figure 8 is a graph of the voltage across an electrochromic film at three locations (near the edge, near the center, and between) as described in Example 1.

圖9係如實例1所述之施加至匯流排之電壓波形之曲線圖。 Figure 9 is a graph of the voltage waveform applied to the busbar as described in Example 1.

圖10係如實例1所述之流動至裝置中之電流對時間之曲線圖。 Figure 10 is a graph of current versus time flowing into the apparatus as described in Example 1.

圖11係如實例1所述之在三個位置上(邊緣附近、中心附近及此二者之間)之跨電致變色膜之電壓之曲線圖。 Figure 11 is a graph of the voltage across an electrochromic film at three locations (near the edge, near the center, and between the two) as described in Example 1.

圖12係如實例2所述之用於模擬電致變色裝置之動態表現之1-D集總元件電路模型圖。 Figure 12 is a circuit diagram of a 1-D lumped element circuit for simulating the dynamic performance of an electrochromic device as described in Example 2.

圖13係如實例1所述之施加至匯流排條之電壓波形之曲線圖。 Figure 13 is a graph of the voltage waveform applied to the bus bar as described in Example 1.

圖14係如實例1所述之流動至裝置中之電流對時間之曲線圖。 Figure 14 is a graph of current versus time flowing into the apparatus as described in Example 1.

圖15係如實例1所述之在三個位置上(邊緣附近、中心附近及此二者之間)之跨電致變色膜之電壓之曲線圖。 Figure 15 is a graph of the voltage across an electrochromic film at three locations (near the edge, near the center, and between the two) as described in Example 1.

圖16係如實例3所述之用於模擬電致變色裝置之動態表現之1-D集總元件電路模型圖。 Figure 16 is a circuit diagram of a 1-D lumped element circuit for simulating the dynamic performance of an electrochromic device as described in Example 3.

圖17係如實例1所述之施加至匯流排條之電壓波形之曲線圖。 Figure 17 is a graph of the voltage waveform applied to the bus bar as described in Example 1.

圖18係如實例1所述之流動至裝置中之電流對時間之曲線圖。 Figure 18 is a graph of current versus time flowing into the apparatus as described in Example 1.

圖19係如實例1所述之在三個位置上(邊緣附近、中心附近及此二者之間)之跨電致變色膜之電壓之曲線圖。 Figure 19 is a graph of the voltage across the electrochromic film at three locations (near the edge, near the center, and between the two) as described in Example 1.

圖20係本發明之多層電致變色裝置之替代實施例之示意截面。 Figure 20 is a schematic cross section of an alternative embodiment of the multilayer electrochromic device of the present invention.

圖21係圖1之多層裝置之分解圖。 Figure 21 is an exploded view of the multilayer device of Figure 1.

在圖中，相應參考符號表示相應零件。此外，不同圖 中之層之相對厚度不代表真實尺寸關係。舉例而言，基板通常比其他層厚得多。圖僅為闡釋連接原理之目的而繪製，不給定任何尺寸資訊。 In the figures, corresponding reference symbols indicate corresponding parts. In addition, different maps The relative thickness of the layers in the middle does not represent the true dimensional relationship. For example, the substrate is typically much thicker than the other layers. The diagram is drawn for the purpose of explaining the connection principle and does not give any size information.

1‧‧‧多層電致變色裝置 1‧‧‧Multilayer electrochromic device

10‧‧‧離子傳導層 10‧‧‧Ion Conductive Layer

20‧‧‧第一電極層 20‧‧‧First electrode layer

21‧‧‧第二電極層 21‧‧‧Second electrode layer

22‧‧‧第一導電層 22‧‧‧First conductive layer

23‧‧‧第二導電層 23‧‧‧Second conductive layer

24‧‧‧第一基板 24‧‧‧First substrate

25‧‧‧第二基板 25‧‧‧second substrate

26‧‧‧匯流排條 26‧‧‧ Bus bar

27‧‧‧匯流排條 27‧‧‧ Bus bar

28‧‧‧電致變色堆疊 28‧‧‧Electrochromic stacking

Claims (32)

一種電致變色裝置，其包括一第一基板、一第一導電層、一第一電極層、一第二導電層及一第二基板，該第一及第二基板為玻璃或塑膠，該第一及第二導電層各具有針對以在該第一及第二導電層中之位置為函數而變化之分別穿過該第一及第二導電層之電流之流動之一薄層電阻R_s，其中在該第一導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約10，且在該第二導電層中最大薄層電阻之值R_max對最小薄層電阻之值R_min之比率為至少約10，該第一基板及該第一導電層透射對具有在紅外光、可見光或紫外光之範圍中至少一者之一波長之電磁輻射透明，其中(i)該第一導電層具有以在該第一導電層中之位置為函數而變化之一空間變化薄層電阻R_s，(ii)以在該第一導電層內之位置為函數之該薄層電阻R_s之一等高線圖含有一組等電阻線及與該等等電阻線垂直之一組電阻梯度線，及(iii)具有該等梯度線之一者之至少1cm之長度之一線段突出至該第二導電層上界定該第二導電層中之一互補線段，其中(a)該梯度線段上方之該第一導電層之該薄層電阻之斜度之平均值S¹ _avg為正值或負值，及(b)該互補線段上方之該第二導電層之該薄層電阻之斜度之平均值S² _avg為零或符號與S¹ _avg相反。 An electrochromic device comprising a first substrate, a first conductive layer, a first electrode layer, a second conductive layer and a second substrate, wherein the first and second substrates are glass or plastic, the first The first and second conductive layers each have a sheet resistance R _{s for a} flow of current through the first and second conductive layers as a function of position in the first and second conductive layers, Wherein the ratio of the maximum sheet resistance value R _max to the minimum sheet resistance value R _min in the first conductive layer is at least about 10, and the maximum sheet resistance value R _max in the second conductive layer is the smallest The ratio of the value of the sheet resistance R _min is at least about 10. The first substrate and the first conductive layer are transparent to electromagnetic radiation having a wavelength of at least one of infrared light, visible light or ultraviolet light, wherein (i) the first conductive layer has a spatially varying sheet resistance R _s as a function of position in the first conductive layer, (ii) as a function of position within the first conductive layer one line high sheet resistance R _s groups, etc. FIG comprising a resistance wire and the like One of the resistive gradient lines of the resistance line vertical, and (iii) one of the lengths of at least 1 cm of one of the gradient lines protruding to the second conductive layer defining a complementary line segment of the second conductive layer, Wherein (a) the average value S ¹ _avg of the slope resistance of the first conductive layer above the gradient line segment is positive or negative, and (b) the second conductive layer above the complementary line segment The average value of the slope of the sheet resistance S ² _avg is zero or the sign is opposite to S ¹ _avg . 如請求項1之電致變色裝置，其中(i)由一第一凸多 邊形限定之該第一導電層之一第一區域中之平均薄層電阻對由一第二凸多邊形限定之該第一導電層之一第二區域中之平均薄層電阻之比率為至少5，該第一導電層之該第一及第二區域各包括該第一導電層之表面積之至少25%及(ii)由一第二凸多邊形限定之該第二導電層之一第一區域中之平均薄層電阻對由一第二凸多邊形限定之該第二導電層之一第二區域中之平均薄層電阻之比率為至少5，該第二導電層之該第一及第二區域各包括該第二導電層之表面積之至少25%。 The electrochromic device of claim 1, wherein (i) is a first convex The ratio of the average sheet resistance in the first region of one of the first conductive layers defined by the edge to the average sheet resistance in the second region of the first conductive layer defined by a second convex polygon is at least 5 The first and second regions of the first conductive layer each comprise at least 25% of the surface area of the first conductive layer and (ii) the first region of the second conductive layer defined by a second convex polygon The ratio of the average sheet resistance to the average sheet resistance in the second region of the second conductive layer defined by a second convex polygon is at least 5, and the first and second regions of the second conductive layer are Included at least 25% of the surface area of the second electrically conductive layer. 如請求項1之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、一離子傳導層、一第二電極層、該第二導電層及該第二基板，且其中該第一導電層包含一電致變色材料，且該第二電極層包含一電致變色材料。 The electrochromic device of claim 1, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, an ion conductive layer, a second electrode layer, The second conductive layer and the second substrate, and wherein the first conductive layer comprises an electrochromic material, and the second electrode layer comprises an electrochromic material. 如請求項1之電致變色裝置，其中該第一導電層具有以在該第一導電層中之位置為函數而變化之一空間變化薄層電阻R_s，以在該第一導電層內之位置為函數之該薄層電阻R_s之一等高線圖含有一組等電阻線及垂直於該等等電阻線之一組電阻梯度線，且在該組中沿著一梯度線之該薄層電阻增大、減小、增大直至其達到最大值且隨後減小或減小直至其達到最小值且隨後增大。 The electrochromic device of claim 1, wherein the first conductive layer has a spatially varying sheet resistance R _s as a function of position in the first conductive layer to be within the first conductive layer One of the sheet resistances R _s of the position function has a set of equal resistance lines and a set of resistance gradient lines perpendicular to the resistance lines, and the sheet resistance along a gradient line in the group Increase, decrease, increase until it reaches a maximum and then decrease or decrease until it reaches a minimum and then increases. 如請求項4之電致變色裝置，其中該第二導電層具有以在該第二導電層中之位置為函數而變化之一空間變化 薄層電阻R_s，以在該第二導電層內之位置為函數之該薄層電阻R_s之一等高線圖含有一組等電阻線及垂直於該等等電阻線之一組電阻梯度線，且在該組中沿著一梯度線之該薄層電阻增大、減小、增大直至其達到最大值且隨後減小或減小直至其達到最小值且隨後增大。 The electrochromic device of claim 4, wherein the second conductive layer has a spatially varying sheet resistance R _s as a function of position in the second conductive layer to be within the second conductive layer One of the sheet resistances R _s of the position function has a set of equal resistance lines and a set of resistance gradient lines perpendicular to the resistance lines, and the sheet resistance along a gradient line in the group Increase, decrease, increase until it reaches a maximum and then decrease or decrease until it reaches a minimum and then increases. 如請求項5之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、一離子傳導層、一第二電極層、該第二導電層及該第二基板，且其中該第一及第二電極層包含一電致變色材料。 The electrochromic device of claim 5, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, an ion conductive layer, a second electrode layer, which are disposed in a continuous manner, The second conductive layer and the second substrate, and wherein the first and second electrode layers comprise an electrochromic material. 如請求項5之電致變色裝置，其中由一第一凸多邊形限定之該第一導電層之一第一區域中之平均薄層電阻對由一第二凸多邊形限定之該第一導電層之一第二區域中之平均薄層電阻之比率為至少5，且分別由該第一凸多邊形及該第二凸多邊形限定之該第一區域及該第二區域各包括該第一導電層之表面積之至少25%。 The electrochromic device of claim 5, wherein the average sheet resistance in the first region of one of the first conductive layers defined by a first convex polygon is the first conductive layer defined by a second convex polygon The ratio of the average sheet resistance in a second region is at least 5, and the first region and the second region respectively defined by the first convex polygon and the second convex polygon respectively include a surface area of the first conductive layer At least 25%. 如請求項5之電致變色裝置，其中該第一導電層之一第一區域中之平均薄層電阻R¹ _avg對該第一導電層之一第二區域中之平均薄層電阻R² _avg之比率為至少1.25，該第一導電層之該第二區域中之平均薄層電阻R² _avg對該第一導電層之一第三區域中之平均薄層電阻R³ _avg之比率為至少1.25，該第一導電層之該第三區域中之平均薄層電阻R³ _avg對該第一導電層之一第四區域中之平均 薄層電阻R⁴ _avg之比率為至少1.25，其中該第一區域與該第二區域鄰接，該第二區域與該第三區域鄰接，該第三區域與該第四區域鄰接，該等區域之各者由一凸多邊形限定且各包括該第一導電層之表面積之至少10%。 The electrochromic device of claim 5, wherein the average sheet resistance R ¹ _avg in the first region of the first conductive layer is an average sheet resistance R ² _avg in the second region of the first conductive layer The ratio is at least 1.25, and the ratio of the average sheet resistance R ² _avg in the second region of the first conductive layer to the average sheet resistance R ³ _avg in the third region of the first conductive layer is at least 1.25. The ratio of the average sheet resistance R ³ _avg in the third region of the first conductive layer to the average sheet resistance R ⁴ _avg in the fourth region of the first conductive layer is at least 1.25, wherein the first The region is adjacent to the second region, the second region is adjacent to the third region, and the third region is adjacent to the fourth region, each of the regions being defined by a convex polygon and each comprising the first conductive layer At least 10% of the surface area. 如請求項8之電致變色裝置，其中該第二導電層之一第一區域中之平均薄層電阻R¹ _avg對該第二導電層之一第二區域中之平均薄層電阻R² _avg之比率為至少1.25，該第二導電層之該第二區域中之平均薄層電阻R² _avg對該第二導電層之一第三區域中之平均薄層電阻R³ _avg之比率為至少1.25，該第二導電層之該第三區域中之平均薄層電阻R³ _avg對該第二導電層之一第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.25，其中該第一區域與該第二區域鄰接，該第二區域與該第三區域鄰接，該第三區域與該第四區域鄰接，該等區域之各者由一凸多邊形限定，且各包括該第二導電層之表面積之至少10%。 The electrochromic device of claim 8, wherein the average sheet resistance R ¹ _avg in the first region of the second conductive layer is the average sheet resistance R ² _avg in the second region of the second conductive layer the ratio is at least 1.25, the second region of the second conductive layer in the average sheet resistance R ² _avg third region of the second conductive layer of one of the average sheet resistance ratio R is at least ³ _avg 1.25 The ratio of the average sheet resistance R ³ _avg in the third region of the second conductive layer to the average sheet resistance R ⁴ _avg in the fourth region of the second conductive layer is at least 1.25, wherein the first The region is adjacent to the second region, the second region is adjacent to the third region, the third region is adjacent to the fourth region, each of the regions is defined by a convex polygon, and each includes the second conductive layer At least 10% of the surface area. 如請求項1之電致變色裝置，其中該第二基板及該第二導電層對具有在紅外光、可見光或紫外光之範圍中至少一者之一波長之電磁輻射透明。 The electrochromic device of claim 1, wherein the second substrate and the second conductive layer are transparent to electromagnetic radiation having a wavelength of at least one of infrared, visible or ultraviolet light. 如請求項10之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、一離子傳導層、一第二電極層、該第二導電層及該第二基板，且其中該第一及第二電極層包 含一電致變色材料。 The electrochromic device of claim 10, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, an ion conductive layer, a second electrode layer, configured in a continuous manner, The second conductive layer and the second substrate, and wherein the first and second electrode layers are packaged Contains an electrochromic material. 如請求項1之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、一離子傳導層、一第二電極層、該第二導電層及該第二基板。 The electrochromic device of claim 1, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, an ion conductive layer, a second electrode layer, The second conductive layer and the second substrate. 如請求項12之電致變色裝置，其中該第一電極層包括一電致變色材料。 The electrochromic device of claim 12, wherein the first electrode layer comprises an electrochromic material. 如請求項12之電致變色裝置，其中該第一及第二電極層包括一電致變色材料。 The electrochromic device of claim 12, wherein the first and second electrode layers comprise an electrochromic material. 如請求項1之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、該第二導電層及該第二基板。 The electrochromic device of claim 1, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, the second conductive layer, and the second substrate disposed in a continuous manner. 如請求項1之電致變色裝置，其中該電致變色裝置包括以連續方式配置之該第一基板、該第一導電層、該第一電極層、一離子傳導層、該第二導電層及該第二基板。 The electrochromic device of claim 1, wherein the electrochromic device comprises the first substrate, the first conductive layer, the first electrode layer, an ion conductive layer, the second conductive layer and The second substrate. 如請求項1之電致變色裝置，其中(a)該第一導電層包括一區域A₁及一區域B₁，其中區域A₁及區域B₁各包括該第一導電層之表面積之至少25%，各由一凸多邊形限定且互不相交，(b)區域A₁突出至該第二導電層上界定由該第二導電層中之一凸多邊形限定之包括該第二導電層之表面積之至少25%之一區域A，(c)區域B₁突出至該第二導電層上界定由該第二導電層中之一凸多邊形限定之包括該第二導電層之表面積之至少25%之一 區域B，(d)該第一導電層具有區域A₁中對應於R^A1 _avg之一平均薄層電阻及區域B₁中對應於R^B1 _avg之一平均薄層電阻，(e)該第二導電層具有區域A中對應於R^A _avg之一平均薄層電阻及區域B中對應於R^B _avg之一平均薄層電阻，(f)R^A1 _avg對R^B1 _avg之比率或R^B _avg對R^A _avg之比率為至少1.5，及(g)(R^A1 _avg/R^A _avg)對(R^B1 _avg/R^B _avg)之比率為至少1.5。 The electrochromic device of claim 1, wherein (a) the first conductive layer comprises a region A ₁ and a region B ₁ , wherein the regions A ₁ and B ₁ each comprise at least 25 of a surface area of the first conductive layer %, each polygon defined and mutually cross-linked by a convex, (b) to define the projection area a ₁ of the polygon defined by the second conductive layer comprises one of the surface area of the projection of the second conductive layer on the second conductive layer At least 25% of the area A, (c) the area B ₁ protruding to the second conductive layer defining at least 25% of the surface area of the second conductive layer defined by one of the second conductive layers including the second conductive layer Region B, (d) the first conductive layer has an average sheet resistance corresponding to one of R ^A1 _avg in region A ₁ and an average sheet resistance corresponding to one of R ^B1 _avg in region B ₁ , (e) the second The conductive layer has an average sheet resistance corresponding to one of R ^A _avg in region A and an average sheet resistance corresponding to one of R ^B _avg in region B, (f) a ratio of R ^A1 _avg to R ^B1 _avg or a ratio of R ^B _avg The ratio of R ^A _avg is at least 1.5, and the ratio of (g) (R ^A1 _avg /R ^A _avg ) to (R ^B1 _avg /R ^B _avg ) is at least 1.5. 如請求項17之電致變色裝置，其中該第一電極層包括一電致變色材料。 The electrochromic device of claim 17, wherein the first electrode layer comprises an electrochromic material. 如請求項17之電致變色裝置，其中該電致變色裝置進一步包括一第二電極層，且該第二電極層包括一電致變色材料。 The electrochromic device of claim 17, wherein the electrochromic device further comprises a second electrode layer, and the second electrode layer comprises an electrochromic material. 如請求項1之電致變色裝置，其中該第一導電層之組合物或厚度成梯度。 The electrochromic device of claim 1, wherein the composition or thickness of the first conductive layer is gradient. 如請求項1之電致變色裝置，其中該第一基板對具有在紅外光、可見光或紫外光之範圍中至少一者之一波長之電磁輻射透明。 The electrochromic device of claim 1, wherein the first substrate is transparent to electromagnetic radiation having a wavelength of at least one of infrared, visible or ultraviolet light. 如請求項1之電致變色裝置，其中該第一電極層包括一電致變色材料。 The electrochromic device of claim 1, wherein the first electrode layer comprises an electrochromic material. 如請求項1之電致變色裝置，其中該電致變色裝置進一步包括一第二電極層，且該第二電極層包括一電致變色材料。 The electrochromic device of claim 1, wherein the electrochromic device further comprises a second electrode layer, and the second electrode layer comprises an electrochromic material. 如請求項1之電致變色裝置，其進一步包括一離子傳導層，該第一電極層介於該離子傳導層與該第一導電層 之間，該離子傳導層係在25℃下具有至少10^-7西門子/cm之針對載體離子之離子導電性之一介電材料。 The electrochromic device of claim 1, further comprising an ion conducting layer interposed between the ion conducting layer and the first conductive layer, the ion conducting layer having at least 10 at 25 ° C ^-7 Siemens/cm is a dielectric material for ion conductivity of carrier ions. 如請求項24之電致變色裝置，其中該電致變色裝置進一步包括一第二電極層，且該第二電極層包括一電致變色材料。 The electrochromic device of claim 24, wherein the electrochromic device further comprises a second electrode layer, and the second electrode layer comprises an electrochromic material. 如請求項1之電致變色裝置，其中該第二基板對具有在紅外光、可見光或紫外光之範圍中至少一者之一波長之電磁輻射透明。 The electrochromic device of claim 1, wherein the second substrate is transparent to electromagnetic radiation having a wavelength of at least one of infrared, visible or ultraviolet light. 如請求項1之電致變色裝置，其中該第一基板具有面向該第一導電層之一內表面，該第一基板之該內表面之表面積為至少0.1m²。 The electrochromic device of claim 1, wherein the first substrate has an inner surface facing the first conductive layer, and the inner surface of the first substrate has a surface area of at least 0.1 m ² . 一種用於製備一多層裝置之製程，其包括形成包括介於一第一導電層及一第二導電層之間且與該第一導電層及第二導電層電接觸之一電致變色層之一多層之層結構，該第一導電層、第二導電層或其二者具有以在該第一導電層、第二導電層或其二者中之位置為函數而變化之分別針對穿過該第一導電層、該第二導電層或其二者之電流之流動之一空間變化薄層電阻R_s，其中由一第一凸多邊形限定之該第一導電層之一第一區域中之平均薄層電阻對由一第二凸多邊形限定之該第一導電層之一第二區域中之平均薄層電阻之比率為至少5，分別由該第一凸多邊形及該第二凸多邊形限定之該第一區域及該第二區域各包括該第一導電層之表面積之至少25%，其中(i)該第一導電層具有以在該第 一導電層中之位置為函數而變化之一空間變化薄層電阻R_s，(ii)以在該第一導電層內之位置為函數之該薄層電阻R_s之一等高線圖含有一組等電阻線及與該等等電阻線垂直之一組電阻梯度線，及(iii)具有該等梯度線之一者之至少1cm之長度之一線段突出至該第二導電層上界定該第二導電層中之一互補線段，其中(a)該梯度線段上方之該第一導電層之該薄層電阻之斜度之平均值S¹ _avg為正值或負值，及(b)該互補線段上方之該第二導電層之該薄層電阻之斜度之平均值S² _avg為零或符號與S¹ _avg相反。 A process for preparing a multilayer device, comprising forming an electrochromic layer comprising a first conductive layer and a second conductive layer and in electrical contact with the first conductive layer and the second conductive layer a multilayer structure in which the first conductive layer, the second conductive layer, or both have a change in position as a function of position in the first conductive layer, the second conductive layer, or both a spatially varying sheet resistance R _s across a flow of current of the first conductive layer, the second conductive layer, or both, wherein the first region of the first conductive layer is defined by a first convex polygon The ratio of the average sheet resistance to the average sheet resistance in the second region of the first conductive layer defined by a second convex polygon is at least 5, respectively defined by the first convex polygon and the second convex polygon The first region and the second region each comprise at least 25% of the surface area of the first conductive layer, wherein (i) the first conductive layer has a change as a function of position in the first conductive layer Spatially varying sheet resistance R _s , (ii) to the first conductive layer A contour map of the sheet resistance R _s having a position within the function is a set of equal resistance lines and a set of resistance gradient lines perpendicular to the resistance lines, and (iii) having one of the gradient lines One of the lengths of at least 1 cm protrudes onto the second conductive layer to define a complementary line segment of the second conductive layer, wherein (a) the slope of the sheet resistance of the first conductive layer above the gradient line segment The average value S ¹ _avg is a positive or negative value, and (b) the average value of the slope of the sheet resistance of the second conductive layer above the complementary line segment S ² _avg is zero or the sign is opposite to S ¹ _avg . 如請求項28之製程，其中該第一導電層之一第一區域中之平均薄層電阻R¹ _avg對該第一導電層之一第二區域中之平均薄層電阻R² _avg之比率為至少1.25，該第一導電層之該第二區域中之平均薄層電阻R² _avg對該第一導電層之一第三區域中之平均薄層電阻R³ _avg之比率為至少1.25，該第一導電層之該第三區域中之平均薄層電阻R³ _avg對該第一導電層之一第四區域中之平均薄層電阻R⁴ _avg之比率為至少1.25，其中該第一區域與該第二區域鄰接，該第二區域與該第三區域鄰接，該第三區域與該第四區域鄰接，該等區域之各者由一凸多邊形限定，且各包括該第一導電層之表面積之至少10%。 The process of claim 28, wherein the ratio of the average sheet resistance R ¹ _avg in the first region of the first conductive layer to the average sheet resistance R ² _avg in the second region of the first conductive layer is At least 1.25, a ratio of an average sheet resistance R ² _avg in the second region of the first conductive layer to an average sheet resistance R ³ _avg in a third region of the first conductive layer is at least 1.25, the first the third region of a conductive layer in the average sheet resistance R ³ _avg the fourth region of one of the first conductive layer, the average sheet resistance R ⁴ _avg ratio is at least 1.25, wherein the first region and the a second region adjacent to the third region, the third region being adjacent to the fourth region, each of the regions being defined by a convex polygon, and each comprising a surface area of the first conductive layer At least 10%. 如請求項28之製程，其中該第一導電層具有以在該第一導電層中之位置為函數而變化之一空間變化薄層電阻R_s，以在該第一導電層內之位置為函數之該薄層電 阻R_s之一等高線圖含有一組等電阻線及垂直於該等等電阻線之一組電阻梯度線，且在該組中沿著一梯度線之該薄層電阻增大、減小、增大直至其達到最大值且隨後減小或減小直至其達到最小值且隨後增大。 The process of claim 28, wherein the first conductive layer has a spatially varying sheet resistance R _s as a function of position in the first conductive layer, as a function of position within the first conductive layer One of the sheet resistances R _s has a set of equal resistance lines and a set of resistance gradient lines perpendicular to the resistance lines, and the sheet resistance increases along a gradient line in the group, It decreases, increases until it reaches a maximum and then decreases or decreases until it reaches a minimum and then increases. 如請求項28之製程，其中該製程包括將該第一導電層沈積在一玻璃或塑膠基板上，及以在該第一導電層中之位置為函數而變化該所沈積之層之薄層電阻。 The process of claim 28, wherein the process comprises depositing the first conductive layer on a glass or plastic substrate, and varying the sheet resistance of the deposited layer as a function of position in the first conductive layer . 如請求項28之製程，其中該製程包括沈積一第一導電層，其具有以在該第一導電層中之位置為函數而變化之組合物或厚度。 The process of claim 28, wherein the process comprises depositing a first conductive layer having a composition or thickness that varies as a function of position in the first conductive layer.