TWI525762B - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

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Publication number
TWI525762B
TWI525762B TW103101138A TW103101138A TWI525762B TW I525762 B TWI525762 B TW I525762B TW 103101138 A TW103101138 A TW 103101138A TW 103101138 A TW103101138 A TW 103101138A TW I525762 B TWI525762 B TW I525762B
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Taiwan
Prior art keywords
substrate
wafer
line
circuit device
manufacturing
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TW103101138A
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Chinese (zh)
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TW201528456A (en
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Huai Liang Chien
Chia Hung Yang
Lung Hui Chang
Feng Lin Chen
Chien Ya Hung
wei yi Guo
Huai Ken Tsai
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Taiwan Green Point Entpr Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

電路裝置及其製造方法 Circuit device and method of manufacturing same

本發明是有關於一種電路裝置及其製造方法，特別是指一種適用於採用塑膠基材的電路裝置及其製造方法。 The present invention relates to a circuit device and a method of fabricating the same, and more particularly to a circuit device suitable for use with a plastic substrate and a method of fabricating the same.

目前可在塑膠基材上裝配晶片與線路的技術有多種類型，例如美國US 7031170號專利、美國US 6671024號專利、美國US 6664645號專利等，各提出不同的技術，分述如下。 There are various types of techniques for assembling wafers and wires on plastic substrates, such as U.S. Patent No. 7,031,170, U.S. Patent No. 6,667,1024, U.S. Patent No. 6,664,645, et al.

在美國專利US 7031170方面，其提出的方案是將晶片設置於塑膠基座後，藉由打線技術(wire bonding)將晶片的接點透過導線連接於塑膠基座上的線路。然而，該專利的技術方案存在部分缺點。首先，打線技術必須分次在晶片的眾多接點與基板上的線路之間進行打線步驟，需耗費較長的製程時間。其次，根據不同材質的導線，晶片的接點與基板上的線路於線寬、排列間距方面都有最低規格要求，因此採用打線技術不利於晶片接點、基板線路的線寬縮減與分佈密集化。此外，導線通常是以懸空橫跨的 方式連接晶片接點與基板線路，因此不管在垂直方向或水平方向都會增加整體結構的分布空間，而不利於微型化、輕薄化的發展。而在製造成本方面，執行打線步驟的打線設備價格昂貴，不利於製造成本的降低。 In the case of US Pat. No. 7,031,170, the proposed solution is to connect the wafer contacts to the wires on the plastic base by wire bonding after the wafer is placed on the plastic base. However, the technical solution of this patent has some disadvantages. First, the wire bonding technique must perform the wire bonding step between the plurality of contacts of the wafer and the wires on the substrate in a divided manner, which requires a long process time. Secondly, according to the wires of different materials, the wiring contacts and the lines on the substrate have the minimum specification requirements in terms of line width and arrangement pitch. Therefore, the wire bonding technique is disadvantageous for the line width reduction and distributed density of the wafer contacts and the substrate lines. . In addition, the wires are usually traversed by a dangling The method connects the wafer contacts and the substrate lines, so that the distribution space of the overall structure is increased in the vertical direction or the horizontal direction, which is disadvantageous for the development of miniaturization and thinning. In terms of manufacturing cost, the wire bonding equipment that performs the wire bonding step is expensive, which is not conducive to the reduction of manufacturing cost.

在美國專利US 6671024方面，其提出的方案是藉由異方性導電膠(anisotropic conductive film/anisotropic conductive paste，簡稱為ACF/ACP)將晶片的接點以覆晶方式連接於基板上的線路。然而，在晶片的貼合過程中，必須對晶片施壓並施以高溫(例如高於140℃的溫度)處理，才能讓異方性導電膠發揮固接與垂直導電的效用，但此種高溫、施壓的製程條件較不適合應用在塑膠基材上，且異方性導電膠屬於較昂貴的製造原料，使用該種材料會導致製造成本的增加。 In the US patent 6671024, the proposed solution is to connect the contacts of the wafer to the circuit on the substrate by flip-chip bonding by anisotropic conductive film/anisotropic conductive paste (ACF/ACP). However, during the bonding process of the wafer, the wafer must be pressed and subjected to a high temperature (for example, a temperature higher than 140 ° C) to allow the anisotropic conductive adhesive to function as a fixed and vertical conductive, but such a high temperature The process conditions for pressing are less suitable for application on plastic substrates, and the anisotropic conductive adhesive is a relatively expensive manufacturing material, and the use of such materials leads to an increase in manufacturing costs.

在美國專利US 6664645方面，其提出的方案是在塑膠基板上設置金屬線路，並在覆晶式晶片的接點與金屬線路之間設置熱熔膠(hot melt adhesive)類型的膠體。隨後，對膠體施加超音波而使膠體熔融(反應溫度達150℃)，並於膠體熔融的同時對晶片施壓而使晶片的接點接觸基板的金屬線路，最終於膠體冷卻凝固後讓晶片接點與金屬線路保持在接觸導通狀態。然而，此技術亦存在部分問題。首先，該技術於製程過程中的高溫、施壓條件有可能會造成塑膠基板的變形或損傷。其次，於晶片接合後，晶片接點與金屬線路之間可能夾存少量膠體，不導電的膠體會影響晶片接點與金屬線路之間的導電性。此外，上述膠體的 黏著性較差，會影響晶片設置的穩固性。 In the case of U.S. Patent No. 6,664,645, the proposed solution is to provide a metal line on a plastic substrate and a hot melt adhesive type colloid between the contacts of the flip chip and the metal line. Subsequently, ultrasonic waves are applied to the colloid to melt the colloid (reaction temperature reaches 150 ° C), and the wafer is pressed while the colloid is melted, so that the contact of the wafer contacts the metal line of the substrate, and finally the wafer is cooled after the colloid is cooled and solidified. The point is kept in contact with the metal line. However, this technology also has some problems. First of all, the high temperature and pressure conditions of the technology during the process may cause deformation or damage of the plastic substrate. Secondly, after the wafer is bonded, a small amount of colloid may be trapped between the wafer contacts and the metal lines, and the non-conductive colloid may affect the conductivity between the wafer contacts and the metal lines. In addition, the above colloidal Poor adhesion can affect the stability of the wafer setup.

綜合上述，目前的技術分別存在不同的問題，亟需提出一種創新的技術。 In summary, the current technologies have different problems, and it is urgent to propose an innovative technology.

因此，本發明之目的，即在提供一種電路裝置及其製造方法，以解決現有技術的各種問題。 Accordingly, it is an object of the present invention to provide a circuit device and a method of fabricating the same that solve various problems of the prior art.

於是本發明電路裝置，包含一第一基板、一晶片及至少一條延伸線路。第一基板為絕緣而具有相反的一上表面及一下表面，其上表面凹陷形成一凹槽。晶片設置於第一基板的凹槽中，並包括至少一個顯露於凹槽外的接點。延伸線路連接於晶片的接點，且由晶片的接點至少延伸至第一基板的上表面。 Thus, the circuit device of the present invention comprises a first substrate, a wafer and at least one extension line. The first substrate is insulated and has an opposite upper surface and a lower surface, and the upper surface is recessed to form a recess. The wafer is disposed in the recess of the first substrate and includes at least one contact exposed outside the recess. The extension line is connected to the contacts of the wafer and extends from the contacts of the wafer to at least the upper surface of the first substrate.

在本發明的第二實施例中，第一基板還形成至少一個貫穿其上表面與下表面並對應延伸線路位置的通孔，通孔供另一部分延伸線路進一步設置及延伸其中。電路裝置還包含一第二基板，第二基板具有相反的一上表面及一下表面，並包括至少一設置於其上表面的導電線路。該第二基板供第一基板設置其上，使第一基板的下表面鄰接第二基板的上表面，並使延伸於通孔中的延伸線路連接於第二基板的該導電線路。 In a second embodiment of the present invention, the first substrate further defines at least one through hole extending through the upper surface and the lower surface thereof and corresponding to the extended line position, and the through hole is further disposed and extended in the other portion of the extension line. The circuit device further includes a second substrate having an opposite upper surface and a lower surface and including at least one conductive trace disposed on the upper surface thereof. The second substrate is disposed on the first substrate such that a lower surface of the first substrate abuts an upper surface of the second substrate, and an extension line extending in the through hole is connected to the conductive line of the second substrate.

本發明的製造方法，用於製造前述電路裝置，並包含一準備步驟、一覆蓋層設置步驟、一通道形成步驟、一延伸線路形成步驟及一移除步驟。準備步驟係準備一絕緣基板及一晶片。基板具有相反的一上表面及一下表 面，其上表面凹陷形成一凹槽。晶片設置於基板的凹槽中，且包括至少一個顯露於外的接點。覆蓋層設置步驟係覆蓋一覆蓋層於基板的上表面與晶片的表面。通道形成步驟係依一預定路徑覆蓋層由其表面凹陷形成至少一條由晶片的接點延伸至基板的上表面的線路通道。延伸線路形成步驟是在線路通道中形成一連接於晶片的接點，並由晶片的接點延伸至基板的上表面的延伸線路。移除步驟係從基板的上表面與晶片的表面移除覆蓋層。 The manufacturing method of the present invention is for manufacturing the foregoing circuit device, and comprises a preparation step, a cover layer setting step, a channel forming step, an extension line forming step, and a removing step. The preparation step is to prepare an insulating substrate and a wafer. The substrate has an opposite upper surface and a lower surface The surface of the surface is recessed to form a groove. The wafer is disposed in the recess of the substrate and includes at least one exposed contact. The cover layer setting step covers a cover layer on the upper surface of the substrate and the surface of the wafer. The channel forming step is formed by recessing a surface thereof to form at least one line channel extending from the junction of the wafer to the upper surface of the substrate by a predetermined path. The extension line forming step is to form a contact line connected to the wafer in the line path and extend from the junction of the wafer to the extension line of the upper surface of the substrate. The removing step removes the cover layer from the upper surface of the substrate and the surface of the wafer.

本發明提出的另一種製造方法，包含一準備步驟、一覆蓋層設置步驟、一通道形成步驟、一延伸線路形成步驟及一移除步驟。準備步驟係準備一第一基板、一第二基板及一晶片，第二基板具有相反的一上表面及一下表面，並包括至少一條設置於其上表面的導電線路。第一基板設置於第二基板上，並具有相反的一上表面及一下表面。第一基板的下表面緊鄰第二基板的上表面，而其上表面凹陷形成一凹槽，並形成至少一個貫穿至其下表面且位置對應導電線路的通孔。此外，第一基板的上表面還被一層第一覆蓋層覆蓋。晶片設置於第一基板的凹槽中，且包括至少一個顯露於外的接點。覆蓋層設置步驟係至少對晶片覆蓋一層第二覆蓋層。通道形成步驟係依一預定路徑使第一覆蓋層與第二覆蓋層相互配合，由兩者表面凹陷形成至少一條由晶片的接點延伸至第一基板的通孔的線路通道。延伸線路形成步驟是在線路通道與通孔中形成一延伸線路，該延伸線路係連接晶片的接點並連接第二基板的該導 電線路，且於接點與導電線路之間延伸。移除步驟是從第一基板的上表面與晶片的表面移除第一覆蓋層與第二覆蓋層。 Another manufacturing method proposed by the present invention comprises a preparation step, a cover layer setting step, a channel forming step, an extension line forming step, and a removing step. The preparation step is to prepare a first substrate, a second substrate and a wafer, the second substrate has opposite upper and lower surfaces, and includes at least one conductive line disposed on the upper surface thereof. The first substrate is disposed on the second substrate and has an opposite upper surface and a lower surface. The lower surface of the first substrate is adjacent to the upper surface of the second substrate, and the upper surface thereof is recessed to form a recess, and at least one through hole penetrating to the lower surface thereof and corresponding to the conductive line is formed. Furthermore, the upper surface of the first substrate is also covered by a first cover layer. The wafer is disposed in the recess of the first substrate and includes at least one exposed contact. The cover layer setting step is to cover at least one layer of the second cover layer to the wafer. The channel forming step cooperates with the first cover layer and the second cover layer according to a predetermined path, and the surface is recessed to form at least one line channel extending from the contact of the wafer to the through hole of the first substrate. The extension line forming step is to form an extension line in the line channel and the via hole, the extension line connecting the contacts of the wafer and connecting the guide of the second substrate Electrical circuit extending between the contact and the conductive line. The removing step is to remove the first cover layer and the second cover layer from the upper surface of the first substrate and the surface of the wafer.

本發明之功效在於：本發明的製造方法採用低溫製程，且無須執行施壓步驟，因此適用於採用各式基板(特別是塑膠基板)的電路裝置的製作。此外，藉由雷射蝕刻法在覆蓋層界定線路通道，可有效控制、縮減延伸線路的線寬與線徑，並適用於非平坦基板的加工。再者，將晶片收容於基板的凹槽中的設計，有助於電路裝置的微型化與薄型化。而不採用打線製程或藉由異方性導電膠進行晶片設置的製造方式，有助於生產成本的降低及增加晶片與基板的結合力。 The invention has the effect that the manufacturing method of the invention adopts a low-temperature process and does not need to perform a pressing step, and is therefore suitable for the fabrication of a circuit device using various substrates (especially plastic substrates). In addition, by defining the line channel in the cover layer by laser etching, the line width and wire diameter of the extended line can be effectively controlled and reduced, and is suitable for processing of a non-flat substrate. Furthermore, the design of accommodating the wafer in the recess of the substrate contributes to miniaturization and thinning of the circuit device. The manufacturing method of wafer setting without using a wire bonding process or by an anisotropic conductive paste contributes to a reduction in production cost and an increase in the bonding force between the wafer and the substrate.

100、100’‧‧‧電路裝置 100, 100’‧‧‧ circuit devices

101‧‧‧電子裝置 101‧‧‧Electronic devices

102‧‧‧前殼體 102‧‧‧ front housing

103‧‧‧後殼體 103‧‧‧ Rear housing

1‧‧‧第一基板 1‧‧‧First substrate

11‧‧‧上表面 11‧‧‧ upper surface

12‧‧‧下表面 12‧‧‧ Lower surface

13‧‧‧凹槽 13‧‧‧ Groove

14‧‧‧通孔 14‧‧‧through hole

2、2’‧‧‧晶片 2, 2'‧‧‧ wafer

21‧‧‧接點 21‧‧‧Contacts

3‧‧‧填充層 3‧‧‧fill layer

31、31’‧‧‧覆蓋層 31, 31’‧‧ Cover

32‧‧‧線路通道 32‧‧‧Line channel

4‧‧‧延伸線路 4‧‧‧Extended lines

5‧‧‧導光結構 5‧‧‧Light guiding structure

51‧‧‧反射層 51‧‧‧reflective layer

52‧‧‧導光體 52‧‧‧Light guide

6‧‧‧第二基板 6‧‧‧second substrate

61‧‧‧上表面 61‧‧‧ upper surface

62‧‧‧下表面 62‧‧‧ lower surface

63‧‧‧導電線路 63‧‧‧Electrical circuit

7‧‧‧黏著層 7‧‧‧Adhesive layer

8‧‧‧噴嘴 8‧‧‧ nozzle

S01~S17‧‧‧流程步驟 S01~S17‧‧‧ Process steps

本發明之其他的特徵及功效，將於參照圖式的較佳實施例詳細說明中清楚地呈現，其中：圖1是一立體分解圖，說明本發明電路裝置應用於一行動電話的實施態樣；圖2是沿圖1的II-II方向所呈現的剖面圖，說明本發明電路裝置的第一較佳實施例；圖3是一流程圖，說明第一較佳實施例的電路裝置的製造方法；圖4至圖7是側視圖，分別說明該第一較佳實施例的電路裝置的製造過程態樣；圖8是一側視圖，說明該第一較佳實施例的電路裝置的 變化實施態樣；圖9是一側視圖，說明該第一較佳實施例的電路裝置的另一應用態樣；圖10是一上視圖，說明本發明電路裝置的第二較佳實施例；圖11是沿圖10的XI-XI方向所呈現的剖面圖；圖12是一流程圖，說明第二較佳實施例的電路裝置的製造方法；圖13至圖18是側視圖，分別說明該第二較佳實施例的電路裝置的製造過程態樣。 Other features and advantages of the present invention will be apparent from the detailed description of the preferred embodiments of the invention, wherein: FIG. 1 is a perspective exploded view showing an embodiment of the circuit device of the present invention applied to a mobile phone. Figure 2 is a cross-sectional view taken along the line II-II of Figure 1, illustrating a first preferred embodiment of the circuit device of the present invention; and Figure 3 is a flow chart illustrating the fabrication of the circuit device of the first preferred embodiment 4 to 7 are side views respectively illustrating a manufacturing process of the circuit device of the first preferred embodiment; and FIG. 8 is a side view showing the circuit device of the first preferred embodiment FIG. 9 is a side elevational view showing another application of the circuit device of the first preferred embodiment; FIG. 10 is a top view showing a second preferred embodiment of the circuit device of the present invention; Figure 11 is a cross-sectional view taken along line XI-XI of Figure 10; Figure 12 is a flow chart illustrating a method of manufacturing the circuit device of the second preferred embodiment; and Figures 13 through 18 are side views respectively illustrating The manufacturing process aspect of the circuit device of the second preferred embodiment.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之兩個較佳實施例的詳細說明中，將可清楚的呈現。 The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

第一實施例First embodiment

參閱圖1與圖2，為本發明電路裝置100的第一較佳實施例。電路裝置100可運用於各式電子裝置，此處應用的電子裝置101是以行動電話為例，其包含一前殼體102及一後殼體103，前殼體102與後殼體103係採用塑膠材質，並供電路裝置100設置其上。 Referring to Figures 1 and 2, a first preferred embodiment of the circuit device 100 of the present invention is shown. The circuit device 100 can be applied to various electronic devices. The electronic device 101 used herein is a mobile phone, which includes a front case 102 and a rear case 103. The front case 102 and the rear case 103 are used. The plastic material is provided on the circuit device 100.

具體來說，本實施例的電路裝置100包含一第一基板1、一晶片2、一填充層3及至少一條(此處為多條) 延伸線路4。 Specifically, the circuit device 100 of the embodiment includes a first substrate 1, a wafer 2, a filling layer 3, and at least one strip (here, a plurality of strips) Extend line 4.

第一基板1為前述前殼體102或後殼體103的一部分，其可為塑膠或其他絕緣材質，且具有相反的一上表面11及一下表面12。第一基板1的上表面11凹陷形成一凹槽13(如圖4)，凹槽13可供晶片2設置其中。 The first substrate 1 is a part of the front case 102 or the rear case 103, which may be plastic or other insulating material, and has an opposite upper surface 11 and a lower surface 12. The upper surface 11 of the first substrate 1 is recessed to form a recess 13 (Fig. 4), and the recess 13 is provided for the wafer 2 to be disposed therein.

晶片2設置於第一基板1的凹槽13中，其可為積體電路晶片、發光二極體晶片等類型的晶片，並包括至少一個(此處為多個)接點21。接點21於晶片2設置於凹槽13後係顯露於凹槽13外，以供延伸線路4形成電性連接。 The wafer 2 is disposed in the recess 13 of the first substrate 1, which may be a wafer of a type such as an integrated circuit wafer, a light emitting diode wafer, or the like, and includes at least one (herein a plurality of) contacts 21. The contact 21 is exposed to the outside of the recess 13 after the wafer 2 is disposed on the recess 13 for electrically connecting the extension line 4.

填充層3設置於第一基板1的凹槽13中並圍繞晶片2，其由絕緣材質製作，例如聚胺酯甲酸基(Polyurethane)或丙烯酸樹脂，可作為延伸線路4跨越凹槽13的支撐結構。 The filling layer 3 is disposed in the recess 13 of the first substrate 1 and surrounds the wafer 2, which is made of an insulating material, such as polyurethane or acrylic resin, and can serve as a support structure for the extension line 4 to span the groove 13.

延伸線路4連接於晶片2的接點21，且由各接點經由填充層3的表面延伸至第一基板1的上表面11，可供電子裝置101內部的各式電子元件(未圖式)藉由延伸線路4而與晶片2形成電連接。 The extension line 4 is connected to the contact 21 of the wafer 2, and each contact extends to the upper surface 11 of the first substrate 1 via the surface of the filling layer 3, and various electronic components (not shown) inside the electronic device 101 are provided. An electrical connection is made to the wafer 2 by extending the line 4.

其中，本實施例將晶片2設置於第一基板1的凹槽13中的設計有助於減少電路裝置100的整體厚度。此外，上述第一基板1的上表面11、填充層3顯露於凹槽13外的表面以及晶片2顯露於凹槽13外的表面係大致齊平，讓延伸線路4可穩固地設置其上，避免不平整表面導致延伸線路4發生斷裂、斷路的問題。 The design of the wafer 2 disposed in the recess 13 of the first substrate 1 in the present embodiment helps to reduce the overall thickness of the circuit device 100. In addition, the upper surface 11 of the first substrate 1 and the surface of the filling layer 3 exposed on the outside of the groove 13 and the surface of the wafer 2 exposed outside the groove 13 are substantially flush, so that the extension line 4 can be stably disposed thereon. The problem that the uneven surface causes the breakage and disconnection of the extension line 4 is avoided.

參閱圖3的流程圖及相關圖式，以下說明電路裝置100的具體製造方法。 Referring to the flowchart of FIG. 3 and related drawings, a specific manufacturing method of the circuit device 100 will be described below.

步驟S01、S02：參閱圖3、圖4，此等為準備步驟。於步驟S01中，需準備一第一基板1以及一晶片2，第一基板1需預先製備面積、深度對應於晶片2的凹槽13。隨後，於步驟S02可將晶片2設置於第一基板1的凹槽13中，並使接點21顯露於凹槽13外，以供後續製程進行。上述過程中，晶片2可透過散熱黏膠黏著於凹槽13中，但不以此方式為限。 Steps S01, S02: Referring to FIG. 3 and FIG. 4, these are preparation steps. In step S01, a first substrate 1 and a wafer 2 are prepared. The first substrate 1 needs to be prepared in advance with a groove 13 corresponding to the wafer 2 in area and depth. Subsequently, in step S02, the wafer 2 can be placed in the recess 13 of the first substrate 1, and the contact 21 can be exposed outside the recess 13 for subsequent processing. In the above process, the wafer 2 can be adhered to the groove 13 through the heat-dissipating adhesive, but is not limited thereto.

步驟S03：參閱圖3、圖5，此為覆蓋層31設置步驟。覆蓋層31係採用可從第一基板1與晶片2的表面分離的材料，本實施例係採用行動電話的機殼漆。本步驟係採用噴漆(spray painting)的方式覆蓋覆蓋層31於第一基板1的上表面11與晶片2的表面，覆蓋層31填充於凹槽13的部分最終會形成前述的填充層3。而在不同的實施態樣中，覆蓋層31不限於要使用機殼漆，且其形成方式也不限於要使用噴漆技術。 Step S03: Referring to FIG. 3 and FIG. 5, this is a step of setting the cover layer 31. The cover layer 31 is made of a material that can be separated from the surface of the wafer 2 from the first substrate 1. This embodiment employs a casing paint for a mobile phone. In this step, the cover layer 31 is covered on the upper surface 11 of the first substrate 1 and the surface of the wafer 2 by spray painting, and the portion of the cover layer 31 filled in the recess 13 eventually forms the aforementioned filling layer 3. While in various embodiments, the cover layer 31 is not limited to use a chassis paint, and the manner in which it is formed is not limited to the use of painting techniques.

步驟S04：參閱圖3、圖6，此為通道形成步驟。本實施例中，此步驟是要依一預定路徑對覆蓋層31施以雷射蝕刻，使覆蓋層31由其頂面凹陷形成多條分別由晶片2的接點21各自延伸至上表面11之不同區域的線路通道32，該等中空的線路通道32可供後續製作延伸線路4。於其他實施例中，亦可透過例如機械、化學蝕刻或其他將覆蓋層31部分去除方式於覆蓋層31形成線路通道32。 Step S04: Referring to FIG. 3 and FIG. 6, this is a channel forming step. In this embodiment, the step is to apply a laser etching to the cover layer 31 according to a predetermined path, so that the cover layer 31 is recessed from the top surface thereof to form a plurality of different extensions from the contacts 21 of the wafer 2 to the upper surface 11, respectively. The line channels 32 of the area, which are available for subsequent fabrication of the extension lines 4. In other embodiments, the line channel 32 may also be formed on the cover layer 31 by, for example, mechanical, chemical etching, or other partial removal of the cover layer 31.

步驟S05：參閱圖3、圖7，此為延伸線路4形成步驟。此步驟是藉由噴嘴8在覆蓋層31的線路通道32中灌注導電膠體(例如導電銀漿或銅漿)，且隨後對導電膠體施以固化處理(例如照光固化或者以低於120℃的溫度加熱固化)，而使延伸線路4中的導電膠體固化形成從晶片2的接點21向外延伸的延伸線路4。 Step S05: Referring to FIG. 3 and FIG. 7, this is a step of forming the extension line 4. This step is to inject a conductive colloid (such as conductive silver paste or copper paste) into the line channel 32 of the cover layer 31 by the nozzle 8, and then apply a curing treatment to the conductive paste (for example, photocuring or a temperature lower than 120 ° C). The heat-curing is cured to form the conductive paste in the extension line 4 to form an extension line 4 extending outward from the contact 21 of the wafer 2.

步驟S06：參閱圖3、圖8，此為移除步驟。本步驟是要從第一基板1的上表面11與晶片2的表面移除覆蓋層31，由於本實施例的覆蓋層31是採用機殼漆，其固化後可直接被剝離。但如果覆蓋層31採用不同的材質製作，其分離步驟亦可對應調整。 Step S06: Referring to FIG. 3 and FIG. 8, this is a removal step. This step is to remove the cover layer 31 from the upper surface 11 of the first substrate 1 and the surface of the wafer 2. Since the cover layer 31 of the present embodiment is made of a casing paint, it can be directly peeled off after curing. However, if the cover layer 31 is made of a different material, the separation step can be adjusted accordingly.

綜合上述內容，由於本製造方法不需要對電路裝置100進行施壓處理，且步驟S05的延伸線路4形成步驟是由照光固化或低溫固化進行，此等製程設計可避免高溫、施壓製程對第一基板1產生損傷，適用於採用塑膠材質之電路裝置100的製作。此外，藉由對雷射束的束徑調整，可將線路通道32、延伸線路4的寬度與間距控制在較小範圍內(例如200微米以下)，因而有助於線寬、線距的縮減。再者，本實施例將晶片2設置於凹槽13中，使得晶片2大部分體積縮藏於第一基板1中，此設計有助於電路裝置100的微型化與輕薄化發展。而另一方面，由於本實施例對覆蓋層31的圖案化步驟(即形成線路通道32的步驟)是藉由雷射蝕刻所得，相較於一般半導體技術的黃光微影製程僅適用於平坦表面基板的限制，藉由雷射蝕刻進行圖案化製 程可應用於撓曲或非平坦表面的基板。例如，本實施例的第一基板1是電子裝置101的後殼體103的一部分，該後殼體103的周緣係相較於其底面突起，因此雷射蝕刻製程較適合用於對後殼體103進行加工，故本實施例採用雷射蝕刻製程具有較高的基板表面形貌相容性，尤其是適用於3D立體結構。 In view of the above, since the manufacturing method does not require the pressing process of the circuit device 100, and the step of forming the extension line 4 of the step S05 is performed by photo curing or low temperature curing, the process design can avoid high temperature and apply the pressing process. A substrate 1 is damaged and is suitable for the fabrication of a circuit device 100 made of a plastic material. In addition, by adjusting the beam diameter of the laser beam, the width and spacing of the line channel 32 and the extension line 4 can be controlled within a small range (for example, below 200 micrometers), thereby contributing to line width and line spacing reduction. . Furthermore, in this embodiment, the wafer 2 is placed in the recess 13 so that most of the volume of the wafer 2 is confined in the first substrate 1. This design contributes to the miniaturization and thinning of the circuit device 100. On the other hand, since the patterning step of the cap layer 31 in the present embodiment (that is, the step of forming the line channel 32) is obtained by laser etching, the yellow light lithography process compared to the general semiconductor technology is only applicable to the flat surface substrate. Limitation, patterning by laser etching The process can be applied to substrates that are curved or non-planar surfaces. For example, the first substrate 1 of the present embodiment is a part of the rear case 103 of the electronic device 101, and the periphery of the rear case 103 is protruded from the bottom surface thereof, so the laser etching process is more suitable for the rear case. The processing is performed on the 103, so the laser etching process of the embodiment has a high surface conformal compatibility of the substrate, and is particularly suitable for a 3D solid structure.

進一步來說，本發明還對以上述方法製作的電路裝置100進行其延伸線路4的信賴性測試(reliability test)。 Further, the present invention also performs a reliability test of the extension line 4 of the circuit device 100 fabricated by the above method.

參照圖2，關於延伸線路4的信賴性測試，本發明是在延伸線路4對應接點21的A處以及位於第一基板1上且遠離接點21的B處，分別以一探針接觸延伸線路4的表面，藉以量測A、B點之間的電阻值，並比較延伸線路4於特定測試環境中的電阻值、附著性變化趨勢。 Referring to FIG. 2, with respect to the reliability test of the extension line 4, the present invention extends at a point A of the corresponding line 21 of the extension line 4 and B located on the first substrate 1 and away from the contact 21, respectively, with a probe contact extension. The surface of the line 4 is used to measure the resistance between the points A and B, and compare the resistance value and the tendency of adhesion of the extension line 4 in a specific test environment.

本實施例以三種不同的方式對電路裝置100進行信賴性測試。第一種測試為高溫高濕環境測試(heat soak test)，具體來說是將電路裝置100放置於溫度85℃、相對濕度85%的測試環境中，測試延伸線路4的A、B點之間電阻值隨時間(例如200小時)的變化。第二種測試為冷熱循環測試(thermal cycling test)，具體來說是將電路裝置100放置在多次冷熱交替循環的環境中，測試延伸線路4的A、B點之間的電阻值隨時間的變化，該冷熱交替循環可以是例如為-40℃/+85℃的200次循環交替。第三種測試為高溫高濕環境下的百格測試(cross cut test with heat soak)，是在高 溫高濕環境下，將一特別設置的延伸線路4區分為多個不相連的小格，並逐格測試該格的延伸線路4於第一基板1上的附著性與電阻值變化。 This embodiment performs a reliability test on the circuit device 100 in three different ways. The first test is a heat soak test, specifically, placing the circuit device 100 in a test environment at a temperature of 85 ° C and a relative humidity of 85%, and testing between the A and B points of the extension line 4 The resistance value changes with time (for example, 200 hours). The second test is a thermal cycling test, specifically placing the circuit device 100 in an environment of multiple cycles of alternating hot and cold, testing the resistance value between points A and B of the extension line 4 over time. Alternatively, the alternating hot and cold cycle may be, for example, 200 cycles of -40 ° C / + 85 ° C alternating. The third test is a cross cut test with heat soak, which is high. In a warm and humid environment, a specially arranged extension line 4 is divided into a plurality of unconnected cells, and the adhesion and resistance value of the extension line 4 of the cell on the first substrate 1 are tested in a grid-by-cell manner.

根據測試結果，在第一種測試中，延伸線路4未放置於高溫高濕環境前的電阻值為8.1歐姆(Ω)，在高溫高濕環境中置放200小時後的電阻值為5.1歐姆(Ω)，此結果表示電路裝置100的延伸線路4在會加速產品劣化的高溫高濕測試環境中，仍能保持良好的導電特性。在第二種測試中，延伸線路4未放置於冷熱循環環境前的電阻值為4.1歐姆(Ω)，在冷熱循環200次以後的電阻值為4.8歐姆(Ω)，表示電路裝置100的延伸線路4在溫度多次急劇變化的環境中仍能保持良好的導電性。在第三種測試中，延伸線路4在高溫高濕環境前後的電阻值變化為從4.9歐姆(Ω)變為6.5歐姆(Ω)，而附著性測試中有95%以上的受測延伸線路4的小格通過附著性測試，表示延伸線路4在高溫高濕環境中仍能保持穩定的導電性及附著性。因此，綜合上述內容，本實施例提出的電路裝置100及製造方法於裝置性能及製程技術上均確實具備優良的特性。 According to the test results, in the first test, the resistance value of the extension line 4 before being placed in a high temperature and high humidity environment was 8.1 ohm (Ω), and the resistance value after placing it in a high temperature and high humidity environment for 200 hours was 5.1 ohm ( Ω), this result indicates that the extension line 4 of the circuit device 100 can maintain good electrical conductivity characteristics in a high-temperature and high-humidity test environment which accelerates product deterioration. In the second test, the resistance value of the extension line 4 before being placed in the cold and heat cycle environment is 4.1 ohms (Ω), and the resistance value after 200 times of the cold and heat cycle is 4.8 ohms (Ω), indicating the extension line of the circuit device 100. 4 It maintains good electrical conductivity in an environment where the temperature changes abruptly many times. In the third test, the resistance value of the extension line 4 before and after the high temperature and high humidity environment was changed from 4.9 ohms (Ω) to 6.5 ohms (Ω), and more than 95% of the tested extension lines 4 in the adhesion test. The small cell passes the adhesion test, indicating that the extension line 4 can maintain stable conductivity and adhesion in a high temperature and high humidity environment. Therefore, in summary of the above, the circuit device 100 and the manufacturing method of the present embodiment do have excellent characteristics in terms of device performance and process technology.

參閱圖8，本實施例中，電路裝置100還可以有不同的變化態樣，其製造方法略不同於前。 Referring to FIG. 8, in the embodiment, the circuit device 100 can also have different variations, and the manufacturing method is slightly different from the former.

具體來說，此處的電路裝置100的製造方式，於步驟S01、S02的準備步驟中，晶片2與第一基板1的製備是藉由嵌入成型(insert molding)技術，將晶片2預先放置於製作第一基板1的模穴(未圖示)中，而在基板藉由射出 成型方式製作後，即讓晶片2嵌合於基板中。因此，藉由此方式，不需再進行將晶片2設置於凹槽13中的程序，且晶片2會與第一基板1完全密合，因此於後續步驟S03製作覆蓋層31的過程中，不會形成填充層3。 Specifically, in the manufacturing method of the circuit device 100 herein, in the preparation steps of steps S01 and S02, the wafer 2 and the first substrate 1 are prepared by insert molding the wafer 2 in advance by an insert molding technique. Making a cavity (not shown) of the first substrate 1 and emitting it on the substrate After the molding method is produced, the wafer 2 is fitted into the substrate. Therefore, in this way, the process of disposing the wafer 2 in the recess 13 is not required, and the wafer 2 is completely adhered to the first substrate 1, so that in the process of fabricating the cap layer 31 in the subsequent step S03, A filling layer 3 is formed.

參閱圖9，為本實施例的另一應用態樣。此處，電子裝置的外殼上係設置兩組電路裝置100、100’，並同時設置一導光結構5。電路裝置100的晶片2係為一積體電路晶片，因此電路裝置100係主要用於資料運算處理與控制程序；而電路裝置100’的晶片2’係為一發光二極體，因此電路裝置100’是應用於發光照明功能。導光結構5包括一設於晶片2’鄰近表面的反射層51及一連接反射層51並穿設於第一基板1中的導光體52，據此晶片2’(發光二極體)發出的光線由反射層51反射後可由導光體52傳導於外。 Referring to Figure 9, another application aspect of the present embodiment is shown. Here, two sets of circuit devices 100, 100' are disposed on the outer casing of the electronic device, and a light guiding structure 5 is simultaneously disposed. The chip 2 of the circuit device 100 is an integrated circuit chip, so the circuit device 100 is mainly used for data processing and control programs; and the chip 2' of the circuit device 100' is a light emitting diode, so the circuit device 100 'is applied to the lighting function. The light guiding structure 5 includes a reflective layer 51 disposed on the adjacent surface of the wafer 2' and a light guiding body 52 connected to the reflective layer 51 and passing through the first substrate 1. According to the wafer 2' (light emitting diode) The light is reflected by the reflective layer 51 and can be conducted outside by the light guide 52.

第二實施例Second embodiment

參照圖10、圖11、圖13，為本發明電路裝置100的第二較佳實施例，本實施例的電路裝置100是以應用於射頻識別標籤(radio-frequency identification tag，簡稱為RFID tag)的實施態樣進行說明，但本實施例的電路裝置100的應用方式不以此為限。 Referring to FIG. 10, FIG. 11, and FIG. 13, a second preferred embodiment of the circuit device 100 of the present invention is applied to a radio-frequency identification tag (RFID tag). The implementation of the circuit device 100 of the present embodiment is not limited thereto.

具體來說，相較於前述第一實施例，本實施例中第一基板1的凹槽13係貫穿至第一基板1的下表面12，且第一基板1還形成至少一個(此處以兩個為例)貫穿其上表面11與下表面12並對應延伸線路4位置的通孔14，通 孔14可供延伸線路4進一步設置及延伸其中。此外，電路裝置100還包含一第二基板6及一黏著層7，第二基板6具有相反的一上表面61及一下表面62，並包括至少一設置於其上表面61的導電線路63。第二基板6供第一基板1設置其上，使第一基板1的下表面12緊鄰第二基板6的上表面61，並使延伸於通孔14中的延伸線路4連接於第二基板6的導電線路63。黏著層7設置於第一基板1與第二基板6之間，提供第一基板1與第二基板6的黏著效果。 Specifically, compared with the foregoing first embodiment, the groove 13 of the first substrate 1 is penetrated to the lower surface 12 of the first substrate 1 in the embodiment, and the first substrate 1 is further formed at least one (here two For example, a through hole 14 penetrating the upper surface 11 and the lower surface 12 and corresponding to the position of the extension line 4, Holes 14 are provided for extension line 4 to be further disposed and extended therein. In addition, the circuit device 100 further includes a second substrate 6 and an adhesive layer 7. The second substrate 6 has an opposite upper surface 61 and a lower surface 62, and includes at least one conductive line 63 disposed on the upper surface 61 thereof. The second substrate 6 is disposed on the first substrate 1 such that the lower surface 12 of the first substrate 1 is adjacent to the upper surface 61 of the second substrate 6, and the extension line 4 extending in the through hole 14 is connected to the second substrate 6. Conductive line 63. The adhesive layer 7 is disposed between the first substrate 1 and the second substrate 6 to provide an adhesion effect between the first substrate 1 and the second substrate 6.

根據上述實施例及其基於射頻識別標籤的應用，第一基板1、第二基板6可使用例如聚對苯二甲酸乙二酯(polyethylene terephthalate，簡稱為PET)的材質製作；而所述導電線路63則為天線線路，可根據晶片2的控制而發出無線射頻信號，以供外部裝置(未圖式)讀取相關資訊。 According to the above embodiment and its application based on the radio frequency identification tag, the first substrate 1 and the second substrate 6 can be made of a material such as polyethylene terephthalate (PET); and the conductive line 63 is an antenna line, which can emit a radio frequency signal according to the control of the chip 2, so that the external device (not shown) reads the related information.

以下參照圖12與相關圖式，說明第二實施例的電路裝置100的製作流程。 The fabrication flow of the circuit device 100 of the second embodiment will be described below with reference to FIG. 12 and related drawings.

步驟S11~S13：參閱圖12至圖15，此等為準備步驟。於步驟S11，需預先製備第一基板1、晶片2與第二基板6，其中第一基板1的上表面11被一層第一覆蓋層31覆蓋(如圖13)。如圖14，於步驟S12第一基板1藉由黏著層7黏合於第二基板6，使第一基板1的通孔14位置對應第二基板6的導電線路63，並使第一基板1的凹槽13位置對應黏著層7。如圖15，步驟S13是將晶片2設置於凹槽13中，由於本實施例中凹槽13係為一貫孔，因此晶片2設置於凹槽13中後係藉由黏著層7固著。 Steps S11 to S13: Referring to FIG. 12 to FIG. 15, these are preparation steps. In step S11, the first substrate 1, the wafer 2 and the second substrate 6 are prepared in advance, wherein the upper surface 11 of the first substrate 1 is covered by a first cover layer 31 (as shown in Fig. 13). As shown in FIG. 14 , the first substrate 1 is adhered to the second substrate 6 by the adhesive layer 7 in step S12 , so that the through hole 14 of the first substrate 1 is positioned corresponding to the conductive line 63 of the second substrate 6 and the first substrate 1 is The groove 13 is positioned corresponding to the adhesive layer 7. As shown in FIG. 15, step S13 is to place the wafer 2 in the recess 13. Since the recess 13 is a uniform hole in the embodiment, the wafer 2 is placed in the recess 13 and then fixed by the adhesive layer 7.

與前述實施例類似，於準備步驟中，晶片2亦可透過嵌入成型技術於第一基板1製作完成的同時即鑲嵌於第一基板1中，因此上述步驟S11~S13可調整為直接將第一基板1連同晶片2同時設置於第二基板6上。 Similar to the previous embodiment, in the preparation step, the wafer 2 can also be embedded in the first substrate 1 while being completed by the insert molding technology, so that the above steps S11 to S13 can be adjusted to directly The substrate 1 is placed on the second substrate 6 simultaneously with the wafer 2.

步驟S14：參閱圖12、圖16，此為覆蓋層設置步驟，由於在前述準備步驟中，第一基板1的上表面11已預先覆蓋一層第一覆蓋層31，因此本步驟主要是在晶片2及凹槽13處覆蓋一層第二覆蓋層31’，使第一基板1的上表面11以及晶片2的表面除了通孔14以外的部分均覆蓋覆蓋層31、31’。 Step S14: Referring to FIG. 12 and FIG. 16, this is a cover layer setting step. Since the upper surface 11 of the first substrate 1 has been covered with a first cover layer 31 in the foregoing preparation step, this step is mainly on the wafer 2. And the recess 13 is covered with a second cover layer 31' such that the upper surface 11 of the first substrate 1 and the surface of the wafer 2 cover the cover layers 31, 31' except for the through holes 14.

步驟S15：參閱圖12、圖17，此為通道形成步驟。類似前述步驟S04，本實施例中此步驟是依一預定路徑對第一覆蓋層31與第二覆蓋層31’施以雷射蝕刻，使第一覆蓋層31與第二覆蓋層31’相互配合，由兩者表面凹陷形成至少一條(此處為兩條)由晶片2的接點21分別延伸至第一基板1的通孔14的線路通道32，該等線路通道32用於後續的延伸線路4的製作。 Step S15: Referring to FIG. 12 and FIG. 17, this is a channel forming step. Similar to the foregoing step S04, in this embodiment, the first cover layer 31 and the second cover layer 31' are subjected to laser etching according to a predetermined path, so that the first cover layer 31 and the second cover layer 31' cooperate with each other. Forming at least one (here, two) from the surface depressions of the wafer 2 extends from the contacts 21 of the wafer 2 to the line channels 32 of the through holes 14 of the first substrate 1, respectively, and the line channels 32 are used for subsequent extension lines 4 production.

步驟S16：參閱圖12、圖18，此為延伸線路形成步驟。本步驟是藉由噴嘴8在線路通道32與通孔14中灌注導電膠體，並對導電膠體進行照光固化或加熱固化處理而形成延伸線路4。延伸線路4於第一基板1的上表面11、晶片2的頂面及填充層3的頂面係水平延伸，在第一基板1的通孔14中係垂直延伸，其兩端係分別連接晶片2的接點21及第二基板6的導電線路63，而使晶片2得以 電連接於導電線路63(天線線路)。 Step S16: Referring to FIG. 12 and FIG. 18, this is an extension line forming step. In this step, the conductive paste is infused in the line channel 32 and the through hole 14 by the nozzle 8, and the conductive paste is subjected to photo curing or heat curing treatment to form the extension line 4. The extension line 4 extends horizontally on the upper surface 11 of the first substrate 1, the top surface of the wafer 2, and the top surface of the filling layer 3, and extends vertically in the through hole 14 of the first substrate 1, and the ends thereof are respectively connected to the wafer. The contact 21 of 2 and the conductive line 63 of the second substrate 6 enable the wafer 2 to Electrically connected to the conductive line 63 (antenna line).

步驟S17，參閱圖11、圖12、圖18，此為移除步驟。此步驟將上述第一覆蓋層31與該第二覆蓋層31’移除後，即完成電路裝置100的製作。 Step S17, referring to FIG. 11, FIG. 12, FIG. 18, this is a removal step. After this step removes the first cover layer 31 and the second cover layer 31', the fabrication of the circuit device 100 is completed.

綜合前述兩個實施例，本發明提出的製造方法屬於低溫製程，且無須執行施壓步驟，因此適用於採用塑膠基板的電路裝置100的製作。當然，本發明的製造方法也可以應用於非塑膠基版的電路裝置100，並不以塑膠材質的基板為限。此外，本發明的製造方法一例中以雷射蝕刻法進行線路圖案的界定，有助於縮小及控制線路的線寬與線距，並適用於採用非平坦基板的電路裝置100的製作，但諸如機械蝕刻、化學蝕刻等方式也能運用於線路圖案的界定，並不以雷射蝕刻為限。而將晶片2的大部分體積收容於凹槽13中的設計，有助於電路裝置100的微型化與輕薄化發展。藉由信賴性測試結果可知，在各種測試環境中，電路裝置100的延伸線路4都可以維持穩定的導電性及附著性。是故，本發明提出的電路裝置100及其製造方法確實具有良好的性能表現及製程優點，而能達成本發明的目的。 In combination with the foregoing two embodiments, the manufacturing method proposed by the present invention is a low temperature process and does not require a pressing step, and is therefore suitable for the fabrication of the circuit device 100 using a plastic substrate. Of course, the manufacturing method of the present invention can also be applied to the circuit device 100 of the non-plastic base plate, and is not limited to the substrate of the plastic material. Further, in the example of the manufacturing method of the present invention, the line pattern is defined by the laser etching method, which contributes to narrowing and controlling the line width and the line pitch of the line, and is suitable for the fabrication of the circuit device 100 using the non-flat substrate, but such as Mechanical etching, chemical etching, etc. can also be applied to the definition of the line pattern, not limited by laser etching. The design of accommodating most of the volume of the wafer 2 in the recess 13 contributes to the miniaturization and thinning of the circuit device 100. As a result of the reliability test, it is understood that the extension line 4 of the circuit device 100 can maintain stable conductivity and adhesion in various test environments. Therefore, the circuit device 100 and the manufacturing method thereof provided by the present invention do have good performance and process advantages, and the object of the present invention can be achieved.

惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。 The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

S01~S06‧‧‧流程步驟 S01~S06‧‧‧ Process steps

Claims (13)

一種電路裝置，包含：一第一基板，具絕緣性，並具有相反的一上表面及一下表面，該第一基板的上表面凹陷形成一凹槽；一晶片，設置於該第一基板的該凹槽中，並包括至少一個顯露於該凹槽外的接點；至少一條延伸線路，連接於該晶片的該接點，且由該晶片的該接點至少延伸至該第一基板的上表面；及一填充層，具絕緣性，該填充層設置於該第一基板的該凹槽中並圍繞該晶片，且供該延伸線路由該晶片的該接點經由其表面而至少延伸至該第一基板的上表面。 A circuit device comprising: a first substrate, having an insulating property, and having an opposite upper surface and a lower surface, wherein an upper surface of the first substrate is recessed to form a recess; and a wafer is disposed on the first substrate a recess and including at least one contact exposed outside the recess; at least one extension line connected to the contact of the wafer, and the contact of the wafer extends at least to an upper surface of the first substrate And a filling layer, having an insulating layer, the filling layer is disposed in the groove of the first substrate and surrounding the wafer, and the extending line extends from the contact of the wafer to the first portion via the surface thereof The upper surface of a substrate. 如請求項1所述的電路裝置，其中，該第一基板還形成至少一個貫穿其上表面與下表面並對應該延伸線路位置的通孔，該通孔供該延伸線路進一步設置及延伸其中；該電路裝置還包含一第二基板，該第二基板具有相反的一上表面及一下表面，並包括至少一設置於其上表面的導電線路；該第二基板供該第一基板設置其上，使該第一基板的下表面鄰接該第二基板的上表面，並使延伸於該通孔中的該延伸線路連接於該第二基板的該導電線路。 The circuit device of claim 1, wherein the first substrate further forms at least one through hole penetrating the upper surface and the lower surface thereof and extending the position of the line, the through hole for the extension line further disposed and extending therein; The circuit device further includes a second substrate having an opposite upper surface and a lower surface, and including at least one conductive line disposed on the upper surface thereof; the second substrate is disposed on the first substrate The lower surface of the first substrate is adjacent to the upper surface of the second substrate, and the extension line extending in the through hole is connected to the conductive line of the second substrate. 一種電路裝置的製造方法，包含以下步驟：準備步驟：準備一絕緣的基板及一晶片，該基板具有相反的一上表面及一下表面，且其上表面凹陷形成一凹槽；該晶片設置於該基板的該凹槽中，且包括至少一 個顯露於外的接點；覆蓋層設置步驟：覆蓋一覆蓋層於該基板的該上表面與該晶片的表面；通道形成步驟：依一預定路徑，使該覆蓋層由其表面凹陷形成至少一條由該晶片的該接點延伸至該基板的該上表面的線路通道；延伸線路形成步驟：於該線路通道中形成一連接於該晶片的該接點，並由該晶片的該接點延伸至該基板的該上表面的延伸線路；及移除步驟：移除位於該基板的該上表面與該晶片的表面的該覆蓋層，並保留位於該凹槽中並圍繞該晶片的該覆蓋層。 A method of manufacturing a circuit device, comprising the steps of: preparing an insulating substrate and a wafer having an opposite upper surface and a lower surface, wherein the upper surface is recessed to form a recess; the wafer is disposed on the substrate In the groove of the substrate, and including at least one a cover exposed step; a cover layer setting step of covering a cover layer on the upper surface of the substrate and a surface of the wafer; and a channel forming step of: recessing the cover layer by at least one surface thereof according to a predetermined path a line extending from the junction of the wafer to the upper surface of the substrate; an extension line forming step of forming a contact connected to the wafer in the line via and extending from the junction of the wafer to An extension line of the upper surface of the substrate; and a removing step of removing the cover layer on the upper surface of the substrate and the surface of the wafer, and retaining the cover layer in the recess and surrounding the wafer. 如請求項3所述的電路裝置的製造方法，其中，該準備步驟是預先分別製備該基板與該晶片，而後再將該晶片裝設於該基板的該凹槽中。 The method of manufacturing a circuit device according to claim 3, wherein the preparing step is to separately prepare the substrate and the wafer in advance, and then mounting the wafer in the recess of the substrate. 如請求項3所述的電路裝置的製造方法，其中，於該延伸線路形成步驟，該延伸線路是藉由灌注導電膠體於該線路通道中，且隨後施以固化處理而形成。 The method of manufacturing a circuit device according to claim 3, wherein in the extending line forming step, the extending line is formed by injecting a conductive paste into the line path and then applying a curing process. 如請求項3所述的電路裝置的製造方法，其中，於該通道形成步驟，係以雷射蝕刻使該覆蓋層由其表面凹陷而形成該線路通道。 The method of manufacturing a circuit device according to claim 3, wherein in the channel forming step, the cover layer is recessed by a surface thereof by laser etching to form the line path. 一種電路裝置的製造方法，包含以下步驟：準備步驟：準備一第一基板、一第二基板及一晶片，該第二基板具有相反的一上表面及一下表面，並包括 至少一條設置於其上表面的導電線路；該第一基板設置於該第二基板上，並具有相反的一上表面及一下表面，該第一基板的該下表面鄰接該第二基板的該上表面，該第一基板的該上表面凹陷形成一凹槽，並形成至少一個貫穿至其下表面且位置對應該導電線路的通孔，該第一基板的該上表面還被一層第一覆蓋層覆蓋；該晶片設置於該第一基板的該凹槽中，且包括至少一個顯露於外的接點；覆蓋層設置步驟：至少對該晶片覆蓋一層第二覆蓋層；通道形成步驟：依一預定路徑，使該第一覆蓋層與該第二覆蓋層表面凹陷形成至少一條由該晶片的該接點延伸至該第一基板的該通孔的線路通道；延伸線路形成步驟：於該線路通道與該通孔中形成一延伸線路，該延伸線路係連接該晶片的該接點並連接該第二基板的該導電線路，且於該接點與該導電線路之間延伸；及移除步驟：自該第一基板的該上表面與該晶片的表面移除該第一覆蓋層與該第二覆蓋層。 A method of manufacturing a circuit device, comprising the steps of: preparing a first substrate, a second substrate, and a wafer, the second substrate having an opposite upper surface and a lower surface, and including At least one conductive line disposed on the upper surface thereof; the first substrate is disposed on the second substrate and has an opposite upper surface and a lower surface, the lower surface of the first substrate abutting the upper surface of the second substrate a surface, the upper surface of the first substrate is recessed to form a recess, and at least one through hole penetrating to a lower surface thereof corresponding to the conductive line is formed, and the upper surface of the first substrate is further covered by a first cover layer Covering; the wafer is disposed in the recess of the first substrate, and includes at least one exposed contact; the cover layer is disposed to: at least cover the wafer with a second cover layer; and the channel forming step: according to a predetermined a path for recessing the first cover layer and the surface of the second cover layer to form at least one line channel extending from the contact of the wafer to the through hole of the first substrate; and extending the line forming step: in the line channel and Forming an extension line in the through hole, the extension line connecting the contact of the wafer and connecting the conductive line of the second substrate, and extending between the contact and the conductive line; Removal step: covering the first layer and the second covering layer is removed and the surface of the wafer from the upper surface of the first substrate. 如請求項7所述的電路裝置的製造方法，其中，該準備步驟是先將該第一基板設置於該第二基板上，再將該晶片設置於該凹槽中。 The method of manufacturing a circuit device according to claim 7, wherein the preparing step is to first dispose the first substrate on the second substrate, and then place the wafer in the recess. 如請求項7所述的電路裝置的製造方法，其中，該第一基板的該凹槽係貫穿至該第一基板的下表面，且於該準 備步驟中，該第一基板是藉由一黏著層黏合於該第二基板，且該晶片設於該凹槽後被該黏著層固著。 The method of manufacturing the circuit device of claim 7, wherein the recess of the first substrate penetrates to a lower surface of the first substrate, and In the preparation step, the first substrate is adhered to the second substrate by an adhesive layer, and the wafer is disposed in the groove and fixed by the adhesive layer. 如請求項7所述的電路裝置的製造方法，其中，該晶片是藉由嵌入成型技術，於該第一基板藉由射出成型方式製作後，即嵌於該基板的該凹槽中；於該準備步驟中，該第一基板連同該晶片是同時被設置於該第二基板上。 The method of manufacturing the circuit device according to claim 7, wherein the wafer is embedded in the groove of the substrate by insert molding after the first substrate is formed by injection molding; In the preparing step, the first substrate and the wafer are simultaneously disposed on the second substrate. 如請求項7所述的電路裝置的製造方法，其中，於該延伸線路形成步驟，該延伸線路是藉由灌注導電膠體於該線路通道與該通孔中，且隨後施以固化處理而形成。 The method of manufacturing a circuit device according to claim 7, wherein in the extending line forming step, the extending line is formed by injecting a conductive paste into the via hole and the via hole, and then applying a curing process. 如請求項7所述的電路裝置的製造方法，其中，於該通道形成步驟，係以雷射蝕刻使該第一覆蓋層及該第二覆蓋層由其表面凹陷而形成該線路通道。 The method of manufacturing a circuit device according to claim 7, wherein in the channel forming step, the first cap layer and the second cap layer are recessed by a surface thereof by laser etching to form the line channel. 一種電路裝置，由請求項3至12中任一項所述的製造方法製成。 A circuit device produced by the manufacturing method according to any one of claims 3 to 12.
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