TWI524377B - Method for manufacturing semiconductor integrated circuit - Google Patents
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- TWI524377B TWI524377B TW100118079A TW100118079A TWI524377B TW I524377 B TWI524377 B TW I524377B TW 100118079 A TW100118079 A TW 100118079A TW 100118079 A TW100118079 A TW 100118079A TW I524377 B TWI524377 B TW I524377B
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Description
本發明係有關於一種半導體積體電路之製作方法，特別有關於一種採用金屬硬遮罩(metal hard mask)的半導體積體電路之製作方法。The present invention relates to a method of fabricating a semiconductor integrated circuit, and more particularly to a method of fabricating a semiconductor integrated circuit using a metal hard mask.
在目前半導體工業中，鑲嵌技術已經是半導體積體電路中多重金屬內連線(multi-level interconnects)的主要技術。鑲嵌技術係可簡述為首先在介電材料層中蝕刻出電路圖案，然後將導電材料如銅填入該電路圖案中，並加以平坦化，進而完成金屬內連線之製作。依在介電材料層中蝕刻圖案之方式來區分，鑲嵌技術可再細分為溝渠優先(trench-first)製程、介層洞優先(via-first)、部分介層洞優先(partial-via-first)製程、以及自行對準(self-aligned)製程等。In the current semiconductor industry, damascene technology has become the main technology for multi-level interconnects in semiconductor integrated circuits. The damascene technique can be briefly described as first etching a circuit pattern in a dielectric material layer, then filling a conductive material such as copper into the circuit pattern, and planarizing it to complete the fabrication of the metal interconnect. According to the way of etching patterns in the dielectric material layer, the mosaic technique can be further subdivided into trench-first process, via-first, and partial-via-first. Process, and self-aligned processes.
習知鑲嵌技術係於一包含導電層的基底上依序形成一介電層結構與一金屬硬遮罩，隨後圖案化金屬硬遮罩形成一開口，再進行一蝕刻製程，藉由開口向下蝕刻介電層結構而形成鑲嵌導線的溝渠圖案或介層洞圖案。值得注意的是，在形成開口或者是在蝕刻製程中常有掉落微粒等污染物產生。且掉落微粒因為受到本身以及金屬硬遮罩之間產生的凡得瓦力(Van der Waals force)吸引，而附著於金屬硬遮罩上，或被吸引在金屬硬遮罩周圍。被吸引的掉落微粒即使利用清洗製程也無法輕易地將掉落微粒移除，且掉落微粒的存在阻礙了後續蝕刻製程的進行，甚至造成蝕刻後的溝渠開口圖案縮小、甚或不完整等問題。更導致後續形成於溝渠開口內的金屬發生斷線等缺陷，降低了金屬內連線的可靠度。The conventional damascene technique sequentially forms a dielectric layer structure and a metal hard mask on a substrate including a conductive layer, and then patterns the metal hard mask to form an opening, and then performs an etching process through the opening downward. The dielectric layer structure is etched to form a trench pattern or via pattern of the damascene. It is worth noting that contaminants such as falling particles are often generated during the formation of openings or during the etching process. And the falling particles are attracted to the metal hard mask or attracted around the metal hard mask because they are attracted by the Van der Waals force generated between themselves and the metal hard mask. The dropped particles that are attracted can not easily remove the falling particles even if the cleaning process is used, and the presence of the falling particles hinders the subsequent etching process, and even causes the pattern of the trench opening after etching to be reduced or even incomplete. . Further, defects such as wire breakage of the metal formed in the opening of the trench are caused, and the reliability of the metal interconnect is reduced.
因此，本發明係於此提供一種半導體積體電路之製作方法，用以解決微粒附著於金屬硬遮罩進而導致蝕刻不完全等問題。Therefore, the present invention provides a method of fabricating a semiconductor integrated circuit for solving the problem that particles adhere to a metal hard mask to cause incomplete etching.
根據本發明所提供之申請專利範圍，係提供一種半導體積體電路之製作方法。該製作方法首先提供一基底，且該基底上形成有至少一金屬硬遮罩。接下來對該金屬硬遮罩進行一圖案化步驟，圖案化該金屬硬遮罩以形成一圖案化金屬硬遮罩。隨後對該圖案化金屬硬遮罩進行一水電漿(H2O plasma)處理。According to the patent application scope provided by the present invention, a method of fabricating a semiconductor integrated circuit is provided. The fabrication method first provides a substrate, and the substrate is formed with at least one metal hard mask. Next, the metal hard mask is subjected to a patterning step of patterning the metal hard mask to form a patterned metal hard mask. The patterned metal hard mask is then subjected to a H 2 O plasma treatment.
根據本發明所提供之半導體積體電路之製作方法，係於形成第一開口之後，藉由一水電漿處理移除該圖案化金屬硬遮罩在圖案化步驟中獲得的正電荷。因此在圖案化步驟中產生的掉落微粒較不易受到凡得瓦力的吸引而附著於圖案化金屬硬遮罩上，而易於由清洗製程被移除。因此，後續進行的蝕刻製程中，係不再因為掉落微粒的存在影響到蝕刻結果，並降低後續填入的金屬層發生斷線的可能。簡單地說，本發明所提供之半導體積體電路之製作方法，係可有效地提高半導體積體電路的可靠度。According to the method of fabricating the semiconductor integrated circuit of the present invention, after the first opening is formed, the positive charge obtained by the patterned metal hard mask in the patterning step is removed by a water plasma treatment. Therefore, the falling particles generated in the patterning step are less likely to be attracted to the patterned metal hard mask by the attraction of the van der Waals force, and are easily removed by the cleaning process. Therefore, in the subsequent etching process, the etching result is no longer affected by the presence of the falling particles, and the possibility of disconnection of the subsequently filled metal layer is reduced. Briefly, the method of fabricating the semiconductor integrated circuit provided by the present invention can effectively improve the reliability of the semiconductor integrated circuit.
請參閱第1圖至第6圖，第1圖至第6圖係為本發明所提供之半導體積體電路之製作方法之一較佳實施例之示意圖。如第1圖所示，本較佳實施例首先提供一基底100，如一矽基底、含矽基底、或矽覆絕緣(silicon-on-insulator，SOI)基底等，且基底100內包含有一導電層102與一覆蓋導電層102的底層104。在本較佳實施例中，導電層102係包含金屬材料，而底層104則包含氮摻雜碳化矽(nitrogen-doped silicon carbide)。另外，基底100更包含一介電層106，且如第1圖所示，介電層106係覆蓋底層104。介電層106可包含低介電常數(dielectric constant，k)材料(介電常數值小於3.9)、超低介電常數(ultra low-k，以下簡稱為ULK)材料、或多孔性超低介電常數(porous ULK)材料，由於低介電常數材料、ULK材料與多孔性ULK材料皆為較不緻密且結構強度較低的材料，因此本較佳實施例係選擇性地在介電層106表面再形成一緻密的覆蓋層108。覆蓋層108可如第1圖所示為一包含氧化矽(silicon oxide，SiO)、氮氧化矽(silicon oxynitride，SiON)或四乙基氧矽烷(tetraethylorthosilicate，TEOS)的單層結構，但亦不限為一複合膜層結構。Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a preferred embodiment of a method for fabricating a semiconductor integrated circuit according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate, and the substrate 100 includes a conductive layer. 102 and a bottom layer 104 covering the conductive layer 102. In the preferred embodiment, conductive layer 102 comprises a metallic material and bottom layer 104 comprises nitrogen-doped silicon carbide. In addition, the substrate 100 further includes a dielectric layer 106, and as shown in FIG. 1, the dielectric layer 106 covers the bottom layer 104. The dielectric layer 106 may comprise a low dielectric constant (k) material (dielectric constant value less than 3.9), an ultra low dielectric constant (ULK) material, or a porous ultra low dielectric. The electrical constant (porous ULK) material, since the low dielectric constant material, the ULK material and the porous ULK material are both less dense and less structurally strong, the preferred embodiment is selectively in the dielectric layer 106. The surface re-forms a uniform cover layer 108. The cover layer 108 can be a single layer structure including silicon oxide (SiO), silicon oxynitride (SiON) or tetraethylorthosilicate (TEOS) as shown in FIG. 1, but it is not Limited to a composite film structure.
請繼續參閱第1圖。接下來，係於基底100上，尤其是覆蓋層108上形成一金屬硬遮罩110。金屬硬遮罩110可為一單層結構或一複合膜層結構，且係選自鈦(titanium，Ti)、氮化鈦(titanium nitride，TiN)、鉭(tantalum，Ta)、與氮化鉭(tantalum nitride，TaN)所組成之群組。舉例來說，本較佳實施例所提供金屬硬遮罩110係可包含一Ti/TiN或Ta/TaN的複合膜層，但不限於此。另外值得注意的是，由於金屬硬遮罩110具有相對於介電層106的應力，因此本較佳實施例中，覆蓋層108更可作為金屬硬遮罩110與介電層106之間的緩衝，避免介電層106直接受到金屬硬遮罩110的應力的影響。如第1圖所示，本較佳實施例更於金屬硬遮罩110上形成一抗反射層(anti-reflective coating，ARC) 120，抗反射層120可包含介電材料如SiON或TEOS，但不限於此。Please continue to see Figure 1. Next, a metal hard mask 110 is formed on the substrate 100, particularly the cover layer 108. The metal hard mask 110 may be a single layer structure or a composite film layer structure, and is selected from titanium (Titanium, Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride. Group of (tantalum nitride, TaN). For example, the metal hard mask 110 provided in the preferred embodiment may include a composite film layer of Ti/TiN or Ta/TaN, but is not limited thereto. It is also worth noting that since the metal hard mask 110 has a stress with respect to the dielectric layer 106, the cover layer 108 can serve as a buffer between the metal hard mask 110 and the dielectric layer 106 in the preferred embodiment. The dielectric layer 106 is prevented from being directly affected by the stress of the metal hard mask 110. As shown in FIG. 1, the preferred embodiment further forms an anti-reflective coating (ARC) 120 on the metal hard mask 110. The anti-reflective layer 120 may comprise a dielectric material such as SiON or TEOS, but Not limited to this.
此外，在本較佳實施例之一變化型中，導電層102係可包含其他導電材料如金屬氮化物、金屬矽化物或摻雜矽，覆蓋層108則可包含氮化矽(silicon nitride，SiN)、SiO或SiON，而金屬硬遮罩110則是直接形成於覆蓋層108上。In addition, in a variation of the preferred embodiment, the conductive layer 102 may comprise other conductive materials such as metal nitrides, metal tellurides or doped germanium, and the cap layer 108 may comprise silicon nitride (SiN). ), SiO or SiON, and the metal hard mask 110 is formed directly on the cover layer 108.
請繼續參閱第1圖。接下來，係於抗反射層120上形成一圖案化光阻122，圖案化光阻122係包含一至少開口124，用以定義一鑲嵌導線的溝渠圖案。Please continue to see Figure 1. Next, a patterned photoresist 122 is formed on the anti-reflective layer 120. The patterned photoresist 122 includes an at least opening 124 for defining a trench pattern of the embedded wire.
請參閱第2圖。在形成圖案化光阻122之後，係對金屬硬遮罩110進行一圖案化步驟，透過圖案化光阻122的開口124蝕刻抗反射層120、金屬硬遮罩110與部分覆蓋層108，以圖案化金屬硬遮罩110形成一包含至少一開口126之圖案化金屬硬遮罩112。值得注意的是，在圖案化步驟之後，圖案化金屬硬遮罩112係帶有電荷，且通常為正電荷。因此，在圖案化步驟中產生的掉落微粒128係受到凡得瓦力的吸引而容易附著於圖案化金屬硬遮罩112的開口126周圍。Please refer to Figure 2. After forming the patterned photoresist 122, a patterning step is performed on the metal hard mask 110, and the anti-reflective layer 120, the metal hard mask 110 and the partial cover layer 108 are etched through the opening 124 of the patterned photoresist 122 to pattern The metal hard mask 110 forms a patterned metal hard mask 112 that includes at least one opening 126. It is worth noting that after the patterning step, the patterned metal hard mask 112 is charged and typically has a positive charge. Therefore, the falling particles 128 generated in the patterning step are attracted by the van der Waals force and are easily attached around the opening 126 of the patterned metal hard mask 112.
請參閱第3圖。在形成圖案化金屬硬遮罩112之後，係進行一水電漿(H2O plasma)處理130，用以同位地移除圖案化光阻122、抗反射層120、與圖案化金屬硬遮罩112之該等正電荷。在本較佳實施例中，首先係通入一水蒸氣(H2O vapor)以進行水電漿處理130，且該水蒸氣之氣體流量係為2000～3000每分鐘標準毫升(standard cubic centimeter per minute，sccm)。接下來轉化(transform)水蒸氣成為具有反應性的水電漿，用以移除圖案化光阻122、抗反射層120與正電荷。在本較佳實施例中，水電漿處理130之一製程時間係介於15秒與60秒之間、其製程壓力係介於3000毫托耳(mTorr)與9000毫托耳、而其製程溫度係介於25℃～350℃。由於水電漿處理130係移除了圖案化金屬硬遮罩112的正電荷，因此掉落微粒128不再受到凡得瓦力的吸引而附著於圖案化金屬硬遮罩112的開口126附近，而容易由後續進行的清洗製程移除。此外值得注意的是，在水電漿處理130以及後續的清洗步驟中，介電層106仍然由較為緻密的覆蓋層108所保護。Please refer to Figure 3. After forming the patterned metal hard mask 112, a H 2 O plasma process 130 is performed for co-located removal of the patterned photoresist 122, the anti-reflective layer 120, and the patterned metal hard mask 112. The positive charges. In the preferred embodiment, first, a water vapor (H 2 O vapor) is introduced to perform the water plasma treatment 130, and the gas flow rate of the water vapor is 2000 to 3000 standard milliliters per minute (standard cubic centimeter per minute) , sccm). The water vapor is then transformed into a reactive aqueous plasma for removing the patterned photoresist 122, the antireflective layer 120 and the positive charge. In the preferred embodiment, the process time of one of the water plasma treatments 130 is between 15 seconds and 60 seconds, and the process pressure is between 3000 millitorr (mTorr) and 9000 millitorr, and the process temperature thereof. The system is between 25 ° C and 350 ° C. Since the hydroelectric plasma treatment 130 removes the positive charge of the patterned metal hard mask 112, the falling particles 128 are no longer attracted by the van der Waals force and are attached to the vicinity of the opening 126 of the patterned metal hard mask 112. It is easy to remove by the subsequent cleaning process. It is also worth noting that in the hydrothermal plasma treatment 130 and subsequent cleaning steps, the dielectric layer 106 is still protected by a relatively dense cover layer 108.
另外，在本較佳實施例中，亦不限於在水電漿處理130之前，先進行一氧電漿(O2 plasma)處理，以確保圖案化光阻122與抗反射層120可完全移除。另外，為了有效地移除圖案化金屬硬遮罩112的正電荷，本較佳實施例所提供之水電漿處理130亦可包含負電荷。另外，若圖案化金屬硬遮罩112在蝕刻製程後帶有負電荷，本較佳實施例所提供之水電漿處理130亦可包含正電荷。In addition, in the preferred embodiment, it is not limited to performing an O 2 plasma treatment prior to the hydrothermal plasma treatment 130 to ensure that the patterned photoresist 122 and the anti-reflective layer 120 are completely removed. Additionally, to effectively remove the positive charge of the patterned metal hard mask 112, the aqueous plasma treatment 130 provided by the preferred embodiment may also include a negative charge. In addition, if the patterned metal hard mask 112 has a negative charge after the etching process, the water plasma treatment 130 provided in the preferred embodiment may also include a positive charge.
請參閱第4圖。在水電漿處理130之後，係進行前述的清洗製程(圖未示)，以將掉落微粒128等移除，隨後於圖案化金屬硬遮罩112上再形成一抗反射層140與一圖案化光阻142。如第4圖所示，抗反射層140係填滿開口126，而圖案化光阻142則具有一對應於開口126位置的開口144，設置於開口126範圍內，用以定義一鑲嵌導線的介層洞圖案。Please refer to Figure 4. After the water plasma treatment 130, the foregoing cleaning process (not shown) is performed to remove the falling particles 128 and the like, and then an anti-reflective layer 140 and a pattern are formed on the patterned metal hard mask 112. Photoresist 142. As shown in FIG. 4, the anti-reflective layer 140 fills the opening 126, and the patterned photoresist 142 has an opening 144 corresponding to the position of the opening 126, which is disposed in the range of the opening 126 for defining a mosaic wire. Layer pattern.
請參閱第5圖。接下來利用圖案化光阻142作為蝕刻遮罩，透過圖案化光阻142的開口144向下蝕刻抗反射層140、覆蓋層108與部分介電層106，而於介電層106的上半部形成另一開口146，開口146係對應於開口126，用以作為一部份介層洞。待形成開口146之後，係可利用氧電漿等方式去除圖案化光阻142與抗反射層140。Please refer to Figure 5. Next, using the patterned photoresist 142 as an etch mask, the anti-reflective layer 140, the cap layer 108 and a portion of the dielectric layer 106 are etched down through the opening 144 of the patterned photoresist 142, and in the upper half of the dielectric layer 106. Another opening 146 is formed which corresponds to the opening 126 for serving as a partial via. After the opening 146 is to be formed, the patterned photoresist 142 and the anti-reflective layer 140 may be removed by means of oxygen plasma or the like.
請參閱第6圖。接下來，再次進行一蝕刻製程，向下蝕刻未被圖案化金屬硬遮罩112覆蓋的覆蓋層108以及介電層106，以將開口126與開口146轉移至介電層106中，而於介電層106內形成鑲嵌導線的一溝渠開口150與一介層洞開口152。且如第6圖所示，底層104係暴露介層洞開口152的底部。Please refer to Figure 6. Next, an etching process is performed again to etch the cap layer 108 and the dielectric layer 106 not covered by the patterned metal hard mask 112 to transfer the opening 126 and the opening 146 into the dielectric layer 106. A trench opening 150 and a via opening 152 are formed in the electrical layer 106. And as shown in FIG. 6, the bottom layer 104 exposes the bottom of the via opening 152.
在完成溝渠開口150與介層洞開口152之製作後，可藉由適合之蝕刻製程移除介層洞開口152底部的底層104，而暴露出導電層102。隨後，係於溝渠開口150與介層洞開口152內形成阻障層(圖未示)與填滿溝渠開口150及介層洞開口152的導電層(圖未示)，最後藉由一平坦化步驟移除多餘的導電層與圖案化金屬層112，完成鑲嵌導線的製作。由於上述步驟係為熟習該項技藝之人士所熟知者，因此在本較佳實施例中不再贅述。值得注意的是，由於掉落微粒128不再受到凡得瓦力的吸引而於清洗製程中完全移除，因此蝕刻製程係可順利且完整地將開口126與開口146轉移至介電層106內，而形成溝渠開口150與介層洞開口152。且後續於溝渠開口150與介層洞開口152填入導電層時，導電材料係可完整地填入溝渠開口150與介層洞開口152中，因此習知技術中因填入不完整而造成的斷線問題係可有效避免。After the fabrication of the trench opening 150 and the via opening 152 is completed, the conductive layer 102 can be exposed by removing the underlayer 104 at the bottom of the via opening 152 by a suitable etching process. Subsequently, a barrier layer (not shown) and a conductive layer (not shown) filling the trench opening 150 and the via opening 152 are formed in the trench opening 150 and the via opening 152, and finally planarized by a flattening. The step removes the excess conductive layer and the patterned metal layer 112 to complete the fabrication of the damascene wires. Since the above-described steps are well known to those skilled in the art, they will not be described again in the preferred embodiment. It is worth noting that since the falling particles 128 are no longer completely attracted by the van der Waals force and are completely removed in the cleaning process, the etching process can smoothly and completely transfer the openings 126 and openings 146 into the dielectric layer 106. The trench opening 150 and the via opening 152 are formed. When the conductive layer is filled in the trench opening 150 and the via opening 152, the conductive material can be completely filled into the trench opening 150 and the via opening 152, so that the prior art is incompletely filled. The disconnection problem can be effectively avoided.
綜上所述，本發明所提供之半導體積體電路之製作方法，係於形成用以定義溝渠位置的開口之後，藉由一水電漿處理移除該圖案化金屬硬遮罩在圖案化步驟中獲得的正電荷。因此在圖案化步驟中產生的掉落微粒較不易受到凡得瓦力的吸引而附著於圖案化金屬硬遮罩上，而易於由清洗製程被移除。因此，後續進行的蝕刻製程中，係不再因為掉落微粒的存在影響到蝕刻結果，並降低後續填入的金屬層發生斷線的可能。簡單地說，本發明所提供之半導體積體電路之製作方法，係可有效地提高半導體積體電路的可靠度。In summary, the method for fabricating a semiconductor integrated circuit according to the present invention is to remove the patterned metal hard mask in a patterning step by a water plasma treatment after forming an opening for defining a trench location. The positive charge obtained. Therefore, the falling particles generated in the patterning step are less likely to be attracted to the patterned metal hard mask by the attraction of the van der Waals force, and are easily removed by the cleaning process. Therefore, in the subsequent etching process, the etching result is no longer affected by the presence of the falling particles, and the possibility of disconnection of the subsequently filled metal layer is reduced. Briefly, the method of fabricating the semiconductor integrated circuit provided by the present invention can effectively improve the reliability of the semiconductor integrated circuit.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．基底100. . . Base
102．．．導電層102. . . Conductive layer
104．．．底層104. . . Bottom layer
106．．．介電層106. . . Dielectric layer
108．．．覆蓋層108. . . Cover layer
110．．．金屬硬遮罩110. . . Metal hard mask
112．．．圖案化金屬硬遮罩112. . . Patterned metal hard mask
120．．．抗反射層120. . . Antireflection layer
122．．．圖案化光阻122. . . Patterned photoresist
124．．．開口124. . . Opening
126．．．開口126. . . Opening
128．．．掉落微粒128. . . Falling particles
130．．．水電漿處理130. . . Hydroponic treatment
140．．．抗反射層140. . . Antireflection layer
142．．．圖案化光阻142. . . Patterned photoresist
144．．．開口144. . . Opening
146．．．開口146. . . Opening
150．．．溝渠開口150. . . Ditch opening
152．．．介層洞開口152. . . Interlayer opening
第1圖至第6圖係為本發明所提供之半導體積體電路之製作方法之一較佳實施例之示意圖。1 to 6 are schematic views of a preferred embodiment of a method of fabricating a semiconductor integrated circuit provided by the present invention.
100．．．基底100. . . Base
102．．．導電層102. . . Conductive layer
104．．．底層104. . . Bottom layer
106．．．介電層106. . . Dielectric layer
108．．．覆蓋層108. . . Cover layer
112．．．圖案化金屬硬遮罩112. . . Patterned metal hard mask
126．．．開口126. . . Opening
128．．．掉落微粒128. . . Falling particles
130．．．水電漿處理130. . . Hydroponic treatment
Claims (14)
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