TWI523156B - Structure of external circuit connection for semiconductor device and method of forming the same - Google Patents

Structure of external circuit connection for semiconductor device and method of forming the same Download PDF

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Publication number
TWI523156B
TWI523156B TW096136711A TW96136711A TWI523156B TW I523156 B TWI523156 B TW I523156B TW 096136711 A TW096136711 A TW 096136711A TW 96136711 A TW96136711 A TW 96136711A TW I523156 B TWI523156 B TW I523156B
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Taiwan
Prior art keywords
film
insulating film
external circuit
pad
semiconductor device
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TW096136711A
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Chinese (zh)
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TW200826249A (en
Inventor
盆子原學
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盆子原學
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Publication of TW200826249A publication Critical patent/TW200826249A/en
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Publication of TWI523156B publication Critical patent/TWI523156B/en

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Description

半導體裝置之外部電路連接部構造及其形成方法External circuit connection portion structure of semiconductor device and method of forming same

本發明係關於半導體裝置及其製造方法，更詳言之，係關於能以簡單的構成獲得所欲之耐熱衝擊性及耐機械衝擊性，且能減低厚度(高度)之半導體裝置之外部電路連接部(連接有外部電路之部位)構造及其形成方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an external circuit connection of a semiconductor device capable of achieving desired thermal shock resistance and mechanical shock resistance with a simple configuration and capable of reducing thickness (height) The structure of the part (the part to which the external circuit is connected) and the method of forming the same.

通常，構裝於晶片尺寸封裝體(Chip Size Package,CSP)之半導體裝置，為形成在半導體晶片內部所形成之積體電路與外部電路的電氣連接，例如構裝至印刷配線基板(Printed Wiring Board,PWB)上，而在一主面具有配置成陣列狀之多數個「外部電路連接部」。外部電路連接部，通常包含形成在覆蓋半導體晶片之輸出入側(與外部電路之連接側)之主面之第1絕緣膜上的配線膜、覆蓋該配線膜的第2絕緣膜、及形成在該第2絕緣膜上的導電性焊墊。前述配線膜係電氣連接於半導體晶片內部之積體電路(電子電路)。前述導電性焊墊係電氣連接於前述配線膜。Generally, a semiconductor device mounted on a chip size package (CSP) is an electrical connection formed between an integrated circuit formed inside a semiconductor wafer and an external circuit, for example, to a printed wiring substrate (Printed Wiring Board) , PWB), and a plurality of "external circuit connection portions" arranged in an array on one main surface. The external circuit connecting portion usually includes a wiring film formed on the first insulating film covering the main surface of the input/output side (the connection side with the external circuit) of the semiconductor wafer, a second insulating film covering the wiring film, and a second insulating film formed thereon. A conductive pad on the second insulating film. The wiring film is electrically connected to an integrated circuit (electronic circuit) inside the semiconductor wafer. The conductive pad is electrically connected to the wiring film.

為了易於與外部電路連接(表面構裝)，在前述導電性焊墊大多固設有由焊料、Au等構成之導電性凸塊(以下亦僅稱凸塊)及焊球。由於將凸塊固設至前述導電性焊墊，係以將經加熱之凸塊或焊球緊壓至焊墊而固設，或將藉由加熱形成熔融狀態之凸塊材料之小片載置於前述導電性焊墊上之後、藉由自然冷卻使之硬化而形成凸塊或球等之方法來進行，因此將凸塊或球固設至前述導電性焊墊時，前述導電形焊墊會被急遽地加熱。亦即，在前述導電性焊墊施加熱衝擊。In order to facilitate connection to an external circuit (surface mounting), conductive bumps (hereinafter also referred to as bumps) and solder balls made of solder, Au, or the like are often fixed to the conductive pads. Since the bump is fixed to the conductive pad, it is fixed by pressing the heated bump or solder ball to the pad, or placing a small piece of the bump material which is heated to form a molten state. After the conductive pad is formed by hardening by natural cooling to form a bump or a ball, the conductive pad is impatient when the bump or the ball is fixed to the conductive pad. Ground heating. That is, thermal shock is applied to the aforementioned conductive pad.

於前述導電性焊墊未固設凸塊或球時，雖前述導電性焊墊本身係作為外部電極(焊墊)使用，但此時，例如使用焊料構裝在PWB上時，自處於熔融狀態之焊料施加熱。是以，此時，在前述導電性焊墊(焊墊)亦施加有熱衝擊。When the conductive pad is not fixed with a bump or a ball, the conductive pad itself is used as an external electrode (pad). However, when the solder is mounted on the PWB, for example, it is in a molten state. The solder applies heat. Therefore, at this time, thermal shock is also applied to the conductive pad (pad).

施加在前述導電性焊墊之此種熱衝擊，當然亦對電氣連接於前述導電性焊墊之半導體晶片內部之積體電路造成不良影響，且產生半導體晶片之性能下降、可靠性下降等問題。該等問題係如近來所示，在前述導電性焊墊本身、凸塊、球非常地微細化，且該等之配置間距亦微細化之狀況下，顯得更加嚴重。因此，期望改善外部電路連接部之耐熱衝擊性。Such thermal shock applied to the conductive pad naturally also adversely affects the integrated circuit electrically connected to the inside of the semiconductor wafer of the conductive pad, and causes problems such as deterioration in performance of the semiconductor wafer and deterioration in reliability. As described recently, the above-described conductive pads themselves, bumps, and balls are extremely fine, and the arrangement pitches are also made finer. Therefore, it is desirable to improve the thermal shock resistance of the external circuit connection portion.

習知外部電路連接部之構成，已知有很多種。最簡易的型態有(a)：由透過層間絕緣膜形成在半導體晶片表面(有活性區域側之主面)上的配線膜、及在從前述層間絕緣膜露出之狀態下形成在前述配線膜上的焊墊構成。此構成中，由於熱直接施加在配線膜及半導體晶片表面而不佳。作為改善上述不佳者，有(b)：於(a)之構成追加聚醯亞胺等合成樹脂製的蓋體。合成樹脂製蓋體係僅露出於焊墊之頂部，覆蓋其餘以外的部分(包含配線膜)整面。根據此構成，由於藉由合成樹脂製蓋體而能防止熱直接施加在配線膜及半導體晶片表面，因此可提高耐熱衝擊性。There are many known types of external circuit connecting portions. The most simple type includes (a) a wiring film formed on the surface of the semiconductor wafer (the main surface on the active region side) through the interlayer insulating film, and a wiring film formed in a state exposed from the interlayer insulating film. The upper pad is formed. In this configuration, it is not preferable because heat is directly applied to the wiring film and the surface of the semiconductor wafer. (b): A cover made of a synthetic resin such as polyimine or the like is added to the composition of (a). The synthetic resin capping system is exposed only on the top of the pad, covering the entire surface (including the wiring film). According to this configuration, since the cover is made of a synthetic resin, heat can be prevented from being directly applied to the surface of the wiring film and the semiconductor wafer, so that thermal shock resistance can be improved.

再者，亦有(c)：於(a)之構成使配線膜形成為多層之構成。此構成中，由於配線膜形成為多層，因此所施加之熱透過配線膜而容易逸散，此外由於熱不易施加於半導體晶片表面，因此可提高耐熱衝擊性。Further, (c) is a configuration in which the wiring film is formed in a plurality of layers in the configuration of (a). In this configuration, since the wiring film is formed in a plurality of layers, the applied heat is easily transmitted through the wiring film, and since heat is less likely to be applied to the surface of the semiconductor wafer, thermal shock resistance can be improved.

再者，亦有(d)：在配線膜下，將具有緩衝功能之絕緣膜重疊設於焊墊及配線膜。此構成中，由於藉由緩衝絕緣膜使熱不易施加在半導體晶片表面，因此可提高耐熱衝擊性。Further, (d): Under the wiring film, an insulating film having a buffer function is superposed on the pad and the wiring film. In this configuration, since heat is hardly applied to the surface of the semiconductor wafer by the buffer insulating film, thermal shock resistance can be improved.

上述(a)~(d)之構成，雖皆為將外部電路連接部形成在半導體晶片表面者，但亦已知有將外部電路連接部形成在半導體晶片背面(與有活性區域側相反側之主面)之構成(e)。此構成係卡西歐計算機股份有限公司(CASIO COMPUTER CO.,LTD.)所提案者，如圖20及圖21所示者。此外，以同樣構造之外部電路連接部形成在半導體晶片表面者，係揭示於例如專利文獻1(日本特開2006－147810號公報)。In the above configuration (a) to (d), the external circuit connecting portion is formed on the surface of the semiconductor wafer. However, it is also known that the external circuit connecting portion is formed on the back surface of the semiconductor wafer (on the side opposite to the active region side). The composition of the main face) (e). This configuration is proposed by CASIO COMPUTER CO., LTD. as shown in Figs. 20 and 21 . In addition, the external circuit connecting portion having the same structure is formed on the surface of the semiconductor wafer, and is disclosed in, for example, Patent Document 1 (JP-A-2006-147810).

圖20中，具有複數個貫通半導體晶片211之周邊區域的貫通電極212，利用表面電極220與貫通電極212將半導體晶片211表面的積體電路221之輸出入端子導出至半導體晶片211背面。貫通電極212之周圍，係以絕緣膜(二氧化矽膜等)213a覆蓋，而自形成半導體晶片211之矽基板電氣絕緣。半導體晶片211背面，除貫通電極212之外的部分，大致整面係以絕緣膜(二氧化矽膜、氮化矽膜等)213b覆蓋。在絕緣膜213b表面形成有薄的聚醯亞胺膜213c。在聚醯亞胺膜213c表面形成有由Cu等構成之配線膜215，且配線膜215之一面係電氣連接於所對應之貫通電極212。在聚醯亞胺膜213c表面形成有合成樹脂製之較厚的密封膜214以覆蓋配線膜215，在密封膜214之內部，在與配線膜215重疊之位置埋設有Cu製之柱狀電極216。柱狀電極216之周圍係以絕緣膜(二氧化矽膜等)217覆蓋。由於柱狀電極216之一端接觸於配線膜215，因此柱狀電極216係電氣連接於半導體晶片211表面之積體電路221。在柱狀電極216之露出端形成有導電性之焊墊218。於焊墊218固設有導電性之凸塊219。In FIG. 20, a plurality of through electrodes 212 penetrating through the peripheral region of the semiconductor wafer 211 are used, and the output electrodes of the integrated circuit 221 on the surface of the semiconductor wafer 211 are led out to the back surface of the semiconductor wafer 211 by the surface electrode 220 and the through electrode 212. The periphery of the through electrode 212 is covered with an insulating film (such as a ruthenium dioxide film) 213a, and is electrically insulated from the substrate on which the semiconductor wafer 211 is formed. On the back surface of the semiconductor wafer 211, a portion other than the through electrode 212 is covered with an insulating film (such as a ruthenium dioxide film or a tantalum nitride film) 213b. A thin polyimide film 213c is formed on the surface of the insulating film 213b. A wiring film 215 made of Cu or the like is formed on the surface of the polyimide film 213c, and one surface of the wiring film 215 is electrically connected to the corresponding through electrode 212. A thick sealing film 214 made of a synthetic resin is formed on the surface of the polyimide film 213c to cover the wiring film 215, and a columnar electrode 216 made of Cu is embedded in the sealing film 214 at a position overlapping the wiring film 215. . The periphery of the columnar electrode 216 is covered with an insulating film (such as a ruthenium dioxide film) 217. Since one end of the columnar electrode 216 is in contact with the wiring film 215, the columnar electrode 216 is electrically connected to the integrated circuit 221 on the surface of the semiconductor wafer 211. A conductive pad 218 is formed on the exposed end of the columnar electrode 216. Conductive bumps 219 are fixed to the solder pads 218.

圖20所示之構成(e)，半導體晶片211背面之大致整體係以聚醯亞胺膜213c覆蓋，且配線膜215與柱狀電極216係重疊配置於聚醯亞胺膜213c。此外，凸塊219係透過具有與密封膜214的厚度大致相同高度(100~150μm)之柱狀電極216連接於配線膜215。因此，凸塊219與半導體晶片211之距離較大，且聚醯亞胺膜213c具有在與外部電路連接時，緩和自凸塊219所施加之熱傳至半導體晶片211之緩衝功能，因此可提高對熱衝擊之耐性。In the configuration (e) shown in FIG. 20, substantially the entire back surface of the semiconductor wafer 211 is covered with the polyimide film 213c, and the wiring film 215 and the columnar electrode 216 are placed on the polyimide film 213c. Further, the bump 219 is connected to the wiring film 215 through a columnar electrode 216 having a height (100 to 150 μm) substantially the same as the thickness of the sealing film 214. Therefore, the distance between the bump 219 and the semiconductor wafer 211 is large, and the polyimide film 213c has a buffer function for alleviating heat applied from the bump 219 to the semiconductor wafer 211 when connected to an external circuit, thereby improving Resistance to thermal shock.

又，圖20之構成(e)，由於聚醯亞胺膜213c亦具有緩和機械力之緩衝功能，因此亦提高在與外部電路連接時對施加於凸塊219之機械衝擊之耐性。Further, in the configuration (e) of Fig. 20, since the polyimide film 213c also has a buffering function for relieving mechanical force, it is also improved in resistance to mechanical impact applied to the bumps 219 when connected to an external circuit.

圖21之構成(f)，除聚醯亞胺膜213c僅選擇性形成於貫通電極212與柱狀電極216附近之區域之點外，係與圖20之構成(e)相同。此時，亦獲得與圖20之構成(e)相同的效果。The configuration (f) of Fig. 21 is the same as the configuration (e) of Fig. 20 except that the polyimide film 213c is selectively formed only at a point in the vicinity of the through electrode 212 and the columnar electrode 216. At this time, the same effect as the configuration (e) of Fig. 20 is also obtained.

〔專利文獻1〕日本特開2006－147810號公報(摘要、圖1)[Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-147810 (abstract, Fig. 1)

雖上述習知外部電路連接部之構成(e)(參照圖20)及構成(f)(參照圖21)，能提高對熱衝擊與機械衝擊之耐性，但由於在半導體晶片211之背面必須形成高度為100~150μm之柱狀電極216，因此不可避免的在半導體晶片211背面會產生較厚的層構造。因此，會有半導體裝置之尺寸將因此而變大(變厚)之問題。Although the configuration (e) (see FIG. 20) and the configuration (f) (see FIG. 21) of the above-described external circuit connecting portion can improve the resistance to thermal shock and mechanical shock, it must be formed on the back surface of the semiconductor wafer 211. The columnar electrode 216 having a height of 100 to 150 μm inevitably results in a thick layer structure on the back surface of the semiconductor wafer 211. Therefore, there is a problem that the size of the semiconductor device will become large (thickness).

又，由於必須在配線膜215與半導體晶片211之間形成聚醯亞胺膜213c，且在配線膜215與焊墊218之間形成柱狀電極216，因此會有外部電路連接部之形成步驟繁雜，且外部電路連接部之構成亦變複雜之問題。Further, since the polyimide film 213c must be formed between the wiring film 215 and the semiconductor wafer 211, and the columnar electrode 216 is formed between the wiring film 215 and the pad 218, the formation step of the external circuit connection portion is complicated. And the configuration of the external circuit connection portion is also complicated.

本發明係考慮該等之點而構成，其目的在於提供能以簡單的構成獲得所欲之耐熱衝擊性及耐機械衝擊性，且能減低厚度(高度)之半導體裝置之外部電路連接部構造及其形成方法。The present invention has been made in consideration of such points, and an object thereof is to provide an external circuit connecting portion structure of a semiconductor device capable of obtaining desired thermal shock resistance and mechanical shock resistance with a simple configuration and capable of reducing thickness (height). Its formation method.

本發明之另一目的在於提供能以簡單的步驟實現之半導體裝置之外部電路連接部構造及其形成方法。Another object of the present invention is to provide an external circuit connection portion structure of a semiconductor device which can be realized in a simple step and a method of forming the same.

在此未寫明之本發明其他目的，將由以下之說明及所附圖式得以明瞭。Other objects of the present invention which are not described herein will be apparent from the following description and drawings.

(1)本發明之第1觀點提供半導體裝置之外部電路連接部構造。此半導體裝置之外部電路連接部構造，其特徵在於，具備：配線膜，透過第1絕緣膜形成在半導體晶片的主面；第2絕緣膜，形成在該第1絕緣膜上以覆蓋該配線膜；以及導電性焊墊，在與該配線膜重疊之位置，形成在該第2絕緣膜上；該導電性焊墊具有配置在該第2絕緣膜上的焊墊本體，及一端連接於該焊墊本體、且另一端貫通該第2絕緣膜而接觸於該配線膜的複數個貫通部，且該焊墊本體係透過複數個該貫通部而電氣/機械連接於該配線膜；該第2絕緣膜之熱傳導性低於該導電性焊墊之該貫通部；在複數個該貫通部之間填充有形成該第2絕緣膜的材料。(1) A first aspect of the present invention provides an external circuit connection portion structure of a semiconductor device. The external circuit connection portion structure of the semiconductor device includes a wiring film formed on a main surface of the semiconductor wafer through the first insulating film, and a second insulating film formed on the first insulating film to cover the wiring film And a conductive pad formed on the second insulating film at a position overlapping the wiring film; the conductive pad has a pad body disposed on the second insulating film, and one end is connected to the solder a pad body and the other end penetrates the second insulating film to contact a plurality of through portions of the wiring film, and the pad system is electrically/mechanically connected to the wiring film through a plurality of the through portions; the second insulation The thermal conductivity of the film is lower than the through portion of the conductive pad, and a material for forming the second insulating film is filled between the plurality of through portions.

(2)本發明第1觀點之半導體裝置之外部電路連接部構造，如上述，該導電性焊墊具有配置在該第2絕緣膜上的焊墊本體，及一端連接於該焊墊本體、且另一端貫通該第2絕緣膜而接觸於該配線膜的複數個貫通部，且該焊墊本體係透過該貫通部而電氣/機械連接於該配線膜。又，該第2絕緣膜之熱傳導性低於該導電性焊墊之該貫通部，在複數個該貫通部之間填充有形成該第2絕緣膜的材料。因此，觀察自前述焊墊本體至前述配線膜之熱傳導路徑的截面時，相較於前述焊墊本體透過單一的貫通部而電氣/機械連接於前述配線膜之情況，熱傳導性低的前述第2絕緣膜的佔有比例增加。亦即，熱傳導性高的前述貫通部的佔有比例減少。此係表示前述第2絕緣膜之與前述焊墊本體重疊之部分，具有熱傳遞時之阻障之功能。(2) The external circuit connecting portion structure of the semiconductor device according to the first aspect of the present invention, wherein the conductive pad has a pad body disposed on the second insulating film, and one end is connected to the pad body, and The other end penetrates the second insulating film and contacts a plurality of through portions of the wiring film, and the pad body system is electrically/mechanically connected to the wiring film through the through portion. Further, the second insulating film has a lower thermal conductivity than the through portion of the conductive pad, and a material for forming the second insulating film is filled between the plurality of through portions. Therefore, when the cross section of the heat conduction path from the pad main body to the wiring film is observed, the second conductive portion is electrically/mechanically connected to the wiring film as compared with the case where the pad body passes through a single through portion. The proportion of the insulating film is increased. In other words, the proportion of the penetration portion having high thermal conductivity is reduced. This means that the portion of the second insulating film that overlaps the pad body has a function of blocking at the time of heat transfer.

因此，可抑制凸塊及球具有之熱傳至前述配線膜，且緩和熱透過前述導電性焊墊而施加在前述半導體晶片之影響。亦即，相較於前述焊墊本體透過單一的貫通部而電氣/機械連接於前述配線膜之情況，可改善前述外部電路連接部之耐熱衝擊性。Therefore, it is possible to suppress the heat of the bump and the ball from being transmitted to the wiring film, and to alleviate the influence of heat applied to the semiconductor wafer by the conductive pad. That is, the thermal shock resistance of the external circuit connecting portion can be improved as compared with the case where the pad body is electrically/mechanically connected to the wiring film through a single through portion.

又，由於前述第2絕緣膜之與前述焊墊本體重疊之部分，亦具有緩和機械力之緩衝功能，因此亦抑制自外部所施加之力。其結果，相較於前述焊墊本體透過單一的貫通部而電氣/機械連接於前述配線膜之情況，亦改善對機械衝擊之耐性。Further, since the portion of the second insulating film that overlaps the pad body also has a buffering function for relieving mechanical force, the force applied from the outside is also suppressed. As a result, the resistance to mechanical shock is improved as compared with the case where the pad body is electrically/mechanically connected to the wiring film through a single through portion.

因此，可獲得所欲之耐熱衝擊性及耐機械衝擊性，且能因應所改善之耐熱衝擊/機械衝擊性減低該外部電路連接部之厚度(高度)。Therefore, the desired thermal shock resistance and mechanical shock resistance can be obtained, and the thickness (height) of the external circuit connecting portion can be reduced in accordance with the improved thermal shock resistance/mechanical impact resistance.

再者，由於使前述第2絕緣膜介於之間而使前述焊墊本體與前述配線膜相對向，且藉由複數個前述貫通部實現前述焊墊本體與前述配線膜之電氣連接/機械連接，因此構成較簡單。Furthermore, the pad body is opposed to the wiring film by interposing the second insulating film therebetween, and electrical connection/mechanical connection between the pad body and the wiring film is realized by a plurality of the through portions. Therefore, the composition is relatively simple.

(3)本發明第1觀點之半導體裝置之外部電路連接部之較佳例中，該第2絕緣膜之厚度，在與該配線膜重疊的位置為10μm以上。本例中，確實獲得本發明之效果。(3) In a preferred example of the external circuit connecting portion of the semiconductor device according to the first aspect of the invention, the thickness of the second insulating film is 10 μm or more at a position overlapping the wiring film. In this example, the effects of the present invention are surely obtained.

本發明第1觀點之半導體裝置之外部電路連接部之另一較佳例中，該焊墊本體延伸至比複數個該貫通部更外側。In another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the pad body extends beyond the plurality of the through portions.

本發明第1觀點之半導體裝置之外部電路連接部之另一較佳例中，複數個該貫通部之截面形狀為圓形或圓環形，且配置成同心狀。In another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the plurality of through portions have a circular or circular cross-sectional shape and are arranged concentrically.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，複數個該貫通部之截面形狀為多角形或多角環形，且配置成同心狀。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the plurality of through portions have a polygonal or polygonal annular shape and are arranged concentrically.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，複數個該貫通部並非同心狀，而是彼此分開配置在該配線膜上。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the plurality of the through portions are not concentric, but are disposed apart from each other on the wiring film.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，該第2絕緣膜之與該導電性焊墊重疊之部分的厚度，係設定為大於其以外之部分的厚度。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the thickness of the portion of the second insulating film overlapping the conductive pad is set to be larger than a thickness of the portion other than the conductive pad. .

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，在該導電性焊墊固設外部電極(焊球等)，該外部電極之側面係以補強用樹脂圍繞。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, an external electrode (such as a solder ball) is fixed to the conductive pad, and a side surface of the external electrode is surrounded by a reinforcing resin.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，該焊墊本體分割為第1部分與第2部分，在該第1部分連接複數個該貫通部之一個，而在該第2部分連接複數個該貫通部之另一個。此時，例如能將該第1部分作為訊號或電源用，將該第2部分作為接地用。較佳為，分別電氣連接於該第1部分及該第2部分之第1及第2連接用導電性焊墊係個別設置。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the pad body is divided into a first portion and a second portion, and one of the plurality of through portions is connected to the first portion. The other part of the plurality of through portions is connected to the second portion. In this case, for example, the first portion can be used as a signal or a power source, and the second portion can be used as a ground. Preferably, the first and second connection conductive pads electrically connected to the first portion and the second portion are separately provided.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，該第2絕緣膜，係使糊狀之絕緣性材料硬化而成者。糊狀之絕緣性材料，例舉有耐焊劑、環氧樹脂等。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the second insulating film is formed by curing a paste-like insulating material. The paste-like insulating material is exemplified by a solder resist, an epoxy resin, or the like.

本發明第1觀點之半導體裝置之外部電路連接部之又另一較佳例中，該導電性焊墊，係使糊狀之導電性材料硬化而成者。糊狀之導電性材料，例舉有焊料糊、銅(Cu)糊、銀(Ag)糊等。In still another preferred embodiment of the external circuit connecting portion of the semiconductor device according to the first aspect of the present invention, the conductive pad is formed by curing a paste-like conductive material. The paste-like conductive material is exemplified by a solder paste, a copper (Cu) paste, a silver (Ag) paste, or the like.

(4)本發明之第2觀點提供半導體裝置之外部電路連接部之形成方法。此半導體裝置之外部電路連接部構造之形成方法，其特徵在於，具備：配線膜形成步驟，透過第1絕緣膜在半導體晶片之主面形成配線膜；第2絕緣膜形成步驟，將在與該配線膜重疊之位置具有複數個透孔的第2絕緣膜形成在該第1絕緣膜上以覆蓋該配線膜；以及導電性焊墊形成步驟，在該第2絕緣膜上載置導電材料，且將該導電材料填充於該第2絕緣膜之複數個該透孔，以形成導電性焊墊；載置於該第2絕緣膜上之該導電材料，係形成該導電性焊墊的本體部；填充於複數個該透孔之該導電材料，係形成該導電性焊墊的複數個貫通部，該焊墊本體係透過該等貫通部電氣/機械連接於該配線膜；該第2絕緣膜之熱傳導性低於該導電性焊墊的該貫通部。(4) A second aspect of the present invention provides a method of forming an external circuit connection portion of a semiconductor device. A method of forming an external circuit connecting portion structure of the semiconductor device, comprising: forming a wiring film, forming a wiring film on a main surface of the semiconductor wafer through the first insulating film; and forming a second insulating film; a second insulating film having a plurality of through holes at a position where the wiring film overlaps is formed on the first insulating film to cover the wiring film; and a conductive pad forming step is performed on the second insulating film, and the conductive material is placed thereon The conductive material is filled in the plurality of through holes of the second insulating film to form a conductive pad; the conductive material placed on the second insulating film forms a body portion of the conductive pad; The conductive material of the plurality of through holes forms a plurality of through portions of the conductive pads, and the pad system is electrically/mechanically connected to the wiring film through the through portions; heat conduction of the second insulating film The property is lower than the through portion of the conductive pad.

(5)本發明第2觀點之半導體裝置之外部電路連接部構造之形成方法，如上述，透過第1絕緣膜在半導體晶片之主面形成配線膜之後，將在與前述配線膜重疊之位置具有複數個透孔之第2絕緣膜形成在前述第1絕緣膜上以覆蓋前述配線膜。接著，將導電材料載置於前述第2絕緣膜上，且將該導電材料填充於前述第2絕緣膜之複數個前述透孔，以形成導電性焊墊。載置於前述第2絕緣膜上之前述導電材料，係形成前述導電性材料之本體部。又，填充於複數個前述透孔之前述導電性材料，係形成前述導電性焊墊之複數個貫通部，前述焊墊本體係透過該等貫通部電氣/機械連接於前述配線膜。前述第2絕緣膜之熱傳導性低於前述導電性焊墊之前述貫通部。是以，形成本發明第1觀點之半導體裝置之外部電路連接部構造。(5) The method of forming the structure of the external circuit connection portion of the semiconductor device according to the second aspect of the present invention, wherein the wiring film is formed on the main surface of the semiconductor wafer through the first insulating film, and then has a position overlapping the wiring film. A second insulating film having a plurality of through holes is formed on the first insulating film to cover the wiring film. Next, a conductive material is placed on the second insulating film, and the conductive material is filled in a plurality of the through holes of the second insulating film to form a conductive pad. The conductive material placed on the second insulating film forms a main portion of the conductive material. Further, the conductive material filled in the plurality of through holes forms a plurality of penetration portions of the conductive pads, and the pad system is electrically/mechanically connected to the wiring film through the through portions. The thermal conductivity of the second insulating film is lower than the through portion of the conductive pad. Therefore, the external circuit connection portion structure of the semiconductor device according to the first aspect of the present invention is formed.

又，由於僅進行該等步驟，因此能以簡單的步驟形成本發明第1觀點之半導體裝置之外部電路連接部構造。Moreover, since only these steps are performed, the external circuit connection portion structure of the semiconductor device according to the first aspect of the present invention can be formed in a simple procedure.

(6)本發明第2觀點之半導體裝置之外部電路連接部構造之形成方法之較佳例中，形成該第2絕緣膜之步驟，係使糊狀絕緣性材料形成為膜狀以使其硬化的步驟。糊狀之絕緣性材料，例舉有耐焊劑、環氧樹脂等。(6) In a preferred embodiment of the method for forming the structure of the external circuit connecting portion of the semiconductor device according to the second aspect of the present invention, the step of forming the second insulating film is such that the paste insulating material is formed into a film shape to be hardened. A step of. The paste-like insulating material is exemplified by a solder resist, an epoxy resin, or the like.

本發明第2觀點之半導體裝置之外部電路連接部構造之形成方法之另一較佳例中，該導電材料，係使用焊料糊、銅(Cu)糊、銀(Ag)糊等糊狀導電材料。In another preferred embodiment of the method for forming the structure of the external circuit connecting portion of the semiconductor device according to the second aspect of the present invention, the conductive material is a paste conductive material such as a solder paste, a copper (Cu) paste, or a silver (Ag) paste. .

本發明第2觀點之半導體裝置之外部電路連接部構造之形成方法之另一較佳例中，包含在該導電性焊墊固設外部電極(焊球等)的步驟、及形成圍繞該外部電極側面之補強用樹脂的步驟。In another preferred embodiment of the method for forming the structure of the external circuit connection portion of the semiconductor device according to the second aspect of the present invention, the method includes: a step of fixing an external electrode (such as a solder ball) on the conductive pad, and forming a surrounding electrode The step of reinforcing the resin on the side.

本發明第2觀點之半導體裝置之外部電路連接部構造之形成方法之另一較佳例中，以該第2絕緣膜之與該導電性焊墊重疊之部分的厚度大於其以外之部分的厚度之方式，將該第2絕緣膜圖案化。In another preferred embodiment of the method for forming the structure of the external circuit connecting portion of the semiconductor device according to the second aspect of the present invention, the thickness of the portion of the second insulating film overlapping the conductive pad is larger than the thickness of the portion other than the conductive film. In this manner, the second insulating film is patterned.

(7)本發明中，「第1絕緣膜」及「配線膜」之材質係為任意。(7) In the present invention, the materials of the "first insulating film" and the "wiring film" are arbitrary.

「第2絕緣膜」，只要熱傳導性低於前述導電性焊墊之前述貫通部，則可使用任意者。較佳為有機樹脂膜(例如環氧樹脂等)，但並非限於此。又，較佳為使糊狀之絕緣性材料硬化而成者，糊狀之絕緣性材料可使用例如耐焊劑、光阻劑、環氧樹脂、及聚醯亞胺等。其耐熱性只要可耐於半導體裝置之構裝步驟即可，因此只要有250~260℃程度即足夠。考慮可使用光微影法時，以具有感光性者較佳。The "second insulating film" may be any one as long as the thermal conductivity is lower than the through portion of the conductive pad. An organic resin film (for example, an epoxy resin or the like) is preferred, but is not limited thereto. Further, it is preferable to cure the paste-like insulating material, and for example, a solder resist, a photoresist, an epoxy resin, and a polyimide may be used as the insulating material for the paste. The heat resistance is sufficient as long as it can withstand the assembly process of the semiconductor device, and therefore it is sufficient if it is 250 to 260 °C. When it is considered that the photolithography method can be used, it is preferable to have photosensitivity.

「導電性焊墊」，只要為能貫通前述第2絕緣膜而形成接觸於前述配線膜之複數個貫通部，藉此，透過前述貫通部能將前述導電性焊墊電氣連接於前述配線膜者即可。The "conductive pad" is a plurality of penetration portions that are in contact with the wiring film so as to penetrate the second insulating film, thereby electrically connecting the conductive pad to the wiring film through the through portion. Just fine.

「糊狀之導電材料」，只要為能藉由塗布填充於前述第2絕緣膜之前述透孔，可藉由加熱、紫外線照射等使之硬化之導電材料，則可使用任意。The "paste-like conductive material" may be any conductive material that can be cured by heating, ultraviolet irradiation or the like by coating the through hole filled in the second insulating film.

根據本發明半導體裝置之外部電路連接部構造及其形成方法，可獲得下述效果，(a)以簡單的構成獲得所欲之耐熱衝擊性及耐機械衝擊性，且能減低外部電路連接部之厚度、及(b)能以簡單的方法實現。According to the structure of the external circuit connecting portion of the semiconductor device of the present invention and the method of forming the same, the following effects can be obtained, (a) obtaining a desired thermal shock resistance and mechanical shock resistance with a simple configuration, and reducing the connection portion of the external circuit. The thickness, and (b) can be achieved in a simple manner.

以下，參照所附圖式詳細說明本發明最佳實施形態。Hereinafter, the best mode for carrying out the invention will be described in detail with reference to the accompanying drawings.

(第1實施形態)(First embodiment)

圖1(a)及(b)係顯示本發明第1實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖、及沿A－A線的截面圖。1 (a) and (b) are a plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a first embodiment of the present invention, and a cross-sectional view taken along line A-A.

該半導體裝置之外部電路連接部，具備形成在半導體晶片(未圖示)之一主面(例如其表面或背面)的絕緣膜(第1絕緣膜)51、以既定圖案形成在絕緣膜51上的配線膜20、形成在絕緣膜51上以覆蓋配線膜20的絕緣性耐焊劑膜(第2絕緣膜)10、及形成在耐焊劑膜10上之具有圓形平面形狀的導電性焊墊30。The external circuit connecting portion of the semiconductor device includes an insulating film (first insulating film) 51 formed on one main surface (for example, a front surface or a back surface thereof) of a semiconductor wafer (not shown), and is formed on the insulating film 51 in a predetermined pattern. The wiring film 20, the insulating solder resist film (second insulating film) 10 formed on the insulating film 51 to cover the wiring film 20, and the conductive pad 30 having a circular planar shape formed on the solder resist film 10. .

耐焊劑膜10在與配線膜20重疊之部位，對應配線膜20之厚度而***。在配線膜20上之耐焊劑膜10之厚度為T，可視需要而任意設定。The solder resist film 10 is raised at a portion overlapping the wiring film 20 in accordance with the thickness of the wiring film 20. The thickness of the solder resist film 10 on the wiring film 20 is T, which can be arbitrarily set as needed.

此處，設為T＝20μm，但設為10μm~15μm亦可。將厚度T設為10μm未滿(或15μm未滿)時，會有無法充分獲得本發明之提高耐熱衝擊/機械衝擊之效果之虞。然而，藉由耐焊劑膜10之改良等而充分獲得本發明之效果時，當然亦可設為10μm未滿。另一方面，厚度T之最大值並無限制，雖亦可大於20μm(例如設為T＝30μm或50μm亦可)，但在構裝於CSP之半導體裝置，由於厚度T小較佳，因此不會設的太大。Here, it is set to T=20 μm, but it may be 10 μm to 15 μm. When the thickness T is set to 10 μm or less (or 15 μm or less), the effect of improving the thermal shock resistance/mechanical impact of the present invention may not be sufficiently obtained. However, when the effect of the present invention is sufficiently obtained by the improvement of the solder resist film 10 or the like, it is of course possible to set it to 10 μm or less. On the other hand, the maximum value of the thickness T is not limited, and may be larger than 20 μm (for example, T=30 μm or 50 μm), but in the semiconductor device mounted on the CSP, since the thickness T is small, it is not It will be too big.

圖20及圖21所示之習知構成(e)及(f)所使用之柱狀電極216，係厚度(高度)為100~150μm左右之大小，但本實施形態中，可設定為遠小於其之值(T＝20μm)，是以，外部電路連接部整體之厚度亦能設的格外的小。The columnar electrode 216 used in the conventional configurations (e) and (f) shown in Figs. 20 and 21 has a thickness (height) of about 100 to 150 μm. However, in the present embodiment, it can be set to be much smaller. The value (T = 20 μm) is such that the thickness of the entire external circuit connecting portion can be made small.

耐焊劑膜10覆蓋絕緣膜51之整面(亦即半導體晶片之該主面整面)亦可，部分地覆蓋亦可。The solder resist film 10 may cover the entire surface of the insulating film 51 (that is, the entire surface of the main surface of the semiconductor wafer), and may be partially covered.

如圖2所明示，絕緣膜20具有大致圓形之平面形狀，透過其細線狀之引出部而電氣連接於半導體晶片內部之積體電路。配線膜20之厚度並未特別限定，可設為例如2~3μm。配線膜20可使用例如Cu、Ni等而能藉由公知之鍍敷法加以形成。As is apparent from Fig. 2, the insulating film 20 has a substantially circular planar shape and is electrically connected to an integrated circuit inside the semiconductor wafer through the thin-line lead-out portion. The thickness of the wiring film 20 is not particularly limited, and may be, for example, 2 to 3 μm. The wiring film 20 can be formed by a known plating method using, for example, Cu, Ni, or the like.

如圖1(a)及(b)所示，耐焊劑膜10在與配線膜20重疊之位置，具有形成為同心圓狀之第1環狀透孔14及第2環狀透孔15。第2環狀透孔15位在第1環狀透孔14之外側。在第1環狀透孔14及第2環狀透孔15分別填充有導電性焊墊30之圓環狀貫通部30a。該等兩個貫通部30a，一者(上端)係露出於耐焊劑膜10上而連接於與外部電路之連接所使用之焊墊本體30b，另一者(下端)係貫通耐焊劑膜10而接觸於配線膜20。是以，導電性焊墊30之焊墊本體30b係透過兩個貫通部30a而電氣連接於配線膜20。因此，將外部電路固設於焊墊本體30b時，其外部電路係電氣連接於該半導體晶片內部之積體電路。As shown in FIGS. 1(a) and 1(b), the solder resist film 10 has a first annular through hole 14 and a second annular through hole 15 which are formed concentrically at a position overlapping the wiring film 20. The second annular through hole 15 is located on the outer side of the first annular through hole 14. Each of the first annular through hole 14 and the second annular through hole 15 is filled with an annular through portion 30a of the conductive pad 30. One of the two penetration portions 30a is exposed on the solder resist film 10 and connected to the pad main body 30b used for connection to an external circuit, and the other (lower end) is passed through the solder resist film 10. Contact with the wiring film 20. Therefore, the pad main body 30b of the conductive pad 30 is electrically connected to the wiring film 20 through the two penetration portions 30a. Therefore, when the external circuit is fixed to the pad main body 30b, the external circuit is electrically connected to the integrated circuit inside the semiconductor wafer.

又，耐焊劑膜10在與導電性焊墊30之焊墊本體30b重疊之部位，於第1環狀透孔14(內側之貫通部30a)之內側具有圓柱狀中央部11，在第1環狀透孔14與第2環狀透孔15(內外兩個貫通部30a)之間具有圓環狀第1環狀部12，在第2環狀透孔15(外側之貫通部30a)之外側具有第2環狀部13。焊墊本體30b之直徑大於外側的貫通部30a之直徑。Further, the solder resist film 10 has a columnar central portion 11 inside the first annular through hole 14 (the inner through portion 30a) at a portion overlapping the pad main body 30b of the conductive pad 30, and is in the first ring. The annular through hole 14 and the second annular through hole 15 (the inner and outer two through portions 30a) have an annular first annular portion 12 and are outside the second annular through hole 15 (the outer through portion 30a). The second annular portion 13 is provided. The diameter of the pad body 30b is larger than the diameter of the outer through portion 30a.

如上述，本第1實施形態中，導電性焊墊30具有露出於耐焊劑膜10上之大致圓板狀焊墊本體30b、及埋設於耐焊劑膜10內部之兩個圓環狀貫通部30a。此外，由於在導電性焊墊30之兩個貫通部30a之間存在有熱傳導率低於貫通部30a之耐焊劑膜10的中央部11、第1環狀部12、及第2環狀部13，因此即使厚度(高度)小於圖20及圖21所示之習知構成(e)及(f)之柱狀電極216，亦可充分抑制施加在焊墊本體30b之熱傳至配線膜20(或半導體晶片內部之積體電路)。此點與僅使習知構成(e)及(f)之柱狀電極216變薄(變低)而得者明顯不同。As described above, in the first embodiment, the conductive pad 30 has a substantially disk-shaped pad main body 30b exposed on the solder resist film 10, and two annular through-hole portions 30a embedded in the solder resist film 10. . Further, the central portion 11, the first annular portion 12, and the second annular portion 13 of the solder resist film 10 having a thermal conductivity lower than that of the penetration portion 30a are present between the two penetration portions 30a of the conductive pad 30. Therefore, even if the thickness (height) is smaller than the columnar electrodes 216 of the conventional configurations (e) and (f) shown in FIGS. 20 and 21, the heat applied to the pad main body 30b can be sufficiently suppressed from being transmitted to the wiring film 20 ( Or an integrated circuit inside the semiconductor wafer). This point is significantly different from the fact that only the columnar electrodes 216 of the conventional configurations (e) and (f) are thinned (lowered).

接著，參照圖2~圖5說明具有以上構成之本發明第1實施形態之半導體裝置之外部電路連接部之形成方法。Next, a method of forming an external circuit connecting portion of the semiconductor device according to the first embodiment of the present invention having the above configuration will be described with reference to Figs. 2 to 5 .

首先，藉由公知之方法(例如光微影與蝕刻)，如圖2所示，在絕緣膜51上形成具有既定圖案之配線膜20。此處，形成與導電性焊墊30之焊墊本體30b相同的大致圓形圖案。First, a wiring film 20 having a predetermined pattern is formed on the insulating film 51 by a known method (for example, photolithography and etching). Here, the same substantially circular pattern as the pad main body 30b of the conductive pad 30 is formed.

接著，如圖3所示，藉由網版印刷法，以既定厚度將糊狀之耐焊劑43選擇性印刷(塗布)在絕緣膜51上，將其加熱而使之硬化，以形成具有第1環狀透孔14及第2環狀透孔15之耐焊劑膜10。Next, as shown in FIG. 3, the paste-like solder resist 43 is selectively printed (coated) on the insulating film 51 at a predetermined thickness by a screen printing method, and heated to be hardened to form the first The solder resist film 10 of the annular through hole 14 and the second annular through hole 15.

亦即，首先，準備形成有開口部40a,40b及40c與遮斷部40d之金屬光罩40以獲得所欲的圖案，並以圖3所示之狀態固定。該金屬光罩40，係藉由複數個遮斷部40d形成有圓柱形開口部40a、圓筒形開口部40b、及該等外側之開口部40c，且遮斷部40d彼此係藉由連結部40e相互連結。That is, first, the metal mask 40 having the openings 40a, 40b, and 40c and the blocking portion 40d is prepared to obtain a desired pattern, and is fixed in the state shown in FIG. In the metal mask 40, a cylindrical opening 40a, a cylindrical opening 40b, and the outer opening 40c are formed by a plurality of blocking portions 40d, and the blocking portions 40d are connected to each other by a connecting portion. 40e is connected to each other.

耐焊劑43，能使用構裝至PWB時所使用之耐熱溫度約250~260℃之耐焊劑(例如環氧樹脂系、聚醯亞胺系)。As the solder resist 43, a solder resist (for example, an epoxy resin or a polyimide) which is used in a PWB heat-resistant temperature of about 250 to 260 ° C can be used.

接著，在金屬光罩40上配置網版41，在網版41上載置糊狀之耐焊劑43，以刮漿板42延展於網版41整面。如此，耐焊劑43係通過網版41之微細孔(未圖示)而被壓入金屬光罩40內部。由於耐焊劑43未進入具有遮斷部40d之部分，其結果，如圖4所示，將具有配置成同心圓狀之第1環狀透孔14與第2環狀透孔15之耐焊劑膜10形成在絕緣膜51上。第1環狀透孔14與第2環狀透孔15係於配線膜20重疊成同心狀。Next, a screen 41 is placed on the metal mask 40, and a paste-like solder resist 43 is placed on the screen 41, and the squeegee 42 is spread over the entire surface of the screen 41. In this manner, the solder resist 43 is pressed into the inside of the metal mask 40 through the fine holes (not shown) of the screen 41. Since the solder resist 43 does not enter the portion having the blocking portion 40d, as shown in FIG. 4, the solder resist film having the first annular through hole 14 and the second annular through hole 15 arranged concentrically is provided. 10 is formed on the insulating film 51. The first annular through hole 14 and the second annular through hole 15 are formed so as to be concentrically overlapped with the wiring film 20.

之後，在耐焊劑膜10上，準備圖5所示之金屬光罩44，且以圖5所示之狀態固定。該金屬光罩44係藉由遮斷部44b形成在圓形開口部44a與配線膜20重疊之位置。開口部44a係形成在待形成焊墊本體30b之位置。Thereafter, the metal mask 44 shown in Fig. 5 is prepared on the solder resist film 10, and is fixed in the state shown in Fig. 5. The metal mask 44 is formed at a position where the circular opening portion 44a overlaps the wiring film 20 by the blocking portion 44b. The opening portion 44a is formed at a position where the pad body 30b is to be formed.

接著，在金屬光罩44上配置網版45，在網版45上載置焊料糊(糊狀焊料)47，以刮漿板46延展於網版45整面。如此，焊料糊47係通過網版45之微細孔(未圖示)而填充於金屬光罩44之開口部44a。由於焊料糊47未進入具有遮斷部44d之部分，其結果，如圖1所示，藉由焊料糊47形成大致圓板形之焊墊本體30b。Next, a screen 45 is placed on the metal mask 44, and a solder paste (paste solder) 47 is placed on the screen 45, and the squeegee 46 is spread over the entire surface of the screen 45. In this manner, the solder paste 47 is filled in the opening 44a of the metal mask 44 through the fine holes (not shown) of the screen 45. Since the solder paste 47 does not enter the portion having the blocking portion 44d, as a result, as shown in FIG. 1, the substantially disk-shaped pad body 30b is formed by the solder paste 47.

將焊料糊47壓入於金屬光罩44之開口部44a內時，亦填充於開口部44a內所露出之耐焊劑膜10之第1環狀透孔14與第2環狀透孔15。其結果，如圖1所示，與藉由焊料糊47形成大致圓板形焊墊本體30b同時形成圓環形之兩個貫通部30a。之後，藉由溶劑之揮發等，使焊料糊47在維持此狀態下硬化。When the solder paste 47 is pressed into the opening 44a of the metal mask 44, the first annular through hole 14 and the second annular through hole 15 of the solder resist film 10 exposed in the opening 44a are also filled. As a result, as shown in FIG. 1, two substantially penetrating portions 30a are formed in a circular shape while forming a substantially disk-shaped pad main body 30b by the solder paste 47. Thereafter, the solder paste 47 is cured by maintaining the state by volatilization of the solvent or the like.

經過以上之步驟，形成圖1所示之本第1實施形態之半導體裝置之外部電路連接部。Through the above steps, the external circuit connecting portion of the semiconductor device of the first embodiment shown in Fig. 1 is formed.

此外，取代焊料糊47，使用銅(Cu)糊或銀(Ag)糊、或其他糊狀導電性材料，來形成導電性焊墊30亦可。又，不使用糊狀導電性材料，藉由以使用光罩之鍍敷法選擇性堆積Cu、Ni等之金屬來形成導電性焊墊30亦可。Further, instead of the solder paste 47, a conductive pad 30 may be formed using a copper (Cu) paste or a silver (Ag) paste or another paste-like conductive material. Further, the conductive pad 30 may be formed by selectively depositing a metal such as Cu or Ni by a plating method using a photomask without using a paste conductive material.

如上述，於本第1實施形態之半導體裝置之外部電路連接部之構造，導電性焊墊30具備配置在耐焊劑膜10上的焊墊本體30b、及貫通耐焊劑膜10而接觸於配線膜20的兩個圓環狀貫通部30a，且焊墊本體30b係透過該等貫通部30a電氣連接於配線膜20。又，熱傳導性低於導電性焊墊30之貫通部30a的耐焊劑膜10之中央部11、第1環狀部12、及第2環狀部13，係配置在焊墊本體30b與配線膜20之間。因此，耐焊劑膜10之與焊墊本體30b重疊之中央部11、第1環狀部12、及第2環狀部13(尤其位在耐焊劑膜10之比貫通部30a內側之中央部11與第1環狀部12)，成為熱自焊墊本體30b傳至配線膜20(或半導體晶片)時之緩衝(阻障)，因此能有效抑制凸塊及球體具有之熱自焊墊本體30b傳至配線膜20。亦即，可緩和透過焊墊本體30b傳至配線膜20之熱之影響。其結果，由於配線膜20(或前述半導體晶片)所受之熱量減少，因此相較於僅有一個貫通部之習知一般構造，能改善由導電性焊墊30與耐焊劑膜10之中央部11、第1環狀部12、及第2環狀部13所構成之該外部電路連接部之耐熱衝擊性。As described above, in the structure of the external circuit connecting portion of the semiconductor device of the first embodiment, the conductive pad 30 includes the pad main body 30b disposed on the solder resist film 10, and the solder resist film 10 is passed through to the wiring film. The two annular through portions 30a of the 20 are electrically connected to the wiring film 20 through the through portions 30a. Further, the central portion 11, the first annular portion 12, and the second annular portion 13 of the solder resist film 10 having a thermal conductivity lower than the penetration portion 30a of the conductive pad 30 are disposed on the pad main body 30b and the wiring film. Between 20. Therefore, the central portion 11, the first annular portion 12, and the second annular portion 13 of the solder resist film 10 overlapping the pad main body 30b (especially in the central portion 11 of the solder resist film 10 inside the through portion 30a) Since the first annular portion 12) serves as a buffer (barrier) when the heat is transferred from the pad main body 30b to the wiring film 20 (or the semiconductor wafer), it is possible to effectively suppress the thermal self-pad body 30b of the bump and the ball. It is transmitted to the wiring film 20. That is, the influence of heat transmitted to the wiring film 20 through the pad main body 30b can be alleviated. As a result, since the heat received by the wiring film 20 (or the semiconductor wafer) is reduced, the central portion of the conductive pad 30 and the solder resist film 10 can be improved compared to the conventional structure having only one through portion. 11. The thermal shock resistance of the external circuit connecting portion formed by the first annular portion 12 and the second annular portion 13.

又，耐焊劑膜10之與焊墊本體30b重疊之中央部11、第1環狀部12、及第2環狀部13，由於亦具有緩和機械力之緩衝功能，因此亦可有效抑制自外部所施加之力。其結果，亦能改善對機械衝擊之耐性。Further, the central portion 11, the first annular portion 12, and the second annular portion 13 of the solder resist film 10 which overlap with the pad main body 30b also have a buffering function for relieving mechanical force, and therefore can be effectively suppressed from the outside. The force exerted. As a result, the resistance to mechanical shock can also be improved.

再者，使耐焊劑膜10之中央部11、第1環狀部12、及第2環狀部13介於之間而使焊墊本體30b與配線膜20相對向，且藉由兩個圓環狀貫通部30a而實現焊墊本體30b與配線膜20之電氣連接，因此不需要上述習知外部電路連接部之構成(e)及(f)(參照圖20及圖21)所使用之柱狀電極216。因此，能大幅減低外部電路連接部之厚度，且構成亦非常簡單。亦即，比起上述習知外部電路連接部之構成(e)及(f)，能使該外部電路連接部(或半導體裝置)之厚度格外的變薄，且構造亦能變得更簡單。Further, the center portion 11, the first annular portion 12, and the second annular portion 13 of the solder resist film 10 are interposed therebetween, and the pad main body 30b faces the wiring film 20, and is formed by two circles. Since the ring-shaped through portion 30a electrically connects the pad main body 30b and the wiring film 20, the columns used in the above-described conventional external circuit connecting portions (e) and (f) (see FIGS. 20 and 21) are not required. Electrode 216. Therefore, the thickness of the external circuit connecting portion can be greatly reduced, and the configuration is also very simple. That is, the thickness of the external circuit connecting portion (or semiconductor device) can be made thinner and the structure can be made simpler than the above-described configurations (e) and (f) of the conventional external circuit connecting portion.

又，本第1實施形態之外部電路連接部，在絕緣膜51上形成具有第1環狀透孔14與第2環狀透孔15之耐焊劑膜10後，在耐焊劑膜10上形成導電性焊墊30以填充第1環狀透孔14與第2環狀透孔15，藉此能僅以透過第1環狀透孔14與第2環狀透孔15將焊墊本體30b與配線膜20相互電氣連接而形成。是以，能以網版印刷等之簡單的步驟實現。Further, in the external circuit connecting portion of the first embodiment, the solder resist film 10 having the first annular through hole 14 and the second annular through hole 15 is formed on the insulating film 51, and then conductive is formed on the solder resist film 10. The pad 30 fills the first annular through hole 14 and the second annular through hole 15 , whereby the pad body 30 b and the wiring can be made only through the first annular through hole 14 and the second annular through hole 15 . The films 20 are formed by electrically connecting to each other. Therefore, it can be realized by simple steps such as screen printing.

此外，如上述，本第1實施形態中，不僅改善對熱衝擊及機械衝擊之耐性，亦能減低外部電路連接部(或半導體裝置)之厚度與簡化構成，但本發明並非限於此。例如，雖減低外部電路連接部之厚度(高度)、亦簡化構成，但對熱衝擊及機械衝擊之耐性與習知相同之情形，亦包含於本發明。此外，相反地，對熱衝擊及機械衝擊之耐性雖改善，但外部電路連接部之厚度(高度)與習知相同之情況亦包含於本發明。Further, as described above, in the first embodiment, not only the resistance to thermal shock and mechanical shock but also the thickness and simplified configuration of the external circuit connecting portion (or semiconductor device) can be reduced, but the present invention is not limited thereto. For example, although the thickness (height) of the external circuit connecting portion is reduced and the configuration is simplified, the case where the resistance to thermal shock and mechanical shock is the same as the conventional one is also included in the present invention. Further, conversely, the resistance to thermal shock and mechanical shock is improved, but the thickness (height) of the external circuit connecting portion is also included in the present invention.

本第1實施形態中，由於導電性焊墊30本身作為外部電極使用，亦即，由於導電性焊墊30成為焊墊，因此該半導體裝置之外部電極的構成係成為平面柵陣列(land Grid Array,LGA)。然而，在導電性焊墊30上固設以Ni(鎳)或Au(金)被覆金屬球表面之焊球(未圖示)時，成為球柵陣列(Ball Grid Array,BGA)。In the first embodiment, since the conductive pad 30 itself is used as an external electrode, that is, since the conductive pad 30 serves as a pad, the external electrode of the semiconductor device is configured as a planar grid array (land Grid Array). , LGA). However, when a solder ball (not shown) coated with Ni (nickel) or Au (gold) on the surface of the metal ball is fixed to the conductive pad 30, it is a Ball Grid Array (BGA).

此外，本第1實施形態中，雖使用耐焊劑膜10作為第2絕緣膜，但本發明並未限於此。只要熱傳導性低於導電性焊墊30之貫通部30a，亦可使用其他任意之絕緣膜。Further, in the first embodiment, the solder resist film 10 is used as the second insulating film, but the present invention is not limited thereto. Any other insulating film may be used as long as the thermal conductivity is lower than the through portion 30a of the conductive pad 30.

又，本第1實施形態中，雖以網版印刷法形成耐焊劑膜10，但本發明並未限於此，藉由其他任意之方法形成亦可。例如，使用感光性之耐焊劑43，藉由公知之光微影法及蝕刻法將耐焊劑43之膜圖案化，形成具有第1環狀透孔14與第2環狀透孔15之耐焊劑膜10亦可。此外，取代耐焊劑膜10，將絕緣性薄膜層壓後，藉由雷射蝕刻等將其蝕刻，來形成與耐焊劑膜10同樣圖案化之第2絕緣膜亦可。Further, in the first embodiment, the solder resist film 10 is formed by the screen printing method, but the present invention is not limited thereto, and may be formed by any other method. For example, the photosensitive solder resist 43 is used to pattern the film of the solder resist 43 by a known photolithography method and etching method to form a solder resist having the first annular through hole 14 and the second annular through hole 15. The film 10 can also be used. Further, in place of the solder resist film 10, after laminating the insulating film, it may be etched by laser etching or the like to form a second insulating film which is patterned similarly to the solder resist film 10.

又，本第1實施形態中，雖亦以使用焊料糊之網版印刷法形成導電性焊墊30，但本發明並未限於此。例如，藉由使用光罩之電鍍法，選擇性形成金屬膜亦可。Further, in the first embodiment, the conductive pad 30 is formed by a screen printing method using a solder paste, but the present invention is not limited thereto. For example, a metal film can be selectively formed by a plating method using a photomask.

(第2實施形態)(Second embodiment)

圖6(a)及(b)係顯示本發明第2實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖與截面圖。(a) and (b) of FIG. 6 are a plan view and a cross-sectional view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a second embodiment of the present invention.

本實施形態之外部電路連接部，於第1實施形態之外部電路連接部中，僅在導電性焊墊30上固設有焊球33之點不同。除此之外之點與第1實施形態之外部電路連接部為相同之構成。是以，賦予與圖1所示之第1實施形態之外部電路連接部相同之符號而省略其說明。In the external circuit connecting portion of the first embodiment, the solder ball 33 is fixed only to the conductive pad 30 in the external circuit connecting portion of the first embodiment. The other points are the same as those of the external circuit connecting portion of the first embodiment. The same reference numerals are given to the external circuit connecting portions of the first embodiment shown in FIG. 1, and the description thereof is omitted.

本第2實施形態中，由於使用焊球33作為外部電極，因此該半導體裝置之外部電極係BGA。In the second embodiment, since the solder ball 33 is used as the external electrode, the external electrode of the semiconductor device is BGA.

(第3實施形態)(Third embodiment)

圖7(a)及(b)係顯示本發明第3實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖與截面圖。(a) and (b) of FIG. 7 are a plan view and a cross-sectional view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a third embodiment of the present invention.

本第3實施形態之外部電路連接部中，僅耐焊劑膜10A之透孔14A及15A、及填充於該等透孔14A及15A之導電性焊墊30A之貫通部30Aa之點不同，其他之構成與上述第1實施形態之外部電路連接部相同。In the external circuit connecting portion of the third embodiment, only the through holes 14A and 15A of the solder resist film 10A and the through portion 30Aa of the conductive pads 30A filled in the through holes 14A and 15A are different, and the other points are different. The configuration is the same as that of the external circuit connecting portion of the first embodiment described above.

本第3實施形態之外部電路連接部，具備形成在半導體晶片(未圖示)之一主面(例如，其表面或背面)的絕緣膜(第1絕緣膜)51、以既定圖案形成在絕緣膜51上的配線膜20、形成在絕緣膜51上以覆蓋配線膜20的絕緣性耐焊劑膜(第2絕緣膜)10A、及形成在耐焊劑膜10A上之具有圓形平面形狀的導電性焊墊30A。The external circuit connecting portion of the third embodiment includes an insulating film (first insulating film) 51 formed on one main surface (for example, a front surface or a back surface) of a semiconductor wafer (not shown), and is formed in a predetermined pattern in insulation. The wiring film 20 on the film 51, the insulating solder resist film (second insulating film) 10A formed on the insulating film 51 to cover the wiring film 20, and the conductive property having a circular planar shape formed on the solder resist film 10A. Pad 30A.

耐焊劑膜10A在與配線膜20重疊之部位，對應配線膜20之厚度而***。在配線膜20上之耐焊劑膜10A之厚度係T(參照圖1)，與第1實施形態之情況以相同方式加以決定。耐焊劑膜10A覆蓋絕緣膜51之整面(亦即半導體晶片之該主面整面)亦可，或部分地覆蓋亦可。The solder resist film 10A is raised at a portion overlapping the wiring film 20 in accordance with the thickness of the wiring film 20. The thickness T of the solder resist film 10A on the wiring film 20 (see Fig. 1) is determined in the same manner as in the case of the first embodiment. The solder resist film 10A may cover the entire surface of the insulating film 51 (that is, the entire surface of the main surface of the semiconductor wafer), or may be partially covered.

耐焊劑膜10A在與配線膜20重疊之位置，具有形成為同心圓狀之圓形透孔14A及環狀透孔15A。環狀透孔15A位在圓形透孔14A之外側。在圓形透孔14A及環狀透孔15A分別填充有導電性焊墊30A之圓環狀貫通部30Aa。該等兩個貫通部30Aa，一者連接於焊墊本體30Ab，另一者貫通耐焊劑膜10A而接觸於配線膜20。是以，導電性焊墊30A之焊墊本體30Ab係透過兩個貫通部30Aa而電氣連接於配線膜20。The solder resist film 10A has a circular through hole 14A and a ring-shaped through hole 15A formed in a concentric shape at a position overlapping the wiring film 20. The annular through hole 15A is located on the outer side of the circular through hole 14A. Each of the circular through hole 14A and the annular through hole 15A is filled with an annular through portion 30Aa of the conductive pad 30A. One of the two penetration portions 30Aa is connected to the pad main body 30Ab, and the other is in contact with the wiring film 20 through the solder resist film 10A. Therefore, the pad main body 30Ab of the conductive pad 30A is electrically connected to the wiring film 20 through the two penetration portions 30Aa.

耐焊劑膜10A在與導電性焊墊30A重疊之部位，在圓形透孔14A與環狀透孔15A(內外兩個貫通部30Aa)之間具有圓環狀第1環狀部12A，在環狀透孔15A(外側之貫通部30Aa)之外側具有第2環狀部13A。The solder resist film 10A has an annular first annular portion 12A between the circular through hole 14A and the annular through hole 15A (the inner and outer two through portions 30Aa) at a portion overlapping the conductive pad 30A. The outer side of the through hole 15A (the outer through portion 30Aa) has a second annular portion 13A.

如上述，本第3實施形態中，導電性焊墊30A具備露出於耐焊劑膜10A上之大致圓板狀焊墊本體30Ab、及埋設在耐焊劑膜10A內部之兩個圓環狀貫通部30Aa。此外，在導電性焊墊30A的兩個貫通部30Aa之間與外側，分別存在熱傳導率低於貫通部30Aa之耐焊劑膜10A之第1環狀部12A與第2環狀部13A，因此即使厚度(高度)小於圖20及圖21所示之習知構成(e)及(f)之柱狀電極216，施加在焊墊本體30Ab之熱不易傳至配線膜20(或半導體晶片內部之積體電路)。As described above, in the third embodiment, the conductive pad 30A includes a substantially disk-shaped pad main body 30Ab exposed to the solder resist film 10A, and two annular through-hole portions 30Aa embedded in the solder resist film 10A. . Further, even if the first annular portion 12A and the second annular portion 13A having the thermal conductivity lower than the solder resist film 10A of the penetration portion 30Aa are present between the two through portions 30Aa of the conductive pad 30A and the outside, even if The thickness (height) is smaller than the columnar electrode 216 of the conventional configurations (e) and (f) shown in Figs. 20 and 21, and the heat applied to the pad body 30Ab is not easily transmitted to the wiring film 20 (or the product inside the semiconductor wafer). Body circuit).

以下，參照圖8~圖10說明具有以上構成之本第3實施形態之半導體裝置之外部電路連接部之形成方法。Hereinafter, a method of forming an external circuit connecting portion of the semiconductor device of the third embodiment having the above configuration will be described with reference to FIGS. 8 to 10.

首先，藉由與第1實施形態相同之方法，如圖7所示，在絕緣膜51上形成具有大致圓形圖案之配線膜20。First, as shown in FIG. 7, a wiring film 20 having a substantially circular pattern is formed on the insulating film 51 by the same method as in the first embodiment.

接著，如圖8所示，利用網版印刷法，在絕緣膜51上以既定厚度選擇性印刷(塗布)糊狀之耐焊劑43，將其加熱而使之硬化，以形成具有圓形透孔14A及環狀透孔15A之耐焊劑膜10A。亦即，首先，準備形成有開口部40Ab及40Ac與遮斷部40Ad之金屬光罩40A以獲得所欲之圖案，且以圖8所示之狀態固定。該金屬光罩40A，係藉由複數個遮斷部40Ad形成有圓筒形開口部40Ab與其外側之開口部40Ac，遮斷部40Ad彼此係藉由連結部40Ae相互連結。Next, as shown in FIG. 8, a paste-like solder resist 43 is selectively printed (coated) on the insulating film 51 at a predetermined thickness by a screen printing method, and heated to be hardened to form a circular through hole. 14A and the solder resist film 10A of the annular through hole 15A. That is, first, the metal mask 40A in which the openings 40Ab and 40Ac and the blocking portion 40Ad are formed is prepared to obtain a desired pattern, and is fixed in the state shown in FIG. In the metal mask 40A, the cylindrical opening portion 40Ab and the opening portion 40Ac on the outer side thereof are formed by a plurality of blocking portions 40Ad, and the blocking portions 40Ad are connected to each other by the connecting portion 40Ae.

接著，在金屬光罩40A上配置網版41，在網版41上載置糊狀之耐焊劑43，以刮漿板42延展於網版41整面。如此，耐焊劑43係通過網版41之微細孔(未圖示)而被壓入至金屬光罩40A之內部。耐焊劑43未進入具有遮斷部40Ad之部分，其結果，如圖9所示，在絕緣膜51上形成具有配置成同心圓狀之圓形透孔14A與環狀透孔15A之耐焊劑膜10A。圓形透孔14A與環狀透孔15A係重疊於配線膜20。Next, a screen 41 is placed on the metal mask 40A, and a paste-like solder resist 43 is placed on the screen 41, and the squeegee 42 is spread over the entire surface of the screen 41. In this manner, the solder resist 43 is pressed into the inside of the metal mask 40A through the fine holes (not shown) of the screen 41. The solder resist 43 does not enter the portion having the blocking portion 40Ad. As a result, as shown in FIG. 9, a solder resist film having a circular through hole 14A and a ring-shaped through hole 15A arranged in a concentric shape is formed on the insulating film 51. 10A. The circular through hole 14A and the annular through hole 15A are overlapped with the wiring film 20.

之後，在耐焊劑膜10A上，準備圖10所示之金屬光罩44A，並以圖10所示之狀態固定。該金屬光罩44A係藉由遮斷部44Ab形成有圓形開口部44Aa。開口部44Aa係形成在待形成焊墊本體30Ab之位置。Thereafter, the metal mask 44A shown in FIG. 10 is prepared on the solder resist film 10A, and is fixed in the state shown in FIG. The metal mask 44A is formed with a circular opening 44Aa by a blocking portion 44Ab. The opening portion 44Aa is formed at a position where the pad body 30Ab is to be formed.

接著，在金屬光罩44A上配置網版45，在網版45上載置焊料糊(糊狀焊料)47，以刮漿板46延展於網版45整面。如此，焊料糊47係通過網版45之微細孔(未圖示)而填充於金屬光罩44A之開口部44Aa。焊料糊47未進入具有遮斷部44Ad之部分，其結果，如圖7所示，藉由焊料糊47形成大致圓板形之焊墊本體30Ab。Next, a screen 45 is placed on the metal mask 44A, and a solder paste (passy solder) 47 is placed on the screen 45, and the squeegee 46 is spread over the entire surface of the screen 45. In this manner, the solder paste 47 is filled in the opening 44Aa of the metal mask 44A through the fine holes (not shown) of the screen 45. The solder paste 47 does not enter the portion having the blocking portion 44Ad, and as a result, as shown in FIG. 7, the substantially disk-shaped pad body 30Ab is formed by the solder paste 47.

將焊料糊47壓入於金屬光罩44A之開口部44Aa內時，亦填充於開口部44Aa內所露出之耐焊劑膜10A之圓形透孔14A與環狀透孔15A。其結果，如圖7所示，藉由焊料糊47，與形成大致圓板形焊墊本體30Ab之同時形成圓環狀之兩個貫通部30Aa。When the solder paste 47 is pressed into the opening 44Aa of the metal mask 44A, the circular through hole 14A and the annular through hole 15A of the solder resist film 10A exposed in the opening 44Aa are also filled. As a result, as shown in FIG. 7, the two paste-shaped penetration portions 30Aa are formed by the solder paste 47 while forming the substantially disk-shaped pad main body 30Ab.

經過以上之步驟，形成圖7所示之本第3實施形態之半導體裝置之外部電路連接部。Through the above steps, the external circuit connecting portion of the semiconductor device of the third embodiment shown in Fig. 7 is formed.

此外，取代焊料糊47，而使用Cu糊或Ag糊、或其他糊狀導電性材料，來形成導電性焊墊30A亦可。不使用糊狀導電性材料，藉由以使用光罩之鍍敷法等選擇性堆積Cu、Ni等之金屬來形成導電性焊墊30A亦可。Further, instead of the solder paste 47, a conductive paste 30A may be formed using a Cu paste or an Ag paste or another paste conductive material. The conductive pad 30A may be formed by selectively depositing a metal such as Cu or Ni by a plating method using a photomask or the like without using a paste conductive material.

如上述，本第3實施形態之半導體裝置之外部電路連接部構造中，導電性焊墊30A，具備配置在耐焊劑膜10A上的焊墊本體30Ab、及貫通耐焊劑膜10A而接觸於配線膜20的兩個圓環狀貫通部30Aa，且焊墊本體30Ab係透過該等貫通部30Aa電氣連接於配線膜20。又，熱傳導性低於導電性焊墊30A之貫通部30Aa之耐焊劑膜10的第1環狀部12A及第2環狀部13A，係配置在焊墊本體30Ab與配線膜20之間。因此，耐焊劑膜10A之與焊墊本體30Ab重疊之部分12A及13A(尤其位在耐焊劑膜10A之比貫通部30Aa內側之部分12A)，成為熱自焊墊本體30Ab傳至配線膜20(或半導體晶片)時之緩衝(阻障)，因此能有效抑制凸塊及球體具有之熱自焊墊本體30Ab傳至配線膜20。亦即，可緩和透過焊墊本體30Ab傳至配線膜20之熱的影響。其結果，由於配線膜20(或前述半導體晶片)所受之熱量減少，因此相較於僅有一個貫通部之習知一般構造，能改善由導電性焊墊30A與耐焊劑膜10A之第1環狀部12A及第2環狀部13A所構成之該外部電路連接部之耐熱衝擊性。As described above, in the external circuit connection portion structure of the semiconductor device of the third embodiment, the conductive pad 30A includes the pad main body 30Ab disposed on the solder resist film 10A and the through solder resist film 10A and is in contact with the wiring film. The two annular through portions 30Aa of 20 and the pad main body 30Ab are electrically connected to the wiring film 20 through the through portions 30Aa. Further, the first annular portion 12A and the second annular portion 13A having the thermal conductivity lower than the solder resist film 10 of the penetration portion 30Aa of the conductive pad 30A are disposed between the pad main body 30Ab and the wiring film 20. Therefore, the portions 12A and 13A of the solder resist film 10A overlapping the pad main body 30Ab (particularly the portion 12A of the solder resist film 10A inside the through portion 30Aa) are transferred from the pad body 30Ab to the wiring film 20 ( The buffer (barrier) of the semiconductor wafer or the like can effectively suppress the heat from the bump and the ball from being transferred from the pad body 30Ab to the wiring film 20. That is, the influence of heat transmitted to the wiring film 20 through the pad main body 30Ab can be alleviated. As a result, since the heat received by the wiring film 20 (or the semiconductor wafer) is reduced, the first structure of the conductive pad 30A and the solder resist film 10A can be improved as compared with the conventional structure having only one through portion. The thermal shock resistance of the external circuit connecting portion formed by the annular portion 12A and the second annular portion 13A.

又，耐焊劑膜10A之與焊墊本體30Ab重疊之第1環狀部12A及第2環狀部13A，由於亦具有緩和機械力之緩衝功能，因此亦有效抑制自外部所施加之力。其結果，亦能改善對機械衝擊之耐性。Further, since the first annular portion 12A and the second annular portion 13A of the solder resist film 10A which overlap with the pad main body 30Ab also have a buffering function for relieving mechanical force, the force applied from the outside is also effectively suppressed. As a result, the resistance to mechanical shock can also be improved.

再者，使耐焊劑膜10A之第1環狀部12A及第2環狀部13A介於之間，而使焊墊本體30Ab與配線膜20相對向，且藉由兩個圓環狀貫通部30Aa而實現焊墊本體30Ab與配線膜20之電氣連接，因此不需要上述習知外部電路連接部之構成(e)及(f)(參照圖20及圖21)所使用之柱狀電極216。因此，能大幅減低外部電路連接部之厚度，且構成亦變得非常簡單。亦即，比起上述習知外部電路連接部之構造(e)及(f)，能使該外部電路連接部(或半導體裝置)之厚度格外的變薄，且構成亦能變得更簡單。Further, the first annular portion 12A and the second annular portion 13A of the solder resist film 10A are interposed therebetween, and the pad main body 30Ab is opposed to the wiring film 20, and the two annular through portions are formed. Since the pad body 30Ab is electrically connected to the wiring film 20 by 30Aa, the columnar electrodes 216 used in the above-described conventional external circuit connecting portions (e) and (f) (see Figs. 20 and 21) are not required. Therefore, the thickness of the external circuit connecting portion can be greatly reduced, and the configuration becomes very simple. That is, the thickness of the external circuit connecting portion (or semiconductor device) can be made thinner than the structures (e) and (f) of the above-described conventional external circuit connecting portion, and the configuration can be made simpler.

此外，本第3實施形態之外部電路連接部，在絕緣膜51上形成具有圓形透孔14A與環狀透孔15A之耐焊劑膜10A後，形成導電性焊墊30A以在耐焊劑膜10A上填充圓形透孔14A及環狀透孔15A，藉此能僅以透過圓形透孔14A及環狀透孔15A使焊墊本體30Ab與配線膜20電氣連接而形成。是以，能以簡單的步驟實現。Further, in the external circuit connecting portion of the third embodiment, the solder resist film 10A having the circular through hole 14A and the annular through hole 15A is formed on the insulating film 51, and then the conductive pad 30A is formed to be on the solder resist film 10A. By filling the circular through hole 14A and the annular through hole 15A, the pad main body 30Ab can be electrically connected to the wiring film 20 only by the circular through hole 14A and the annular through hole 15A. Therefore, it can be implemented in a simple step.

本第3實施形態中，由於導電性焊墊30A本身作為外部電極使用，亦即導電性焊墊30A成為焊墊，因此該半導體裝置之外部電極之構成成為LGA。然而，在導電性焊墊30A上固設焊球而成為BGA亦可。In the third embodiment, since the conductive pad 30A itself is used as an external electrode, that is, the conductive pad 30A serves as a pad, the external electrode of the semiconductor device is configured as an LGA. However, it is also possible to form a BGA by attaching a solder ball to the conductive pad 30A.

此外，本第3實施形態中，雖使用耐焊劑膜10A作為第2絕緣膜，但本發明並未限於此。亦可使用第1實施形態所述之其他絕緣膜。Further, in the third embodiment, the solder resist film 10A is used as the second insulating film, but the present invention is not limited thereto. Other insulating films described in the first embodiment can also be used.

又，本第3實施形態中，雖以網版印刷法形成耐焊劑膜10A，但本發明並未限於此。例如，使用感光性之耐焊劑43，藉由公知之光微影法及蝕刻法使耐焊劑43之膜圖案化，形成具有圓形透孔14A與環狀透孔15A之耐焊劑膜10A亦可。此外，取代耐焊劑膜10A，將絕緣性薄膜層壓後，藉由雷射蝕刻等將其蝕刻，來形成與耐焊劑膜10A同樣圖案化之第2絕緣膜亦可。Further, in the third embodiment, the solder resist film 10A is formed by the screen printing method, but the present invention is not limited thereto. For example, by using the photosensitive solder resist 43, the film of the solder resist 43 is patterned by a known photolithography method and etching method, and the solder resist film 10A having the circular through hole 14A and the annular through hole 15A can be formed. . Further, in place of the solder resist film 10A, after laminating the insulating film, it may be etched by laser etching or the like to form a second insulating film which is patterned similarly to the solder resist film 10A.

又，本第3實施形態中，雖亦以使用焊料糊之網版印刷法形成導電性焊墊30A，但本發明並未限於此。例如，藉由使用光罩之電鍍法，選擇性形成金屬膜亦可。Further, in the third embodiment, the conductive pad 30A is formed by a screen printing method using a solder paste, but the present invention is not limited thereto. For example, a metal film can be selectively formed by a plating method using a photomask.

(配線膜之構成例)(Configuration example of wiring film)

圖11係顯示配線膜20之詳細構成之一例。FIG. 11 shows an example of a detailed configuration of the wiring film 20.

如圖11所示，配線膜20係形成雙層構造，由形成在配線膜51上之底層金屬膜52(厚度係例如0.5~1μm)、及重疊於其上而形成之鍍敷金屬膜53(設定為所欲之厚度。例如數μm)構成。用以形成鍍敷金屬膜53之電鍍步驟，係將底層金屬膜52作為種金屬來進行。以Cu鍍敷、Ni鍍敷、TiW鍍敷較佳。As shown in FIG. 11, the wiring film 20 is formed into a two-layer structure, and the underlying metal film 52 (thickness is, for example, 0.5 to 1 μm) formed on the wiring film 51, and a plating metal film 53 formed thereon are superposed thereon ( It is set to have a desired thickness, for example, several μm. The plating step for forming the plated metal film 53 is performed by using the underlying metal film 52 as a seed metal. It is preferable to use Cu plating, Ni plating, or TiW plating.

首先，藉由濺鍍法、CVD(化學氣相沉積)法等選擇性形成底層金屬膜52。之後，藉由將底層金屬膜52作為種金屬之化學鍍法，進行Cu鍍敷、Ni鍍敷、及TiW鍍敷等。以此方式獲得鍍敷金屬膜53。First, the underlying metal film 52 is selectively formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. Thereafter, Cu plating, Ni plating, TiW plating, or the like is performed by an electroless plating method using the underlying metal film 52 as a seed metal. The plated metal film 53 is obtained in this way.

此外，配線膜20不一定須為雙層構造，當然亦可為單層構造。相反地，為三層構造或四層以上之多層構造亦可。Further, the wiring film 20 does not necessarily have to have a two-layer structure, and may of course have a single-layer structure. Conversely, it is also possible to have a three-layer structure or a multilayer structure of four or more layers.

(半導體裝置之構成例1)(Configuration Example 1 of Semiconductor Device)

圖12係顯示具備本發明之外部電路連接部之半導體裝置之詳細構成的一例。該半導體裝置係固態攝影裝置，內裝固態攝影元件晶片。Fig. 12 is a view showing an example of a detailed configuration of a semiconductor device including an external circuit connecting portion of the present invention. The semiconductor device is a solid-state imaging device in which a solid-state imaging element wafer is incorporated.

圖12之固態攝影裝置100，係在包含透明的玻璃蓋體160之晶片尺寸封裝體(CSP)中密封片狀之固態攝影元件110而成者。該固態攝影裝置100在攝影面125與玻璃蓋體160之間的間隙沒有腔室。The solid-state imaging device 100 of Fig. 12 is obtained by sealing a sheet-like solid-state imaging element 110 in a wafer-scale package (CSP) including a transparent glass cover 160. The solid-state imaging device 100 has no chamber in the gap between the photographing surface 125 and the cover glass 160.

固態攝影元件110具備複數個受光元件(未圖示)、及複數個受光區域123形成在其表面區域的矽基板111。該等受光區域123與受光元件係相對各像素PX逐一形成。在矽基板111形成透明的層間絕緣膜112以覆蓋其整個表面。層間絕緣膜112之表面係固態攝影元件110之攝影面125，且形成有配置成陣列狀之複數個微透鏡122，亦即形成微透鏡陣列122A。該等微透鏡122，於攝影面125上，係相對各像素PX逐一形成。各受光區域123係透過層間絕緣膜112配置成重疊於相對應之微透鏡122。在各微透鏡122附近形成R、G、B三色用(或該等三色加上黑色之四色用)之微濾光器124(濾色器)。The solid-state imaging device 110 includes a plurality of light-receiving elements (not shown) and a plurality of light-receiving regions 123 formed on the surface of the substrate 111. The light receiving regions 123 and the light receiving elements are formed one by one with respect to each of the pixels PX. A transparent interlayer insulating film 112 is formed on the germanium substrate 111 to cover the entire surface thereof. The surface of the interlayer insulating film 112 is a photographic surface 125 of the solid-state photographic element 110, and a plurality of microlenses 122 arranged in an array are formed, that is, a microlens array 122A is formed. The microlenses 122 are formed on the imaging surface 125 one by one with respect to each of the pixels PX. Each of the light receiving regions 123 is disposed so as to be superposed on the corresponding microlenses 122 through the interlayer insulating film 112. A microfilter 124 (color filter) for three colors of R, G, and B (or four colors of the three colors plus black) is formed in the vicinity of each of the microlenses 122.

在層間絕緣膜112表面，於微透鏡陣列122A之外側的區域(攝影面125之周邊區域)，形成複數個表面電極115。該等表面電極115係用以將藉由各受光元件所產生之電氣訊號引出至固態攝影裝置100之外部者，透過形成在矽基板111表面與層間絕緣膜112內部之引出用配線(未圖示)，與各受光元件(各受光區域123)電氣連接。On the surface of the interlayer insulating film 112, a plurality of surface electrodes 115 are formed in a region on the outer side of the microlens array 122A (a peripheral region of the photographing surface 125). The surface electrodes 115 are used to lead the electric signals generated by the respective light-receiving elements to the outside of the solid-state imaging device 100, and pass through the lead wires formed on the surface of the ruthenium substrate 111 and the interlayer insulating film 112 (not shown). ) is electrically connected to each of the light receiving elements (each light receiving region 123).

由圖12明顯可知，在攝影面125存在起因於微透鏡122與表面電極115之凹凸。As is apparent from FIG. 12, the imaging surface 125 has irregularities due to the microlens 122 and the surface electrode 115.

層間絕緣膜112係由實際所積層之複數個絕緣膜構成，但層間絕緣膜112之內部構造對本發明來說並不重要，因此圖12中將其簡單描繪。The interlayer insulating film 112 is composed of a plurality of insulating films actually laminated, but the internal structure of the interlayer insulating film 112 is not important to the present invention, and thus is simply depicted in FIG.

在層間絕緣膜112表面形成透明的無機系SOG(塗式玻璃)材料膜150，且覆蓋層間絕緣膜112整面。由於SOG材料膜150之厚度大於微透鏡122與表面電極115任一者之厚度，因此微透鏡陣列122A與表面電極115係埋設於SOG材料膜150中。是以，SOG材料膜150之表面係平坦。A transparent inorganic SOG (coated glass) material film 150 is formed on the surface of the interlayer insulating film 112, and covers the entire surface of the interlayer insulating film 112. Since the thickness of the SOG material film 150 is larger than the thickness of any of the microlens 122 and the surface electrode 115, the microlens array 122A and the surface electrode 115 are buried in the SOG material film 150. Therefore, the surface of the SOG material film 150 is flat.

在SOG材料膜150表面形成透明的玻璃蓋體160。玻璃蓋體160，在此處由透明的硼矽酸鹽玻璃(B2 O3 /SiO2 )板構成，且藉由將該玻璃板藉由「陽極接合」接合於奈米孔隙SOG材料膜150表面，以與片狀之固態攝影元件110一體化。A transparent glass cover 160 is formed on the surface of the SOG material film 150. A glass lid 160, where (B 2 O 3 / SiO 2 ) formed of a transparent plate of borosilicate glass, and the glass plate by by "anodic bonding" material bonded to the SOG film 150 nm pore The surface is integrated with the sheet-like solid-state imaging element 110.

此外，由固態攝影元件110、SOG材料膜150、及玻璃蓋體160構成之積層體之側面整體，係藉由構成CSP之一部分之絕緣性合成樹脂(未圖示)所覆蓋。Further, the entire side surface of the laminated body composed of the solid-state imaging element 110, the SOG material film 150, and the glass cover 160 is covered with an insulating synthetic resin (not shown) constituting one part of the CSP.

在層間絕緣膜112之內部，在各表面電極115之正下方位置具有貫通該層間絕緣膜112之透孔，在該等透孔分別填充有導電性插塞114。又，在矽基板111之內部，亦在各表面電極115之正下方位置，具有上下貫通該矽基板111之透孔，在該等透孔分別填充有導電性插塞113。各導電性插塞113之全周，係以形成在對應之透孔內壁之絕緣膜116a覆蓋，各導電性插塞113與矽基板111係藉由對應之絕緣膜116a電氣絕緣。各導電性插塞114之上端及下端，係分別接觸於位在該正上方之表面電極115與位在該正下方之導電性插塞113。各導電性插塞113之下端，係自矽基板111之背面露出。相互接觸之導電性插塞114與113構成貫通電極，該貫通電極係使位在矽基板111之層間絕緣膜112表面之表面電極與位在矽基板111背面之配線膜118貫通矽基板111而彼此電氣連接。Inside the interlayer insulating film 112, there are through holes penetrating the interlayer insulating film 112 at positions directly under the surface electrodes 115, and the through holes are filled with conductive plugs 114, respectively. Further, inside the ruthenium substrate 111, a through hole penetrating the ruthenium substrate 111 up and down is provided at a position directly below the surface electrode 115, and the through holes are filled with the conductive plugs 113, respectively. The entire circumference of each of the conductive plugs 113 is covered with an insulating film 116a formed on the inner wall of the corresponding through hole, and each of the conductive plugs 113 and the base substrate 111 is electrically insulated by the corresponding insulating film 116a. The upper end and the lower end of each of the conductive plugs 114 are respectively in contact with the surface electrode 115 located directly above the conductive plug 113 located directly below. The lower end of each of the conductive plugs 113 is exposed from the back surface of the germanium substrate 111. The conductive plugs 114 and 113 that are in contact with each other constitute a through electrode that penetrates the surface electrode of the surface of the interlayer insulating film 112 of the germanium substrate 111 and the wiring film 118 located on the back surface of the germanium substrate 111 through the germanium substrate 111 and mutually Electrical connections.

在矽基板111背面形成絕緣膜116b，覆蓋所露出之導電性插塞113下端以外之區域。在絕緣膜116b表面形成複數個配線膜20。各配線膜20係接觸於露出於矽基板111背面之對應的導電性插塞113的下端。An insulating film 116b is formed on the back surface of the germanium substrate 111 so as to cover a region other than the lower end of the exposed conductive plug 113. A plurality of wiring films 20 are formed on the surface of the insulating film 116b. Each of the wiring films 20 is in contact with the lower end of the corresponding conductive plug 113 exposed on the back surface of the ruthenium substrate 111.

在絕緣膜116b表面形成耐焊劑膜10以覆蓋配線膜20。耐焊劑膜10在與各配線膜20重疊之位置形成有透孔，而在該等透孔之內部形成貫通部30A。A solder resist film 10 is formed on the surface of the insulating film 116b to cover the wiring film 20. The solder resist film 10 has through holes formed at positions overlapping the wiring films 20, and a through portion 30A is formed inside the through holes.

在耐焊劑膜10之表面，在與各貫通部30A重疊之位置形成以既定形狀圖案化之焊墊30。此外，在該等焊墊30上分別形成作為外部電極之焊球33。On the surface of the solder resist film 10, a pad 30 patterned in a predetermined shape is formed at a position overlapping each of the penetrating portions 30A. Further, solder balls 33 as external electrodes are formed on the pads 30, respectively.

如上述，各表面電極11係透過對應之導電性插塞14及13、與對應之配線膜11及導電性接觸件119，電氣連接於位在該固態攝影裝置100背面(圖1中係下面)之對應的焊墊30及焊球33。As described above, each of the surface electrodes 11 is electrically connected to the back surface of the solid-state imaging device 100 (below in FIG. 1) through the corresponding conductive plugs 14 and 13 and the corresponding wiring film 11 and conductive contact 119. Corresponding pads 30 and solder balls 33.

外部之光係通過玻璃蓋體160進入固態攝影裝置100，接著通過SOG膜150、微透鏡122、與微濾光器124，射入至設在各像素PX之受光元件(未圖示)的受光區域123。如此，入射光於各受光區域123進行光電轉換，且在各像素PX產生對應入射光強度之電氣訊號。該等電氣訊號，在藉由於各像素PX與受光區域123相鄰設置之放大元件(未圖示)放大後，透過未圖示之引出用配線傳送至表面電極115。該等電氣訊號進一步透過電氣連接於各表面電極115之導電性插塞114、導電性插塞113、配線膜118、及導電性接觸件119，而導出至對應之銅糊120及焊球121。The external light enters the solid-state imaging device 100 through the glass cover 160, and then enters the light receiving element (not shown) provided in each pixel PX through the SOG film 150, the microlens 122, and the microfilter 124. Area 123. In this manner, the incident light is photoelectrically converted in each of the light receiving regions 123, and an electrical signal corresponding to the intensity of the incident light is generated in each of the pixels PX. The electric signals are amplified by an amplifying element (not shown) provided adjacent to each of the pixels PX and the light receiving region 123, and then transmitted to the surface electrode 115 through a lead wire (not shown). The electrical signals are further electrically connected to the conductive plugs 114, the conductive plugs 113, the wiring film 118, and the conductive contacts 119 of the surface electrodes 115, and are led to the corresponding copper paste 120 and solder balls 121.

此外，上述固態攝影元件110雖包含形成在攝影面125之微透鏡陣列122A，但不含微透鏡陣列122A亦可。此外，上述固態攝影元件110雖包含微濾光器124，但不含微濾光器124亦可。Further, the solid-state imaging element 110 may include the microlens array 122A formed on the imaging surface 125, but may not include the microlens array 122A. Further, although the solid-state imaging element 110 described above includes the micro-filter 124, the micro-filter 124 may not be included.

本發明之外部電路連接部所使用之焊球33，在圖12所示之狀態下，以焊料(未圖示)電氣/機械連接於由形成在PWB 61上之銅(Cu)圖案構成之外部電路60。The solder ball 33 used in the external circuit connecting portion of the present invention is electrically/mechanically connected to the outside of the copper (Cu) pattern formed on the PWB 61 by solder (not shown) in the state shown in FIG. Circuit 60.

(半導體裝置之構成例2)(Configuration Example 2 of Semiconductor Device)

圖13係顯示具備本發明之外部電路連接部之半導體裝置之詳細構成的另一例。Fig. 13 is a view showing another example of the detailed configuration of a semiconductor device including the external circuit connecting portion of the present invention.

圖13中，於表面電極115之重疊位置形成有貫通矽基板111之透孔111a，但該透孔111a未以導電性插塞填充，而以耐焊劑膜10埋設之點，與圖12之構成例不同。除此之外之點與圖12相同，因此對與圖12相同構成之部分賦予相同符號而省略其說明。In Fig. 13, a through hole 111a penetrating the ruthenium substrate 111 is formed at a position where the surface electrode 115 overlaps. However, the through hole 111a is not filled with a conductive plug, and the solder resist film 10 is buried, and the structure of Fig. 12 is formed. The example is different. The same components as those in FIG. 12 are denoted by the same reference numerals, and their description will be omitted.

如圖13所示，構成配線膜20之底層金屬膜52與鍍敷金屬膜53，亦可沿透孔111a之內壁延伸。底層金屬膜52，於透孔111a表面側之端部，隙與表面電極115接觸。此外，透孔111a亦能以鍍敷金屬膜53埋設。As shown in FIG. 13, the underlying metal film 52 and the plated metal film 53 constituting the wiring film 20 may extend along the inner wall of the through hole 111a. The underlying metal film 52 is in contact with the surface electrode 115 at the end portion on the surface side of the through hole 111a. Further, the through hole 111a can also be buried in the plated metal film 53.

(第4實施形態)(Fourth embodiment)

圖14(a)及(b)係顯示本發明第4實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖與截面圖。本實施形態之外部電路連接部相當於上述第3實施形態(參照圖7)之變形例，配線膜與導電性焊墊之兩者係部分的被分割為二，一者作為訊號或電源用，另一者作為接地用。(a) and (b) are a plan view and a cross-sectional view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a fourth embodiment of the present invention. The external circuit connecting portion of the present embodiment corresponds to a modification of the third embodiment (see FIG. 7), and both the wiring film and the conductive pad are divided into two, and one is used as a signal or a power source. The other is used as a grounding.

導電性焊墊30B之接地用焊墊部30B2(第2部分)，如圖14(a)所示，具有將圓形之一部分切開之平面形狀，導電性焊墊30B之訊號/電源用焊墊部(第1部分)30B1具有直線狀之平面形狀，一部分***於接地用焊墊30B2之缺口部分。As shown in FIG. 14(a), the ground pad pad portion 30B2 (second portion) of the conductive pad 30B has a planar shape in which one of the circular portions is cut, and the signal pad/power pad for the conductive pad 30B is used. The portion (first portion) 30B1 has a linear planar shape, and a portion thereof is inserted into a notch portion of the ground pad 30B2.

配線膜20，與導電性焊墊30B相同，分割為訊號/電源用配線部(第1部分)20B1與接地用配線部(第2部分)20B2。接地用配線部20B2具有與接地用焊墊部30B2大致相同之將圓形之一部分切開之平面形狀。訊號/電源用配線部20B1具有與訊號/電源用焊墊部30B1大致相同之直線狀之平面形狀，一部分***於接地用配線部20B2之缺口部分。Similarly to the conductive pad 30B, the wiring film 20 is divided into a signal/power supply wiring portion (first portion) 20B1 and a ground wiring portion (second portion) 20B2. The grounding wiring portion 20B2 has a planar shape in which one of the circular portions is cut substantially the same as the grounding pad portion 30B2. The signal/power supply wiring portion 20B1 has a substantially linear planar shape similar to the signal/power supply pad portion 30B1, and is partially inserted into the notch portion of the ground wiring portion 20B2.

訊號/電源用焊墊部30B1，具有埋設在耐焊劑膜10B之大致圓形透孔14B中的貫通部30B1a、及位在耐焊劑膜10B上的訊號/電源用焊墊部本體30B1b。訊號/電源用焊墊部本體30B1b係透過貫通部30B1a電氣/機械連接於配線膜20B之訊號/電源用配線部20B1。在訊號/電源用焊墊部本體30B1b連接有引出線30B4之一端，藉此將訊號/電源用焊墊部本體30B1b導出至導電性焊墊30B之外側。引出線30B4係位在耐焊劑膜10B上。The signal/power supply pad portion 30B1 has a penetration portion 30B1a embedded in the substantially circular through hole 14B of the solder resist film 10B, and a signal/power pad portion main body 30B1b positioned on the solder resist film 10B. The signal/power supply pad portion main body 30B1b is electrically/mechanically connected to the signal/power supply wiring portion 20B1 of the wiring film 20B through the penetration portion 30B1a. One end of the lead wire 30B4 is connected to the signal/power pad portion main body 30B1b, whereby the signal/power pad portion main body 30B1b is led out to the outside of the conductive pad 30B. The lead wire 30B4 is tied to the solder resist film 10B.

接地用焊墊部30B2，具備埋設在耐焊劑膜10B之大致環狀透孔15B中的貫通部30B2a、及位在耐焊劑膜10B上的接地用焊墊部本體30B2b。接地用焊墊部本體30B2b係透過貫通部30B2a電氣/機械連接於配線膜20B之接地用配線部20B2。在接地用焊墊部本體30B2b連接有引出線30B5之一端，藉此將接地用焊墊部本體30B2b導出至導電性焊墊30B之外側。引出線30B5係位在耐焊劑膜10B上。The grounding pad portion 30B2 includes a penetration portion 30B2a embedded in the substantially annular through hole 15B of the solder resist film 10B, and a ground pad portion main body 30B2b positioned on the solder resist film 10B. The grounding pad portion main body 30B2b is electrically/mechanically connected to the grounding wiring portion 20B2 of the wiring film 20B through the penetration portion 30B2a. One end of the lead wire 30B5 is connected to the ground pad portion main body 30B2b, whereby the ground pad portion main body 30B2b is led out to the outside of the conductive pad 30B. The lead wire 30B5 is tied to the solder resist film 10B.

在電氣連接於訊號/電源用焊墊部本體30B1b之引出線30B4與接地用焊墊部本體30B2b之間，形成間隙30B3以不會在兩者間電氣短路。A gap 30B3 is formed between the lead line 30B4 electrically connected to the signal/power pad portion main body 30B1b and the ground pad portion main body 30B2b so as not to be electrically short-circuited therebetween.

本發明第4實施形態之半導體裝置之外部電路連接部係上述構成，能利用一個導電性焊墊30B將訊號或電源用配線與接地用配線自半導體晶片內部之積體電路導出至絕緣膜51上。然而，僅以圖14之構成，不易分別在導電性焊墊30B之訊號/電源用焊墊部30B1與接地用焊墊部30B2連接外部電路。因此，如圖15所示，於稍微離開導電性焊墊30B之位置，在耐焊劑膜10B上形成訊號/電源用導電性焊墊部71與接地用導電性焊墊部72。該等焊墊71及72皆形成為稍大於導電性焊墊30B以使外部電路容易連接。In the external circuit connecting portion of the semiconductor device according to the fourth embodiment of the present invention, the signal or power supply wiring and the grounding wiring can be led out from the integrated circuit inside the semiconductor wafer to the insulating film 51 by one conductive pad 30B. . However, with the configuration of Fig. 14, it is not easy to connect an external circuit to the signal/power source pad portion 30B1 and the ground pad portion 30B2 of the conductive pad 30B. Therefore, as shown in FIG. 15, the signal/power source conductive pad portion 71 and the grounding conductive pad portion 72 are formed on the solder resist film 10B at a position slightly apart from the conductive pad 30B. The pads 71 and 72 are formed to be slightly larger than the conductive pads 30B to facilitate connection of external circuits.

訊號/電源用導電性焊墊部71係透過引出線30B4電氣/機械連接於導電性焊墊30B之訊號/電源用焊墊部30B1。接地用導電性焊墊部72係透過引出線30B5電氣/機械連接於導電性焊墊30B之接地用焊墊部30B2。訊號/電源用導電性焊墊部71與接地用導電性焊墊部72不具有如導電性焊墊30B般之貫通部，而僅透過引出線30B4與30B5，分別連接於訊號/電源用焊墊部30B1與接地用焊墊部30B2。The signal/power source conductive pad portion 71 is electrically/mechanically connected to the signal/power source pad portion 30B1 of the conductive pad 30B through the lead wire 30B4. The grounding conductive pad portion 72 is electrically/mechanically connected to the grounding pad portion 30B2 of the conductive pad 30B through the lead wire 30B5. The signal/power supply conductive pad portion 71 and the ground conductive pad portion 72 do not have a penetration portion like the conductive pad 30B, but are connected to the signal/power supply pads only through the lead wires 30B4 and 30B5. The portion 30B1 and the ground pad portion 30B2.

圖16顯示第4實施形態之外部電路連接部之另一使用形態(構裝狀態)。圖16中，PWB61，在一面具有訊號線用外部電路62與接地線用外部電路63，在相反側之面具有透過對應之鍍敷/貫通孔而電氣連接於訊號線用外部電路62之焊墊62a、及透過對應之鍍敷/貫通孔而電氣連接於接地線用外部電路63之焊墊63a。導電性焊墊30B之訊號/電源用焊墊30B1係電氣/機械連接於焊墊62a，導電性焊墊30B之接地用焊墊部30B2係電氣/機械連接於焊墊63a。Fig. 16 shows another usage form (configuration state) of the external circuit connecting portion of the fourth embodiment. In Fig. 16, the PWB 61 has a signal line external circuit 62 and a ground line external circuit 63 on one side, and a pad which is electrically connected to the signal line external circuit 62 through a corresponding plating/through hole on the opposite side. 62a and electrically connected to the pad 63a of the grounding wire external circuit 63 through the corresponding plating/through hole. The signal/power supply pad 30B1 of the conductive pad 30B is electrically/mechanically connected to the pad 62a, and the ground pad portion 30B2 of the conductive pad 30B is electrically/mechanically connected to the pad 63a.

訊號線用外部電路62係延伸至未圖示之訊號線連接用焊墊，藉此連接於對應之訊號線。另一方面，兩側之接地用外部電路63係延伸至未圖示之另一接地線連接用焊墊，藉此相互連接之後連接於接地線。如此，配線膜20B之訊號/電源用配線部20B1到達訊號線連接用焊墊，配線膜20B之接地用配線部20B2到達接地線連接用焊墊，而能恆以將訊號線或電源線以接地線從左右挾持之方式傳送。The signal line external circuit 62 extends to a signal line connection pad (not shown) to be connected to the corresponding signal line. On the other hand, the grounding external circuits 63 on both sides extend to another grounding wire connection pad (not shown), and are connected to each other and then connected to the grounding wire. In this way, the signal/power supply wiring portion 20B1 of the wiring film 20B reaches the signal line connection pad, and the ground wiring portion 20B2 of the wiring film 20B reaches the ground line connection pad, and the signal line or the power supply line can be grounded at all times. The line is transmitted from left to right.

本第4實施形態之外部電路連接部，以如圖16所示之構裝形態使用時，獲得能有效使用於高頻訊號所使用之半導體裝置之效果。在該外部電路連接部亦考慮此種使用法。When the external circuit connecting portion of the fourth embodiment is used in the configuration shown in Fig. 16, the effect of being able to effectively use the semiconductor device used for the high-frequency signal is obtained. This method of use is also considered in the external circuit connection.

(第5實施形態)(Fifth Embodiment)

圖17(a)及(b)係顯示本發明第5實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖與截面圖。17 (a) and (b) are a plan view and a cross-sectional view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a fifth embodiment of the present invention.

本實施形態之外部電路連接部相當於第1實施形態(參照圖1)之變形例，僅耐焊劑膜10之與配線膜20重疊之部分的高度高於第1實施形態之點不同，除此之外與第1實施形態相同。The external circuit connecting portion of the present embodiment corresponds to a modification of the first embodiment (see FIG. 1), and only the height of the portion of the solder resist film 10 overlapping the wiring film 20 is higher than that of the first embodiment, and The same as the first embodiment.

以此方式，由於外部電路連接部之耐焊劑膜10的厚度更大，因此緩和熱/機械衝擊之作用變強。是以，能更加改善外部電路連接部之耐熱衝擊性及耐機械衝擊性。In this way, since the thickness of the solder resist film 10 of the external circuit connecting portion is larger, the effect of mitigating the thermal/mechanical impact becomes stronger. Therefore, the thermal shock resistance and mechanical shock resistance of the external circuit connecting portion can be further improved.

此外，第5實施形態之外部電路連接部能藉由進行兩次圖3之網版印刷步驟來實現。亦即，於第一次之網版印刷步驟，與第1實施形態相同形成耐焊劑膜10，於第二次之網版印刷步驟，僅在耐焊劑膜10之與配線膜20重疊之部分重疊耐焊劑膜10而形成即可。Further, the external circuit connecting portion of the fifth embodiment can be realized by performing the screen printing step of Fig. 3 twice. That is, in the first screen printing step, the solder resist film 10 is formed in the same manner as in the first embodiment, and in the second screen printing step, only the portion of the solder resist film 10 overlapping with the wiring film 20 is overlapped. The solder resist film 10 may be formed.

(第6實施形態)(Sixth embodiment)

圖18(a)及(b)係顯示本發明第6實施形態之半導體裝置之外部電路連接部之概略構成的俯視圖與截面圖。18 (a) and (b) are a plan view and a cross-sectional view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a sixth embodiment of the present invention.

本實施形態之外部電路連接部，於第2實施形態之外部電路連接部中，僅於在焊球33周圍圓環狀固設有補強用樹脂35之點不同。除此以外之點與第2實施形態之外部電路連接部為相同構成。是以，賦予與圖6所示之第2實施形態之外部電路連接部相同之符號而省略其說明。In the external circuit connecting portion of the second embodiment, the external circuit connecting portion of the second embodiment differs only in that the reinforcing resin 35 is annularly fixed around the solder ball 33. The other points are the same as those of the external circuit connecting portion of the second embodiment. The same reference numerals are given to the external circuit connecting portions of the second embodiment shown in FIG. 6, and the description thereof is omitted.

本第6實施形態中，由於在焊球33周圍形成補強用樹脂35，因此有在焊球33的外周緣不易產生裂痕之優點。In the sixth embodiment, since the reinforcing resin 35 is formed around the solder ball 33, there is an advantage that cracks are less likely to occur on the outer peripheral edge of the solder ball 33.

補強用樹脂35之形成，能藉由使用僅在形成有補強用樹脂35之部位形成開口部之金屬光罩，以網版印刷輕易進行。然而，並非限於此。例如，使用感光性合成樹脂時，亦可藉由光微影法來形成。The formation of the reinforcing resin 35 can be easily performed by screen printing by using a metal mask in which an opening portion is formed only at a portion where the reinforcing resin 35 is formed. However, it is not limited to this. For example, when a photosensitive synthetic resin is used, it can also be formed by photolithography.

補強用樹脂35，可使用例如環氧樹脂、聚醯亞胺樹脂等。For the reinforcing resin 35, for example, an epoxy resin, a polyimide resin, or the like can be used.

(其他實施形態)(Other embodiments)

上述第1~第6實施形態係顯示將本發明具體化之例，是以，本發明並非限於該等實施形態，只要不脫離本發明之旨趣當然可進行各種之變形。The above-described first to sixth embodiments are illustrative of the invention, and the invention is not limited to the embodiments, and various modifications may be made without departing from the scope of the invention.

例如，上述第1~第6實施形態中，導電性焊墊之焊墊本體的平面形狀皆為圓形，導電性焊墊之複數個貫通部的平面形狀為圓形或環狀，且該等係配置為同心圓狀，但本發明並非限於此。亦可為其他之任意形狀及配置。將貫通部之幾個變形例顯示於圖19。For example, in the first to sixth embodiments, the planar shape of the pad body of the conductive pad is circular, and the planar shape of the plurality of through portions of the conductive pad is circular or ring-shaped, and the like The configuration is concentric, but the invention is not limited thereto. It can also be any other shape and configuration. Several modifications of the penetration portion are shown in Fig. 19 .

圖19(a)中，將第1實施形態(參照圖1)之兩個貫通部30a設為矩形環狀，圖19(b)中，將第3實施形態(參照圖7)之兩個貫通部30Aa分別設為矩形與矩形環狀。In Fig. 19 (a), the two penetration portions 30a of the first embodiment (see Fig. 1) are formed in a rectangular ring shape, and in Fig. 19(b), the third embodiment (see Fig. 7) is penetrated. The portions 30Aa are respectively formed in a rectangular shape and a rectangular ring shape.

圖19(c)中，將第1實施形態(參照圖1)之兩個貫通部30a設為八角形環狀，圖19(d)中，將第3實施形態(參照圖7)之兩個貫通部30Aa分別設為八角形與八角形環狀。In Fig. 19(c), the two penetration portions 30a of the first embodiment (see Fig. 1) are formed in an octagonal ring shape, and in Fig. 19(d), two of the third embodiment (see Fig. 7) are used. Each of the penetration portions 30Aa is formed in an octagonal shape and an octagonal annular shape.

本發明中，如上述，不僅將貫通部設為圓形或圓環狀，亦可設為多角形或多角形環狀。In the present invention, as described above, not only the through portion but also a circular or annular shape may be used, and a polygonal shape or a polygonal annular shape may be used.

圖19(e)中，將各貫通部30a設成截面圓形的棒狀，將該等集合八個者。圖19(f)中，將兩個貫通部30B1a與30B2a分別設為半圓形，將兩者隔著間隙相對向配置，整體形狀成為大致圓形。In Fig. 19(e), each of the penetration portions 30a is formed in a rod shape having a circular cross section, and eight of them are assembled. In Fig. 19 (f), the two penetration portions 30B1a and 30B2a are each formed in a semicircular shape, and the two are disposed to face each other with a gap therebetween, and the overall shape is substantially circular.

本發明中，如上述，不需要將複數個貫通部之至少一個設為環狀。由圖19(e)與(f)所示之例明顯可知，貫通部之形狀與配置可任意變更。In the present invention, as described above, it is not necessary to form at least one of the plurality of penetration portions into a ring shape. As is apparent from the examples shown in Figs. 19(e) and (f), the shape and arrangement of the penetration portion can be arbitrarily changed.

又，上述第1~第6實施形態中，配線膜之平面形狀雖設成大致圓形，但此係僅與導電性焊墊之焊墊本體之平面形狀一致，設成與配線膜之平面形狀不同之形狀亦可。Further, in the above-described first to sixth embodiments, the planar shape of the wiring film is substantially circular, but this is only in accordance with the planar shape of the pad body of the conductive pad, and is formed in a planar shape with the wiring film. Different shapes are also available.

10,10A．．．耐焊劑膜10,10A. . . Solder resist film

11,11C．．．中央部11,11C. . . Central department

12,12A,12C．．．第1環狀部12, 12A, 12C. . . First annular part

12B．．．第1大致環狀部12B. . . First approximate annular portion

13,13A,13C．．．第2環狀部13,13A, 13C. . . Second annular part

13B．．．第2大致環狀部13B. . . Second approximate annular portion

14A,14C．．．第1環狀透孔14A, 14C. . . First annular through hole

14B．．．大致圓形透孔14B. . . Rough circular through hole

15A,15C．．．第2環狀透孔15A, 15C. . . Second annular through hole

15B．．．第2大致環狀透孔15B. . . Second substantially annular through hole

20,20B．．．配線膜20,20B. . . Wiring film

20B1．．．訊號/電源用配線部20B1. . . Signal/power supply wiring department

20B2．．．接地用配線部20B2. . . Grounding wiring section

30．．．導電性焊墊30. . . Conductive pad

30a．．．貫通部30a. . . Penetration

30b．．．焊墊本體30b. . . Pad body

30A．．．導電性焊墊30A. . . Conductive pad

30Aa．．．貫通部30Aa. . . Penetration

30Ab．．．焊墊本體30Ab. . . Pad body

30B．．．導電性焊墊30B. . . Conductive pad

30B1．．．訊號電源用焊墊部30B1. . . Signal power supply pad

30B1a．．．貫通部30B1a. . . Penetration

30B1b．．．訊號電源用焊墊部本體30B1b. . . Wiring pad body for signal power supply

30B2．．．接地用焊墊部30B2. . . Grounding pad

30B2a．．．貫通部30B2a. . . Penetration

30B2b．．．接地用焊墊部本體30B2b. . . Grounding pad body

30B3．．．間隙30B3. . . gap

30B4．．．引出線30B4. . . Lead line

30B5．．．引出線30B5. . . Lead line

30C．．．導電性焊墊30C. . . Conductive pad

30Ca．．．貫通部30Ca. . . Penetration

30Cb．．．焊墊本體30Cb. . . Pad body

33．．．焊球33. . . Solder ball

35．．．補強樹脂35. . . Reinforcing resin

40,40A．．．金屬光罩40,40A. . . Metal mask

40a,40b,40c,40Ab,40Ac．．．開口部40a, 40b, 40c, 40Ab, 40Ac. . . Opening

40d,40Ad．．．遮断部40d, 40Ad. . . Interrupted part

40e,40Ae．．．連結部40e, 40Ae. . . Linkage

41．．．網版41. . . Web version

42．．．刮漿板42. . . Scraper

43．．．耐焊劑43. . . Solder resist

44,44A．．．金屬光罩44,44A. . . Metal mask

44a,44Aa．．．開口部44a, 44Aa. . . Opening

44b,44Ab．．．遮断部44b, 44Ab. . . Interrupted part

45．．．網版45. . . Web version

46．．．刮漿板46. . . Scraper

47．．．焊料糊47. . . Solder paste

51．．．絕緣膜51. . . Insulating film

52．．．底層金屬膜52. . . Underlying metal film

53．．．鍍敷金屬膜53. . . Plated metal film

60．．．外部電路60. . . External circuit

61．．．PWB61. . . PWB

62．．．訊號線/電源線用外部電路62. . . External circuit for signal line/power line

62a．．．焊墊62a. . . Solder pad

63．．．接地線用外部電路63. . . Ground circuit with external circuit

63a．．．焊墊63a. . . Solder pad

71．．．訊號/電源用導電性焊墊71. . . Conductive pad for signal/power supply

72．．．接地用導電性焊墊72. . . Conductive pad for grounding

100．．．固態攝影裝置100. . . Solid state photography device

110．．．固態攝影元件110. . . Solid state imaging element

111．．．矽基板111. . .矽 substrate

111a．．．矽基板之透孔111a. . . Through hole of the substrate

112．．．層間絕緣膜112. . . Interlayer insulating film

112a．．．層間絕緣膜之透孔112a. . . Through hole of interlayer insulating film

113．．．導電性插塞113. . . Conductive plug

114．．．導電性插塞114. . . Conductive plug

115．．．表面電極115. . . Surface electrode

116a,116b．．．絕緣膜116a, 116b. . . Insulating film

122．．．微透鏡122. . . Microlens

122A．．．微透鏡陣列122A. . . Microlens array

123．．．受光區域123. . . Light receiving area

124．．．微濾光器124. . . Microfilter

125．．．攝影面125. . . Photographic surface

150．．．SOG材料膜150. . . SOG material film

PX．．．像素PX. . . Pixel

圖1(a)係顯示本發明第1實施形態之半導體裝置之外部電路連接部之概略構成的放大俯視圖、(b)係沿其A－A線的截面圖。1 (a) is an enlarged plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a first embodiment of the present invention, and (b) is a cross-sectional view taken along line A-A.

圖2係顯示本發明第1實施形態之半導體裝置之外部電路連接部之形成方法，(a)係放大俯視圖、(b)係沿圖1之A－A線的截面圖。2 is a cross-sectional view showing a method of forming an external circuit connecting portion of the semiconductor device according to the first embodiment of the present invention, wherein (a) is an enlarged plan view and (b) is a cross-sectional view taken along line A-A of FIG. 1.

圖3(a)、(b)係與顯示本發明第1實施形態之半導體裝置之外部電路連接部之形成方法之圖2相同的圖，為圖2之續圖。3(a) and 3(b) are the same as Fig. 2 showing a method of forming an external circuit connecting portion of the semiconductor device according to the first embodiment of the present invention, and are a continuation of Fig. 2.

圖4(a)、(b)係與顯示本發明第1實施形態之半導體裝置之外部電路連接部之形成方法之圖2相同的圖，為圖3之續圖。4(a) and 4(b) are the same as Fig. 2 showing a method of forming an external circuit connecting portion of the semiconductor device according to the first embodiment of the present invention, and are a continuation of Fig. 3.

圖5(a)、(b)係與顯示本發明第1實施形態之半導體裝置之外部電路連接部之形成方法之圖2相同的圖，為圖4之續圖。5(a) and 5(b) are the same as Fig. 2 showing a method of forming an external circuit connecting portion of the semiconductor device according to the first embodiment of the present invention, and are a continuation of Fig. 4.

圖6(a)係顯示本發明第2實施形態之半導體裝置之外部電路連接部之概略構成的放大俯視圖、(b)係沿其A－A線的截面圖。Fig. 6 (a) is an enlarged plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a second embodiment of the present invention, and (b) is a cross-sectional view taken along line A-A.

圖7(a)係顯示本發明第3實施形態之半導體裝置之外部電路連接部之概略構成的放大俯視圖、(b)係沿其A－A線的截面圖。Fig. 7 (a) is an enlarged plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a third embodiment of the present invention, and (b) is a cross-sectional view taken along line A-A.

圖8(a)、(b)係顯示本發明第3實施形態之半導體裝置之外部電路連接部之形成方法，(a)係放大俯視圖、(b)係沿圖7之A－A線的截面圖。8(a) and 8(b) are views showing a method of forming an external circuit connecting portion of a semiconductor device according to a third embodiment of the present invention, wherein (a) is an enlarged plan view and (b) is a cross section taken along line A-A of Fig. 7. Figure.

圖9(a)、(b)係與顯示本發明第3實施形態之半導體裝置之外部電路連接部之形成方法之圖8相同的圖，為圖8之續圖。9(a) and 9(b) are the same as Fig. 8 showing a method of forming an external circuit connecting portion of the semiconductor device according to the third embodiment of the present invention, and are a continuation of Fig. 8.

圖10(a)、(b)係與顯示本發明第3實施形態之半導體裝置之外部電路連接部之形成方法之圖8相同的圖，為圖9之續圖。Figs. 10(a) and 10(b) are the same as Fig. 8 showing a method of forming an external circuit connecting portion of the semiconductor device according to the third embodiment of the present invention, and are a continuation of Fig. 9.

圖11係顯示本發明第1~第3實施形態之半導體裝置之外部電路連接部所使用之配線膜之詳細構成之一例的放大截面圖。FIG. 11 is an enlarged cross-sectional view showing an example of a detailed configuration of a wiring film used in an external circuit connection portion of the semiconductor device according to the first to third embodiments of the present invention.

圖12係顯示本發明之半導體裝置之外部電路連接部之使用形態之一例的放大截面圖。Fig. 12 is an enlarged cross-sectional view showing an example of a use form of an external circuit connecting portion of the semiconductor device of the present invention.

圖13係顯示本發明之半導體裝置之外部電路連接部之使用形態之另一例的截面圖。Fig. 13 is a cross-sectional view showing another example of the use form of the external circuit connecting portion of the semiconductor device of the present invention.

圖14(a)係顯示本發明第4實施形態之半導體裝置之外部電路連接部之概略構成的放大俯視圖、(b)係沿其A－A線的截面圖。Fig. 14 (a) is an enlarged plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a fourth embodiment of the present invention, and (b) is a cross-sectional view taken along line A-A.

圖15(a)係顯示本發明第4實施形態之半導體裝置之外部電路連接部之整體構成的放大俯視圖、(b)係沿其B－B線的截面圖。Fig. 15 (a) is an enlarged plan view showing an overall configuration of an external circuit connecting portion of a semiconductor device according to a fourth embodiment of the present invention, and (b) is a cross-sectional view taken along line B-B.

圖16係顯示本發明第4實施形態之半導體裝置之外部電路連接部之另一使用形態的概略立體圖。Fig. 16 is a schematic perspective view showing another usage mode of an external circuit connecting portion of the semiconductor device according to the fourth embodiment of the present invention.

圖17係顯示本發明第5實施形態之半導體裝置之外部電路連接部之沿圖1之A－A線的截面圖。Fig. 17 is a cross-sectional view taken along line A-A of Fig. 1 showing an external circuit connecting portion of the semiconductor device according to the fifth embodiment of the present invention.

圖18(a)係顯示本發明第6實施形態之半導體裝置之外部電路連接部之概略構成的放大俯視圖、(b)係沿其A－A線的截面圖。18 (a) is an enlarged plan view showing a schematic configuration of an external circuit connecting portion of a semiconductor device according to a sixth embodiment of the present invention, and (b) is a cross-sectional view taken along line A-A.

圖19(a)~(f)係顯示本發明半導體裝置之外部電路連接部之導電性焊墊之貫通部之變形例的概略截面圖。19(a) to 19(f) are schematic cross-sectional views showing a modification of the penetration portion of the conductive pad of the external circuit connection portion of the semiconductor device of the present invention.

圖20係顯示習知半導體裝置之外部電路連接部之一例的主要部分概略截面圖。Fig. 20 is a schematic cross-sectional view showing the main part of an example of an external circuit connecting portion of a conventional semiconductor device.

圖21係顯示習知半導體裝置之外部電路連接部之另一例的主要部分概略截面圖。Fig. 21 is a schematic cross-sectional view showing the main part of another example of the external circuit connecting portion of the conventional semiconductor device.

10．．．耐焊劑膜10. . . Solder resist film

11．．．中央部11. . . Central department

12．．．第1環狀部12. . . First annular part

13．．．第2環狀部13. . . Second annular part

14．．．第1環狀透孔14. . . First annular through hole

15．．．第2環狀透孔15. . . Second annular through hole

20．．．配線膜20. . . Wiring film

30．．．導電性焊墊30. . . Conductive pad

30a．．．貫通部30a. . . Penetration

30b．．．焊墊本體30b. . . Pad body

51．．．絕緣膜51. . . Insulating film

T．．．厚度T. . . thickness

Claims (16)

一種半導體裝置之外部電路連接部構造，其特徵在於，具備：配線膜，透過第1絕緣膜形成在半導體晶片的主面；第2絕緣膜，形成在該第1絕緣膜上以覆蓋該配線膜；以及導電性焊墊，在與該配線膜重疊之位置，形成在該第2絕緣膜上；該導電性焊墊具有配置在該第2絕緣膜上的焊墊本體，及一端連接於該焊墊本體、且另一端貫通該第2絕緣膜而接觸於該配線膜的複數個貫通部，且該焊墊本體係透過複數個該貫通部而電氣/機械連接於該配線膜；該第2絕緣膜之熱傳導性低於該導電性焊墊之該貫通部；在複數個該貫通部之間填充有形成該第2絕緣膜的材料；藉由該第2絕緣膜之與該焊墊本體重疊之部分，抑制施加於該導電性焊墊之熱及外力往該配線膜之傳遞；在該導電性焊墊固設外部電極，該外部電極之側面係以補強用樹脂圍繞。 An external circuit connection portion structure of a semiconductor device, comprising: a wiring film formed on a main surface of a semiconductor wafer through a first insulating film; and a second insulating film formed on the first insulating film to cover the wiring film And a conductive pad formed on the second insulating film at a position overlapping the wiring film; the conductive pad has a pad body disposed on the second insulating film, and one end is connected to the solder a pad body and the other end penetrates the second insulating film to contact a plurality of through portions of the wiring film, and the pad system is electrically/mechanically connected to the wiring film through a plurality of the through portions; the second insulation The thermal conductivity of the film is lower than the through portion of the conductive pad; a material forming the second insulating film is filled between the plurality of through portions; and the second insulating film overlaps the pad body In part, the transfer of heat and external force applied to the conductive pad to the wiring film is suppressed, and an external electrode is fixed to the conductive pad, and a side surface of the external electrode is surrounded by a reinforcing resin. 如申請專利範圍第1項之半導體裝置之外部電路連接部構造，其中，該第2絕緣膜之厚度，在與該配線膜重疊的位置為10μm以上。 The external circuit connecting portion structure of the semiconductor device according to the first aspect of the invention, wherein the thickness of the second insulating film is 10 μm or more at a position overlapping the wiring film. 如申請專利範圍第1或2項之半導體裝置之外部電路 連接部構造，其中，該焊墊本體延伸至比複數個該貫通部更外側。 An external circuit of a semiconductor device as claimed in claim 1 or 2 The connection portion structure, wherein the pad body extends to be outside of the plurality of through portions. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，複數個該貫通部之截面形狀為圓形或圓環形，且配置成同心狀。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the plurality of through portions have a circular or circular cross-sectional shape and are arranged concentrically. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，複數個該貫通部之截面形狀為多角形或多角環形，且配置成同心狀。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the plurality of through portions have a polygonal or polygonal annular shape and are arranged concentrically. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，複數個該貫通部並非同心狀，而是彼此分開配置在該配線膜上。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the plurality of through portions are not concentric, but are disposed apart from each other on the wiring film. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，該第2絕緣膜之與該導電性焊墊重疊之部分的厚度，係設定為大於其以外之部分的厚度。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein a thickness of a portion of the second insulating film overlapping the conductive pad is set to be larger than a thickness of the portion other than the conductive film. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，該焊墊本體分割為第1部分與第2部分，在該第1部分連接複數個該貫通部之一個，而在該第2部分連接複數個該貫通部之另一個。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the pad body is divided into a first portion and a second portion, and a plurality of the through portions are connected to the first portion, and The other of the plurality of through portions is connected to the second portion. 如申請專利第8項之半導體裝置之外部電路連接部構造，其進一步具備分別電氣連接於該第1部分及該第2部分之第1及第2連接用導電性焊墊。 The external circuit connecting portion structure of the semiconductor device of claim 8, further comprising first and second connecting conductive pads electrically connected to the first portion and the second portion, respectively. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，該第2絕緣膜，係使糊狀之絕緣性材料硬化而成者。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the second insulating film is formed by curing a paste-like insulating material. 如申請專利範圍第1或2項之半導體裝置之外部電路連接部構造，其中，該導電性焊墊，係使糊狀之導電性材料硬化而成者。 The external circuit connecting portion structure of the semiconductor device according to claim 1 or 2, wherein the conductive pad is formed by curing a paste-like conductive material. 一種半導體裝置，具有申請專利範圍第1至11項中任一項之外部電路連接部構造。 A semiconductor device having an external circuit connection portion structure according to any one of claims 1 to 11. 一種半導體裝置之外部電路連接部構造之形成方法，其特徵在於，具備：配線膜形成步驟，透過第1絕緣膜在半導體晶片之主面形成配線膜；第2絕緣膜形成步驟，將在與該配線膜重疊之位置具有複數個透孔的第2絕緣膜形成在該第1絕緣膜上以覆蓋該配線膜；以及導電性焊墊形成步驟，在該第2絕緣膜上載置導電材料，且將該導電材料填充於該第2絕緣膜之複數個該透孔，以形成導電性焊墊；在該導電性焊墊固設外部電極的步驟；形成圍繞該外部電極側面之補強用樹脂的步驟；載置於該第2絕緣膜上之該導電材料，係形成該導電性焊墊的本體部；填充於複數個該透孔之該導電材料，係形成該導電性焊墊的複數個貫通部，該焊墊本體係透過該等貫通部電氣/機械連接於該配線膜；該第2絕緣膜之熱傳導性低於該導電性焊墊的該貫通部； 藉由該第2絕緣膜之與該焊墊本體重疊之部分，抑制施加於該導電性焊墊之熱及外力往該配線膜之傳遞。 A method of forming an external circuit connection portion structure of a semiconductor device, comprising: a wiring film forming step of forming a wiring film on a main surface of a semiconductor wafer through a first insulating film; and a second insulating film forming step; a second insulating film having a plurality of through holes at a position where the wiring film overlaps is formed on the first insulating film to cover the wiring film; and a conductive pad forming step is performed on the second insulating film, and the conductive material is placed thereon The conductive material is filled in the plurality of through holes of the second insulating film to form a conductive pad; the step of fixing the external electrode on the conductive pad; and the step of forming a reinforcing resin surrounding the side surface of the external electrode; The conductive material placed on the second insulating film forms a main body portion of the conductive pad; and the conductive material filled in the plurality of through holes forms a plurality of through portions of the conductive pad. The pad system is electrically/mechanically connected to the wiring film through the through portions; the thermal conductivity of the second insulating film is lower than the through portion of the conductive pad; The portion of the second insulating film that overlaps the pad body suppresses the transfer of heat and external force applied to the conductive pad to the wiring film. 如申請專利範圍第13項之半導體裝置之外部電路連接部構造之形成方法，其中，形成該第2絕緣膜之步驟，係使糊狀絕緣性材料形成為膜狀以使其硬化的步驟。 The method of forming an external circuit connecting portion structure of a semiconductor device according to claim 13, wherein the step of forming the second insulating film is a step of forming a paste-like insulating material into a film shape to be cured. 如申請專利範圍第13或14項之半導體裝置之外部電路連接部構造之形成方法，其中，該導電材料，係使用糊狀導電材料。 A method of forming an external circuit connecting portion structure of a semiconductor device according to claim 13 or 14, wherein the conductive material is a paste conductive material. 如申請專利範圍第13或14項之半導體裝置之外部電路連接部構造之形成方法，其中，以該第2絕緣膜之與該導電性焊墊重疊之部分的厚度大於其以外之部分的厚度之方式，將該第2絕緣膜圖案化。 The method of forming an external circuit connecting portion structure of a semiconductor device according to claim 13 or 14, wherein a thickness of a portion of the second insulating film overlapping the conductive pad is larger than a thickness of a portion other than the conductive film. In this manner, the second insulating film is patterned.
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