TWI521609B - Method for forming semiconductor structure and method for forming memory using the same - Google Patents
Method for forming semiconductor structure and method for forming memory using the same Download PDFInfo
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Description
本發明是有關於一種半導體結構的形成方法及應用其之記憶體形成方法，且特別是有關於一種氧化物-氮化物-氧化物層形成於半導體基材之單面上的半導體結構的形成方法及應用其之記憶體形成方法。The present invention relates to a method for forming a semiconductor structure and a memory forming method using the same, and more particularly to a method for forming a semiconductor structure in which an oxide-nitride-oxide layer is formed on one surface of a semiconductor substrate And a memory forming method using the same.
傳統的氧化物-氮化物-氧化物層的形成過程中，晶圓之正面及背面於爐管中同時形成氧化物-氮化物-氧化物層。於後續記憶體的製造過程中，僅對晶圓正面的氧化物-氮化物-氧化物層進行製程處理，晶圓背面的氧化物-氮化物-氧化物層保留在晶圓之背面上。In the formation of a conventional oxide-nitride-oxide layer, an oxide-nitride-oxide layer is simultaneously formed on the front and back sides of the wafer in the furnace tube. In the subsequent memory manufacturing process, only the oxide-nitride-oxide layer on the front side of the wafer is processed, and the oxide-nitride-oxide layer on the back side of the wafer remains on the back side of the wafer.
然而，晶圓背面的氧化物-氮化物-氧化物層阻隔熱量的傳遞，使得在後續快速熱處理製程(Rapid Thermal Process,RTP)中，系統誤判晶圓的溫度不足而提升製程溫度，如此將導致最終形成的記憶體的阻值過高，這會降低產品良率，嚴重者甚至報廢無法出貨。However, the transmission of the oxide-nitride-oxide layer on the back side of the wafer causes the system to misjudge the temperature of the wafer and increase the process temperature in the subsequent Rapid Thermal Process (RTP), which will result in The resulting memory has too high a resistance value, which will reduce the yield of the product, and even if it is scrapped, it cannot be shipped.
本發明係有關於一種半導體結構的形成方法及應用其之記憶體的形成方法，可提高記憶體的品質與良率。The present invention relates to a method of forming a semiconductor structure and a method of forming a memory therewith, which can improve the quality and yield of the memory.
根據本發明之一實施例，提出一種半導體結構的形成方法。半導體結構的形成方法包括以下步驟。提供一基底結構，其中基底結構包括一半導體基材、一第一氧化物-氮化物-氧化物層(Oxide Nitride Oxide,ONO)及一第二氧化物-氮化物-氧化物層，半導體基材具有相對的一第一面與一第二面，第一氧化物-氮化物-氧化物層包括於第一面上依序形成之一第一氧化物層、一第一氮化物層及一第二氧化物層，第二氧化物-氮化物-氧化物層包括於第二面上依序形成之一第三氧化物層、一第二氮化物層及一第四氧化物層；形成一氮化物遮蔽層於第一氧化物-氮化物-氧化物層上；移除第四氧化物層；移除第二氮化物層及氮化物遮蔽層；移除第二氧化物層及第三氧化物層；以及，形成一第五氧化物層於第一氮化物層上。According to an embodiment of the invention, a method of forming a semiconductor structure is presented. The method of forming a semiconductor structure includes the following steps. Providing a substrate structure, wherein the substrate structure comprises a semiconductor substrate, a first oxide-nitride-oxide layer (ONO), and a second oxide-nitride-oxide layer, the semiconductor substrate Having a first surface and a second surface, the first oxide-nitride-oxide layer includes a first oxide layer, a first nitride layer and a first layer sequentially formed on the first surface a second oxide-nitride-oxide layer comprising a third oxide layer, a second nitride layer and a fourth oxide layer sequentially formed on the second surface; forming a nitrogen Masking layer on the first oxide-nitride-oxide layer; removing the fourth oxide layer; removing the second nitride layer and the nitride shielding layer; removing the second oxide layer and the third oxide And forming a fifth oxide layer on the first nitride layer.
根據本發明之另一實施例，提出一種記憶體的形成方法。半導體結構的形成方法包括以下步驟。提供一基底結構，其中基底結構包括一半導體基材、一第一氧化物-氮化物-氧化物層及一第二氧化物-氮化物-氧化物層，半導體基材具有相對的一第一面與一第二面，第一氧化物-氮化物-氧化物層包括於第一面上依序形成之一第一氧化物層、一第一氮化物層及一第二氧化物層，第二氧化物-氮化物-氧化物層包括於第二面上依序形成之一第三氧化物層、一第二氮化物層及一第四氧化物層；形成一氮化物遮蔽層於第一氧化物-氮化物-氧化物層上；移除第四氧化物層；移除第二氮化物層及氮化物遮蔽層；移除第二氧化物層及第三氧化物層；形成一第五氧化物層於第一氮化物層上，其中第一氧化物層、第一氮化物層與第五氧化物層係構成一第三氧化物-氮化物-氧化物層；圖案化第三氧化物-氮化物-氧化物層以形成一圖案化的第三氧化物-氮化物-氧化物層；形成一電極層於圖案化的第三氧化物-氮化物-氧化物層上；以及，於圖案化的第三氧化物-氮化物-氧化物層之相對側邊上的半導體基材中分別形成一源極及一汲極。According to another embodiment of the present invention, a method of forming a memory is proposed. The method of forming a semiconductor structure includes the following steps. Providing a substrate structure, wherein the substrate structure comprises a semiconductor substrate, a first oxide-nitride-oxide layer and a second oxide-nitride-oxide layer, the semiconductor substrate having a first side opposite And a second surface, the first oxide-nitride-oxide layer includes a first oxide layer, a first nitride layer and a second oxide layer sequentially formed on the first surface, and second The oxide-nitride-oxide layer includes a third oxide layer, a second nitride layer and a fourth oxide layer sequentially formed on the second surface; forming a nitride shielding layer for the first oxidation On the nitride-oxide layer; removing the fourth oxide layer; removing the second nitride layer and the nitride mask layer; removing the second oxide layer and the third oxide layer; forming a fifth oxidation The layer is on the first nitride layer, wherein the first oxide layer, the first nitride layer and the fifth oxide layer form a third oxide-nitride-oxide layer; the patterned third oxide- a nitride-oxide layer to form a patterned third oxide-nitride-oxide layer; forming a The electrode layer is on the patterned third oxide-nitride-oxide layer; and a source is formed in the semiconductor substrate on the opposite side of the patterned third oxide-nitride-oxide layer Extreme and a bungee.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
請參照第1A至1F圖，其繪示依照本發明一實施例之半導體結構的形成過程圖。Please refer to FIGS. 1A to 1F for a process of forming a semiconductor structure in accordance with an embodiment of the present invention.
如第1A圖所示，提供一基底結構100，其包括一半導體基材110、一第一氧化物-氮化物-氧化物(Oxide Nitride Oxide,ONO)層120及一第二氧化物-氮化物-氧化物層130。As shown in FIG. 1A, a base structure 100 including a semiconductor substrate 110, a first oxide-nitride-oxide (ONO) layer 120, and a second oxide-nitride is provided. - an oxide layer 130.
半導體基材110具有相對之一第一面110u與一第二面110b。半導體基材110包括矽，例如是P型矽基材。The semiconductor substrate 110 has a first surface 110u and a second surface 110b. The semiconductor substrate 110 comprises tantalum, such as a P-type tantalum substrate.
第一氧化物-氮化物-氧化物層120形成於半導體基材110之第一面110u上且包括一第一氧化物層121、一第一氮化物層122及一第二氧化物層123。其中，第一氧化物層121、第一氮化物層122及第二氧化物層123係依序形成於半導體基材110之第一面110u上。The first oxide-nitride-oxide layer 120 is formed on the first surface 110u of the semiconductor substrate 110 and includes a first oxide layer 121, a first nitride layer 122, and a second oxide layer 123. The first oxide layer 121, the first nitride layer 122, and the second oxide layer 123 are sequentially formed on the first surface 110u of the semiconductor substrate 110.
第二氧化物-氮化物-氧化物層130形成於半導體基材110之第二面110b上且包括一第三氧化物層131、一第二氮化物層132及一第四氧化物層133。其中，第三氧化物層131、第二氮化物層132及第四氧化物層133係依序形成於半導體基材110之第二面110b上。The second oxide-nitride-oxide layer 130 is formed on the second surface 110b of the semiconductor substrate 110 and includes a third oxide layer 131, a second nitride layer 132, and a fourth oxide layer 133. The third oxide layer 131, the second nitride layer 132, and the fourth oxide layer 133 are sequentially formed on the second surface 110b of the semiconductor substrate 110.
一實施例中，第一氧化物-氮化物-氧化物層120及第二氧化物-氮化物-氧化物層130是利用爐管製程形成。在爐管製程中，第一氧化物層121與第三氧化物層131係同時形成，第一氮化物層122與第二氮化物層132係同時形成，且第二氧化物層123與第四氧化物層133係同時形成。In one embodiment, the first oxide-nitride-oxide layer 120 and the second oxide-nitride-oxide layer 130 are formed using a furnace control process. In the furnace control process, the first oxide layer 121 and the third oxide layer 131 are simultaneously formed, the first nitride layer 122 and the second nitride layer 132 are simultaneously formed, and the second oxide layer 123 and the fourth The oxide layer 133 is formed simultaneously.
如第1B圖所示，形成氮化物遮蔽層140於第一氧化物-氮化物-氧化物層120之第二氧化物層123上。本實施例中，氮化物遮蔽層140例如是氮化矽(SiN)。此外，氮化物遮蔽層140的厚度可介於約120埃()至200 之間，然此非用以限制本發明實施例。於一實施例中，氮化物遮蔽層140之厚度可依據第二氮化物層132之厚度與第二氮化物層132相對於氮化物遮蔽層140之蝕刻選擇比(例如，於熱磷酸中)進行調整。例如，氮化物遮蔽層140之厚度與蝕刻率分別為T1及R1，第二氮化物層132之厚度與蝕刻率分別為T2及R2，氮化物遮蔽層140之厚度T1=T2×(R2/R1)。於一實施例中，當氮化物遮蔽層140及第二氮化物層132之蝕刻率大致相等時，氮化物遮蔽層140之厚度係與第二氮化物層132之厚度大致相等，以利於後續步驟中同時移除氮化物遮蔽層140及第二氮化物層132。As shown in FIG. 1B, a nitride shielding layer 140 is formed on the second oxide layer 123 of the first oxide-nitride-oxide layer 120. In the present embodiment, the nitride shielding layer 140 is, for example, tantalum nitride (SiN). In addition, the nitride shielding layer 140 may have a thickness of about 120 angstroms ( ) to 200 However, this is not intended to limit the embodiments of the present invention. In one embodiment, the thickness of the nitride shielding layer 140 can be determined according to the thickness of the second nitride layer 132 and the etching selectivity of the second nitride layer 132 relative to the nitride shielding layer 140 (for example, in hot phosphoric acid). Adjustment. For example, the thickness and etching rate of the nitride shielding layer 140 are T1 and R1, respectively, the thickness and etching rate of the second nitride layer 132 are T2 and R2, respectively, and the thickness of the nitride shielding layer 140 is T1=T2×(R2/R1). ). In one embodiment, when the etching rates of the nitride shielding layer 140 and the second nitride layer 132 are substantially equal, the thickness of the nitride shielding layer 140 is substantially equal to the thickness of the second nitride layer 132 to facilitate subsequent steps. The nitride shielding layer 140 and the second nitride layer 132 are simultaneously removed.
如第1C圖所示，以例如是稀釋氫氟酸(Diluted HF,DHF)，移除第二氧化物-氮化物-氧化物層130之第四氧化物層133。由於第一氧化物-氮化物-氧化物層120之第二氧化物層123受到氮化物遮蔽層140的保護，故可避免第二氧化物層123被稀釋氫氟酸蝕刻。As shown in FIG. 1C, the fourth oxide layer 133 of the second oxide-nitride-oxide layer 130 is removed, for example, by diluting hydrofluoric acid (Diluted HF, DHF). Since the second oxide layer 123 of the first oxide-nitride-oxide layer 120 is protected by the nitride shielding layer 140, the second oxide layer 123 can be prevented from being etched by the diluted hydrofluoric acid.
如第1D圖所示，以例如是熱磷酸(H3PO4)，同時移除第二氧化物-氮化物-氧化物層130之第二氮化物層132及形成於第一氧化物-氮化物-氧化物層120上的氮化物遮蔽層140。氮化物遮蔽層140移除後，第一氧化物-氮化物-氧化物層120係露出。As shown in FIG. 1D, the second nitride layer 132 of the second oxide-nitride-oxide layer 130 is simultaneously removed and formed in the first oxide-nitrogen, for example, by hot phosphoric acid (H 3 PO 4 ). A nitride mask layer 140 on the compound-oxide layer 120. After the nitride shielding layer 140 is removed, the first oxide-nitride-oxide layer 120 is exposed.
如第1E圖所示，以例如是稀釋氫氟酸，同時移除第一氧化物-氮化物-氧化物層120之第二氧化物層123及第二氧化物-氮化物-氧化物層130之第三氧化物層131。至此，完全移除形成於半導體基材110之第二面110b上的第二氧化物-氮化物-氧化物層130。As shown in FIG. 1E, the second oxide layer 123 and the second oxide-nitride-oxide layer 130 of the first oxide-nitride-oxide layer 120 are simultaneously removed, for example, by diluting hydrofluoric acid. The third oxide layer 131. To this end, the second oxide-nitride-oxide layer 130 formed on the second face 110b of the semiconductor substrate 110 is completely removed.
由於位於半導體基材110之第二面110b上的第二氧化物-氮化物-氧化物層130完全被移除，因此在後續的快速熱處理製程(RTP)中可避免系統誤判晶圓溫度不足而過度提高製程溫度。此處的快速熱處理製程例如是形成輕摻雜擴散區(lightly doped diffusion,LDD)、形成源/汲極及金屬矽化物(salicide)等製程後的熱處理製程。Since the second oxide-nitride-oxide layer 130 on the second side 110b of the semiconductor substrate 110 is completely removed, the system can be prevented from misjudged wafer temperature shortage in the subsequent rapid thermal processing process (RTP). Excessively increase the process temperature. The rapid thermal processing process herein is, for example, a heat treatment process after forming a lightly doped diffusion (LDD), forming a source/drain and a salicide.
如第1F圖所示，應用例如是臨場蒸汽產生器(in-situ stream generator,ISSG)方法或其它氧化製程，形成第五氧化層150於第一氧化物-氮化物-氧化物層120之第一氮化物層122上。第五氧化層150例如是閘極氧化層。As shown in FIG. 1F, the application is, for example, an in-situ stream generator (ISSG) method or other oxidation process to form the fifth oxide layer 150 in the first oxide-nitride-oxide layer 120. On a nitride layer 122. The fifth oxide layer 150 is, for example, a gate oxide layer.
第一氧化物層121、第一氮化物層122與第五氧化層150係構成一第三氧化物-氮化物-氧化物層160。The first oxide layer 121, the first nitride layer 122, and the fifth oxide layer 150 constitute a third oxide-nitride-oxide layer 160.
為避免半導體基材110或位於其上的薄膜(例如第1E圖中的第一氮化物層122)暴露在空氣或是含氧環境產生原生氧化層(native oxide)，而影響後續形成之薄膜(例如第1F圖中的第五氧化層150)的品質，或影響第三氧化物-氮化物-氧化物層160的品質，於實施例中，在以稀釋氫氟酸移除薄膜(例如第1E圖中的第二氧化物層123)之後，半導體基材110可儘快進入ISSG機台來形成下一層薄膜(例如第1F圖中的第五氧化層150)。In order to prevent the semiconductor substrate 110 or the film located thereon (for example, the first nitride layer 122 in FIG. 1E) from being exposed to air or an oxygen-containing environment to generate a native oxide, the subsequently formed film is affected ( For example, the quality of the fifth oxide layer 150 in the FIG. 1F, or the quality of the third oxide-nitride-oxide layer 160, in the embodiment, the film is removed by diluting hydrofluoric acid (eg, 1E) After the second oxide layer 123) in the figure, the semiconductor substrate 110 can enter the ISSG machine as soon as possible to form the next film (for example, the fifth oxide layer 150 in FIG. 1F).
本實施例之半導體結構的形成方法可應用於各種需要氧化物-氮化物-氧化物層結構的半導體裝置中，例如記憶體，如快閃記憶體(flash memory)、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)或SONOS(矽-氧-氮化矽-氧-矽)記憶體。以下係以SONOS為例說明應用上述半導體結構形成記憶體的其中一種方法。The method for forming a semiconductor structure of the present embodiment can be applied to various semiconductor devices requiring an oxide-nitride-oxide layer structure, such as a memory such as a flash memory or a dynamic random access memory ( Dynamic Random Access Memory (DRAM) or SONOS (矽-oxygen-nitridium-oxygen-oxide) memory. The following is a description of one of the methods of forming a memory using the above semiconductor structure using SONOS as an example.
請參照第2A至2E圖，其繪示依照本發明一實施例之記憶體的形成過程圖。Please refer to FIGS. 2A to 2E for illustrating a process of forming a memory according to an embodiment of the invention.
如第2A圖所示，形成電極層220於第五氧化層150上。形成電極層220的方法包括化學氣相沈積法(CVD)或物理氣相沈積法(PVD)等。此外，電極層220可包括金屬、多晶矽、或金屬矽化物(silicide)。As shown in FIG. 2A, the electrode layer 220 is formed on the fifth oxide layer 150. The method of forming the electrode layer 220 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). Further, the electrode layer 220 may include a metal, a polysilicon, or a metal silicide.
如第2B圖所示，以例如是微影製程(photolithography)，圖案化電極層220、第五氧化層150、第一氮化物層122及第一氧化物層121。其中圖案化的第五氧化層150、第一氮化物層122及第一氧化物層121係形成圖案化的第三氧化物-氮化物-氧化物層210。圖案化的第一氧化物層121可作為穿遂層，且包括二氧化矽。圖案化的第一氮化物層122可作為電荷捕捉層，且包括氮化矽。圖案化的第五氧化層150可作為阻擋層，且包括二氧化矽。As shown in FIG. 2B, the electrode layer 220, the fifth oxide layer 150, the first nitride layer 122, and the first oxide layer 121 are patterned by, for example, photolithography. The patterned fifth oxide layer 150, the first nitride layer 122, and the first oxide layer 121 form a patterned third oxide-nitride-oxide layer 210. The patterned first oxide layer 121 can serve as a passthrough layer and include hafnium oxide. The patterned first nitride layer 122 can function as a charge trapping layer and includes tantalum nitride. The patterned fifth oxide layer 150 can serve as a barrier layer and includes hafnium oxide.
如第2C圖所示，可以電極層220與圖案化的第三氧化物-氮化物-氧化物層210作為遮罩，對半導體基材110進行離子植入製程，以形成摻雜區域230於圖案化的第三氧化物-氮化物-氧化物層210之相對側邊上的半導體基材110中。其中，摻雜區域230可為輕摻雜的，例如是n型輕摻雜區域。As shown in FIG. 2C, the semiconductor substrate 110 may be subjected to an ion implantation process by using the electrode layer 220 and the patterned third oxide-nitride-oxide layer 210 as a mask to form the doped region 230 in the pattern. The semiconductor substrate 110 on the opposite side of the third oxide-nitride-oxide layer 210. The doped region 230 may be lightly doped, such as an n-type lightly doped region.
如第2D圖所示，形成間隙壁(spacer)240於電極層220的側壁220s及圖案化的第三氧化物-氮化物-氧化物層210的側壁210s上。間隙壁240之材質係絕緣材料或介電材料，例如包括二氧化矽或氮化矽。本實施例中，間隙壁240的形成方法係在如第2C圖所示的結構上順應性地形成一薄膜，然後進行蝕刻步驟移除部分的薄膜，薄膜留下的部分即構成間隙壁240。另一實施例中，亦可省略間隙壁240之形成。As shown in FIG. 2D, a spacer 240 is formed on the sidewall 220s of the electrode layer 220 and the sidewall 210s of the patterned third oxide-nitride-oxide layer 210. The material of the spacer 240 is an insulating material or a dielectric material, and includes, for example, hafnium oxide or tantalum nitride. In the present embodiment, the spacer 240 is formed by conformally forming a film on the structure as shown in FIG. 2C, and then performing an etching step to remove a portion of the film, and the portion left by the film constitutes the spacer 240. In another embodiment, the formation of the spacers 240 may also be omitted.
如第2E圖所示，以間隙壁240做為遮罩，應用例如是離子植入製程，形成摻雜區域250及摻雜區域260於半導體基材110中。本實施例中，摻雜區域250及摻雜區域260係重摻雜的，例如是n型重摻雜區域。一實施例中，於摻雜區域250及260形成後，可執行一快速熱處理製程，以適當地活化、擴散摻雜離子。位於圖案化的第三氧化物-氮化物-氧化物層210之相對側邊上之半導體中的摻雜區域250及260可分別作為源極及汲極。至此，形成本實施例之記憶體200。As shown in FIG. 2E, with the spacers 240 as a mask, for example, an ion implantation process is used to form the doped regions 250 and the doped regions 260 in the semiconductor substrate 110. In this embodiment, the doped region 250 and the doped region 260 are heavily doped, such as an n-type heavily doped region. In one embodiment, after the doped regions 250 and 260 are formed, a rapid thermal processing process can be performed to properly activate and diffuse the dopant ions. The doped regions 250 and 260 in the semiconductor on opposite sides of the patterned third oxide-nitride-oxide layer 210 can serve as the source and drain, respectively. So far, the memory 200 of the present embodiment has been formed.
綜合上述，由於位於半導體基材110之第二面110b的第二氧化物-氮化物-氧化物層130完全被移除(第1A圖)，因此在後續的快速熱處理製程中可避免系統誤判半導體基材110溫度不足而過度提高製程溫度。如此一來，可避免最終形成的記憶體200的阻值過高，且亦可提升記憶體200的良率及效能。In summary, since the second oxide-nitride-oxide layer 130 on the second side 110b of the semiconductor substrate 110 is completely removed (FIG. 1A), the system can be prevented from misjudged by the semiconductor in the subsequent rapid thermal processing process. The substrate 110 is insufficient in temperature to excessively increase the process temperature. In this way, the resistance of the finally formed memory 200 can be prevented from being too high, and the yield and performance of the memory 200 can also be improved.
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
100．．．基底結構100. . . Base structure
110．．．半導體基材110. . . Semiconductor substrate
110u．．．第一面110u. . . First side
110b．．．第二面110b. . . Second side
120．．．第一氧化物-氮化物-氧化物層120. . . First oxide-nitride-oxide layer
121．．．第一氧化物層121. . . First oxide layer
122．．．第一氮化物層122. . . First nitride layer
123．．．第二氧化物層123. . . Second oxide layer
130．．．第二氧化物-氮化物-氧化物層130. . . Second oxide-nitride-oxide layer
131．．．第三氧化物層131. . . Third oxide layer
132．．．第二氮化物層132. . . Second nitride layer
133．．．第四氧化物層133. . . Fourth oxide layer
140．．．氮化物遮蔽層140. . . Nitride shielding layer
150．．．第五氧化層150. . . Fifth oxide layer
160．．．第三氧化物-氮化物-氧化物層160. . . Third oxide-nitride-oxide layer
200．．．記憶體200. . . Memory
210．．．圖案化的第三氧化物-氮化物-氧化物層210. . . Patterned third oxide-nitride-oxide layer
210s、220s．．．側壁210s, 220s. . . Side wall
220．．．電極層220. . . Electrode layer
230、250、260．．．摻雜區域230, 250, 260. . . Doped region
240．．．間隙壁240. . . Clearance wall
第1A至1F圖繪示依照本發明一實施例之半導體結構的形成過程圖。1A to 1F are views showing a process of forming a semiconductor structure in accordance with an embodiment of the present invention.
第2A至2E圖，其繪示依照本發明一實施例之記憶體的形成過程圖。2A to 2E are views showing a process of forming a memory according to an embodiment of the present invention.
110．．．半導體基材110. . . Semiconductor substrate
121．．．第一氧化物層121. . . First oxide layer
122．．．第一氮化物層122. . . First nitride layer
150．．．第五氧化層150. . . Fifth oxide layer
160．．．第三氧化物-氮化物-氧化物層160. . . Third oxide-nitride-oxide layer
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