TWI521576B

TWI521576B - Resistive random-access memory and method for fabricating the same

Info

Publication number: TWI521576B
Application number: TW102134697A
Authority: TW
Inventors: 許博硯; 沈鼎瀛; 江明崇
Original assignee: 華邦電子股份有限公司
Priority date: 2013-09-26
Filing date: 2013-09-26
Publication date: 2016-02-11
Also published as: TW201513180A

Description

電阻式記憶體及其製造方法 Resistive memory and manufacturing method thereof

本發明係有關一種電阻式記憶體(resistive random-access memory,RRAM)及其製造方法。 The present invention relates to a resistive random-access memory (RRAM) and a method of fabricating the same.

非揮發性記憶體具有存入的資料在斷電後也不會消失之優點，因此是許多電器產品維持正常操作所必備的記憶元件。目前，電阻式隨機存取記憶體(resistive random access memory，RRAM)是業界積極發展的一種非揮發性記憶體，其具有寫入操作電壓低、寫入抹除時間短、記憶時間長、非破壞性讀取、多狀態記憶、結構簡單以及所需面積小等優點，在未來個人電腦和電子設備上極具應用潛力。 Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electrical products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

然而，在大量生產RRAM之前，仍有許多挑戰亟待克服。其中一個挑戰是RRAM之操作電流-電壓(I-V)特性的變異，所述變異是來自頂電極與底電極之間的多個可能的導電細絲(filament)形成路徑。較大的電極會產生較多可能的導電細絲形成路徑，其會增加RRAM操作之I-V特性的變異。為了使這些變異減到最少，最直接的作法就是縮小電極。 However, there are still many challenges to overcome before mass production of RRAM. One of the challenges is the variation in the operating current-voltage (I-V) characteristics of the RRAM, which is the path from which a plurality of possible conductive filaments are formed between the top and bottom electrodes. Larger electrodes create more likely conductive filament formation paths that increase the variation of the I-V characteristics of the RRAM operation. In order to minimize these variations, the most straightforward approach is to shrink the electrodes.

另一方面，傳統RRAM之底電極材料於形成時，常自然地(inherently)在其表面形成柱狀晶的結構，使得後續電極間介電層沉積時均勻度不佳，影響導電燈絲形成路徑之生成，增加RRAM操作之I-V特性的變異。 On the other hand, when the bottom electrode material of the conventional RRAM is formed, a columnar crystal structure is often formed on the surface thereof, so that the uniformity of the subsequent inter-electrode dielectric layer deposition is poor, which affects the formation path of the conductive filament. generate, Increase the variation of the I-V characteristics of the RRAM operation.

本發明一實施例提供一種電阻式記憶體的製造方法，包括：提供一基底；形成一介電層於基底之上；形成一停止層於介電層上；形成一開口穿過停止層與介電層；形成一底電極於開口之中，其中底電極與停止層共平面(coplanar)；沉積一介電層於底電極與停止層之上；沉積一頂電極材料於介電層上；以及圖案化頂電極材料與介電層，以定義出一頂電極以及其下的一電極間介電層，其中頂電極具有一第二表面與底電極之一第一表面相對，且第二表面的面積大於第一表面的面積。 An embodiment of the present invention provides a method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer An electric layer; forming a bottom electrode in the opening, wherein the bottom electrode is coplanar with the stop layer; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric layer; The top electrode material and the dielectric layer are patterned to define a top electrode and an inter-electrode dielectric layer thereunder, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the second surface The area is larger than the area of the first surface.

本發明另一實施例提供一種電阻式記憶體，包括：一基底；一介電層，於基底之上；一停止層，於介電層之上；一開口，穿過停止層與介電層；一底電極，於開口之中，且與停止層共平面；一電極間介電層，於底電極之上且延伸至部份的停止層之上；以及一頂電極，於電極間介電層之上，其中頂電極具有一第二表面與底電極之一第一表面相對，且第二表面的面積大於第一表面的面積。 Another embodiment of the present invention provides a resistive memory comprising: a substrate; a dielectric layer over the substrate; a stop layer over the dielectric layer; and an opening through the stop layer and the dielectric layer a bottom electrode, in the opening, and coplanar with the stop layer; an inter-electrode dielectric layer over the bottom electrode and extending over a portion of the stop layer; and a top electrode dielectrically interposed between the electrodes Above the layer, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the area of the second surface is larger than the area of the first surface.

100、200‧‧‧RRAM 100, 200‧‧‧RRAM

102‧‧‧基底 102‧‧‧Base

112a、250‧‧‧底電極 112a, 250‧‧‧ bottom electrode

116a‧‧‧頂電極 116a‧‧‧ top electrode

104、104a‧‧‧導電層 104, 104a‧‧‧ conductive layer

106‧‧‧介電層 106‧‧‧Dielectric layer

108‧‧‧停止層 108‧‧‧stop layer

110‧‧‧開口 110‧‧‧ openings

112、230、230a、240、240a‧‧‧底電極材料 112, 230, 230a, 240, 240a‧‧‧ bottom electrode materials

114‧‧‧介電層 114‧‧‧Dielectric layer

114a‧‧‧電極間介電層 114a‧‧‧Interelectrode dielectric layer

116‧‧‧頂電極材料 116‧‧‧Top electrode material

106a、118‧‧‧燈絲結構 106a, 118‧‧‧ filament structure

116S‧‧‧下表面 116S‧‧‧ lower surface

112S‧‧‧上表面 112S‧‧‧ upper surface

220‧‧‧襯層 220‧‧‧ lining

第1A~1H圖根據本發明實施例繪示出製造RRAM 100的中間階段之剖面示意圖。 1A-1H are schematic cross-sectional views showing an intermediate stage of fabricating the RRAM 100 in accordance with an embodiment of the present invention.

第2A~2E圖根據本發明另一實施例繪示出製造RRAM 200的中間階段之剖面示意圖。 2A-2E are schematic cross-sectional views showing an intermediate stage of fabricating the RRAM 200 in accordance with another embodiment of the present invention.

以下依本發明之不同特徵舉出數個不同的實施例。本發明中特定的元件及安排係為了簡化，但本發明並不以這些實施例為限。舉例而言，於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例，亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外，為簡明起見，本發明在不同例子中以重複的元件符號及/或字母表示，但不代表所述各實施例及/或結構間具有特定的關係。 Several different embodiments are set forth below in accordance with various features of the invention. The specific elements and arrangements of the present invention are intended to be simplified, but the invention is not limited to these embodiments. For example, a description of forming a first element on a second element can include an embodiment in which the first element is in direct contact with the second element, and also includes having additional elements formed between the first element and the second element such that An embodiment in which one element is not in direct contact with the second element. In addition, the present invention is represented by the repeated reference numerals and/or letters in the different examples for the sake of brevity, but does not represent a particular relationship between the various embodiments and/or structures.

第1A~1H圖為依據本發明第一實施例所繪示之RRAM100之製造方法的剖面示意圖。請參照第1A圖，在一基底102上形成一導電材料104。基底102可為矽基底、鍺化矽基底、碳化矽基底、矽覆絕緣體(silicon-on insulator,SOI)基底、多層(multi-layered)基底、梯度(gradient)基底、或混成定向(hybrid orientation)基底等。在一實施例中，基底102為一矽晶圓(wafer)。導電材料104例如為鎢、銅、鋁、銀、金、或其他合適的導電材料(例如，摻雜的多晶矽(doped polysilicon))。接著，請參照第1B圖，圖案化導電材料104以形成導電層104a。在本發明實施例中，可透過進行一微影(lithography)與乾蝕刻製程(例如是反應式離子蝕刻(reactive ion etching,RIE))將導電材料104圖案化。 1A to 1H are schematic cross-sectional views showing a method of manufacturing the RRAM 100 according to the first embodiment of the present invention. Referring to FIG. 1A, a conductive material 104 is formed on a substrate 102. The substrate 102 can be a germanium substrate, a germanium germanium substrate, a tantalum carbide substrate, a silicon-on insulator (SOI) substrate, a multi-layered substrate, a gradient substrate, or a hybrid orientation. Substrate, etc. In one embodiment, substrate 102 is a wafer. Conductive material 104 is, for example, tungsten, copper, aluminum, silver, gold, or other suitable electrically conductive material (eg, doped polysilicon). Next, referring to FIG. 1B, the conductive material 104 is patterned to form the conductive layer 104a. In the embodiment of the present invention, the conductive material 104 can be patterned by performing a lithography and dry etching process, such as reactive ion etching (RIE).

接著，請參照第1C圖，在基底102上方形成介電層106、以及介電層106上方的停止層108。介電層106可包括氧化矽、氮化矽、氮氧化矽、低介電常數材料(low-k dielectrics)、或其他合適的介電材料。在一些實施例中，停止層108為含氮的材料，例如，氮化矽、氮氧化矽。介電層106與停止層108的形成方法例如是化學氣相沉積法(chemical vapor deposition,CVD)、旋轉塗佈法(spin on coating)。 Next, referring to FIG. 1C, a dielectric layer 106 and a stop layer 108 over the dielectric layer 106 are formed over the substrate 102. Dielectric layer 106 can include hafnium oxide, tantalum nitride, hafnium oxynitride, low-k dielectrics, or other suitable dielectric materials. In some embodiments, the stop layer 108 is nitrogen-containing Materials such as tantalum nitride and niobium oxynitride. The method of forming the dielectric layer 106 and the stop layer 108 is, for example, chemical vapor deposition (CVD) or spin on coating.

請參照第1D圖，在形成介電層106與停止層108後，形成一貫穿介電層106與停止層108的開口110。開口110暴露出部分的導電層104a。形成開口110的方法可包括乾蝕刻製程，例如RIE。值得注意的是，在進行至後續的步驟前，可選擇性地在開口110之側壁與底部上形成一襯層(liner)(未顯示)。 Referring to FIG. 1D, after the dielectric layer 106 and the stop layer 108 are formed, an opening 110 is formed through the dielectric layer 106 and the stop layer 108. The opening 110 exposes a portion of the conductive layer 104a. The method of forming the opening 110 may include a dry etching process such as RIE. It is noted that a liner (not shown) may be selectively formed on the sidewalls and bottom of the opening 110 prior to proceeding to subsequent steps.

接著，請參照第1E圖，於開口110中以及停止層上形成一底電極材料112。底電極材料112例如為鈦、氮化鈦、鉑、鎢、鋁、其他合適的電極材料。形成底電極材料的方法例如為物理氣相沉積法(PVD)、原子層沉積(atomic layer deposition,ALD)、有機金屬化學汽相沈積(metal organic CVD,MOCVD)或其他合適的沉積製程。 Next, referring to FIG. 1E, a bottom electrode material 112 is formed in the opening 110 and on the stop layer. The bottom electrode material 112 is, for example, titanium, titanium nitride, platinum, tungsten, aluminum, or other suitable electrode material. The method of forming the bottom electrode material is, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic CVD (MOCVD), or other suitable deposition process.

接著，請參照第1F圖，移除部分底電極材料112以於開口110中形成底電極112a。移除部分底電極材料112的方法例如是以停止層108作為研磨停止層，對底電極材料進行一平坦化製程(如化學機械研磨法(CMP))，使底電極112a的上表面112S與停止層108的頂表面共平面(coplanar)。其中，該平坦化製程更可同時去除襯層(若存在)。有別於傳統的RRAM，本發明藉由在開口108中形成地底電極材料112，並以停止層108作為研磨停止層進行一平坦化製程，能有效地於底電極112a上形成平坦的的上表面112S，進而提升後續電極間介電層與頂電極之均勻度，避免傳統RRAM於底電極表面形成之柱狀晶結構的問題，大幅減少RRAM操作之 I-V特性的變異。 Next, referring to FIG. 1F, a portion of the bottom electrode material 112 is removed to form the bottom electrode 112a in the opening 110. The method of removing a portion of the bottom electrode material 112 is, for example, using the stop layer 108 as a polishing stop layer, and performing a planarization process (such as chemical mechanical polishing (CMP)) on the bottom electrode material to cause the upper surface 112S of the bottom electrode 112a to stop. The top surface of layer 108 is coplanar. Wherein, the planarization process can simultaneously remove the liner (if present). Different from the conventional RRAM, the present invention can effectively form a flat upper surface on the bottom electrode 112a by forming the ground electrode material 112 in the opening 108 and performing a planarization process using the stop layer 108 as a polishing stop layer. 112S, thereby improving the uniformity of the dielectric layer and the top electrode between the subsequent electrodes, avoiding the problem of the columnar crystal structure formed by the conventional RRAM on the surface of the bottom electrode, and greatly reducing the operation of the RRAM Variation of I-V characteristics.

請參照第1G圖，在形成底電極112a之後，於停止層108與底電極112a的表面上依序形成一介電層114與一頂電極材料116。介電層114可包括氧化矽、氮化矽、氮氧化矽、高介電常數材料(high-k dielectrics)、或其他合適的介電材料。其中，高介電常數材料可包括金屬氧化物，例如，Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、等金屬的氧化物。在一實施例中，介電層114例如為二氧化鉿(HfO₂)。頂電極材料116可包括鈦、氮化鈦、鉑、鎢、鋁、或其他合適的電極材料。 Referring to FIG. 1G, after forming the bottom electrode 112a, a dielectric layer 114 and a top electrode material 116 are sequentially formed on the surfaces of the stop layer 108 and the bottom electrode 112a. Dielectric layer 114 can include hafnium oxide, tantalum nitride, hafnium oxynitride, high-k dielectrics, or other suitable dielectric materials. Wherein, the high dielectric constant material may include a metal oxide, for example, Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb An oxide of a metal such as Dy, Ho, Er, Tm, Yb, Lu, or the like. In an embodiment, the dielectric layer 114 is, for example, hafnium oxide (HfO ₂ ). The top electrode material 116 can comprise titanium, titanium nitride, platinum, tungsten, aluminum, or other suitable electrode material.

接著，請參照第1H圖，圖案化介電層114與頂電極材料116，以分別定義出電極間介電層114a與頂電極116a，即完成RRAM 100的製作。其中，電極間介電層114a與頂電極116a部份延伸至開口110兩側的停止層108上。圖案化介電層114與頂電極材料116的方法例如可透過進行一微影與乾蝕刻製程(例如RIE)。在本發明實施例中，頂電極116a具有一下表面116S，下表面116S與底電極112a之上表面112S相對，且頂電極116a的下表面116S之面積大於底電極112a之上表面112S的面積。本發明藉由形成上述非對稱的MIM結構，能有效縮小燈絲結構118於底電極112a之上表面112S之形成區域，進而大幅降低RRAM操作之I-V特性的變異。 Next, referring to FIG. 1H, the dielectric layer 114 and the top electrode material 116 are patterned to define the inter-electrode dielectric layer 114a and the top electrode 116a, respectively, to complete the fabrication of the RRAM 100. The inter-electrode dielectric layer 114a and the top electrode 116a partially extend to the stop layer 108 on both sides of the opening 110. The method of patterning the dielectric layer 114 and the top electrode material 116 can be performed, for example, by performing a lithography and dry etching process (e.g., RIE). In the embodiment of the present invention, the top electrode 116a has a lower surface 116S, the lower surface 116S is opposite to the upper surface 112S of the bottom electrode 112a, and the area of the lower surface 116S of the top electrode 116a is larger than the area of the upper surface 112S of the bottom electrode 112a. By forming the above-mentioned asymmetric MIM structure, the present invention can effectively reduce the formation area of the filament structure 118 on the upper surface 112S of the bottom electrode 112a, thereby greatly reducing the variation of the I-V characteristics of the RRAM operation.

除上述實施例之外，本發明之RRAM可根據電極間介電層114a的材料選擇而進一步地使用複合結構的底電極。以下將搭配第2A~2E圖對本發明另一實施例之RRAM 200作詳述，為了簡潔起見，相同或相似於RRAM 100的元件以相同的標號做標記，且相同的製程步驟將不再贅述。 In addition to the above embodiments, the RRAM of the present invention can further utilize the bottom electrode of the composite structure depending on the material selection of the inter-electrode dielectric layer 114a. The RRAM 200 of another embodiment of the present invention will be described in detail below with reference to FIGS. 2A-2E. For the sake of brevity, components identical or similar to RRAM 100 are labeled with the same reference numerals. Marked, and the same process steps will not be described again.

請參照第2A圖，其為接續在第1D圖的步驟之後的示意圖。在一實施例中，在形成開口110後，可選擇性地(optionally)在開口110中與停止層108上順應性地形成一襯層220，其作用為減少應力。襯層220可為一導電材料，例如為鈦、氮化鈦、或前述之組合。襯層220與導電層104a電性接觸。接著，於開口110中與停止層108上方形成一第一底電極材料230。第一底電極材料230可包括鎢、銅、鋁、或其他合適的電極材料。在一實施例中，第一底電極材料230例如為鎢。第一底電極材料230的形成方法可包括PVD、ALD、MOCVD或其他合適的沉積製程。 Please refer to FIG. 2A, which is a schematic diagram following the step of FIG. 1D. In an embodiment, after the opening 110 is formed, a liner 220 may be selectively formed in the opening 110 and the stop layer 108, which acts to reduce stress. The liner 220 can be a conductive material such as titanium, titanium nitride, or a combination of the foregoing. The liner 220 is in electrical contact with the conductive layer 104a. Next, a first bottom electrode material 230 is formed in the opening 110 and above the stop layer 108. The first bottom electrode material 230 can comprise tungsten, copper, aluminum, or other suitable electrode material. In an embodiment, the first bottom electrode material 230 is, for example, tungsten. The method of forming the first bottom electrode material 230 may include PVD, ALD, MOCVD, or other suitable deposition process.

接著，請參照第2B圖，移除停止層108上與部份位於開口110中的第一底電極材料230以形成第一底電極230a。移除第一底電極材料230的方法可包括乾蝕刻製程，例如RIE製程。在第2B圖的步驟中，停止層108係作為蝕刻停止層，且此步驟同時移除開口110以外的部份襯層220(若存在)。 Next, referring to FIG. 2B, the first bottom electrode material 230 on the stop layer 108 and partially located in the opening 110 is removed to form the first bottom electrode 230a. The method of removing the first bottom electrode material 230 may include a dry etching process, such as an RIE process. In the step of FIG. 2B, the stop layer 108 acts as an etch stop layer, and this step simultaneously removes a portion of the liner 220 (if present) outside of the opening 110.

接著，如第2C圖所示，於第一底電極230a與停止層108之上形成第二底電極材料240。第二底電極材料240可包括鈦、鉑、氮化鈦、或其他合適的電極材料。在一實施例中，第二底電極材料240例如為為氮化鈦。 Next, as shown in FIG. 2C, a second bottom electrode material 240 is formed over the first bottom electrode 230a and the stop layer 108. The second bottom electrode material 240 can comprise titanium, platinum, titanium nitride, or other suitable electrode material. In an embodiment, the second bottom electrode material 240 is, for example, titanium nitride.

接著，請參照第2D圖，移除部分第二底電極材料240以於開口110中形成第二底電極240a，完成本實施例之複合結構的底電極250。如第2D圖所示，底電極250包括第一底電極230a與第二底電極材料240a。移除部分第二底電極材料240的方法例如是以停止層108作為研磨停止層，對第二底電極材料240進行一平坦化製程(例如化學機械研磨法(CMP))，使底電極250的上表面250S與停止層108的頂表面共平面(coplanar)。 Next, referring to FIG. 2D, a portion of the second bottom electrode material 240 is removed to form a second bottom electrode 240a in the opening 110 to complete the bottom electrode 250 of the composite structure of the present embodiment. As shown in FIG. 2D, the bottom electrode 250 includes a first bottom electrode 230a and a second bottom electrode material 240a. The method of removing a portion of the second bottom electrode material 240 is performed by, for example, stopping the layer 108 as a polishing stop layer to planarize the second bottom electrode material 240. A process, such as chemical mechanical polishing (CMP), causes the upper surface 250S of the bottom electrode 250 to be coplanar with the top surface of the stop layer 108.

最後，如第2E圖所示，於停止層108與底電極250上形成電極間介電層114a與頂電極116a，完成本實施例之RRAM 200的結構。電極間介電層114a與頂電極116a的形成方法相同於第1G圖~第1H圖及其相關段落，故在此不再贅述。RRAM 200的頂電極116a具有一下表面116S，下表面116S與底電極250之上表面250S相對，且頂電極116a的下表面116S之面積大於底電極250a之上表面250S的面積。值得注意的是，本實施例藉由形成複合材料的底電極，可有效降低RRAM之電阻，提升RRAM之操作效能。 Finally, as shown in FIG. 2E, the inter-electrode dielectric layer 114a and the top electrode 116a are formed on the stop layer 108 and the bottom electrode 250 to complete the structure of the RRAM 200 of the present embodiment. The method of forming the inter-electrode dielectric layer 114a and the top electrode 116a is the same as that of the first to third figures and the related paragraphs, and therefore will not be described again. The top electrode 116a of the RRAM 200 has a lower surface 116S opposite the upper surface 250S of the bottom electrode 250, and the area of the lower surface 116S of the top electrode 116a is larger than the area of the upper surface 250S of the bottom electrode 250a. It should be noted that, in this embodiment, by forming the bottom electrode of the composite material, the resistance of the RRAM can be effectively reduced, and the operational efficiency of the RRAM can be improved.

本發明藉由在製造RRAM的製程中，將底電極材料形成於開口中，並使用停止層研磨底電極材料以移除底電極材料自然形成的柱狀晶。如此一來，可形成具有平坦表面的底電極，進而提升後續所沉積之電極間介電層的均勻度，大幅減少RRAM操作之I-V特性的變異。除此之外，本發明更藉由形成不對稱的MIM結構(即頂電極的下表面大於底電極的上表面)，能有效縮小燈絲結構於底電極之上表面的形成區域，進而大幅降低RRAM操作之I-V特性的變異。 The present invention forms a bottom electrode material in an opening in a process of fabricating an RRAM, and polishes the bottom electrode material using a stop layer to remove columnar crystals naturally formed by the bottom electrode material. In this way, a bottom electrode having a flat surface can be formed, thereby improving the uniformity of the subsequently deposited inter-electrode dielectric layer and greatly reducing variations in the I-V characteristics of the RRAM operation. In addition, the present invention can effectively reduce the formation area of the filament structure on the upper surface of the bottom electrode by forming an asymmetric MIM structure (ie, the lower surface of the top electrode is larger than the upper surface of the bottom electrode), thereby greatly reducing the RRAM. Variation in the IV characteristics of the operation.

雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧電阻式記憶體 100‧‧‧Resistive memory

102‧‧‧基底 102‧‧‧Base

104a‧‧‧導電層 104a‧‧‧ Conductive layer

106‧‧‧介電層 106‧‧‧Dielectric layer

108‧‧‧停止層 108‧‧‧stop layer

112a‧‧‧底電極 112a‧‧‧ bottom electrode

114a‧‧‧電極間介電層 114a‧‧‧Interelectrode dielectric layer

116a‧‧‧頂電極 116a‧‧‧ top electrode

118‧‧‧絲狀結構 118‧‧‧filament structure

112S‧‧‧上表面 112S‧‧‧ upper surface

116S‧‧‧下表面 116S‧‧‧ lower surface

Claims

一種電阻式記憶體的製造方法，包括：提供一基底；形成一介電層於該基底之上；形成一停止層於該介電層上；形成一開口穿過該停止層與該介電層；形成一底電極於該開口之中，其中該底電極與該停止層共平面(coplanar)；沉積一介電層於該底電極與該停止層之上；沉積一頂電極材料於該介電層上；以及圖案化該頂電極材料與該介電層，以定義出一頂電極以及其下的一電極間介電層，其中該頂電極具有一第二表面與該底電極之一第一表面相對，且該第二表面的面積大於該第一表面的面積，其中形成該底電極的步驟，包括：沉積一底電極材料填滿於該開口中且覆蓋該停止層；以及以該停止層作為研磨停止層並研磨該底電極材料，以去除該開口以外的該底電極材料。 A method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer Forming a bottom electrode in the opening, wherein the bottom electrode is coplanar with the stop layer; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric And patterning the top electrode material and the dielectric layer to define a top electrode and an inter-electrode dielectric layer therebelow, wherein the top electrode has a second surface and the bottom electrode is first The surface is opposite, and the area of the second surface is larger than the area of the first surface, wherein the step of forming the bottom electrode comprises: depositing a bottom electrode material to fill the opening and covering the stop layer; and stopping the layer The bottom electrode material is polished as a polishing stop layer to remove the bottom electrode material other than the opening.

一種電阻式記憶體的製造方法，包括：提供一基底；形成一介電層於該基底之上；形成一停止層於該介電層上；形成一開口穿過該停止層與該介電層；形成一底電極於該開口之中，其中該底電極與該停止層共平面(coplanar)；沉積一介電層於該底電極與該停止層之上；沉積一頂電極材料於該介電層上；以及圖案化該頂電極材料與該介電層，以定義出一頂電極以及其下的一電極間介電層，其中該頂電極具有一第二表面與該底電極之一第一表面相對，且該第二表面的面積大於該第一表面的面積，其中形成該底電極的步驟，包括：沉積一第一底電極材料填滿該開口中且覆蓋該停止層；凹蝕該底電極材料，使該第一底電極材料部分填充於該開口中；沉積一第二底電極材料填滿該開口中的其餘部分且覆蓋該停止層；以及以該停止層作為研磨停止層研磨該第二底電極材料，以去除該開口以外的該第二底電極材料。 A method of manufacturing a resistive memory, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a stop layer on the dielectric layer; forming an opening through the stop layer and the dielectric layer Forming a bottom electrode in the opening, wherein the bottom electrode is associated with the stop layer Coplanar; depositing a dielectric layer over the bottom electrode and the stop layer; depositing a top electrode material on the dielectric layer; and patterning the top electrode material and the dielectric layer to define a a top electrode and an inter-electrode dielectric layer thereunder, wherein the top electrode has a second surface opposite to a first surface of the bottom electrode, and an area of the second surface is larger than an area of the first surface, wherein the top surface is formed The step of the bottom electrode includes: depositing a first bottom electrode material to fill the opening and covering the stop layer; recessing the bottom electrode material to partially fill the first bottom electrode material in the opening; depositing a first A second bottom electrode material fills the remaining portion of the opening and covers the stop layer; and the second bottom electrode material is ground with the stop layer as a polishing stop layer to remove the second bottom electrode material other than the opening.

如申請專利範圍第2項所述之電阻式記憶體的製造方法，其中該第一底電極材料包括鎢、銅、鋁、或前述之組合，而該第二底電極材料包括氮化鈦、鈦、鉑、或前述之組合。 The method of manufacturing a resistive memory according to claim 2, wherein the first bottom electrode material comprises tungsten, copper, aluminum, or a combination thereof, and the second bottom electrode material comprises titanium nitride and titanium. , platinum, or a combination of the foregoing.

如申請專利範圍第1項或第2項所述之電阻式記憶體的製造方法，其中該停止層包括氮化矽、氮氧化矽、或前述之組合。 The method of manufacturing a resistive memory according to claim 1 or 2, wherein the stop layer comprises tantalum nitride, hafnium oxynitride, or a combination thereof.

如申請專利範圍第1項或第2項所述之電阻式記憶體的製造方法，其中在形成該介電層的步驟之前，更包括：形成一導電層於該基底之上；以及圖案化該導電層，其中該導電層於形成該開口的步驟被露出。 The method of manufacturing the resistive memory of claim 1 or 2, wherein before the step of forming the dielectric layer, further comprising: forming a conductive layer on the substrate; The conductive layer is patterned, wherein the conductive layer is exposed at the step of forming the opening.

如申請專利範圍第1項或第2項所述之電阻式記憶體的製造方法，更包括：在形成該底電極的步驟之前，形成一襯層(liner)於該開口的底部與側壁上。 The method for manufacturing a resistive memory according to the first or second aspect of the invention, further comprising: forming a liner on the bottom and the side wall of the opening before the step of forming the bottom electrode.

一種電阻式記憶體，包括：一基底；一介電層，於該基底之上；一停止層，於該介電層之上；一開口，穿過該停止層與該介電層；一底電極，於該開口之中，且與該停止層共平面；一電極間介電層，於該底電極之上且延伸至部份的停止層之上；以及一頂電極，於該電極間介電層之上，其中該頂電極具有一第二表面與該底電極之一第一表面相對，且該第二表面的面積大於該第一表面的面積。 A resistive memory comprising: a substrate; a dielectric layer over the substrate; a stop layer over the dielectric layer; an opening through the stop layer and the dielectric layer; An electrode, in the opening, and coplanar with the stop layer; an inter-electrode dielectric layer over the bottom electrode and extending over a portion of the stop layer; and a top electrode interposed between the electrodes Above the electrical layer, wherein the top electrode has a second surface opposite the first surface of the bottom electrode, and the second surface has an area greater than an area of the first surface.

如申請專利範圍第7項所述之電阻式記憶體，其中該底電極包括：一第一底電極材料，部分填於該開口之中；以及一第二底電極材料，位於該第一底電極材料之上，其中該第二底電極材料之頂表面與該停止層共平面。 The resistive memory of claim 7, wherein the bottom electrode comprises: a first bottom electrode material partially filled in the opening; and a second bottom electrode material located at the first bottom electrode Above the material, wherein a top surface of the second bottom electrode material is coplanar with the stop layer.

如申請專利範圍第8項所述之電阻式記憶體，其中該第一底電極材料包括鎢、銅、鋁、或前述之組合，而該第二底電極材料包括氮化鈦、鈦、鉑、或前述之組合。 The resistive memory of claim 8, wherein the first bottom electrode material comprises tungsten, copper, aluminum, or a combination thereof, and the second bottom electricity The polar material includes titanium nitride, titanium, platinum, or a combination of the foregoing.

如申請專利範圍第7項所述之電阻式記憶體，其中該停止層包括氮化矽、氮氧化矽、或前述之組合。 The resistive memory of claim 7, wherein the stop layer comprises tantalum nitride, hafnium oxynitride, or a combination thereof.

如申請專利範圍第7項所述之電阻式記憶體，更包括：一導電層，於該介電層下，其中該開口暴露出一部份的該導電層。 The resistive memory of claim 7, further comprising: a conductive layer under the dielectric layer, wherein the opening exposes a portion of the conductive layer.

如申請專利範圍第7項所述之電阻式記憶體，更包括：一襯層，內襯於該開口之側壁與底部上，其中該底電極係填於該開口中的該襯層之上。 The resistive memory of claim 7, further comprising: a liner layer lining the sidewall and the bottom of the opening, wherein the bottom electrode is filled on the liner in the opening.