TWI520492B - Level shifter - Google Patents
Level shifter Download PDFInfo
- Publication number
- TWI520492B TWI520492B TW103122517A TW103122517A TWI520492B TW I520492 B TWI520492 B TW I520492B TW 103122517 A TW103122517 A TW 103122517A TW 103122517 A TW103122517 A TW 103122517A TW I520492 B TWI520492 B TW I520492B
- Authority
- TW
- Taiwan
- Prior art keywords
- node
- switch
- voltage
- type transistor
- signal
- Prior art date
Links
Landscapes
- Electronic Switches (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
本發明係有關一種轉壓器,尤指一種能有效縮減布局面積的轉壓器。 The invention relates to a pressure converter, in particular to a pressure converter capable of effectively reducing the layout area.
轉壓器可接收信號範圍較小的輸入信號,並將其對應地轉換為信號範圍較大的輸出信號,是介面電路中的重要構築方塊。譬如說,在驅動顯示面板的源極驅動器(source driver)晶片中,晶片中原始控制信號的信號範圍可以是0到1.5伏特,然而輸出驅動顯示面板的源極時,所需的信號範圍可能就要轉換擴大到-5到0伏特。為了在兩種信號範圍間進行轉換,就需要使用到轉壓器,用以將0到1.5伏特的輸入信號轉換為-5到0伏特的輸出信號。由於此種轉換是將輸入信號的信號範圍下限轉換為輸出信號的信號範圍上限,故可視為一種轉負壓的操作。 The converter can receive an input signal with a small signal range and convert it correspondingly into an output signal with a large signal range, which is an important building block in the interface circuit. For example, in a source driver chip that drives a display panel, the signal range of the original control signal in the chip can be 0 to 1.5 volts. However, when the output drives the source of the display panel, the required signal range may be To convert to expand to -5 to 0 volts. In order to convert between the two signal ranges, a transducer is required to convert the input signal from 0 to 1.5 volts to an output signal of -5 to 0 volts. Since this conversion is to convert the lower limit of the signal range of the input signal to the upper limit of the signal range of the output signal, it can be regarded as an operation of turning negative pressure.
請參考第1圖,其所示意的是一習知轉壓器10,用以達成轉負壓的目的。在習知技術中,若要將信號範圍介於電壓VSS至VPP的輸入信號IN轉負壓為信號範圍在電壓VSSL至VSS間的輸出信號OUT,習知轉壓器10必須經過三階段才能實現此種轉負壓運作。 Please refer to Fig. 1, which is a conventional converter 10 for achieving the purpose of turning negative pressure. In the prior art, if the input signal IN of the signal range of VSS to VPP is to be converted to the output signal OUT of the signal range between the voltages VSSL and VSS, the conventional converter 10 must undergo three stages. This type of negative pressure operation.
在轉壓器10中,轉壓器LS1、反相器INV0與另一轉壓器LS2即分別進行上述三階段的轉換,其中,運作於電壓VPP至VSSH的轉壓器LS1進行第一重轉壓,將輸入信號IN轉換為信號OUTa,使信號OUTa的信號範圍在電壓VSSH至VPP之間;運作於電壓VSS至VSSH的反相器INV0進行第二重轉壓, 將信號OUTa轉換為信號OUTb,並使信號OUTb的信號範圍落在電壓VSSH至VSS之間;最後,運作於電壓VSS至VSSL的轉壓器LS2則進行第三重轉壓,將信號OUTb轉換為輸出信號OUT,使輸出信號OUT的信號範圍能在電壓VSSL至VSS之間。 在上述各重轉換中,舉例來說,電壓VSSL、VSSH、VSS與VPP可分別為-5、-1.5、0,及1.5伏特,用以將0至1.5伏特的輸入信號IN轉負壓為-5至0伏特的輸出信號OUT。 In the converter 10, the converter LS1, the inverter INV0 and the other converter LS2 respectively perform the above three-stage conversion, wherein the converter LS1 operating at the voltages VPP to VSSH performs the first re-rotation Pressing, the input signal IN is converted into the signal OUTa, the signal range of the signal OUTa is between the voltage VSSH to VPP; the inverter INV0 operating at the voltage VSS to VSSH performs the second re-rotation, The signal OUTa is converted into the signal OUTb, and the signal range of the signal OUTb falls between the voltages VSSH to VSS; finally, the voltage converter LS2 operating at the voltage VSS to VSSL performs the third re-transfer, converting the signal OUTb into The output signal OUT is such that the signal range of the output signal OUT can be between the voltages VSSL to VSS. In the above various conversions, for example, the voltages VSSL, VSSH, VSS, and VPP may be -5, -1.5, 0, and 1.5 volts, respectively, for converting the input signal IN of 0 to 1.5 volts to a negative voltage - Output signal OUT of 5 to 0 volts.
雖然輸入信號IN的信號範圍下限相當於輸出信號 OUT的信號範圍上限(均為電壓VSS),不過在上述各重轉換中,當轉換器LS1、LS2與反相器INV0各自在輸出入信號範圍間進行轉換時,都只能基於相同的信號範圍上限或下限進行轉換。也就是說,轉換器LS1是以輸出入信號的信號範圍上限為基準而進行轉換,輸入信號IN的信號範圍上限需與信號OUTa的信號範圍上限(即電壓VPP)相等。反相器INV0則是基於共同的輸出入信號範圍下限而進行轉換,信號OUTa的信號範圍下限與信號OUTb的信號範圍下限相等。轉換器LS2則在輸出入信號間以相同的信號範圍上限進行轉換,信號OUTb的信號範圍上限須與輸出信號OUT的信號範圍上限相等。綜合上述三重轉換,習知轉壓器10才能實現轉負壓的目的。 Although the lower limit of the signal range of the input signal IN is equivalent to the output signal The upper limit of the signal range of OUT (both voltage VSS), but in each of the above-mentioned re-conversions, when the converters LS1, LS2 and inverter INV0 are each converted between the input and output signal ranges, they can only be based on the same signal range. The upper or lower limit is converted. That is to say, the converter LS1 is converted based on the upper limit of the signal range of the input/output signal, and the upper limit of the signal range of the input signal IN is equal to the upper limit of the signal range of the signal OUTa (that is, the voltage VPP). The inverter INV0 is converted based on the lower limit of the common input-in signal range, and the lower limit of the signal range of the signal OUTa is equal to the lower limit of the signal range of the signal OUTb. The converter LS2 converts the same signal range upper limit between the input and output signals, and the signal range upper limit of the signal OUTb must be equal to the upper limit of the signal range of the output signal OUT. In combination with the above three-fold conversion, the conventional pressure converter 10 can achieve the purpose of turning negative pressure.
更進一步說明,習知轉換器10須以三個電路(轉壓 器LS1、LS2與反相器INV0)分別進行三重轉換的原因之一是要確保各電路中的電晶體不會因過大的電壓差而造成崩潰損壞,其中,在將信號轉換至較大信號範圍時,各電晶體在各極間的電壓差也會變大,進而影響電晶體的可靠度。不過,由於在三重轉換架構下,轉壓器LS1、LS2與反相器INV0的布局面積總和也會較大,使得習知轉壓器10的整體布局面積無法有效縮減。 To further illustrate, the conventional converter 10 must be in three circuits (rotating One of the reasons for the triple conversion of LS1, LS2 and inverter INV0) is to ensure that the transistors in each circuit are not damaged by excessive voltage differences, in which the signal is converted to a larger signal range. At the same time, the voltage difference between the electrodes of each transistor also becomes large, which in turn affects the reliability of the transistor. However, since the total layout area of the converters LS1, LS2 and the inverter INV0 is also large under the triple conversion architecture, the overall layout area of the conventional converter 10 cannot be effectively reduced.
本發明係有關於一種轉壓器,將一輸入信號轉換為 一輸出信號,包括:一第一N型電晶體,具有一第一汲極連接至一第一電源電壓,一第一閘極接收該輸入信號,以及一第一源極連接至一第一節點;一第二N型電晶體,具有一第二汲極連接至該第一電源電壓,一第二閘極接收反相的該輸入信號,以及一第二源極連接至一第二節點;一第一P型電晶體,具有一第三源極連接至該第一節點,一第三汲極連接至一第三節點,以及一第三閘極連接至一第四節點;一第二P型電晶體,具有一第四源極連接至該第二節點,一第四汲極連接至該第四節點,以及一第四閘極連接至該第三節點,其中該第三節點產生該輸出信號,且該第四節點產生反相的該輸出信號;一第三N型電晶體,具有一第五汲極連接至該第三節點,一第五源極連接至一第二電源電壓,以及一第五閘極連接至該第四節點;一第四N型電晶體,具有一第六汲極連接至該第四節點,一第六源極連接至該第二電源電壓,以及一第六閘極連接至該第三節點;以及一開關單元,連接於該第三節點與該第四節點之間,於該輸入信號轉換準位時,控制該開關單元根據一致能訊號用以關閉一時間周期後斷開,進而使得該輸出信號轉換準位;其中,該輸出信號具有一第一準位時為該第一電源電壓,該輸出信號具有一第二準位時為該第二電源電壓,該第一電源電壓大於該第二電源電壓,以及該第二電源電壓為負值。 The invention relates to a pressure converter for converting an input signal into An output signal includes: a first N-type transistor having a first drain connected to a first supply voltage, a first gate receiving the input signal, and a first source connected to a first node a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a second source coupled to a second node; a first P-type transistor having a third source connected to the first node, a third drain connected to a third node, and a third gate connected to a fourth node; a second P-type a transistor having a fourth source connected to the second node, a fourth drain connected to the fourth node, and a fourth gate connected to the third node, wherein the third node generates the output signal And the fourth node generates the inverted output signal; a third N-type transistor having a fifth drain connected to the third node, a fifth source connected to a second supply voltage, and a a fifth gate is connected to the fourth node; a fourth N-type transistor has a sixth a pole connected to the fourth node, a sixth source connected to the second power voltage, and a sixth gate connected to the third node; and a switching unit connected to the third node and the fourth node During the switching of the input signal, the switching unit is controlled to be turned off according to the consistent energy signal for a period of time, thereby causing the output signal to be converted to a level; wherein the output signal has a first level The first power voltage is when the output signal has a second level, the second power voltage is greater than the second power voltage, and the second power voltage is a negative value.
本發明更提出一種轉壓器,用以將一輸入信號轉換 為一輸出信號,包括:一第一N型電晶體,具有一第一汲極連接至一第一電源電壓,一第一閘極接收該輸入信號,以及一第一源極連接至一第一節點;一第二N型電晶體,具有一第二汲極連接至該第一電源電壓,一第二閘極接收反相的該輸入信號,以及一第二源極連接至一第二節點;一第三節點,產生該輸出信號;一第四節點,產生反相的該輸出信號;一第一P型電晶體,具有一第三源極連接至該第一節點,一第三汲極,以及一第三閘極連接至該第四節點;一第二P型電晶體,具有一第四源極連接至該第 二節點,一第四汲極,以及一第四閘極連接至該第三節點;一第一開關,連接於第一P型電晶體的該第三汲極與該第三節點之間,並根據一第一致能信號動作;一第二開關,連接於該第二P型電晶體的該第四汲極與該第四節點之間,並根據該第一致能信號動作;一第三N型電晶體,具有一第五汲極連接至該第三節點,一第五源極連接至一第二電源電壓,以及一第五閘極連接至該第四節點;一第四N型電晶體,具有一第六汲極連接至該第四節點,一第六源極連接至該第二電源電壓,以及一第六閘極連接至該第三節點;以及一開關單元,連接於該第三節點與該第四節點之間,用以根據一第二致能信號於該輸入信號轉換準位時,控制該開關單元關閉一時間周期後斷開,進而使得該輸出信號轉換準位;其中,該輸出信號具有的一第一準位時為該第一電源電壓,該輸出信號具有一第二準位時為該第二電源電壓,該第一電源電壓大於該第二電源電壓,該第二電源電壓為負值,以及該第一開關與該第二開關係根據該第一致能信號於該時間周期內斷開。 The invention further provides a converter for converting an input signal An output signal includes: a first N-type transistor having a first drain connected to a first supply voltage, a first gate receiving the input signal, and a first source connected to a first a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a second source coupled to a second node; a third node generating the output signal; a fourth node generating the inverted output signal; a first P-type transistor having a third source connected to the first node and a third drain And a third gate is connected to the fourth node; a second P-type transistor has a fourth source connected to the first a second node, a fourth drain, and a fourth gate connected to the third node; a first switch connected between the third drain of the first P-type transistor and the third node, and Acting according to a first enable signal; a second switch connected between the fourth drain of the second P-type transistor and the fourth node, and acting according to the first enable signal; An N-type transistor having a fifth drain connected to the third node, a fifth source connected to a second supply voltage, and a fifth gate connected to the fourth node; a fourth N-type a crystal having a sixth drain connected to the fourth node, a sixth source connected to the second supply voltage, and a sixth gate connected to the third node; and a switching unit coupled to the first Between the three nodes and the fourth node, when the second signal is used to switch the level according to the second enable signal, the switch unit is controlled to be turned off after a period of time, and then the output signal is converted into a level; When the output signal has a first level, the first power voltage is When the output signal has a second level, the second power voltage is greater than the second power voltage, the second power voltage is a negative value, and the first switch and the second switch relationship are The first consistent energy signal is turned off during the time period.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下: In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
10‧‧‧轉壓器 10‧‧‧Transducer
20‧‧‧轉壓器 20‧‧‧Transducer
30‧‧‧轉壓器 30‧‧‧Transducer
40‧‧‧轉壓器 40‧‧‧Transducer
LS1、LS2‧‧‧轉壓器 LS1, LS2‧‧‧Transducer
INV0‧‧‧反相器 INV0‧‧‧Inverter
MN1、MN2、MN3、MN4‧‧‧N型電晶體 MN1, MN2, MN3, MN4‧‧‧N type transistor
MP1、MP2‧‧‧P型電晶體 MP1, MP2‧‧‧P type transistor
SW、SW1、SW2、SW3、SW4‧‧‧開關 SW, SW1, SW2, SW3, SW4‧‧‧ switch
VSS‧‧‧第一電源電壓 VSS‧‧‧First supply voltage
IN‧‧‧輸入信號 IN‧‧‧ input signal
INB‧‧‧反相輸入信號 INB‧‧‧Inverting input signal
a、b、c、d‧‧‧第一至第四節點 a, b, c, d‧‧‧ first to fourth nodes
EN‧‧‧致能信號 EN‧‧‧Enable signal
OUT‧‧‧輸出信號 OUT‧‧‧ output signal
OUTB‧‧‧反相輸出信號 OUTB‧‧‧Inverted output signal
VSSL‧‧‧第二電源電壓 VSSL‧‧‧second supply voltage
第1圖所示意的是一習知轉壓器。 Figure 1 shows a conventional pressure converter.
第2A圖與第2B圖所繪示為本發明的轉壓器的第一實施例及其相關信號示意圖。 2A and 2B are diagrams showing a first embodiment of the converter of the present invention and related signal diagrams.
第3圖所繪示為本發明的轉壓器的第二實施例。 Figure 3 is a view showing a second embodiment of the pressure converter of the present invention.
第4圖所繪示為本發明的轉壓器的第三實施例。 Figure 4 is a view showing a third embodiment of the pressure converter of the present invention.
本發明利用少數幾個電晶體來組成轉壓器,並實現轉負壓的目的。再者,以下實施例係以輸入信號(IN)與反相輸入 信號(INB)的信號範圍為1.5伏特至0伏特區間,且輸出信號(OUT)與反相輸出信號(OUTB)的信號範圍為0伏特與-5伏特區間。然而本發明並非限定於此。 The invention utilizes a few transistors to form a converter and achieve the purpose of turning negative pressure. Furthermore, the following embodiments use an input signal (IN) and an inverting input. The signal (INB) has a signal range of 1.5 volts to 0 volts, and the output signal (OUT) and inverted output signal (OUTB) have a signal range of 0 volts to -5 volts. However, the invention is not limited thereto.
請參照第2A圖與第2B圖,其所繪示為本發明的轉 壓器的第一實施例及其相關信號示意圖。其中,轉壓器20包括:一開關(SW)、第一N型電晶體(MN1)、第二N型電晶體(MN2)、第三N型電晶體(MN3)、第四N型電晶體(MN4)、第一P型電晶體(MP1)、與第二P型電晶體(MP2)。再者,第一電源電壓(VSS)為0伏特,第二電源電壓(VSSL)為-5伏特。 Please refer to FIG. 2A and FIG. 2B, which are illustrated as the turn of the present invention. A first embodiment of the press and its associated signal schematic. The converter 20 includes: a switch (SW), a first N-type transistor (MN1), a second N-type transistor (MN2), a third N-type transistor (MN3), and a fourth N-type transistor. (MN4), a first P-type transistor (MP1), and a second P-type transistor (MP2). Furthermore, the first supply voltage (VSS) is 0 volts and the second supply voltage (VSSL) is -5 volts.
第一N型電晶體(MN1)汲極連接至第一電源電壓 (VSS);閘極接收輸入信號(IN);源極連接至第一節點(a)。第二N型電晶體(MN2)汲極連接至第一電源電壓(VSS);閘極接收反相輸入信號(INB);源極連接至第二節點(b)。 The first N-type transistor (MN1) is connected to the first supply voltage (VSS); the gate receives the input signal (IN); the source is connected to the first node (a). The second N-type transistor (MN2) is connected to the first supply voltage (VSS), the gate receives the inverted input signal (INB), and the source is connected to the second node (b).
第一P型電晶體(MP1)源極連接至第一節點(a);汲 極連接至第三節點(c);閘極連接至第四節點(d)。第二P型電晶體(MP2)源極連接至第二節點(b);汲極連接至第四節點(d);閘極連接至第三節點(c)。 The first P-type transistor (MP1) source is connected to the first node (a); The pole is connected to the third node (c); the gate is connected to the fourth node (d). The second P-type transistor (MP2) source is connected to the second node (b); the drain is connected to the fourth node (d); and the gate is connected to the third node (c).
第三N型電晶體(MN3)汲極連接至第三節點(c);源 極連接至第二電源電壓(VSSL);閘極連接至第四節點(d)。第四N型電晶體(MN4)汲極連接至第四節點(d);源極連接至第二電源電壓(VSSL);閘極連接至第三節點(c)。 The third N-type transistor (MN3) is connected to the third node (c); the source The pole is connected to the second supply voltage (VSSL); the gate is connected to the fourth node (d). The fourth N-type transistor (MN4) is connected to the fourth node (d); the source is connected to the second supply voltage (VSSL); and the gate is connected to the third node (c).
開關(SW)連接於第三節點(c)與第四節點(d)之間,且 該開關受控於致能信號(EN)。再者,第三節點(c)可產生輸出信號(OUT),第四節點(d)可產生反相輸出信號(OUTB)。 a switch (SW) is connected between the third node (c) and the fourth node (d), and The switch is controlled by an enable signal (EN). Furthermore, the third node (c) can generate an output signal (OUT), and the fourth node (d) can generate an inverted output signal (OUTB).
當轉壓器20處於第一穩定狀態(steady state)時,致能信號(EN)為禁能(disable),輸入信號(IN)為1.5伏特;反相輸入信號(INB)為0伏特;輸出信號(OUT)為0伏特的第一電源電壓(VSS);反相輸出信號(OUTB)為-5伏特的第二電源電壓(VSSL)。很明顯地,於第一穩定狀態時,開關(SW)為斷開(open);第一N 型電晶體(MN1)開啟(turn on);第二N型電晶體(MN2)不開啟(turn off);第一P型電晶體(MP1)開啟(turn on);第二P型電晶體(MP2)不開啟(turn off);第三N型電晶體(MN3)不開啟(turn off);第四N型電晶體(MN4)開啟(turn on)。 When the converter 20 is in the first steady state, the enable signal (EN) is disabled, the input signal (IN) is 1.5 volts; the inverting input signal (INB) is 0 volts; The signal (OUT) is a first supply voltage (VSS) of 0 volts; the inverted output signal (OUTB) is a second supply voltage (VSSL) of -5 volts. Obviously, in the first steady state, the switch (SW) is open; the first N The type transistor (MN1) turns on; the second N-type transistor (MN2) does not turn off; the first P-type transistor (MP1) turns on; the second P-type transistor ( MP2) does not turn off; the third N-type transistor (MN3) does not turn off; the fourth N-type transistor (MN4) turns on.
當輸入信號(IN)由1.5伏特轉換為0伏特,且反相輸 入信號(INB)由0伏特轉換為1.5伏特時,致能信號(EN)為禁能(disable),輸出信號(OUT)維持在0伏特的第一電源電壓(VSS),反相輸出信號(OUTB)維持在-5伏特的第二電源電壓(VSSL)。 When the input signal (IN) is converted from 1.5 volts to 0 volts, and the inverting input When the input signal (INB) is converted from 0 volts to 1.5 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at 0 volts of the first supply voltage (VSS), and the inverted output signal ( OUTB) maintains a second supply voltage (VSSL) at -5 volts.
此時,開關(SW)為斷開(open);第一N型電晶體 (MN1)與第一P型電晶體(MP1)皆不開啟(turn off),使得第一節點(a)為浮接狀態(floating);第二N型電晶體(MN2)開啟(turn off)且第二P型電晶體(MP2)不開啟(turn off),使得第二節點(b)為0伏特的第一電源電壓(VSS);第三N型電晶體(MN3)不開啟(turn off);第四N型電晶體(MN4)開啟(turn on)。 At this time, the switch (SW) is open; the first N-type transistor (MN1) and the first P-type transistor (MP1) are not turned off, so that the first node (a) is floating (floating); the second N-type transistor (MN2) is turned off (turn off) And the second P-type transistor (MP2) is not turned off, so that the second node (b) is a first power supply voltage (VSS) of 0 volts; the third N-type transistor (MN3) is not turned on (turn off) ); the fourth N-type transistor (MN4) turns on.
接著,利用致能信號(EN)短暫地致能(enable)開關 (SW)後再次禁能(disable),使得開關(SW)短暫的關閉(close)又斷開(open)。於開關(SW)關閉的短暫時間周期中,由於第三節點(c)與第四節點(d)之間短路,造成電賀分享(charge sharing)使得第三節點(c)與第四節點(d)的電壓變化至相同的電壓(例如-2.5伏特)。 亦即,第三節點(c)的電壓由0伏特的第一電源電壓(VSS)下降至-2.5伏特,第四節點(d)的電壓由-5伏特的第二電源電壓(VSSL)上升至-2.5伏特。 Next, enable the switch briefly with the enable signal (EN) After (SW), disable again, causing the switch (SW) to briefly close and open. During a short period of time during which the switch (SW) is turned off, due to a short circuit between the third node (c) and the fourth node (d), charge sharing is performed such that the third node (c) and the fourth node (d) The voltage changes to the same voltage (for example -2.5 volts). That is, the voltage of the third node (c) drops from the first supply voltage (VSS) of 0 volts to -2.5 volts, and the voltage of the fourth node (d) rises from the second supply voltage (VSSL) of -5 volts to -2.5 volts.
由於第三節點(c)的電壓下降至-2.5伏特,將使得第 二P型電晶體(MP2)開啟(turn on)且第四N型電晶體(MN4)不開啟(turn off),使得第四節點(d)的電壓由-2.5伏特繼續上升至0伏特的第一電源電壓(VSS)。再者,第三N型電晶體(NM3)由於第四節點(d)的電壓升高而開啟(turn on),使得第三節點(c)的電壓由-2.5伏特繼續下降至-5伏特的第二電源電壓(VSSL)。 Since the voltage at the third node (c) drops to -2.5 volts, it will make The second P-type transistor (MP2) turns on and the fourth N-type transistor (MN4) does not turn off, so that the voltage of the fourth node (d) continues to rise from -2.5 volts to 0 volts. A power supply voltage (VSS). Furthermore, the third N-type transistor (NM3) turns on due to the voltage increase of the fourth node (d), so that the voltage of the third node (c) continues to drop from -2.5 volts to -5 volts. Second supply voltage (VSSL).
由以上的說明可知,當輸入信號(IN)由1.5伏特轉換 為0伏特,且反相輸入信號(INB)由0伏特轉換為1.5伏特時,只要利用致能信號(EN)控制開關(SW)短暫的關閉(close)又斷開(open),即可順利地讓第三節點(c)的電壓由0伏特的第一電源電壓(VSS)變化至-5伏特的第二電源電壓(VSSL),並讓第四節點(d)的電壓由-5伏特的第二電源電壓(VSSL)變化升至0伏特的第一電源電壓(VSS)。之後,即維持在第二穩定狀態。 As can be seen from the above description, when the input signal (IN) is converted by 1.5 volts When it is 0 volts, and the inverting input signal (INB) is converted from 0 volts to 1.5 volts, as long as the enable signal (EN) is used to control the switch (SW) to briefly close and open, it can be smooth. Ground the voltage of the third node (c) from a first supply voltage (VSS) of 0 volts to a second supply voltage (VSSL) of -5 volts, and let the voltage of the fourth node (d) be -5 volts The second supply voltage (VSSL) changes to a first supply voltage (VSS) of 0 volts. After that, it is maintained in the second stable state.
當轉壓器20處於第二穩定狀態時,致能信號(EN) 為禁能(disable),輸入信號(IN)為0伏特;反相輸入信號(INB)為1.5伏特;輸出信號(OUT)為-5伏特的第二電源電壓(VSSL);反相輸出信號(OUTB)為0伏特的第一電源電壓(VSS)。很明顯地,於第二穩定狀態時,開關(SW)為斷開(open);第一N型電晶體(MN1)不開啟(turn off);第二N型電晶體(MN2)開啟(turn on);第一P型電晶體(MP1)不開啟(turn off);第二P型電晶體(MP2)開啟(turn on);第三N型電晶體(MN3)開啟(turn on);第四N型電晶體(MN4)不開啟(turn off)。 When the converter 20 is in the second stable state, the enable signal (EN) For disable, the input signal (IN) is 0 volts; the inverting input signal (INB) is 1.5 volts; the output signal (OUT) is -5 volts of the second supply voltage (VSSL); the inverted output signal ( OUTB) is the first supply voltage (VSS) of 0 volts. Obviously, in the second steady state, the switch (SW) is open; the first N-type transistor (MN1) is not turned off; the second N-type transistor (MN2) is turned on (turn) On); the first P-type transistor (MP1) is not turned off; the second P-type transistor (MP2) is turned on; the third N-type transistor (MN3) is turned on; The four N-type transistors (MN4) are not turned off.
當輸入信號(IN)由0伏特轉換為1.5伏特,且反相輸 入信號(INB)由1.5伏特轉換為0伏特時,致能信號(EN)為禁能(disable),輸出信號(OUT)維持在-5伏特的第二電源電壓(VSSL),反相輸出信號(OUTB)維持在0伏特的第一電源電壓(VSS)。 When the input signal (IN) is converted from 0 volts to 1.5 volts, and the inverted input When the input signal (INB) is converted from 1.5 volts to 0 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at -5 volts of the second supply voltage (VSSL), and the inverted output signal (OUTB) maintains the first supply voltage (VSS) at 0 volts.
此時,開關(SW)為斷開(open);第一N型電晶體 (MN1)開啟(turn off),而第一P型電晶體(MP1)不開啟(turn off),使得第一節點(a)為0伏特的第一電源電壓(VSS);第二N型電晶體(MN2)與第二P型電晶體(MP2)皆不開啟(turn off),使得第二節點(b)為浮接狀態(floating);第三N型電晶體(MN3)開啟(turn on);第四N型電晶體(MN4)不開啟(turn off)。 At this time, the switch (SW) is open; the first N-type transistor (MN1) turns off, and the first P-type transistor (MP1) does not turn off, so that the first node (a) is a first power supply voltage (VSS) of 0 volts; the second N-type power The crystal (MN2) and the second P-type transistor (MP2) are not turned off, so that the second node (b) is floating; the third N-type transistor (MN3) is turned on (turn on ); the fourth N-type transistor (MN4) does not turn off.
接著,利用致能信號(EN)短暫地致能(enable)開關 (SW)後再次禁能(disable),使得開關(SW)短暫的關閉(close)又斷開(open)。於開關(SW)關閉的短暫時間周期中,由於第三節點(c)與第四節點(d)之間短路,造成電賀分享(charge sharing)使得第三 節點(c)與第四節點(d)的電壓變化至相同的電壓(例如-2.5伏特)。亦即,第三節點(c)的電壓由-5伏特的第二電源電壓(VSSL)上升至-2.5伏特;且第四節點(d)的電壓由0伏特的第一電源電壓(VSS)下降至-2.5伏特。 Next, enable the switch briefly with the enable signal (EN) After (SW), disable again, causing the switch (SW) to briefly close and open. In a short period of time during which the switch (SW) is turned off, due to a short circuit between the third node (c) and the fourth node (d), charging sharing is caused to make the third The voltage at node (c) and fourth node (d) changes to the same voltage (eg, -2.5 volts). That is, the voltage of the third node (c) rises from -5 volts of the second power supply voltage (VSSL) to -2.5 volts; and the voltage of the fourth node (d) drops by the first supply voltage (VSS) of 0 volts. To -2.5 volts.
由於第四節點(d)的電壓下降至-2.5伏特,將使得第一P型電晶體(MP1)開啟(turn on)且第三N型電晶體(MN3)不開啟(turn off),使得第三節點(c)的電壓由-2.5伏特繼續上升至0伏特的第一電源電壓(VSS)。再者,第四N型電晶體(NM4)由於第三節點(c)的電壓升高而開啟(turn on),使得第四節點(d)的電壓由-2.5伏特繼續下降至-5伏特的第二電源電壓(VSSL)。 Since the voltage of the fourth node (d) drops to -2.5 volts, the first P-type transistor (MP1) will be turned on and the third N-type transistor (MN3) will not be turned off, so that The voltage at the three node (c) continues to rise from -2.5 volts to a first supply voltage (VSS) of zero volts. Furthermore, the fourth N-type transistor (NM4) turns on due to the voltage increase of the third node (c), so that the voltage of the fourth node (d) continues to drop from -2.5 volts to -5 volts. Second supply voltage (VSSL).
由以上的說明可知,當輸入信號(IN)由0伏特轉換為1.5伏特,且反相輸入信號(INB)由1.5伏特轉換為0伏特時,只要利用致能信號(EN)控制開關(SW)短暫的關閉(close)又斷開(open),即可順利地讓第三節點(c)的電壓由-5伏特的第二電源電壓(VSSL)變化升至0伏特的第一電源電壓(VSS),並讓第四節點(d)的電壓由0伏特的第一電源電壓(VSS)變化至-5伏特的第二電源電壓(VSSL)。之後,即維持在第一穩定狀態。 As can be seen from the above description, when the input signal (IN) is converted from 0 volts to 1.5 volts, and the inverted input signal (INB) is converted from 1.5 volts to 0 volts, the switch (SW) is controlled by the enable signal (EN). A short close (open) and open (open), you can smoothly increase the voltage of the third node (c) from the second supply voltage (VSSL) of -5 volts to the first supply voltage of 0 volts (VSS) And let the voltage of the fourth node (d) be changed from a first supply voltage (VSS) of 0 volts to a second supply voltage (VSSL) of -5 volts. After that, it is maintained in the first stable state.
而隨著輸入信號(IN)與反相輸入信號(INB)的變化,僅需要利用致能信號(EN)控制開關(SW)短暫的關閉(close)又斷開(open)。即可使得轉壓器20在第一穩定狀態與第二穩定狀態之間變化。 With the change of the input signal (IN) and the inverted input signal (INB), it is only necessary to use the enable signal (EN) to control the switch (SW) to briefly close and open. The converter 20 can be varied between a first steady state and a second steady state.
如第2B圖所示,於時間點t1之前為第一穩定狀態。於時間點t1時,輸入信號(IN)與反相輸入信號(INB)開始轉換準位。由於時間點t1與時間點t2之間,致能信號(EN)短暫致能(enable),使得輸出信號(OUT)與反相輸出信號(OUTB)順利轉換準位。而在時間點t2至時間點t3之間為第二穩定狀態。其中,致能信號(EN)短暫致能(enable)的時間周期約為10ns~40ns。 As shown in FIG. 2B, it is the first stable state before time point t1. At time t1, the input signal (IN) and the inverted input signal (INB) start to shift the level. Since the enable signal (EN) is temporarily enabled between the time point t1 and the time point t2, the output signal (OUT) and the inverted output signal (OUTB) are smoothly switched to the level. And between the time point t2 and the time point t3 is a second stable state. Among them, the enable signal (EN) is briefly enabled for a time period of about 10 ns to 40 ns.
同理,於時間點t3時,輸入信號(IN)與反相輸入信號(INB)開始轉換準位。由於時間點t3與時間點t4之間,致能信 號(EN)短暫致能(enable),使得輸出信號(OUT)與反相輸出信號(OUTB)順利轉換準位。而在時間點t4之後回復為第一穩定狀態。其中,致能信號(EN)短暫致能(enable)的時間周期約為10ns~40ns。 Similarly, at time t3, the input signal (IN) and the inverted input signal (INB) start to shift the level. Since the time point t3 and the time point t4, the enable letter The number (EN) is temporarily enabled (enable), so that the output signal (OUT) and the inverted output signal (OUTB) are smoothly converted to the level. And after the time point t4, it returns to the first stable state. Among them, the enable signal (EN) is briefly enabled for a time period of about 10 ns to 40 ns.
根據本發明的實施例,開關(SW)可以利用電晶體來實現,例如N型電晶體。當致能信號(EN)為0伏特時,使得開關(SW)被致能而關閉(close);當致能信號(EN)為-5伏特時,使得開關(SW)被禁能而斷開(open)。 According to an embodiment of the invention, the switch (SW) can be implemented using a transistor, such as an N-type transistor. When the enable signal (EN) is 0 volts, the switch (SW) is enabled and turned off; when the enable signal (EN) is -5 volts, the switch (SW) is disabled and disconnected (open).
由以上的說明可知,本發明第一實施例包含開關總共僅需要七個電晶體,因此轉壓器20的整體布局面積將可大幅地縮減。再者,本發明的轉壓器20更利用致能信號(EN)來控制開關(SW),來實現轉壓器20轉負壓的目的。 As apparent from the above description, the first embodiment of the present invention includes only a total of seven transistors for the switch, so that the overall layout area of the converter 20 can be greatly reduced. Furthermore, the converter 20 of the present invention further utilizes an enable signal (EN) to control the switch (SW) to achieve the purpose of the negative pressure of the converter 20.
請參照第3圖,其所繪示為本發明的轉壓器的第二實施例。其中,轉壓器30包括:第一開關(SW1)、第二開關(SW2)、第一N型電晶體(MN1)、第二N型電晶體(MN2)、第三N型電晶體(MN3)、第四N型電晶體(MN4)、第一P型電晶體(MP1)、與第二P型電晶體(MP2)。再者,第一電源電壓(VSS)為0伏特,第二電源電壓(VSSL)為-5伏特。 Please refer to FIG. 3, which illustrates a second embodiment of the pressure converter of the present invention. The voltage converter 30 includes: a first switch (SW1), a second switch (SW2), a first N-type transistor (MN1), a second N-type transistor (MN2), and a third N-type transistor (MN3). a fourth N-type transistor (MN4), a first P-type transistor (MP1), and a second P-type transistor (MP2). Furthermore, the first supply voltage (VSS) is 0 volts and the second supply voltage (VSSL) is -5 volts.
第一N型電晶體(MN1)至第四N型電晶體(MN4),第一P型電晶體(MP1)與第二P型電晶體(MP2)的連接關係相同於第一實施例,此處不再贅述。 The first N-type transistor (MN1) to the fourth N-type transistor (MN4), the connection relationship between the first P-type transistor (MP1) and the second P-type transistor (MP2) is the same as that of the first embodiment, I won't go into details here.
與第一實施例的差異在於,利用致能信號(EN)來同時控制第一開關(SW1)與第二開關(SW2)。並且,第一開關(SW1)的第一端連接至該第三節點(c),第二端連接至該第二電源電壓(VSSL);第二開關(SW2)的第二端連接至該第四節點(d),第二端連接至該第二電源電壓(VSSL)。 The difference from the first embodiment is that the first switch (SW1) and the second switch (SW2) are simultaneously controlled by the enable signal (EN). And, the first end of the first switch (SW1) is connected to the third node (c), the second end is connected to the second power voltage (VSSL); the second end of the second switch (SW2) is connected to the first Four nodes (d), the second end is connected to the second supply voltage (VSSL).
運第二實施例轉壓器30的連接關係,當輸入信號(IN)以及反相輸入信號(INB)轉換其準位時,利用致能信號(EN)讓第一開關(SW1)與第二開關(SW2)短暫的關閉(close)又斷開(open),即可讓第三節點(c)與第四節點(d)的電壓變化至相同的電 壓(例如-5伏特)。如此,也可以讓輸出信號(OUT)與反相輸出信號(OUTB)順利轉換準位。 In the second embodiment, the connection relationship of the converter 30 is such that when the input signal (IN) and the inverted input signal (INB) are converted to their levels, the first switch (SW1) and the second switch are made by the enable signal (EN). The switch (SW2) is briefly turned off and then turned on, so that the voltages of the third node (c) and the fourth node (d) are changed to the same power. Pressure (eg -5 volts). In this way, the output signal (OUT) and the inverted output signal (OUTB) can be smoothly converted to the level.
舉例來說,當轉壓器30處於第一穩定狀態(steady state)時,致能信號(EN)為禁能(disable),輸入信號(IN)為1.5伏特;反相輸入信號(INB)為0伏特;輸出信號(OUT)為0伏特的第一電源電壓(VSS);反相輸出信號(OUTB)為-5伏特的第二電源電壓(VSSL)。意即,於第一穩定狀態時,第一開關(SW1)與第二開關(SW2)皆為為斷開(open);第一N型電晶體(MN1)開啟(turn on);第二N型電晶體(MN2)不開啟(turn off);第一P型電晶體(MP1)開啟(turn on);第二P型電晶體(MP2)不開啟(turn off);第三N型電晶體(MN3)不開啟(turn off);第四N型電晶體(MN4)開啟(turn on)。 For example, when the pressure converter 30 is in the first steady state (steady State), the enable signal (EN) is disabled, the input signal (IN) is 1.5 volts; the inverting input signal (INB) is 0 volts; the output signal (OUT) is 0 volts of the first supply voltage (VSS); the inverted output signal (OUTB) is a second supply voltage (VSSL) of -5 volts. That is, in the first stable state, the first switch (SW1) and the second switch (SW2) are both open; the first N-type transistor (MN1) is turned on; the second N The type transistor (MN2) does not turn off; the first P-type transistor (MP1) turns on; the second P-type transistor (MP2) does not turn off; the third N-type transistor (MN3) does not turn off; the fourth N-type transistor (MN4) turns on.
當輸入信號(IN)由1.5伏特轉換為0伏特,且反相輸 入信號(INB)由0伏特轉換為1.5伏特時,致能信號(EN)為禁能(disable),輸出信號(OUT)維持在0伏特的第一電源電壓(VSS),反相輸出信號(OUTB)維持在-5伏特的第二電源電壓(VSSL)。 When the input signal (IN) is converted from 1.5 volts to 0 volts, and the inverting input When the input signal (INB) is converted from 0 volts to 1.5 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at 0 volts of the first supply voltage (VSS), and the inverted output signal ( OUTB) maintains a second supply voltage (VSSL) at -5 volts.
此時,第一開關(SW1)與第二開關(SW2)皆為斷開 (open);第一N型電晶體(MN1)與第一P型電晶體(MP1)皆不開啟(turn off),使得第一節點(a)為浮接狀態(floating);第二N型電晶體(MN2)開啟(turn off)且第二P型電晶體(MP2)不開啟(turn off),使得第二節點(b)為0伏特的第一電源電壓(VSS);第三N型電晶體(MN3)不開啟(turn off);第四N型電晶體(MN4)開啟(turn on)。 At this time, both the first switch (SW1) and the second switch (SW2) are disconnected. (open); neither the first N-type transistor (MN1) nor the first P-type transistor (MP1) is turned off, so that the first node (a) is floating (floating); the second N-type The transistor (MN2) turns off and the second P-type transistor (MP2) does not turn off, such that the second node (b) is a first supply voltage (VSS) of 0 volts; the third N-type The transistor (MN3) is not turned off; the fourth N-type transistor (MN4) is turned on.
接著,利用致能信號(EN)短暫地致能(enable)第一 開關(SW1)與第二開關(SW2)後再次禁能(disable),使得第一開關(SW1)與第二開關(SW2)同時短暫的關閉(close)又斷開(open)。於第一開關(SW1)與第二開關(SW2)關閉的短暫時間周期中,將使得第三節點(c)與第四節點(d)的電壓變化至相同的電壓(例如-5伏特的第二電源電壓(VSSL))。 Then, enable the first enable with the enable signal (EN) The switch (SW1) and the second switch (SW2) are again disabled (disable), so that the first switch (SW1) and the second switch (SW2) are simultaneously closed and opened simultaneously. In a short period of time during which the first switch (SW1) and the second switch (SW2) are turned off, the voltages of the third node (c) and the fourth node (d) will be changed to the same voltage (for example, -5 volts) Two power supply voltage (VSSL)).
由於第三節點(c)的電壓下降至-5伏特,將使得第二 P型電晶體(MP2)開啟(turn on)且第四N型電晶體(MN4)不開啟(turn off),使得第四節點(d)的電壓由-5伏特繼續上升至0伏特的第一電源電壓(VSS)。再者,第三N型電晶體(NM3)由於第四節點(d)的電壓升高而開啟(turn on),使得第三節點(c)的電壓維持在-5伏特的第二電源電壓(VSSL)。之後,即維持在第二穩定狀態。 Since the voltage at the third node (c) drops to -5 volts, it will make the second The P-type transistor (MP2) turns on and the fourth N-type transistor (MN4) does not turn off, so that the voltage of the fourth node (d) continues to rise from -5 volts to the first of 0 volts. Power supply voltage (VSS). Furthermore, the third N-type transistor (NM3) turns on because the voltage of the fourth node (d) rises, so that the voltage of the third node (c) is maintained at the second supply voltage of -5 volts ( VSSL). After that, it is maintained in the second stable state.
而利用相同的方式,可由第二穩定狀態變化至第一 穩定狀態。此處不再贅述。 And in the same way, can change from the second stable state to the first stable state. I will not repeat them here.
當然,第二實施例中,第一開關(SW1)與第二開關 (SW2)的第二端並非限定於連接至第二電源電壓(VSSL)。第一開關(SW1)與第二開關(SW2)的第二端也可以連接至一參考電壓,該參考電壓例如介於-2.5伏特與-5伏特之間,也可以讓轉壓器30正常運作。 Of course, in the second embodiment, the first switch (SW1) and the second switch The second end of (SW2) is not limited to being connected to a second supply voltage (VSSL). The second ends of the first switch (SW1) and the second switch (SW2) may also be connected to a reference voltage, for example between -2.5 volts and -5 volts, which may also allow the converter 30 to operate normally. .
為了防止開關在關閉時造成短路電流而造成過多的 能量耗損。本發明提出轉壓器的第三實施例,用以防止短路電流的產生。 To prevent the switch from causing a short-circuit current when it is turned off, causing excessive Energy consumption. The present invention proposes a third embodiment of a voltage converter for preventing the generation of a short circuit current.
請參照第4圖,其所繪示為本發明轉壓器的第三實 施例。與第二實施例的差異在於,第一P型電晶體(MP1)汲極與第三節點(c)之間連接一第三開關(SW3),第二P型電晶體(MP2)汲極與第四節點(c)之間連接一第四開關(SW4)。再者,第一開關(SW1)與第二開關(SW2)係受控於第一致能信號(EN1);第三開關(SW3)與第四開關(SW4)係受控於第二致能信號(EN2)。其中,第一開關(SW1)與第二開關(SW2)係受控於第一致能信號(EN1),且第一致能信號(EN1)的動作方式相同於第二實施例。其詳細動作原理不再贅述。 Please refer to FIG. 4, which is a third embodiment of the present invention. Example. The difference from the second embodiment is that a third switch (SW3) is connected between the first P-type transistor (MP1) and the third node (c), and the second P-type transistor (MP2) is connected to the drain. A fourth switch (SW4) is connected between the fourth node (c). Furthermore, the first switch (SW1) and the second switch (SW2) are controlled by the first enable signal (EN1); the third switch (SW3) and the fourth switch (SW4) are controlled by the second enablement Signal (EN2). The first switch (SW1) and the second switch (SW2) are controlled by the first enable signal (EN1), and the first enable signal (EN1) operates in the same manner as the second embodiment. The detailed action principle will not be described again.
根據本發明的第三實施例,在第一開關(SW1)與第 二開關(SW2)為關閉(close)的時間周期中,第三開關(SW3)與第四開關(SW4)會斷開(open),而第三開關(SW3)與第四開關(SW4)在其他時間皆會關閉(close)。換句話說,當第一開關(SW1)與第二開關(SW2)關閉,並且使得第三節點(c)與第四節點(d)之短路的時間 周期中,第三開關(SW3)與第四開關(SW4)會斷開(open)。因此,可以防止第一電源電壓(VSSL)與第三節點(c)之間,或者防止第一電源電壓(VSSL)與第四節點(d)之間產生短路電流。 According to a third embodiment of the present invention, at the first switch (SW1) and During the time period in which the second switch (SW2) is closed, the third switch (SW3) and the fourth switch (SW4) are opened (open), and the third switch (SW3) and the fourth switch (SW4) are in the It will be closed at other times. In other words, when the first switch (SW1) and the second switch (SW2) are turned off, and the third node (c) is short-circuited with the fourth node (d) During the cycle, the third switch (SW3) and the fourth switch (SW4) are opened. Therefore, it is possible to prevent a short-circuit current from being generated between the first power supply voltage (VSSL) and the third node (c) or between the first power supply voltage (VSSL) and the fourth node (d).
再者,利用相同的動作方式,第三開關(SW3)與第 四開關(SW4)運用於第一實施例,一樣也可以防止短路電流的發生。亦即,於第一實施例的轉壓器中,第一P型電晶體(MP1)汲極與第三節點(c)之間新增一第三開關(SW3),第二P型電晶體(MP2)汲極與第四節點(c)之間新增一第四開關(SW4)。其詳細動作原理不再贅述。 Furthermore, using the same action mode, the third switch (SW3) and the third The four switches (SW4) are applied to the first embodiment, as well as preventing the occurrence of short-circuit current. That is, in the converter of the first embodiment, a third switch (SW3) is added between the first P-type transistor (MP1) and the third node (c), and the second P-type transistor is added. A fourth switch (SW4) is added between the (MP2) drain and the fourth node (c). The detailed action principle will not be described again.
由上述的說明可知,本發明的轉壓器僅由少數的電晶體所組成,因此轉壓器的整體布局面積將可大幅地縮減,並且實現轉壓器轉負壓的目的。 It can be seen from the above description that the pressure converter of the present invention is composed only of a small number of transistors, so that the overall layout area of the pressure converter can be greatly reduced, and the purpose of turning the negative pressure of the pressure converter is achieved.
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
20‧‧‧轉壓器 20‧‧‧Transducer
MN1、MN2、MN3、MN4‧‧‧N型電晶體 MN1, MN2, MN3, MN4‧‧‧N type transistor
MP1、MP2‧‧‧P型電晶體 MP1, MP2‧‧‧P type transistor
SW‧‧‧開關 SW‧‧ switch
VSS‧‧‧第一電源電壓 VSS‧‧‧First supply voltage
IN‧‧‧輸入信號 IN‧‧‧ input signal
INB‧‧‧反相輸入信號 INB‧‧‧Inverting input signal
a、b、c、d‧‧‧第一至第四節點 a, b, c, d‧‧‧ first to fourth nodes
EN‧‧‧致能信號 EN‧‧‧Enable signal
OUT‧‧‧輸出信號 OUT‧‧‧ output signal
OUTB‧‧‧反相輸出信號 OUTB‧‧‧Inverted output signal
VSSL‧‧‧第二電源電壓 VSSL‧‧‧second supply voltage
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103122517A TWI520492B (en) | 2014-06-30 | 2014-06-30 | Level shifter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103122517A TWI520492B (en) | 2014-06-30 | 2014-06-30 | Level shifter |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201601461A TW201601461A (en) | 2016-01-01 |
TWI520492B true TWI520492B (en) | 2016-02-01 |
Family
ID=55641353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103122517A TWI520492B (en) | 2014-06-30 | 2014-06-30 | Level shifter |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI520492B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112073048B (en) * | 2020-09-02 | 2022-11-04 | 敦泰电子(深圳)有限公司 | Level shift circuit |
-
2014
- 2014-06-30 TW TW103122517A patent/TWI520492B/en active
Also Published As
Publication number | Publication date |
---|---|
TW201601461A (en) | 2016-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI538404B (en) | Level shifter | |
US10811085B2 (en) | Dual rail device with power detector | |
JPH08298445A (en) | Differential amplifier device | |
CN106899288B (en) | Level conversion circuit | |
TW202025594A (en) | Power switch circuit | |
US20190286178A1 (en) | Wide common mode high resolution comparator | |
JP5527044B2 (en) | Mode control circuit | |
TW201105037A (en) | Level shifting circuit | |
JPWO2018055666A1 (en) | Interface circuit | |
TWI422154B (en) | Level shifter and related apparatus | |
US9787310B2 (en) | Level-shifter circuit for low-input voltages | |
TWI520492B (en) | Level shifter | |
JP2012023533A5 (en) | ||
JP4774287B2 (en) | Output circuit | |
JP4724575B2 (en) | Level conversion circuit | |
JP5727220B2 (en) | Charge pump circuit and driver and display device including the same | |
JP2012080380A (en) | Semiconductor integrated circuit | |
TWI584596B (en) | Level shifter | |
JPH11308092A (en) | Level shift circuit and nonvolatile memory provided with the same | |
TWI539751B (en) | Level shifter | |
JP2012114504A (en) | Power switch circuit | |
JP2012114610A (en) | Electronic circuit | |
CN105281746B (en) | A kind of transformer | |
JP4588436B2 (en) | Level shifter circuit | |
TW201524125A (en) | Level shifter |