TWI520230B - 影像感測裝置及其製造方法 - Google Patents

影像感測裝置及其製造方法 Download PDF

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TWI520230B
TWI520230B TW102116333A TW102116333A TWI520230B TW I520230 B TWI520230 B TW I520230B TW 102116333 A TW102116333 A TW 102116333A TW 102116333 A TW102116333 A TW 102116333A TW I520230 B TWI520230 B TW I520230B
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epitaxial layer
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semiconductor
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TW201351512A (zh
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張簡旭珂
洪敏皓
陳科維
鄭志成
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台灣積體電路製造股份有限公司
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Description

影像感測裝置及其製造方法
本發明係關於半導體製作，且特別是關於一種影像感測裝置及其製造方法。
包括前側照光影像感測晶片(front side illumination image sensor chips)與後側照光影像感測晶片(backside illumination image sensor chips)等之影像感測晶片已廣泛地應用於如相機之各種應用之中。於影像感測晶片的製作中，係於一晶圓之一矽基板上形成影像感測器(image sensors，例如為感光二極體)與邏輯電路(logic circuits)，以及接著形成內連結構(interconnect structure)於此晶圓的一前側表面之上。於前側型影像感測晶片的製作中，於形成內連結構之後接著形成彩色濾光物與微透鏡。而於後側照光影像感測晶片的製作中，於形成內連結構之後則薄化此晶圓，並形成如彩色濾光物與微透鏡之後側結構(backside structure)於矽基板的後側(backside)之上。當使用影像感測晶片時，光線(light)可投射至影像感測器處，並由影像感測器將光線轉換成為電子訊號(electrical signals)。
於影像感測晶片內之影像感測器可對應於光子刺激(stimulation of photons)而產生了電子訊號。影像感測器之全 井容量(full well capacity)與信噪比(signal-to-noise ratio)越高越好。為了增加如感光二極體之影像感測器的全井容量與信噪比，可增加感光二極體之P型區及/或N型區的摻質濃度(impurity concentration)。然而，如此之增加情形則導致了更高佈值能量與更高劑量的需求。由於佈值之摻質對於半導體基板的轟炸情形，增加了感光二極體的漏電流(leak currents)，因而劣化了影像感測器之暗電流(dark currents)與白像素(white pixel)等表現。
依據一實施例，本發明提供了一種影像感測裝置之製造方法，包括：施行一第一磊晶製程，成長具有一第一導電類型之一第一磊晶層；施行一第二磊晶製程，成長一第二磊晶層於該第一磊晶層上，其中該第二磊晶層具有相反於該第一導電特性之一第二導電類型，且其中該第一磊晶層與該第二磊晶層形成了一二極體；形成一閘介電物於該第一磊晶層上；形成一閘電極於該閘介電物上；以及佈植該第一磊晶層與該第二磊晶層之一頂部，形成鄰近該閘介電物之一源極/汲極區。
依據另一實施例，本發明提供了一種影像感測裝置之製造方法，包括：磊晶成長一第一磊晶層於一半導體基板上；磊晶成長一第二磊晶層於該第一磊晶層上；磊晶成長一第三磊晶層於該第二磊晶層上；磊晶成長一第四磊晶層於該第三磊晶層上，其中該第二磊晶層與該第三磊晶層臨場地摻雜有具有第一導電類型之摻質，而該第一磊晶層與該第四磊晶層臨場地摻雜有具有相反於該第一導電類型之一第二導電類型之摻 質；佈植該第三磊晶層與該第四磊晶層，形成具有該第二導電類型之一半導體隔離區，其中該第三磊晶層之一部與該第四磊晶層之一部係為該半導體隔離區所環繞以形成一感光二極體；形成一閘介電物於該第四磊晶層上；形成一閘電極於該閘介電物上；以及佈植該第四磊晶層，形成鄰近該閘介電物之具有該第一導電類型之一源極/汲極區，其中該源極/汲極區、該閘介電物與該閘電極形成了一電晶體之數個部分。
依據又一實施例，本發明提供了一種一種影像感測裝置，包括：一感光二極體，包括：具有一第一導電類型之一第一半導體層；以及具有相反於該第一導電類型之一第二導電類型之一第二半導體層，其中至少該第一半導體層與該第二半導體層之一具有大體均勻之摻質分佈；一閘介電物，位於該第二半導體層上；一閘電極，位於該閘介電物上；以及一源極/汲極區，具有該第一導電類型，其中該源極/汲極區、該閘介電物與該閘電極形成了一電晶體之數個部分，而其中該電晶體係作為開啟與關閉介於該感光二極體與該電晶體間之一電性連結之用。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
20‧‧‧影像感測晶圓
22‧‧‧半導體基板
24‧‧‧P型層
26‧‧‧N型層
28‧‧‧N型層
30‧‧‧P型層
32‧‧‧厚度
34‧‧‧光阻
35‧‧‧佈植
36‧‧‧隔離區/淺溝槽隔離區
37‧‧‧P型層
37A‧‧‧通道區
38‧‧‧P型區
39‧‧‧佈植
40‧‧‧深井區
41‧‧‧光阻
48‧‧‧閘介電物
50‧‧‧閘電極
52‧‧‧輕度摻雜汲極/源極
58‧‧‧感光二極體
60‧‧‧電晶體
62‧‧‧重度摻雜N型區
64‧‧‧金屬矽化物區
66‧‧‧接觸插栓
68‧‧‧層間介電層
70‧‧‧閘間隔物
72‧‧‧接觸蝕刻停止層
76‧‧‧後側照光膜層堆疊物
78‧‧‧彩色濾光物
80‧‧‧微透鏡
T1、T2、T3、T4‧‧‧厚度
第1-8圖為一系列示意圖，顯示了依據本發明之多個實施例之一種影像感測晶圓於其製作中之多個階段的剖面情形。
本發明提供了依據多個實施例之影像感測晶圓/晶片之形成方法，並繪示了影像感測晶圓/晶片之形成方法於製作過程中之中間階段，以及討論了此些實施例間的差異。於以下的多個圖式與多個實施例之中，相同標號係代表了相同構件。
第1圖繪示了一影像感測晶圓20，其包括了一半導體基板22。於部分實施例中，半導體基板22為結晶矽基板(crystalline silicon substrate)。或者，半導體基板22係由其他之半導體材料所形成，例如為矽鍺、碳化矽、III-V族化合物半導體材料及相似物。
請參照第2圖，施行數個磊晶步驟，以形成數個磊晶層。於部分實施例中，此些磊晶層包括了一P型層24、位於P型層上之一N型層26、位於N型層26上之一N型層28、以及位於N型層28上之一P型層30。於其他實施例中，可形成更多的磊晶層。舉例來說，可於N型層24與26之上堆疊更多之N型層。或於其他實施例中，可省略P型層24，而於半導體基板22之上可形成接觸半導體基板22一N型層(例如N型層26)。
於部分實施例中，P型層24為一矽層。於其他實施例中，P型層24為一矽鍺層。於P型層24內之鍺的原子百分比可介於如20%-40%。隨著P型層24磊晶的進行，可臨場地摻雜如硼、銦或其組合之P型摻質。所摻雜的摻質濃度可介於如1*1016/立方公分至1*1019/立方公分。然而，值得注意的是，於本文中之此些數值僅作為範例之用，並可為其他數值。於部分實施例 中，P型層24具有由上至下大體均勻之摻雜濃度。P型層24之厚度T1可介於如約10奈米至2微米。
N型層26可為一矽層，其可大體不包含有鍺，雖然亦可能包含鍺。N型層26摻雜有如磷、砷、銻或其組合之N型摻質。此些N型摻質係於各別之磊晶步驟中臨場地摻雜。N型層26之N型摻質濃度可介於如約1*1014/立方公分至約1*1016/立方公分。於部分實施例中，N型層26具有從上至下大體均勻之摻雜濃度。於其他實施例中，摻雜濃度可從下至上逐漸地增加。N型層26之厚度T2可介於如約1微米至2微米，雖然其亦可具有較大或較小之厚度。
N型層28可為摻雜有N型摻質之一矽層，其中N型摻質係於各別之磊晶步驟中臨場地摻雜。N型層28內之N型摻質濃度可高於N型層26內之摻質濃度。於部分實施例中，N型層28之N型摻質濃度可介於約1*1013/立方公分至1*1017/立方公分。於部分實施例中，N型層28具有從下至上為大體均勻之摻雜濃度。於其他實施例中，N型摻雜濃度可從下至上逐漸增加。N型層28之厚度T3可介於如1.5微米至2.5微米，雖然其亦可具有較大或較小的厚度。
雖然在此已繪示了兩個N型層26與28，然而於N型層24之下、介於N型層24與26之間、及/或於N型層28之上可更堆疊有更多的N型層。再者，對於此些堆疊之N型層(如膜層24與26或更多的膜層)而言，其內摻質濃度可逐漸地自此些N型層之較下方膜層朝向較上方膜層而增加。
於部分實施例中，P型層30為一矽層。於其他實施 例中，P型層30為一矽鍺層。於P型層30內之鍺的原子百分比可介於如20%-40%。隨著P型層30的磊晶進行，可臨場地摻雜P型摻質至如1*1018/立方公分至1*1020/立方公分之一程度。於部分實施例中，P型層30具有從上至下大體均勻的摻雜濃度。P型層30之厚度T4可介於如約0.1微米至0.5微米。
請參照第3圖，藉由蝕刻以形成數個溝槽32，此些溝槽32其自P型層30的頂面延伸進入P型層30之內。此些溝槽32延伸進入N型層28之內，且於部分實施例中亦可能向下延伸進入N型層26或P型層24之內。
接著，請參照第4圖，形成一光阻34並圖案化之，而此些溝槽32可為形成於光阻34內之數個開口所露出。接著採用光阻34作為佈植罩幕而施行一或數個佈植35。於此佈植之中，可佈植P型摻質(p-type impurity)於P型層30與N型層28與26之內，進而形成數個P型區38。雖然此些P型區38為如第4圖所示之數個分隔區域，然而此些分隔之P型區38如第4圖之結構之上視情形中可為一整合區的數個部分。此些P型區38亦可稱為一場輕度摻雜區(field light doping region，FLD region)。此些P型區38可具有介於約1014/立方公分至1018/立方公分之一P型摻質濃度。於形成此些P型區38之後，移除光阻34。
第4圖亦繪示了P型層37的形成，其亦可採用一佈植所形成。其所使用之光阻在此則並未顯示。於此區域內之P型層37係為由P型層38所形成之環狀物所環繞。P型層37之P型摻質濃度可介於約1014/立方公分至1018/立方公分。
第5圖繪示了數個隔離區(isolation regions)36與深 井區(deep well regions)40的形成。於下文中此些隔離區36亦稱為淺溝槽隔離區36。此些淺溝槽隔離區36的形成可包括填入一介電材料於此些溝槽32(第4圖)之內，並接著施行一化學機械研磨(CMP)以移除過量之介電材料，此些過量之介電材料部分係高於P型層30。介電材料的剩餘部分形成了此些淺溝槽隔離區36。
接著，形成光阻41並圖案化之。此些淺溝槽隔離區36可為光阻41內之數個開口所露出。接著施行一或多個佈植39以佈植P型摻質至N型層26與N型層24之內，進而形成數個深井區40。此些深井區40可具有介於如約1014/立方公分-1018/立方公分之一P型摻質濃度。深井區40係位於P型區38之下方且為P型區所重疊。於下文中，P型區38與深井區40亦可稱為數個半導體隔離區(semiconductor isolation region)。於形成深井區40之後，接著移除光阻41。
請參照第6圖，形成一閘介電物(gate dielectric)48與一閘電極(gate electrode)50。閘介電物48可包括氧化物、氮化物、氮氧化物、碳化物、其組合及或其之多重膜層。閘電極50係為導電或半導電的。於部分實施例中，閘電極層為多晶矽所形成。於其他實施例中，閘電極50係由如金屬、金屬矽化物、金屬氮化物或其組合之其他導電材料所形成。閘介電物48與閘電極50的形成包括了形成了坦覆之一閘介電層與坦覆之一閘電極層，並接著圖案化此閘介電層與此閘電極層。閘電極50覆蓋了P型區37之一部。
於形成閘介電物48與閘電極50之後，可透過一佈 植步驟而形成一輕度摻雜汲極/源極區(lightly doped drain/source region)52。閘電極50可做為一佈植罩幕，進而使得輕度摻雜汲極/源極區52的左側邊緣大體對準於閘電極50之右側邊緣。
第7圖繪示了具有作為閘堆疊物之閘介電物48與閘電極50之電晶體60之其他部分的形成。電晶體60之其他部分可更包括重度摻雜N型區62、金屬矽化物區64以及閘間隔物70。重度摻雜N型區62係為電晶體60之一源極區或一汲極區(於下文中通稱為源極/汲極區)。此外，亦可形成接觸插栓66、層間介電層68、阻劑保護氧化物(resist protective oxide，RPO)、與接觸蝕刻停止層(contact etch stop layer，CESL)72等構件。
於第7圖所示之結構中，形成了一感光二極體58。此感光二極體58包括了作為感光二極體58的P型側之P型層30，以及作為感光二極體58的N型側之N型層26與28。感光二極體58的N型側與P型側形成了一P-N接面。於本文中，為半導體隔離區38與40所環繞之P型層30與N型層26與28之部分亦可稱為一P型區30、一N型區26與一N型區28。
於如第7圖所示之結構中，P型區37之一部37A形成了電晶體60之通道區。感光二極體58與電晶體60係作為同一影像感測單元內之一感光二極體(photo diode)與一轉移閘電晶體(transfer gate transistor)。當開啟電晶體60時，通道37A可作為感光二極體58與源極/汲極區62間之電性連結。由發光二極體58所產生的電荷可因此流經通道37A而至源極/汲極區62，電荷從而可經過收集且處理而成為各影像感測單元之電子訊號。當 關閉電晶體60後，便中斷了介於感光二極體58與源極/汲極區62的電性連結情形。
如第8圖所示，於部分實施例中可施行部分之後側製程，以將晶圓20形成為一後側照光影像感測晶圓(back side illumination image sensor wafer)，其包括位於其內之數個影像感測晶片。於此後側製程中，可首先施行一薄化製程(例如一研磨製程)以移除半導體基板22，如第8圖所示。於此實施例中，其中P型層24形成並具有大於期望厚度之一厚度時，P型層24可經過薄化至如少於0.1微米之一厚度。而於當P型層24足夠薄之一實施例中，則可省略上述針對P型層24的薄化情形。然而，當此些磊晶層(參見第1圖)並未包括有P型層24時，則可於N型層26之後側施行一佈植或一磊晶步驟，進而形成等同於P型層24之一P型層。
於後續製程步驟中，形成後側照光膜層堆疊物76，其可包括氧化物層、高介電常數介電層(例如氧化鉿、氧化鋯或相似物)、抗反射層、金屬格柵(metal grids)或相似物。接著可形成如彩色濾光物78與微透鏡80之其他構件。於其他實施例中(未顯示)，則繼續製程步驟(自第7圖所示結構開始)，以將晶圓20形成為一前側照光影像感測晶圓(front side illumination image sensor wafer)，其中金屬層(未顯示)、彩色濾光物78、與微透鏡80係形成於第7圖所示結構之上。
雖然經摻雜之半導體區(例如區域24、26、28、30、38、40、52與62等)的摻雜類型於圖示之實施例中具有特定的實施情形，然而本發明之實施例的教示情形亦適用於形成其內 之摻雜半導體區具有相反的導電特性之一裝置。
於上述之多個實施例中，感光二極體58的P型區與N型區係由磊晶而非佈植所形成。如此，各膜層24、26、28與30內之摻質濃度可大體為均勻的，由於此些磊晶層內之摻質具有相同擴散距離，其摻質濃度甚至於後續熱製程步驟施行之後亦為均勻的。
由於採用磊晶方式形成感光二極體58，因而可增加P型區30與N型區26與28的厚度至一期望厚度，且亦可增加摻質濃度至一期望數值，且不會造成起因於佈植的毀損情形。因此最終得到的二極體中的漏電流極少。進而改善了暗電流(dark current)與白像素表現(white pixel performance)等表現。再者，磊晶操作亦使得矽鍺材質之P型層24的形成成為可能。由於N型層26可為大體不具有鍺的一矽層。因而於含矽鍺之P型層24內便可產生一應力，其導致了感光二極體58內之漏電流的降低。如此亦導致了改善了暗電流(dark current)與白像素表現(white pixel performance)等表現。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧影像感測晶圓
22‧‧‧半導體基板
24‧‧‧P型層
26‧‧‧N型層
28‧‧‧N型層
30‧‧‧P型層
36‧‧‧隔離區
37‧‧‧P型層
37A‧‧‧通道區
38‧‧‧P型區
40‧‧‧深井區
48‧‧‧閘介電物
50‧‧‧閘電極
52‧‧‧輕度摻雜汲極/源極
58‧‧‧感光二極體
60‧‧‧電晶體
62‧‧‧重度摻雜N型區
64‧‧‧金屬矽化物區
66‧‧‧接觸插栓
68‧‧‧層間介電層
70‧‧‧閘間隔物
72‧‧‧接觸蝕刻停止層

Claims (10)

  1. 一種影像感測裝置之製造方法，包括：施行一第一磊晶製程，成長具有一第一導電類型之一第一磊晶層；施行一第二磊晶製程，成長一第二磊晶層於該第一磊晶層上，其中該第二磊晶層具有相反於該第一導電特性之一第二導電類型，且其中該第一磊晶層與該第二磊晶層形成了一二極體；佈植該第二磊晶層與該第一磊晶層，以形成沿伸進入該第二磊晶層與該第一磊晶層內之一半導體隔離區，其中該半導體隔離區具有該第二導電類型；形成一閘介電物於該第一磊晶層上；形成一閘電極於該閘介電物上；以及佈植該第一磊晶層與該第二磊晶層之一頂部，形成鄰近該閘介電物之一源極/汲極區，其中該源極/汲極區位於該半導體隔離區內。
  2. 如申請專利範圍第1項所述之影像感測裝置之製造方法，其中該第一磊晶層與該第二磊晶層係成長於一半導體基板上，且該製造方法更包括：施行一薄化步驟，以移除該半導體基板；以及形成對準於該二極體之一彩色濾光物與一微透鏡，其中該彩色濾光物與該微透鏡係位於相對於該閘電極之該第一磊晶層與該第二磊晶層之一側上。
  3. 如申請專利範圍第1項所述之影像感測裝置之製造方法，其 中該半導體隔離區環繞該二極體。
  4. 如申請專利範圍第1項所述之影像感測裝置之製造方法，於成長該第一磊晶層與該第二磊晶層之前，更包括：施行一第三磊晶步驟，成長具有該第二導電類型之一第三磊晶層，其中該第一磊晶層係成長於該第三磊晶層上。
  5. 一種影像感測裝置之製造方法，包括：磊晶成長一第一磊晶層於一半導體基板上；磊晶成長一第二磊晶層於該第一磊晶層上；磊晶成長一第三磊晶層於該第二磊晶層上；磊晶成長一第四磊晶層於該第三磊晶層上，其中該第二磊晶層與該第三磊晶層臨場地摻雜有具有第一導電類型之摻質，而該第一磊晶層與該第四磊晶層臨場地摻雜有具有相反於該第一導電類型之一第二導電類型之摻質；佈植該第三磊晶層與該第四磊晶層，形成具有該第二導電類型之一半導體隔離區，其中該第三磊晶層之一部與該第四磊晶層之一部係為該半導體隔離區所環繞以形成一感光二極體；形成一閘介電物於該第四磊晶層上；形成一閘電極於該閘介電物上；以及佈植該第四磊晶層，形成鄰近該閘介電物之具有該第一導電類型之一源極/汲極區，其中該源極/汲極區、該閘介電物與該閘電極形成了一電晶體之數個部分。
  6. 如申請專利範圍第5項所述之影像感測裝置之製造方法，更包括施行一薄化步驟，以移除該半導體基板直到露出該第 一磊晶層，而該製造方法更包括形成對準於該二極體之一彩色濾光物與一微透鏡，其中該彩色濾光物與該微透鏡係位於該第一磊晶層之相對於該閘電極之一側上。
  7. 如申請專利範圍第5項所述之影像感測裝置之製造方法，於成長該第一磊晶層與該第二磊晶層之後，更包括：施行一佈植，形成具有該第二導電類型之一半導體隔離區，其中該半導體隔離區環繞該二極體。
  8. 一種影像感測裝置，包括：一感光二極體，包括：具有一第一導電類型之一第一半導體層；具有相反於該第一導電類型之一第二導電類型之一第二半導體層，其中至少該第一半導體層與該第二半導體層之一具有大體均勻之摻質分佈；一半導體隔離區，位於該第二半導體層與該第一半導體層之內，其中該半導體隔離區具有該第二導電類型；一閘介電物，位於該第二半導體層上；一閘電極，位於該閘介電物上；以及一源極/汲極區，具有該第一導電類型，其中該源極/汲極區、該閘介電物與該閘電極形成了一電晶體之數個部分，其中該源極/汲極區係位於該半導體隔離區內，而其中該電晶體係作為開啟與關閉介於該感光二極體與該電晶體間之一電性連結之用。
  9. 如申請專利範圍第8項所述之影像感測裝置，其中，更包括：具有該第二導電類型之一矽鍺層，位於該第一半導體層下。
  10. 如申請專利範圍第8項所述之影像感測裝置，更包括：一彩色濾光物，與該感光二極體相重疊；以及一微透鏡，與該彩色濾光物相重疊。
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