TWI518874B - Semiconductor package, semiconductor package unit and method of manufacturing semiconductor package - Google Patents

Semiconductor package, semiconductor package unit and method of manufacturing semiconductor package Download PDF

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TWI518874B
TWI518874B TW103103431A TW103103431A TWI518874B TW I518874 B TWI518874 B TW I518874B TW 103103431 A TW103103431 A TW 103103431A TW 103103431 A TW103103431 A TW 103103431A TW I518874 B TWI518874 B TW I518874B
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semiconductor
semiconductor wafer
layer
semiconductor package
wiring layer
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TW103103431A
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Chinese (zh)
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TW201445698A (en
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權容台
李俊奎
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Ｎｅｐｅｓ股份有限公司
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

半導體封裝、半導體封裝單元以及半導體封裝製造方法 Semiconductor package, semiconductor package unit, and semiconductor package manufacturing method

本發明係有關於半導體封裝、半導體封裝單元以及半導體封裝製造方法。 The present invention relates to semiconductor packages, semiconductor package units, and semiconductor package fabrication methods.

這些年來，因為半導體製程技術的微縮以及功能性的多樣化，半導體元件之晶片大小漸漸減小並且電極接合墊間距(electrode pad pitches)也漸漸的越來越好。此外，隨著各種功能整合的加速，多種元件整合於其中之系統層次的封裝技術已經出現。系統層次的封裝技術轉換至三維堆疊技術以維持較短的信號傳輸距離，以便降低操作間的雜訊以及增進信號速度。 Over the years, due to the miniaturization and functional diversification of semiconductor process technology, the wafer size of semiconductor devices has gradually decreased and the electrode pad pitches have gradually become better and better. In addition, with the acceleration of various functional integrations, system-level packaging technologies in which various components are integrated have emerged. System-level packaging technology is converted to 3D stacking technology to maintain short signal transmission distances to reduce noise between operations and increase signal speed.

同時，能夠增進製造效率並且藉由堆疊許多半導體晶片的方式降低製造成本之堆疊型式的半導體封裝(如package on package,PoP)目前正在研究與發展。然而，一般堆疊型式的半導體封裝技術具有降低半導體封裝之總厚度的限制，例如，可能需要根據行動式產品之應用的模組以及規格而縮小半導體封裝之厚度。在常見的堆疊式封裝方法中，半導 體晶片使用密封膠分別黏於分離的封裝中且安置於基體上。因此，半導體封裝之總厚度根據半導體晶片模子的厚度而增加。 At the same time, stacked-type semiconductor packages (such as package on package, PoP) capable of improving manufacturing efficiency and reducing manufacturing costs by stacking a plurality of semiconductor wafers are currently under research and development. However, generally stacked types of semiconductor packaging techniques have limitations that reduce the overall thickness of the semiconductor package. For example, it may be desirable to reduce the thickness of the semiconductor package in accordance with the modules and specifications of the application of the mobile product. In common stacked packaging methods, semi-conducting The body wafers are respectively adhered to the separate packages using a sealant and placed on the substrate. Therefore, the total thickness of the semiconductor package increases in accordance with the thickness of the semiconductor wafer mold.

有鑑於此，韓國專利公開號2008-0022452(公佈於2008年3月11日)揭露了關於避免短路之堆疊式封裝方法，即使放置於下半部的半導體晶片封裝之厚度較厚。然而，此方法也不適用於降低半導體封裝之厚度。 In view of this, Korean Patent Publication No. 2008-0022452 (published on March 11, 2008) discloses a stacked package method for avoiding short circuits even if the thickness of the semiconductor chip package placed in the lower half is thick. However, this method is also not suitable for reducing the thickness of a semiconductor package.

所以，本發明係提供一半導體封裝、一半導體封裝單元以及半導體封裝製造方法。複數第一半導體晶片以一既定距離相間隔而黏於一平板，複數第二半導體晶片分別堆疊於上述第一半導體晶片上，使得上述第二半導體晶片電性連接至上述第一半導體晶片而結構因此緊密結合，以降低上述半導體封裝之總厚度。 Therefore, the present invention provides a semiconductor package, a semiconductor package unit, and a semiconductor package manufacturing method. The plurality of first semiconductor wafers are adhered to a flat plate at a predetermined distance, and the plurality of second semiconductor wafers are respectively stacked on the first semiconductor wafer, so that the second semiconductor wafer is electrically connected to the first semiconductor wafer, thereby Tightly bonded to reduce the total thickness of the above semiconductor package.

本發明之其他方面將於以下說明中做部分闡述，且某部分係可由以下說明中清楚可得，或可由實做本發明而得。 Other aspects of the invention will be set forth in part in the description which follows.

根據本發明之一實施例，一種半導體封裝，包括：一第一半導體晶片封裝，包括一第一半導體晶片、用以固定上述第一半導體晶片之一第一鑄模層以及電性連接至上述第一半導體晶片之外部的一外部區域；以及一第二半導體晶片包括電性連接至上述第一半導體晶片之一第二半導體晶片以及用以固定上述第二半導體晶片與一外部端子而使得上述外部端子之一部分裸露之一第二鑄模層。 According to an embodiment of the present invention, a semiconductor package includes: a first semiconductor chip package including a first semiconductor wafer, a first mold layer for fixing the first semiconductor wafer, and an electrical connection to the first An outer region of the outer portion of the semiconductor wafer; and a second semiconductor wafer including a second semiconductor wafer electrically connected to one of the first semiconductor wafers and a second semiconductor wafer and an external terminal for fixing the external terminal One part is exposed to one of the second mold layers.

上述外部端子包括一銲錫球。 The external terminal includes a solder ball.

上述外部端子之高度係高於上述第二半導體晶片之高度。 The height of the external terminal is higher than the height of the second semiconductor wafer.

上述第一鑄模層固定上述第一半導體晶片，使得上述第一半導體晶片之一表面係為裸露，其中上述第一半導體晶片封裝更包括一佈線層，上述佈線層連接至上述第一半導體晶片之裸露的上述表面之一第一信號接合墊，以及其中上述外部端子突起而使得上述外部端子係電性連接至上述佈線層之一邊之一裸露部分，上述佈線層係延伸至上述第一半導體晶片之一外部區域。 The first mold layer fixes the first semiconductor wafer such that one surface of the first semiconductor wafer is exposed, wherein the first semiconductor chip package further comprises a wiring layer, and the wiring layer is connected to the bare of the first semiconductor wafer a first signal bonding pad of the surface, wherein the external terminal is protruded such that the external terminal is electrically connected to one of the exposed portions of the wiring layer, and the wiring layer extends to one of the first semiconductor wafers External area.

上述第二半導體晶片封裝更包括突起的一連接端子，使得上述連接端子電性連接至位於上述第二半導體晶片之一表面之一第二信號接合墊、上述連接端子連接到連接至上述第一信號接合墊之上述佈線層之另一邊以及上述第二鑄模層固定上述第二半導體晶片以及上述外部端子而使得上述外部端子之一部分裸露。 The second semiconductor chip package further includes a connection terminal of the protrusion, wherein the connection terminal is electrically connected to a second signal bonding pad located on one surface of the second semiconductor wafer, and the connection terminal is connected to the first signal The other side of the wiring layer of the bonding pad and the second mold layer fix the second semiconductor wafer and the external terminal to expose one of the external terminals.

上述佈線層包括：一第一絕緣層，形成於上述第一半導體晶片，使得上述第一信號接合墊裸露；一佈線圖層，用以將上述佈線圖層之一邊電性連接至裸露之上述第一信號接合墊，而上述佈線圖層之另一邊堆疊於上述第一半導體晶片之上述外部區域之上述第一絕緣層上；以及一第二絕緣層，堆疊於上述第一絕緣層以及上述佈線圖層之上，使得上述佈線圖層之一邊以及另一邊的一部份裸露。 The wiring layer includes: a first insulating layer formed on the first semiconductor wafer such that the first signal bonding pad is exposed; and a wiring layer configured to electrically connect one side of the wiring layer to the bare first signal a bonding pad, wherein the other side of the wiring layer is stacked on the first insulating layer of the outer region of the first semiconductor wafer; and a second insulating layer is stacked on the first insulating layer and the wiring layer, One side of the above wiring layer and a part of the other side are exposed.

上述外部端子係連接至上述佈線圖層之裸露的另一邊，且上述連接端子係連接至上述佈線圖層之裸露的另一 邊。 The external terminal is connected to the exposed other side of the wiring layer, and the connection terminal is connected to the exposed another of the wiring layer side.

上述第一半導體晶片封裝更包括一支撐架，上述支撐架具有一孔洞，其中上述第一半導體晶片安置於上述孔洞中。 The first semiconductor chip package further includes a support frame, the support frame having a hole, wherein the first semiconductor wafer is disposed in the hole.

上述支撐架包括一電路，上述電路形成於上述支撐架之單或雙面。 The support frame includes a circuit, and the circuit is formed on one or both sides of the support frame.

上述第一鑄模層以及上述第二鑄模層係為相同材料，上述第一半導體晶片係經由上述第一鑄模層與上述支撐架結合在一起，上述第二半導體晶片係經由上述第二鑄模層與上述外部端子結合在一起。 The first mold layer and the second mold layer are made of the same material, the first semiconductor wafer is bonded to the support frame via the first mold layer, and the second semiconductor wafer is connected to the second mold layer via the second mold layer The external terminals are combined.

上述第一半導體晶片之主動表面係面對上述第二半導體晶片之主動表面。 The active surface of the first semiconductor wafer faces the active surface of the second semiconductor wafer.

上述第一鑄模層以及上述第二鑄模層之一或多者係為平坦化，使得上述第一半導體晶片以及上述第二半導體晶片之一或多非主動表面係為裸露。 One or more of the first mold layer and the second mold layer are planarized such that one or more of the first semiconductor wafer and the second semiconductor wafer are bare.

根據本發明之另一實施例，一半導體封裝單元包括包括二或多半導體封裝之一堆疊，上述半導體封裝包括上述半導體封裝。 In accordance with another embodiment of the present invention, a semiconductor package unit includes a stack including one or more semiconductor packages including the semiconductor package described above.

堆疊之相互電性連結之上述半導體封裝之任一者包括：一支撐架，包括一孔洞，其中上述第一半導體晶片係安置於上述孔洞中；以及一導電柱，貫穿上述支撐架，上述導電柱充滿上述支撐架之所有孔洞，或電鍍於孔洞之壁面，上述導電柱係垂直連接至上述外部端子，其中裸露於上述半導體封裝之一上部份之一半導體封裝之一外部端子係連接至裸露於一 下部分之一半導體封裝之一導電柱。 Any one of the semiconductor packages electrically connected to each other by the stack includes: a support frame including a hole, wherein the first semiconductor chip is disposed in the hole; and a conductive post penetrating the support frame, the conductive column Filling all the holes of the support frame or plating on the wall surface of the hole, the conductive pillar is vertically connected to the external terminal, wherein an external terminal of one of the semiconductor packages exposed on one of the upper portions of the semiconductor package is connected to the bare terminal One One of the lower portions of the semiconductor package is a conductive pillar.

根據本發明之另一實施例，一種半導體封裝製造 方法，包括：形成一第一鑄模層以固定複數第一半導體晶片；形成複數外部端子，上述外部端子分別耦接至位於上述第一半導體晶片之外部區域之上述第一半導體晶片；以及形成第二鑄模層以固定複數第二半導體晶片分別連接至上述第一半導體晶片以及上述外部端子，使得上述外部端子之部分裸露。 According to another embodiment of the present invention, a semiconductor package manufacturing The method includes: forming a first mold layer to fix a plurality of first semiconductor wafers; forming a plurality of external terminals, wherein the external terminals are respectively coupled to the first semiconductor wafer located in an outer region of the first semiconductor wafer; and forming a second The mold layer is respectively connected to the first semiconductor wafer and the external terminal by a fixed plurality of second semiconductor wafers such that a portion of the external terminal is exposed.

上述第一鑄模層固定上述第一半導體晶片，使得 相距一既定長度之上述第一半導體晶片之一表面裸露，其中上述半導體封裝製造方法更包括形成一佈線層，使得在上述第一鑄模層形成之後，上述佈線層電性連接至放置於上述第一半導體晶片之裸露的複數表面上之複數第一信號接合墊。 The first mold layer fixes the first semiconductor wafer, such that a surface of one of the first semiconductor wafers of a predetermined length is exposed, wherein the semiconductor package manufacturing method further comprises forming a wiring layer, wherein after the forming of the first mold layer, the wiring layer is electrically connected to the first layer A plurality of first signal bond pads on the exposed plurality of surfaces of the semiconductor wafer.

上述形成上述佈線層步驟包括：形成一第一絕緣 層於上述第一半導體之內部區域以及外部區域中，使得第一信號接合墊裸露；形成複數佈線圖層，使得上述佈線圖層之一邊電性連接至裸露的上述第一信號接合墊，上述佈線圖層之另一邊延伸至上述第一半導體晶圓之外部區域之上述第一絕緣層；以及堆疊一第二絕緣層於上述第一絕緣層以及上述佈線圖層，使得上述佈線圖層之一邊以及上述佈線圖層之另一邊之部分裸露。 The step of forming the above wiring layer includes: forming a first insulation Forming a first signal bonding pad in the inner region and the outer region of the first semiconductor; forming a plurality of wiring layers such that one side of the wiring layer is electrically connected to the exposed first signal bonding pad, and the wiring layer is The other side extends to the first insulating layer of the outer region of the first semiconductor wafer; and a second insulating layer is stacked on the first insulating layer and the wiring layer such that one side of the wiring layer and the wiring layer are different Part of the side is bare.

上述外部端子分別連接至上述佈線圖層之裸露的 另一邊，其中上述半導體封裝製造方法更包括覆晶式安裝複數連接端子至上述佈線圖層之裸露的一邊，於上述形成上述外部端子之後，分別安裝上述第二半導體晶片於上述第一半導體晶 片上。 The external terminals are respectively connected to the exposed portions of the wiring layer On the other hand, the semiconductor package manufacturing method further includes flip-chip mounting a plurality of connection terminals to a bare side of the wiring layer, and after forming the external terminals, respectively mounting the second semiconductor wafer on the first semiconductor crystal Chip.

上述第二半導體晶片之每一者之主動表面係面對上述第一半導體晶片之每一者之主動表面。 The active surface of each of the second semiconductor wafers faces an active surface of each of the first semiconductor wafers.

上述形成上述第一鑄模層包括：分別形成複數孔洞於複數支撐架中，其中上述第一半導體晶片係安裝於上述孔洞中；將一第一載體基板黏接至上述支撐架；分別安裝上述第一半導體晶片於上述孔洞中；形成上述第一鑄模層；以及移除上述第一載體基板。 Forming the first mold layer includes: forming a plurality of holes in the plurality of support frames, wherein the first semiconductor chip is mounted in the hole; bonding a first carrier substrate to the support frame; respectively mounting the first a semiconductor wafer in the hole; forming the first mold layer; and removing the first carrier substrate.

上述半導體封裝製造方法更包括分別形成複數穿孔於上述支撐架中；以及經由將複數導電柱填滿上述穿孔或電鍍上述導電柱於上述穿孔之壁面以形成分別電性連接至上述外部端子之上述導電柱。 The method for fabricating a semiconductor package further includes forming a plurality of vias in the support frame, and filling the plurality of conductive pillars with the plurality of conductive pillars or plating the conductive pillars on the wall surface of the through holes to form the conductive layers respectively electrically connected to the external terminals. column.

上述外部端子之每一者包括一銲錫球，當形成上述外部端子時，上述外部端子之高度係高於上述第二半導體晶片之高度。 Each of the external terminals includes a solder ball, and when the external terminal is formed, the height of the external terminal is higher than the height of the second semiconductor wafer.

上述半導體封裝製造方法更包括平坦化上述第一鑄模層以及上述第二鑄模層之一或多者，使得上述第一半導體晶片以及上述第二半導體晶片之非主動表面之一或多者裸露。 The semiconductor package manufacturing method further includes planarizing one or more of the first mold layer and the second mold layer such that one or more of the inactive surfaces of the first semiconductor wafer and the second semiconductor wafer are exposed.

100‧‧‧第一平板 100‧‧‧ first tablet

200‧‧‧第二平板 200‧‧‧ second tablet

300‧‧‧半導體封裝 300‧‧‧Semiconductor package

301‧‧‧第一半導體晶片封裝 301‧‧‧First semiconductor chip package

302‧‧‧第二半導體晶片封裝 302‧‧‧Second semiconductor chip package

10‧‧‧支撐架 10‧‧‧Support frame

20‧‧‧第一半導體晶片 20‧‧‧First semiconductor wafer

20a‧‧‧第一主動表面 20a‧‧‧First active surface

22‧‧‧第一信號接合墊 22‧‧‧First signal bond pad

30‧‧‧第一鑄模層 30‧‧‧First mold layer

40‧‧‧佈線層 40‧‧‧ wiring layer

41‧‧‧第一絕緣層 41‧‧‧First insulation

42‧‧‧佈線圖層 42‧‧‧ wiring layer

43‧‧‧第二絕緣層 43‧‧‧Second insulation

50‧‧‧外部端子 50‧‧‧External terminals

60‧‧‧第二半導體晶片 60‧‧‧Second semiconductor wafer

60a‧‧‧第二主動表面 60a‧‧‧Second active surface

62‧‧‧第二信號接合墊 62‧‧‧Second signal bonding pad

63‧‧‧接合墊 63‧‧‧Join pad

65‧‧‧連接端子 65‧‧‧Connecting terminal

70‧‧‧第二鑄模層 70‧‧‧Second mold layer

81‧‧‧第一導電柱 81‧‧‧First conductive column

82‧‧‧第二導電柱 82‧‧‧Second conductive column

2‧‧‧第一載體基板 2‧‧‧First carrier substrate

4‧‧‧第二載體基板 4‧‧‧Second carrier substrate

7‧‧‧基體 7‧‧‧ base

8‧‧‧導體層 8‧‧‧Conductor layer

H1‧‧‧孔洞 H1‧‧‧ hole

H1、H2‧‧‧高度 H1, H2‧‧‧ height

S1、S2‧‧‧空間 S1, S2‧‧‧ space

第1圖係顯示根據本發明之一實施例所述之安置於基體的半導體封裝之結構之剖面圖；第2A-2J圖係顯示製造第1圖之半導體封裝製造方法的剖面圖； 第3圖係顯示包括於第1圖之半導體封裝的半導體晶片之一表面被裸露的結構之剖面圖；第4圖係顯示藉由移除第1圖之半導體封裝之支撐架的結構之剖面圖；第5圖係顯示具有包括第1圖之半導體封裝之複數半導體封裝之堆疊結構之半導體封裝單元的剖面圖；以及第6A-6E圖係顯示導電柱提供於第5圖之半導體封裝單元之半導體封裝製造方法之剖面圖。 1 is a cross-sectional view showing a structure of a semiconductor package disposed on a substrate according to an embodiment of the present invention; and FIG. 2A-2J is a cross-sectional view showing a method of manufacturing the semiconductor package of FIG. 1; 3 is a cross-sectional view showing a structure in which one surface of a semiconductor wafer included in the semiconductor package of FIG. 1 is exposed; and FIG. 4 is a cross-sectional view showing a structure of a support frame by removing the semiconductor package of FIG. 5 is a cross-sectional view showing a semiconductor package unit having a stacked structure of a plurality of semiconductor packages including the semiconductor package of FIG. 1; and FIGS. 6A-6E showing a semiconductor having a conductive pillar provided in the semiconductor package unit of FIG. A cross-sectional view of the package manufacturing method.

閱讀時本發明之詳細實施例時，其範例係顯示於附圖中。以下的實施例係為範例，因此本發明將會徹底且完整得傳達本發明在其技術領域範圍內之內容。本說明書體現餘各種不同形式而不以任何型式限定於此。圖式中，薄層(層與圖案)之厚度以及區域將被誇張化以期清楚呈現。此外，要知道當薄層(層與圖案)稱為「上」、「在上」、「在下」、「在...之下」或「在一表面上」時，在此代表另一薄層(層與圖案)可與其他薄層(層與圖案)或中介薄層(層與圖案)相結合。此外，空間相關詞彙，如「在下」、「下」、「在上」或「上」，在此用以描述一元件與其他元件於圖式中之關係。要知道，空間相關詞彙用以環繞元件不同方向，除了描繪於圖式中的方向以及並未使用「上」以及「下」於實際使用中所指定的方向。也就是，元件可指向另一方向且空間相關詞彙可根據實際使用上元件之方向而做解釋。 In reading the detailed embodiments of the present invention, examples thereof are shown in the accompanying drawings. The following examples are presented as examples, and thus the present invention will be thorough and complete in the context of the invention. This description is in various forms and is not limited in any way. In the drawings, the thickness and area of the thin layers (layers and patterns) will be exaggerated for clarity. In addition, it is necessary to know that when thin layers (layers and patterns) are called "up", "on", "below", "below" or "on a surface", here is another thin Layers (layers and patterns) can be combined with other thin layers (layers and patterns) or intermediate layers (layers and patterns). In addition, spatially related terms such as "under", "lower", "upper" or "upper" are used to describe the relationship of a component and other components in the drawings. It should be understood that spatially related terms are used to surround the components in different directions, except for the directions depicted in the drawings and the directions specified in the actual use without "up" and "down". That is, the component can point in the other direction and the spatially related vocabulary can be interpreted according to the direction in which the component is actually used.

第1圖係顯示根據本發明之一實施例所述之安置 於基體的半導體封裝之結構之剖面圖。 Figure 1 shows the placement according to an embodiment of the invention A cross-sectional view of the structure of the semiconductor package of the substrate.

參照第1圖，根據本發明之一實施例，半導體封裝 300包括第一半導體晶片封裝301以及第二半導體晶片封裝302，其中第二半導體晶片封裝302放置於第一半導體晶片封裝301之下。 Referring to FIG. 1, a semiconductor package in accordance with an embodiment of the present invention 300 includes a first semiconductor wafer package 301 and a second semiconductor wafer package 302, wherein the second semiconductor wafer package 302 is placed under the first semiconductor wafer package 301.

第一半導體晶片封裝301包括第一半導體晶片 20、提供放置第一半導體晶片20之孔洞的支撐架10、用以封裝第一半導體晶片20而使第一半導體晶片20之一表面裸露之第一鑄模層30、電性連接放置於第一半導體晶片20之裸露表面上之第一信號接合墊22之佈線層40、以及突出之外部端子50，使得外部端子50電性連接到延伸至第一半導體晶片20之外側部分之佈線層40之一邊。佈線層40包括第一絕緣層41、佈線圖層42以及第二絕緣層43，第一半導體晶片封裝301以及第二半導體晶片封裝302連接至佈線層40以形成扇出結構。 The first semiconductor chip package 301 includes a first semiconductor wafer 20, a support frame 10 for placing a hole of the first semiconductor wafer 20, a first mold layer 30 for encapsulating the first semiconductor wafer 20 to expose one surface of the first semiconductor wafer 20, and electrically connecting the first semiconductor layer The wiring layer 40 of the first signal bonding pad 22 on the exposed surface of the wafer 20, and the protruding external terminal 50 are such that the external terminal 50 is electrically connected to one side of the wiring layer 40 extending to the outer side portion of the first semiconductor wafer 20. The wiring layer 40 includes a first insulating layer 41, a wiring pattern layer 42, and a second insulating layer 43, and the first semiconductor wafer package 301 and the second semiconductor wafer package 302 are connected to the wiring layer 40 to form a fan-out structure.

此外，第二半導體晶片封裝302包括第二半導體晶 片60、電性連接至放置於第二半導體晶片60之表面之第二信號接合墊62且連接到連接至第一信號接合墊22之佈線層40之另一邊的突出之連接端子65、以及用以將第二半導體晶片60以及外部端子50黏住使得外部端子50之下半部裸露之第二鑄模層70。 In addition, the second semiconductor wafer package 302 includes a second semiconductor crystal The chip 60 is electrically connected to the second signal bond pad 62 placed on the surface of the second semiconductor wafer 60 and connected to the protruding connection terminal 65 connected to the other side of the wiring layer 40 of the first signal bond pad 22, and The second mold wafer 70 and the external terminal 50 are adhered to the second mold layer 70 such that the lower half of the external terminal 50 is exposed.

其中，第一半導體晶片20以及第二半導體晶片60 之表面係為面對面之第一主動表面20a以及第二主動表面60a。第一半導體晶片以及第二半導體晶片60之大小與厚度可為相同或不同，第一半導體晶片20以及第二半導體晶片60包括 記憶體晶片或邏輯晶片。記憶體晶片可包括，例如動態存取記憶體(DRAM)、靜態存取記憶體(SRAM)、快閃式記憶體(flash)、相位變化記憶體(PRAM)、電阻式記憶體(ReRAM)、鐵電材料記憶體(FeRAM)或磁性隨機存取記憶體(MRAM)。 邏輯晶片可為一控制器，用以控制記憶體晶片。例如，第一半導體晶片20可實現為邏輯晶片，第二半導體晶片60可實現為記憶體晶片，反之亦然。 Wherein the first semiconductor wafer 20 and the second semiconductor wafer 60 The surface is the first active surface 20a and the second active surface 60a facing each other. The size and thickness of the first semiconductor wafer and the second semiconductor wafer 60 may be the same or different, and the first semiconductor wafer 20 and the second semiconductor wafer 60 include Memory chip or logic chip. The memory chip may include, for example, a dynamic access memory (DRAM), a static access memory (SRAM), a flash memory, a phase change memory (PRAM), a resistive memory (ReRAM), Ferroelectric material memory (FeRAM) or magnetic random access memory (MRAM). The logic chip can be a controller for controlling the memory chip. For example, the first semiconductor wafer 20 can be implemented as a logic wafer and the second semiconductor wafer 60 can be implemented as a memory wafer and vice versa.

半導體封裝300的放置使得外部端子50電性連接 至基體7之導體層8。下文中，半導體封裝製造方法300會參考第2A-2J圖。 The placement of the semiconductor package 300 electrically connects the external terminals 50 To the conductor layer 8 of the substrate 7. Hereinafter, the semiconductor package manufacturing method 300 will refer to FIG. 2A-2J.

第2A-2J圖係顯示製造第1圖之半導體封裝製造方 法300的剖面圖。 2A-2J shows the manufacture of the semiconductor package manufacturer of Figure 1. A cross-sectional view of the method 300.

參考第2A圖，複數孔洞H1形成於支撐架10之中， 以嵌入二或以上之第一半導體晶片20。在此，支撐架10之厚度可等於或大於安置於孔洞H1之第一半導體晶片20之厚度。此外，可拋光支撐架10使得支撐架10具有較第一半導體晶片20更薄的厚度。支撐架10可於其一或二表面上設置一電路，可由如塑膠或聚合物樹脂之類的絕緣材料做成。絕緣材料包括，如矽、玻璃、陶瓷、塑膠、聚合物等等。此外，支撐架10可包括印刷電路板之基體。支撐架10可改進結構的穩定，以防以下所述之嵌板100的形變。孔洞H1可由如佈線、切割晶片、蝕刻、鑽洞或雷射移除的方式形成。第一半導體晶片20所放置之孔洞H1具有大於第一半導體晶片20之大小。藉由提供上述第一半導體晶片20所放置之孔洞H1支撐架10，可改進具有扇出結構之半 導體封裝之製造效率。此將根據以下後續程序予以描述。 Referring to FIG. 2A, a plurality of holes H1 are formed in the support frame 10, The first semiconductor wafer 20 is embedded in two or more. Here, the thickness of the support frame 10 may be equal to or greater than the thickness of the first semiconductor wafer 20 disposed in the hole H1. In addition, the support frame 10 can be polished such that the support frame 10 has a thinner thickness than the first semiconductor wafer 20. The support frame 10 may be provided with an electric circuit on one or both surfaces thereof, and may be made of an insulating material such as plastic or polymer resin. Insulating materials include, for example, enamel, glass, ceramics, plastics, polymers, and the like. Additionally, the support frame 10 can include a base of a printed circuit board. The support frame 10 can improve the stability of the structure to prevent deformation of the panel 100 described below. Hole H1 can be formed by means such as wiring, dicing wafers, etching, drilling holes or laser removal. The hole H1 in which the first semiconductor wafer 20 is placed has a larger size than the first semiconductor wafer 20. By providing the support frame 10 of the hole H1 in which the first semiconductor wafer 20 is placed, the half having the fan-out structure can be improved. Manufacturing efficiency of the conductor package. This will be described in accordance with the following procedures.

然後參考第2B圖，第一載體基板2黏至支撐架10之 下表面，第一半導體晶片20安置於支撐架10之孔洞H1。第一載體基板2可藉由黏合構件包括液體黏著劑或黏著膠帶，黏至支撐架10。第一半導體晶片20可固定至第一載體基板2，使得第一主動表面20a具有面朝下之電路。提供於第一主動表面20a之第一信號接合墊22接觸第一載體基板2。隨後所述之第一載體基板2以及第二載體基板4包括矽、玻璃、陶瓷、塑膠、聚合物等等。此外，第一載體基板2以及第二載體基板4包括硬性材料，例如模壓材料、聚酰亞胺膠帶等等。 Then referring to FIG. 2B, the first carrier substrate 2 is adhered to the support frame 10 The lower surface, the first semiconductor wafer 20 is disposed in the hole H1 of the support frame 10. The first carrier substrate 2 can be adhered to the support frame 10 by an adhesive member including a liquid adhesive or an adhesive tape. The first semiconductor wafer 20 can be fixed to the first carrier substrate 2 such that the first active surface 20a has a circuit facing downward. The first signal bond pad 22 provided on the first active surface 20a contacts the first carrier substrate 2. The first carrier substrate 2 and the second carrier substrate 4 described later include tantalum, glass, ceramic, plastic, polymer, and the like. Further, the first carrier substrate 2 and the second carrier substrate 4 include a hard material such as a molding material, a polyimide tape, or the like.

接著，參考第2C圖，形成用以形成支撐架10以及 第一半導體晶片20之第一鑄模層30。密封膠滲透入且充滿形成於第一半導體晶片20以及支撐架10之間的空間S1(如第2B圖所示)以及形成於支撐架10之間的空間S2(如第2B圖所示)，從而利用第一鑄模層30整合第一半導體晶片20以及支撐架10。黏著劑可包括一絕緣材料，如環氧模造物(epoxy molding compound,EMC)，以下所述之第一鑄模層30以及第二鑄模層70可由一方法，如印刷或模壓成形，而其上表面可經由平坦化過程而平坦化。 Next, referring to FIG. 2C, a support frame 10 is formed to form The first mold layer 30 of the first semiconductor wafer 20. The sealant penetrates into and fills a space S1 (shown in FIG. 2B) formed between the first semiconductor wafer 20 and the support frame 10 and a space S2 formed between the support frames 10 (as shown in FIG. 2B). The first semiconductor wafer 20 and the support frame 10 are thus integrated using the first mold layer 30. The adhesive may include an insulating material such as an epoxy molding compound (EMC), and the first mold layer 30 and the second mold layer 70 described below may be formed by a method such as printing or molding, and the upper surface thereof. It can be planarized by a planarization process.

隨後，參考第2D圖，第一載體基板2係自支撐架10移除而製造第一平板100。第一半導體晶片20之第一主動表面20a以及支撐架10之下表面可藉由移除第一載體基板2而裸露。 Subsequently, referring to the 2D drawing, the first carrier substrate 2 is removed from the support frame 10 to manufacture the first flat plate 100. The first active surface 20a of the first semiconductor wafer 20 and the lower surface of the support frame 10 may be exposed by removing the first carrier substrate 2.

接著，參考第2E圖以及第2F圖，翻轉第一平板100，第二載體基板4係黏至第一鑄模層30之下表面，且佈線層 40係形成於第一平板100之上，也就是第一半導體晶片20之裸露的第一主動表面20a以及支撐架10之上與第一鑄模層30。佈線層40包括第一絕緣層41、佈線圖層42以及第二絕緣層43。佈線層40可與預先生產的基板或經由壓縮、黏附或回流而黏至第一半導體晶片20、支撐架10以及第一鑄模層30。 Next, referring to FIG. 2E and FIG. 2F, the first flat plate 100 is turned over, and the second carrier substrate 4 is adhered to the lower surface of the first mold layer 30, and the wiring layer The 40 series is formed on the first flat plate 100, that is, the exposed first active surface 20a of the first semiconductor wafer 20 and the support frame 10 and the first mold layer 30. The wiring layer 40 includes a first insulating layer 41, a wiring pattern layer 42, and a second insulating layer 43. The wiring layer 40 may be adhered to the first semiconductor wafer 20, the support frame 10, and the first mold layer 30 with a pre-produced substrate or via compression, adhesion, or reflow.

對於第2E圖所示之佈線層40之鑄模，第一絕緣層 41係形成於第一半導體晶片20之內部區域(第一主動表面20a)以及外部區域(也就是支撐架10以及第一鑄模層30)，使得第一半導體晶片20之第一信號接合墊22之上表面裸露。 For the mold of the wiring layer 40 shown in FIG. 2E, the first insulating layer 41 is formed in an inner region (first active surface 20a) of the first semiconductor wafer 20 and an outer region (ie, the support frame 10 and the first mold layer 30) such that the first signal bonding pad 22 of the first semiconductor wafer 20 The upper surface is bare.

如第2F圖所示，佈線圖層42形成，以致於其一邊 電性連接至第一信號接合墊22而其另一邊延伸至第一半導體晶片20外部的外部區域之第一絕緣層41之上表面。在此，佈線圖層42可由許多方式形成，如沈積或電鍍。此外，佈線圖層42可由金屬材料形成，如銅、銅合金、鋁或鋁合金。佈線圖層42可小型化第一半導體晶片20之輸入以及輸出節點，並增加輸入以及輸出節點之數目。此外，佈線圖層42可用以實現扇出半導體封裝以及具有單層或多層結構。 As shown in FIG. 2F, the wiring layer 42 is formed so that one side thereof The first signal bonding pad 22 is electrically connected to the first signal bonding pad 22 and the other side thereof extends to the upper surface of the first insulating layer 41 of the outer region outside the first semiconductor wafer 20. Here, the wiring layer 42 can be formed in a number of ways, such as deposition or plating. Further, the wiring layer 42 may be formed of a metal material such as copper, copper alloy, aluminum or aluminum alloy. The wiring layer 42 can miniaturize the input and output nodes of the first semiconductor wafer 20 and increase the number of input and output nodes. In addition, the wiring layer 42 can be used to implement a fan-out semiconductor package and have a single layer or a multilayer structure.

此外，第二絕緣層43形成於佈線圖層42之上表 面，使得部分之佈線圖層42裸露。在此情況下，第二絕緣層43可形成於第一絕緣層41以及佈線圖層42之上表面，使得佈線圖層42之一邊連接至第一信號接合墊22之上表面，並且使得延伸至第一半導體晶片20之外部的外部區域之第一絕緣層41之上表面之部分佈線圖層42之另一邊裸露。 Further, the second insulating layer 43 is formed on the wiring layer 42 The surface of the wiring layer 42 is exposed. In this case, the second insulating layer 43 may be formed on the first insulating layer 41 and the upper surface of the wiring layer 42 such that one side of the wiring layer 42 is connected to the upper surface of the first signal bonding pad 22, and is extended to the first The other side of the portion of the wiring layer 42 on the upper surface of the first insulating layer 41 of the outer region of the semiconductor wafer 20 is exposed.

接著，參考第2G圖，外部端子50電性連接至佈線 層40。也就是，外部端子50突出使得外部端子50電性連接至佈線圖層42之另一邊的上表面。外部端子50可具有包括導電錫球之突起結構。此外，外部端子50可由具有包括銅、銅合金、鋁或鋁合金或其他導電材料之導電金屬材料的銲錫膏所形成。此外，外部端子50可承受表面處理，如有機鍍模或金屬電鍍以防其表面氧化。例如，有機鍍模可為有機銲錫保護鍍層以及金屬電鍍可利用金(Au)、鎳(Ni)、鉛(Pb)、銀(Ag)或其他。 Next, referring to FIG. 2G, the external terminal 50 is electrically connected to the wiring. Layer 40. That is, the external terminal 50 is protruded such that the external terminal 50 is electrically connected to the upper surface of the other side of the wiring layer 42. The external terminal 50 may have a protruding structure including a conductive tin ball. Further, the external terminal 50 may be formed of a solder paste having a conductive metal material including copper, a copper alloy, aluminum or an aluminum alloy or other conductive material. In addition, the external terminal 50 can withstand surface treatment such as organic plating or metal plating to prevent surface oxidation thereof. For example, the organic plating mold may be an organic solder protective plating layer and the metal plating may use gold (Au), nickel (Ni), lead (Pb), silver (Ag) or the like.

接著，參考第2H圖，第二半導體晶片60係堆疊於 第一平板100之第一半導體晶片20之上表面，使得第二半導體晶片60電性連接至第一半導體晶片20。第二半導體晶片60可包括第二信號接合墊62、形成於第二信號接合墊62下方之接合墊63以及形成於第二信號接合墊62下方之連接端子65。連接端子65可突起，使得連接端子65係電性連接至第二信號接合墊62且具有包括錫球之突起結構。第二半導體晶片60以覆晶之方式安裝，使得連接端子65連接至佈線圖層45之一邊的上表面，而電性連接第一平板100之第一半導體晶片20至第二半導體晶片60。第二半導體晶片60可面朝下黏接，使得第二主動表面60a面朝下。 Next, referring to FIG. 2H, the second semiconductor wafer 60 is stacked on The upper surface of the first semiconductor wafer 20 of the first flat plate 100 is such that the second semiconductor wafer 60 is electrically connected to the first semiconductor wafer 20. The second semiconductor wafer 60 may include a second signal bond pad 62, a bond pad 63 formed under the second signal bond pad 62, and a connection terminal 65 formed under the second signal bond pad 62. The connection terminal 65 may be protruded such that the connection terminal 65 is electrically connected to the second signal bonding pad 62 and has a protruding structure including a solder ball. The second semiconductor wafer 60 is mounted in a flip chip manner such that the connection terminal 65 is connected to the upper surface of one side of the wiring layer 45 and electrically connects the first semiconductor wafer 20 to the second semiconductor wafer 60 of the first panel 100. The second semiconductor wafer 60 can be bonded face down such that the second active surface 60a faces downward.

第一半導體晶片20之第一主動表面20a以及第二 半導體晶片60之第二主動表面60a之放置，使得其面對面。此放置方式降低第一半導體晶片20以及第二半導體晶片60之間的連接距離，因平衡的放置而降低半導體封裝300之厚度以及結構穩定度。此外，第一半導體晶片20經由佈線層40而電性連接至第二半導體晶片60，藉此形成扇出結構。 First active surface 20a and second of first semiconductor wafer 20 The second active surface 60a of the semiconductor wafer 60 is placed such that it faces face to face. This placement reduces the connection distance between the first semiconductor wafer 20 and the second semiconductor wafer 60, reducing the thickness and structural stability of the semiconductor package 300 due to balanced placement. Further, the first semiconductor wafer 20 is electrically connected to the second semiconductor wafer 60 via the wiring layer 40, thereby forming a fan-out structure.

第一半導體晶片20以及第二半導體晶片60之大小 以及厚度可為相同或是不同，而第一半導體晶片20以及第二半導體晶片60包括一記憶體晶片或是邏輯晶片。記憶體晶片可包括動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃式記憶體(flash)、相位變化記憶體(PRAM)、電阻式記憶體(ReRAM)、鐵電材料記憶體(FeRAM)或磁性隨機存取記憶體(MRAM)。邏輯晶片可為控制器或控制記憶體晶片。 Size of the first semiconductor wafer 20 and the second semiconductor wafer 60 And the thicknesses may be the same or different, and the first semiconductor wafer 20 and the second semiconductor wafer 60 comprise a memory wafer or a logic wafer. The memory chip may include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, phase change memory (PRAM), resistive memory (ReRAM), Ferroelectric material memory (FeRAM) or magnetic random access memory (MRAM). The logic chip can be a controller or a control memory chip.

接著，參考第2I圖，第一平板100之整個上表面鑄 模成形，使得外部端子50之上表面之一部分裸露，以製造提供第二鑄模層70之第二平板200。在此情況下，外部端子50之高度可大於放置於佈線層40之第二半導體晶片60之高度。也就是，根據第二絕緣層43之表面，外部端子50之高度H1可大於第二半導體晶片60之高度H2。此原因係為儘管第二鑄模層70用以覆蓋第二半導體晶片60之上表面，外部端子50之上表面還是可以有效地裸露。 Next, referring to FIG. 2I, the entire upper surface of the first flat plate 100 is cast. The molding is performed such that one of the upper surfaces of the external terminal 50 is partially exposed to manufacture the second flat plate 200 which provides the second molding layer 70. In this case, the height of the external terminal 50 may be greater than the height of the second semiconductor wafer 60 placed on the wiring layer 40. That is, according to the surface of the second insulating layer 43, the height H1 of the external terminal 50 may be greater than the height H2 of the second semiconductor wafer 60. The reason for this is that although the second mold layer 70 is used to cover the upper surface of the second semiconductor wafer 60, the upper surface of the external terminal 50 can be effectively exposed.

第二鑄模層70形塑第一平板100上之第二半導體 晶片60以及外部端子50，使得外部端子50之上表面裸露。密封膠注入且充滿由佈線層40以及第二半導體晶片60之間所形成空間S3(如第2H圖所示)、由第二半導體晶片60以及外部端子50之間所形成之空間S4(如第2H圖所示)以及由外部端子50之間所形成之空間S5(如第2H圖所示)，利用第二鑄模層70將第二半導體晶片60與外部端子50整合。因此，第二平板200可與第一平板100整合在一起。 The second mold layer 70 shapes the second semiconductor on the first flat plate 100 The wafer 60 and the external terminal 50 are such that the upper surface of the external terminal 50 is exposed. The sealant is injected and filled with a space S3 formed between the wiring layer 40 and the second semiconductor wafer 60 (as shown in FIG. 2H), and a space S4 formed between the second semiconductor wafer 60 and the external terminal 50 (eg, 2H is shown) and a space S5 formed between the external terminals 50 (as shown in FIG. 2H), and the second semiconductor wafer 60 is integrated with the external terminal 50 by the second mold layer 70. Therefore, the second flat plate 200 can be integrated with the first flat plate 100.

第一鑄模層30以及第二鑄模層70可由相同材料組 成，藉此最小化熱形變且增進結構穩定性。根據本發明之另一實施例，第一鑄模層30以及第二鑄模層70可由不同材料形成。 此外，第一鑄模層30以及第二鑄模層70之厚度可為相同或不同，且可合適的選擇以避免考慮第一鑄模層30以及第二鑄模層70間與第一半導體封裝301以及第二半導體封裝302間之不同的熱膨脹係數(CTE)而產生之扭轉或彎曲。此外，第一鑄模層30以及第二鑄模層70可相互連接以形成整合結構(一體結構)而鑄模，使得佈線層40不會裸露。 The first mold layer 30 and the second mold layer 70 may be of the same material group Thereby, thereby minimizing thermal deformation and improving structural stability. According to another embodiment of the present invention, the first mold layer 30 and the second mold layer 70 may be formed of different materials. In addition, the thicknesses of the first mold layer 30 and the second mold layer 70 may be the same or different, and may be appropriately selected to avoid consideration of the first mold layer 30 and the second mold layer 70 and the first semiconductor package 301 and the second. Torsion or bending due to different coefficients of thermal expansion (CTE) between the semiconductor packages 302. Further, the first mold layer 30 and the second mold layer 70 may be connected to each other to form an integrated structure (integral structure) to be molded so that the wiring layer 40 is not exposed.

接著，參考第2J圖，移除第二載體基板4後，堆疊 之第一半導體晶片20以及第二半導體晶片60分別為上部份與下部分之一體結構，其係根據半導體封裝300之切割流程所區分。切割流程可包括單片流程，單片流程係包括利用由鑽石、衝孔機(punch)或雷射形成之刀片所切割。 Next, referring to FIG. 2J, after removing the second carrier substrate 4, stacking The first semiconductor wafer 20 and the second semiconductor wafer 60 are respectively a one-piece structure of an upper portion and a lower portion, which are distinguished according to a cutting process of the semiconductor package 300. The cutting process can include a one-piece process that includes cutting with a blade formed from a diamond, punch, or laser.

接著，如第1圖所示，半導體封裝300係安裝於基 體7，使得半導體封裝300之外部端子50電性連接至基體7之導電層8。 Next, as shown in FIG. 1, the semiconductor package 300 is mounted on the base. The body 7 electrically connects the external terminal 50 of the semiconductor package 300 to the conductive layer 8 of the substrate 7.

如上所述，根據本實施例，第二半導體晶片60係 以覆晶方式黏接於第一平板100時，第一半導體晶片20由密封膠封存，而非於另一封裝流程。此外，平板級的鑄模係利用密封膠執行，使得第二半導體晶片60被覆蓋，藉此有效地降低半導體封裝300之厚度。此外，第一半導體晶片20以及第二半導體晶片60之上結構以及下結構(垂直地)堆疊方式相類似，基於包括於半導體封裝300之第一半導體晶片20之連線端子65， 因而降低由外部環境所造成之熱形變的差異且增進結構穩定性。 As described above, according to the embodiment, the second semiconductor wafer 60 is When the first flat panel 100 is flip-chip bonded, the first semiconductor wafer 20 is sealed by a sealant instead of another packaging process. In addition, the flat-plate molding is performed using a sealant such that the second semiconductor wafer 60 is covered, thereby effectively reducing the thickness of the semiconductor package 300. In addition, the structure of the first semiconductor wafer 20 and the second semiconductor wafer 60 and the structure of the lower structure (vertical) are similar, based on the connection terminal 65 of the first semiconductor wafer 20 included in the semiconductor package 300, Thus, the difference in thermal deformation caused by the external environment is reduced and structural stability is improved.

第3圖係顯示包括於第1圖之半導體封裝的半導體 晶片之一表面被裸露的結構之剖面圖。第一半導體晶片20以及第二半導體晶片60大小以及厚度可為相同或不同，既定的大小以及厚度係列出以方便說明。 Figure 3 is a diagram showing a semiconductor package included in the semiconductor package of Figure 1. A cross-sectional view of a surface of one of the wafers that is exposed. The size and thickness of the first semiconductor wafer 20 and the second semiconductor wafer 60 may be the same or different, and the predetermined size and thickness are seriesed for convenience of explanation.

參考第3A圖，製造半導體封裝流程如第2A-2J圖所 示，平坦化第一鑄模層30以裸露第一半導體晶片20。第一鑄模層可利用磨平的方式(拋光)、回蝕(etch-back)或化學機械平坦化(chemical-mechanical planarization,CMP)來平坦化。 Referring to FIG. 3A, a semiconductor package process is performed as shown in FIG. 2A-2J. The first mold layer 30 is planarized to expose the first semiconductor wafer 20. The first mold layer can be planarized by means of flattening (polishing), etch-back or chemical-mechanical planarization (CMP).

參考第3B圖，可平坦化第二鑄模層70以裸露第二 半導體晶片60。同時，外部端子50也可平坦化，使得外部端子50之平坦表面齊平第二半導體晶片60之平坦表面。 Referring to FIG. 3B, the second mold layer 70 may be planarized to expose the second Semiconductor wafer 60. At the same time, the external terminal 50 can also be planarized such that the flat surface of the external terminal 50 is flush with the flat surface of the second semiconductor wafer 60.

參考第3C圖，平坦化第一鑄模層30以及第二鑄模 層70以裸露第一半導體晶片20以及第二半導體晶片60，降低厚度且熱排放之半導體封裝300因而被製造。 Referring to FIG. 3C, planarizing the first mold layer 30 and the second mold The layer 70 exposes the first semiconductor wafer 20 and the second semiconductor wafer 60, and the semiconductor package 300 of reduced thickness and heat discharge is thus fabricated.

此平坦化流程可執行於平板級，或在半導體封裝 300為一體之基礎上劃分之後。此外，在此情況下第一半導體晶片20之第一主動表面20a以及第二半導體晶片60之第二主動表面60a面對面，第一半導體晶片20之第一非主動表面20b以及第二半導體晶片60之第二非主動表面60b可經由平坦化之後而裸露。第一非主動表面20b以及第二非主動表面60b係為沒有電路形成之區域。 This flattening process can be performed at the flat panel level, or in a semiconductor package 300 is divided on the basis of integration. In addition, in this case, the first active surface 20a of the first semiconductor wafer 20 and the second active surface 60a of the second semiconductor wafer 60 face each other, the first inactive surface 20b of the first semiconductor wafer 20 and the second semiconductor wafer 60 The second inactive surface 60b may be exposed after being planarized. The first inactive surface 20b and the second inactive surface 60b are regions in which no circuit is formed.

第4圖係顯示藉由移除第1圖之半導體封裝之支撐 架的結構之剖面圖。 Figure 4 shows the support of the semiconductor package by removing Figure 1. A cross-sectional view of the structure of the frame.

參考第4圖，在第2A-2J圖所示之製造半導體封裝 流程中，半導體封裝300可不需支撐架10的情況下而製造。在此狀況下，基於包括於半導體封裝300之第一半導體晶片20之連接端子65，共享佈線層40之第一半導體晶圓20以及第二半導體晶圓60之上結構以及下結構係為相似，因而降低因外部環境所造成之熱形變之差異並增進結構穩定性。 Refer to Figure 4 to manufacture a semiconductor package as shown in Figure 2A-2J. In the process, the semiconductor package 300 can be fabricated without the need for the support frame 10. In this case, based on the connection terminals 65 of the first semiconductor wafer 20 included in the semiconductor package 300, the structures on the first semiconductor wafer 20 and the second semiconductor wafer 60 sharing the wiring layer 40 and the lower structure are similar. Therefore, the difference in thermal deformation caused by the external environment is reduced and structural stability is improved.

第5圖係顯示具有包括第1圖之半導體封裝之複數 半導體封裝之堆疊結構之半導體封裝單元的剖面圖。第6A-6E圖係顯示導電柱提供於第5圖之半導體封裝單元之半導體封裝製造方法之剖面圖。 Figure 5 is a diagram showing a plurality of semiconductor packages including the first Figure A cross-sectional view of a semiconductor package unit of a stacked structure of a semiconductor package. 6A-6E are cross-sectional views showing a method of fabricating a semiconductor package in which the conductive pillars are provided in the semiconductor package unit of FIG. 5.

參考第5圖，半導體封裝單元中之包括半導體封裝 300之堆疊的二或多半導體封裝。個別的半導體封裝300包括穿過支撐架10之導電柱80，使得其互相電性連接。導電柱80的形成，使得支撐架10之穿孔H2(如第6A圖所示)被填滿或在穿孔H2之壁面鍍模。放置於半導體封裝300之上部份之第一鑄模層30可用以覆蓋第一導電柱81之上表面。放置於半導體封裝300之下部份之第一鑄模層30，係用以將第二導電柱82之上表面之一部分裸露而連接至形成於半導體封裝300上至第二導電柱82之外部端子50。 Referring to FIG. 5, a semiconductor package includes a semiconductor package A stack of two or more semiconductor packages of 300. The individual semiconductor packages 300 include conductive posts 80 that pass through the support frame 10 such that they are electrically connected to one another. The conductive post 80 is formed such that the perforation H2 of the support frame 10 (as shown in Fig. 6A) is filled or plated on the wall surface of the perforation H2. A first mold layer 30 placed over a portion of the semiconductor package 300 can be used to cover the upper surface of the first conductive pillar 81. The first mold layer 30 placed under the semiconductor package 300 is used to expose a portion of the upper surface of the second conductive pillar 82 to the external terminal 50 formed on the semiconductor package 300 to the second conductive pillar 82. .

因此，堆疊之個別的半導體封裝300透過第一導電 柱81以及第二導電柱82，電性連接至佈線圖層42以及外部端子50。導電柱80可包括穿透電極，如直通矽晶穿孔(through silicon via,TSV)。利用導電柱80之半導體封裝300製造流程將 參考第6A-6E圖而詳述。與上述第2A-2J圖相同之描述將省略或簡述。 Therefore, the stacked individual semiconductor packages 300 are transmitted through the first conductive The pillar 81 and the second conductive pillar 82 are electrically connected to the wiring layer 42 and the external terminal 50. The conductive post 80 can include a through electrode, such as a through silicon via (TSV). The manufacturing process of the semiconductor package 300 using the conductive pillars 80 will Details are made with reference to Figures 6A-6E. Descriptions identical to those of the above-described 2A-2J drawings will be omitted or briefly described.

參考第6A圖，穿孔H2形成於支撐架10中，穿孔H2 可使得以下所述之導電柱80經由佈線層40而垂直連接至外部端子50。 Referring to FIG. 6A, a perforation H2 is formed in the support frame 10, and the perforation H2 The conductive post 80 described below may be vertically connected to the external terminal 50 via the wiring layer 40.

接著，參考第6B圖，在導電柱80形成於穿孔H2之 後，支撐架10以及第一半導體晶片20被密封膠覆蓋以形成第一鑄模層30。因此，第一平板100製造完成。第一鑄模層30可使得導電柱80之上表面裸露。 Next, referring to FIG. 6B, the conductive pillars 80 are formed in the perforations H2. Thereafter, the support frame 10 and the first semiconductor wafer 20 are covered with a sealant to form a first mold layer 30. Therefore, the first flat plate 100 is manufactured. The first mold layer 30 may expose the upper surface of the conductive post 80.

接著，參考第6C-6D圖，翻轉第一平板100，佈線 層40包括形成於第一平板100之上的第一絕緣層41、佈線圖層42以及第二絕緣層43。導電柱80連接至佈線圖層42。 Next, referring to the 6C-6D diagram, flipping the first flat panel 100, wiring The layer 40 includes a first insulating layer 41, a wiring pattern layer 42, and a second insulating layer 43 formed over the first flat plate 100. The conductive post 80 is connected to the wiring layer 42.

在外部端子50電性連接至佈線層40之後，第二半 導體晶片60堆疊於第一平板100之第一半導體晶片20上，而第二鑄模層70隨後形成。因此，第二平板200之製造完成，且第一平板100與第二平板200整合在一起。 After the external terminal 50 is electrically connected to the wiring layer 40, the second half The conductor wafer 60 is stacked on the first semiconductor wafer 20 of the first flat plate 100, and the second mold layer 70 is subsequently formed. Therefore, the manufacture of the second flat plate 200 is completed, and the first flat plate 100 and the second flat plate 200 are integrated.

隨後，參考第6E圖，形成為一體結構之堆疊的第 一半導體晶片20以及第二半導體晶片60，係基於半導體封裝300以切割流程劃分。半導體封裝300對應至第5圖所示之半導體封裝300之下半部。可以第6A-6E圖相同之製造方法來製造半導體封裝300之下半部，形成第一鑄模層30之流程可由覆蓋整個導電柱80之上表面之流程來取代。 Subsequently, referring to FIG. 6E, the first stack of the integrated structure is formed. A semiconductor wafer 20 and a second semiconductor wafer 60 are divided by a dicing process based on the semiconductor package 300. The semiconductor package 300 corresponds to the lower half of the semiconductor package 300 shown in FIG. The lower half of the semiconductor package 300 can be fabricated by the same manufacturing method as in FIGS. 6A-6E, and the process of forming the first mold layer 30 can be replaced by a process of covering the entire upper surface of the conductive pillar 80.

從上述描述中可看出，根據本發明之一實施例，根據半導體封裝之半導體封裝單元以及半導體封裝製造方 法，間隔一既定距離之複數第一半導體晶片係形成於一平板，複數第二半導體晶片分別堆疊於第一半導體晶片上，使得第二半導體晶片墊性連接至第一半導體晶片，並使得結構因而形成，藉此降低半導體封裝之總厚度。 As can be seen from the above description, a semiconductor package unit and a semiconductor package manufacturer according to a semiconductor package according to an embodiment of the present invention a plurality of first semiconductor wafers are formed on a flat plate at a predetermined distance, and a plurality of second semiconductor wafers are respectively stacked on the first semiconductor wafer such that the second semiconductor wafer is pad-connected to the first semiconductor wafer, and the structure is thus Formed thereby reducing the overall thickness of the semiconductor package.

此外，基於第一半導體晶片以及第二半導體晶片間之連接端子，半導體晶片封裝結構之上部分以及下部分係為相同結構，藉此增進對抗熱形變之結構穩定性。 Further, based on the connection terminals between the first semiconductor wafer and the second semiconductor wafer, the upper portion and the lower portion of the semiconductor wafer package structure have the same structure, thereby enhancing structural stability against thermal deformation.

此外，第一半導體晶片以及第二半導體晶片係以其主動表面相互面對面之方式放置，藉此降低第一半導體晶片以及第二半導體晶片間之連線距離、降低半導體晶片之厚度以及因平衡放置而增進結構穩定性。 In addition, the first semiconductor wafer and the second semiconductor wafer are placed with their active surfaces facing each other, thereby reducing the connection distance between the first semiconductor wafer and the second semiconductor wafer, reducing the thickness of the semiconductor wafer, and balancing placement. Improve structural stability.

此外，平坦化鑄模層以裸露第一半導體晶片以及第二半導體晶片之至少一非主動表面，藉此實現薄的半導體封裝且實現熱排放。 Furthermore, the mold layer is planarized to expose at least one inactive surface of the first semiconductor wafer and the second semiconductor wafer, thereby achieving a thin semiconductor package and achieving heat dissipation.

儘管在此顯示以及描述本發明之一些實施例，但要知道該領域具有通常知識者知道這些實施例的改變並不背離本發明之原則與精神，本發明之範圍係定義於申請專利範圍。 Although some embodiments of the invention have been shown and described herein, it is understood by those of ordinary skill in the art that the invention may be practiced without departing from the spirit and scope of the invention.

300‧‧‧半導體封裝 300‧‧‧Semiconductor package

301‧‧‧第一半導體晶片封裝 301‧‧‧First semiconductor chip package

302‧‧‧第二半導體晶片封裝 302‧‧‧Second semiconductor chip package

10‧‧‧支撐架 10‧‧‧Support frame

20‧‧‧第一半導體晶片 20‧‧‧First semiconductor wafer

20a‧‧‧第一主動表面 20a‧‧‧First active surface

22‧‧‧第一信號接合墊 22‧‧‧First signal bond pad

30‧‧‧第一鑄模層 30‧‧‧First mold layer

40‧‧‧佈線層 40‧‧‧ wiring layer

41‧‧‧第一絕緣層 41‧‧‧First insulation

42‧‧‧佈線圖層 42‧‧‧ wiring layer

43‧‧‧第二絕緣層 43‧‧‧Second insulation

50‧‧‧外部端子 50‧‧‧External terminals

60‧‧‧第二半導體晶片 60‧‧‧Second semiconductor wafer

60a‧‧‧第二主動表面 60a‧‧‧Second active surface

62‧‧‧第二信號接合墊 62‧‧‧Second signal bonding pad

63‧‧‧接合墊 63‧‧‧Join pad

65‧‧‧連接端子 65‧‧‧Connecting terminal

70‧‧‧第二鑄模層 70‧‧‧Second mold layer

7‧‧‧基體 7‧‧‧ base

8‧‧‧導體層 8‧‧‧Conductor layer

Claims (23)

一種半導體封裝，包括：一第一半導體晶片封裝，包括一支撐架、容置於上述支撐架所形成之一孔洞中之一第一半導體晶片以及用以固定上述第一半導體晶片之一第一鑄模層；以及一第二半導體晶片封裝，包括電性連接至上述第一半導體晶片之一第二半導體晶片、電性耦接至上述第一半導體晶片上述第一半導體晶片之外部區域之一外部端子以及用以固定上述第二半導體晶片與上述外部端子而使得上述外部端子之一部分裸露之一第二鑄模層。 A semiconductor package comprising: a first semiconductor chip package comprising a support frame, a first semiconductor wafer received in one of the holes formed by the support frame, and a first mold for fixing the first semiconductor wafer And a second semiconductor chip package including a second semiconductor wafer electrically connected to one of the first semiconductor wafers, and an external terminal electrically coupled to an outer region of the first semiconductor wafer of the first semiconductor wafer and And a second mold layer for fixing the second semiconductor wafer and the external terminal such that one of the external terminals is partially exposed. 如申請專利範圍第1項所述之半導體封裝，其中上述外部端子包括一銲錫球。 The semiconductor package of claim 1, wherein the external terminal comprises a solder ball. 如申請專利範圍第1項所述之半導體封裝，其中上述外部端子之高度係高於上述第二半導體晶片之高度。 The semiconductor package of claim 1, wherein the height of the external terminal is higher than the height of the second semiconductor wafer. 如申請專利範圍第1項所述之半導體封裝，其中上述第一鑄模層固定上述第一半導體晶片，使得上述第一半導體晶片之一表面係為裸露，其中上述第一半導體晶片封裝更包括一佈線層，上述佈線層連接至上述第一半導體晶片之裸露的上述表面之一第一信號接合墊，以及其中上述外部端子突起而使得上述外部端子係電性連接至上述佈線層之一邊之一裸露部分，上述佈線層係延伸至上述第一半導體晶片之外部區域。 The semiconductor package of claim 1, wherein the first mold layer fixes the first semiconductor wafer such that a surface of the first semiconductor wafer is exposed, wherein the first semiconductor chip package further comprises a wiring a layer, the wiring layer is connected to one of the exposed first surface of the first semiconductor wafer, and wherein the external terminal is protruded such that the external terminal is electrically connected to one of the exposed sides of the wiring layer The wiring layer extends to an outer region of the first semiconductor wafer. 如申請專利範圍第4項所述之半導體封裝，其中上述第二 半導體晶片封裝更包括突起的一連接端子，使得上述連接端子電性連接至位於上述第二半導體晶片之一表面之一第二信號接合墊、上述連接端子連接到連接至上述第一信號接合墊之上述佈線層之另一邊以及上述第二鑄模層固定上述第二半導體晶片以及上述外部端子而使得上述外部端子之一部分裸露。 The semiconductor package of claim 4, wherein the second The semiconductor chip package further includes a connection terminal, wherein the connection terminal is electrically connected to a second signal bonding pad located on one surface of the second semiconductor wafer, and the connection terminal is connected to the first signal bonding pad. The other side of the wiring layer and the second mold layer fix the second semiconductor wafer and the external terminal such that one of the external terminals is exposed. 如申請專利範圍第4項所述之半導體封裝，其中上述佈線層包括：一第一絕緣層，形成於上述第一半導體晶片，使得上述第一信號接合墊裸露；一佈線圖層，用以將上述佈線圖層之一邊電性連接至裸露之上述第一信號接合墊，而上述佈線圖層之另一邊堆疊於上述第一半導體晶片之外部區域之上述第一絕緣層上；以及一第二絕緣層，堆疊於上述第一絕緣層以及上述佈線圖層之上，使得上述佈線圖層之一邊以及另一邊的一部份裸露。 The semiconductor package of claim 4, wherein the wiring layer comprises: a first insulating layer formed on the first semiconductor wafer such that the first signal bonding pad is exposed; and a wiring layer for using the wiring layer One side of the wiring layer is electrically connected to the exposed first signal bonding pad, and the other side of the wiring layer is stacked on the first insulating layer of the outer region of the first semiconductor wafer; and a second insulating layer is stacked On one of the first insulating layer and the wiring layer, one side of the wiring layer and a part of the other side are exposed. 如申請專利範圍第6項所述之半導體封裝，其中上述外部端子係連接至上述佈線圖層之裸露的另一邊，且上述連接端子係連接至上述佈線圖層之裸露的另一邊。 The semiconductor package of claim 6, wherein the external terminal is connected to the exposed other side of the wiring layer, and the connection terminal is connected to the exposed other side of the wiring layer. 如申請專利範圍第1項所述之半導體封裝，其中上述外部端子係以一中心軸垂直地放置且延伸，而穿過上述支撐架。 The semiconductor package of claim 1, wherein the external terminal is vertically placed and extended by a central axis and passes through the support frame. 如申請專利範圍第8項所述之半導體封裝，其中上述支撐架包括一電路，上述電路形成於上述支撐架之單或雙面，且由絕緣材料做成。 The semiconductor package of claim 8, wherein the support frame comprises a circuit formed on one or both sides of the support frame and made of an insulating material. 如申請專利範圍第8項所述之半導體封裝，其中上述第一鑄模層以及上述第二鑄模層係為相同材料，上述第一半導體晶片係經由上述第一鑄模層與上述支撐架結合在一起，上述第二半導體晶片係經由上述第二鑄模層與上述外部端子結合在一起。 The semiconductor package of claim 8, wherein the first mold layer and the second mold layer are the same material, and the first semiconductor wafer is bonded to the support frame via the first mold layer. The second semiconductor wafer is bonded to the external terminal via the second mold layer. 如申請專利範圍第1項所述之半導體封裝，其中上述第一半導體晶片之主動表面係面對上述第二半導體晶片之主動表面。 The semiconductor package of claim 1, wherein the active surface of the first semiconductor wafer faces an active surface of the second semiconductor wafer. 如申請專利範圍第1項所述之半導體封裝，其中上述第一鑄模層以及上述第二鑄模層之一或多者係為平坦化，使得上述第一半導體晶片以及上述第二半導體晶片之一或多非主動表面係為裸露。 The semiconductor package of claim 1, wherein one or more of the first mold layer and the second mold layer are planarized such that one of the first semiconductor wafer and the second semiconductor wafer or Many non-active surfaces are bare. 一半導體封裝單元，包括二或多半導體封裝之一堆疊，上述半導體封裝包括申請專利範圍第1-12項所述之半導體封裝。 A semiconductor package unit comprising one of two or more semiconductor packages, the semiconductor package comprising the semiconductor package described in claims 1-12. 如申請專利範圍第13項所述之半導體封裝，其中放置於上述堆疊之一下部分之上述半導體封裝之一者包括：一導電柱，貫穿上述支撐架，上述導電柱充滿上述支撐架之所有孔洞，或電鍍於孔洞之壁面，上述導電柱係電性連接至放置於上述堆疊之一上部分之上述半導體封裝之一者之上述外部端子。 The semiconductor package of claim 13, wherein one of the semiconductor packages placed in a lower portion of the stack comprises: a conductive post extending through the support frame, the conductive post filling all the holes of the support frame, Or electroplating on the wall surface of the hole, the conductive post electrically connected to the external terminal of one of the semiconductor packages placed on a portion of the stack. 一種半導體封裝製造方法，包括：在一支撐架中形成複數孔洞；將複數第一半導體晶片安置於上述孔洞中； 形成一第一鑄模層以固定上述支撐架以及上述第一半導體晶片；形成複數外部端子，上述外部端子分別耦接至位於上述第一半導體晶片之外部區域；將複數第二半導體晶片電性連接至上述第一半導體晶片；以及形成第二鑄模層以固定上述第二半導體晶片以及上述外部端子，使得上述外部端子之部分裸露。 A semiconductor package manufacturing method includes: forming a plurality of holes in a support frame; and placing a plurality of first semiconductor wafers in the holes; Forming a first mold layer to fix the support frame and the first semiconductor wafer; forming a plurality of external terminals, wherein the external terminals are respectively coupled to an outer region of the first semiconductor wafer; and electrically connecting the plurality of second semiconductor wafers to The first semiconductor wafer; and a second mold layer to fix the second semiconductor wafer and the external terminal such that a portion of the external terminal is exposed. 如申請專利範圍第15項所述之半導體封裝製造方法，其中上述第一鑄模層固定上述第一半導體晶片，使得相距一既定長度之上述第一半導體晶片之一表面裸露，其中上述半導體封裝製造方法更包括形成一佈線層，使得在上述第一鑄模層形成之後，上述佈線層電性連接至放置於上述第一半導體晶片之裸露的複數表面上之複數第一信號接合墊。 The method of manufacturing a semiconductor package according to claim 15, wherein the first mold layer fixes the first semiconductor wafer such that a surface of one of the first semiconductor wafers is separated from a predetermined length, wherein the semiconductor package manufacturing method Further comprising forming a wiring layer such that after the first mold layer is formed, the wiring layer is electrically connected to the plurality of first signal bond pads placed on the exposed plurality of surfaces of the first semiconductor wafer. 如申請專利範圍第16項所述之半導體封裝製造方法，其中上述形成上述佈線層步驟包括：形成一第一絕緣層於上述第一半導體之內部區域以及外部區域中，使得第一信號接合墊裸露；形成複數佈線圖層，使得上述佈線圖層之一邊電性連接至裸露的上述第一信號接合墊，上述佈線圖層之另一邊延伸至上述第一半導體晶圓之外部區域之上述第一絕緣層；以及堆疊一第二絕緣層於上述第一絕緣層以及上述佈線圖層，使得上述佈線圖層之一邊以及上述佈線圖層之另一邊之部 分裸露。 The semiconductor package manufacturing method of claim 16, wherein the forming the wiring layer comprises: forming a first insulating layer in an inner region and an outer region of the first semiconductor such that the first signal bonding pad is exposed Forming a plurality of wiring layers such that one side of the wiring layer is electrically connected to the exposed first signal bonding pad, and the other side of the wiring layer extends to the first insulating layer of an outer region of the first semiconductor wafer; Stacking a second insulating layer on the first insulating layer and the wiring layer, such that one side of the wiring layer and the other side of the wiring layer Diluted. 如申請專利範圍第17項所述之半導體封裝製造方法，其中上述外部端子分別連接至上述佈線圖層之裸露的另一邊，其中上述半導體封裝製造方法更包括覆晶式安裝複數連接端子至上述佈線圖層之裸露的一邊，於上述形成上述外部端子之後，分別安裝上述第二半導體晶片於上述第一半導體晶片上。 The semiconductor package manufacturing method of claim 17, wherein the external terminals are respectively connected to the exposed other side of the wiring layer, wherein the semiconductor package manufacturing method further comprises flip-chip mounting a plurality of connection terminals to the wiring layer On the exposed side, after the external terminals are formed as described above, the second semiconductor wafer is mounted on the first semiconductor wafer. 如申請專利範圍第15項所述之半導體封裝製造方法，其中上述第二半導體晶片之每一者之主動表面係面對上述第一半導體晶片之每一者之主動表面。 The semiconductor package manufacturing method of claim 15, wherein the active surface of each of the second semiconductor wafers faces an active surface of each of the first semiconductor wafers. 如申請專利範圍第15項所述之半導體封裝製造方法，其中上述在一支撐架中形成複數孔洞、上述將複數第一半導體晶片安置於上述孔洞中以及上述形成上述第一鑄模層包括：分別形成複數孔洞於複數支撐架中，其中上述第一半導體晶片係安裝於上述孔洞中；將一第一載體基板黏接至上述支撐架；分別安裝上述第一半導體晶片於上述孔洞中；形成上述第一鑄模層；以及移除上述第一載體基板。 The method of manufacturing a semiconductor package according to claim 15, wherein the forming a plurality of holes in a support frame, disposing the plurality of first semiconductor wafers in the holes, and forming the first mold layer comprises: forming separately a plurality of holes in the plurality of support frames, wherein the first semiconductor wafer is mounted in the holes; a first carrier substrate is bonded to the support frame; and the first semiconductor wafer is respectively mounted in the holes; a mold layer; and removing the first carrier substrate. 如申請專利範圍第20項所述之半導體封裝製造方法，更包括：分別形成複數穿孔於上述支撐架中；以及經由將複數導電柱填滿上述穿孔或電鍍上述導電柱於上述 穿孔之壁面以形成分別電性連接至上述外部端子之上述導電柱。 The method of manufacturing a semiconductor package according to claim 20, further comprising: forming a plurality of perforations in the support frame respectively; and filling the perforations or plating the conductive posts by the plurality of conductive posts; The perforated wall faces are formed to form the above-mentioned conductive posts electrically connected to the external terminals, respectively. 如申請專利範圍第15項所述之半導體封裝製造方法，其中上述外部端子之每一者包括一銲錫球，當形成上述外部端子時，上述外部端子之高度係高於上述第二半導體晶片之高度。 The semiconductor package manufacturing method of claim 15, wherein each of the external terminals comprises a solder ball, and when the external terminal is formed, the height of the external terminal is higher than a height of the second semiconductor wafer . 如申請專利範圍第15項所述之半導體封裝製造方法，更包括平坦化上述第一鑄模層以及上述第二鑄模層之一或多者，使得上述第一半導體晶片以及上述第二半導體晶片之非主動表面之一或多者裸露。 The semiconductor package manufacturing method of claim 15, further comprising planarizing one or more of the first mold layer and the second mold layer such that the first semiconductor wafer and the second semiconductor wafer are non- One or more of the active surfaces are bare.
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