TWI518810B - Semiconductor device and method of forming ubm fixed relative to interconnect structure for alignment of semiconductor die - Google Patents
Semiconductor device and method of forming ubm fixed relative to interconnect structure for alignment of semiconductor die Download PDFInfo
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- TWI518810B TWI518810B TW099114344A TW99114344A TWI518810B TW I518810 B TWI518810 B TW I518810B TW 099114344 A TW099114344 A TW 099114344A TW 99114344 A TW99114344 A TW 99114344A TW I518810 B TWI518810 B TW I518810B
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- Prior art keywords
- conductive
- layer
- semiconductor
- interconnect structure
- conductive layer
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Links
- 239000004065 semiconductor Substances 0.000 title claims description 211
- 238000000034 method Methods 0.000 title claims description 119
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- 239000000463 material Substances 0.000 description 71
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 51
- 238000005229 chemical vapour deposition Methods 0.000 description 42
- 238000005240 physical vapour deposition Methods 0.000 description 42
- 229910000679 solder Inorganic materials 0.000 description 41
- 229910052751 metal Inorganic materials 0.000 description 39
- 239000002184 metal Substances 0.000 description 39
- 239000010949 copper Substances 0.000 description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 34
- 229910052802 copper Inorganic materials 0.000 description 34
- 239000011135 tin Substances 0.000 description 33
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 32
- 229910052718 tin Inorganic materials 0.000 description 32
- 239000004020 conductor Substances 0.000 description 30
- 229910052782 aluminium Inorganic materials 0.000 description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 29
- 239000010931 gold Substances 0.000 description 29
- 238000009713 electroplating Methods 0.000 description 28
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 28
- 229910052737 gold Inorganic materials 0.000 description 28
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 27
- 229910052709 silver Inorganic materials 0.000 description 27
- 239000004332 silver Substances 0.000 description 27
- 238000007772 electroless plating Methods 0.000 description 26
- 229910052759 nickel Inorganic materials 0.000 description 25
- 238000007639 printing Methods 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 23
- 230000006870 function Effects 0.000 description 22
- 238000009413 insulation Methods 0.000 description 22
- 230000003647 oxidation Effects 0.000 description 20
- 238000007254 oxidation reaction Methods 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 19
- 238000005245 sintering Methods 0.000 description 19
- 238000004544 sputter deposition Methods 0.000 description 18
- 238000013461 design Methods 0.000 description 16
- 238000004528 spin coating Methods 0.000 description 16
- LJCFOYOSGPHIOO-UHFFFAOYSA-N antimony pentoxide Chemical compound O=[Sb](=O)O[Sb](=O)=O LJCFOYOSGPHIOO-UHFFFAOYSA-N 0.000 description 14
- 229910000420 cerium oxide Inorganic materials 0.000 description 14
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 14
- 229910052684 Cerium Inorganic materials 0.000 description 13
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 13
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 13
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 13
- 239000000945 filler Substances 0.000 description 12
- 239000011133 lead Substances 0.000 description 12
- 238000005498 polishing Methods 0.000 description 12
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 229920000642 polymer Polymers 0.000 description 11
- 238000012545 processing Methods 0.000 description 11
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- 238000005507 spraying Methods 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 9
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 9
- 229910052787 antimony Inorganic materials 0.000 description 8
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 8
- 239000002131 composite material Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000010276 construction Methods 0.000 description 6
- 229910052735 hafnium Inorganic materials 0.000 description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
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- 238000002955 isolation Methods 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 238000000748 compression moulding Methods 0.000 description 4
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- 229920000647 polyepoxide Polymers 0.000 description 4
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910018487 Ni—Cr Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- -1 polyimine Chemical compound 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
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- 229910052804 chromium Inorganic materials 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 238000010295 mobile communication Methods 0.000 description 1
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- 239000005022 packaging material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
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- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本發明大體上關於半導體元件，且更特別地，關於一種半導體元件以及基於該半導體晶粒調準而形成與互連結構相對固定之固定凸塊下金屬化(UMB)層之方法。The present invention relates generally to semiconductor components and, more particularly, to a semiconductor component and a method of forming a fixed under bump metallization (UMB) layer that is relatively fixed to an interconnect structure based on the alignment of the semiconductor die.
半導體元件常見於現代電子產品中。半導體元件在電性構件之數量及密度上有所變化。分立式半導體元件大體上包含某類型電性構件，例如，發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器及功率式金氧半導體場效電晶體(MOSFET)。整合式半導體元件典型地包含成千上萬個電性構件。整合式半導體元件範例包含微控制器、微處理機、電荷耦合元件(CCD)、太陽能蓄電池及數位微型反射鏡元件(DMD)。Semiconductor components are common in modern electronic products. Semiconductor components vary in the number and density of electrical components. Discrete semiconductor components generally comprise a type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power MOSFET. Integrated semiconductor components typically contain thousands of electrical components. Examples of integrated semiconductor components include microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror elements (DMDs).
半導體元件執行廣泛功能，例如，高速計算、傳輸並接收電磁波訊號、控制電子元件、轉換光線成為電力及產生電視顯示器之視覺投影。半導體元件為見於娛樂、通訊、電力轉換、網路、電腦及消費產品領域中。半導體元件也見於軍事應用、航空、汽車、工業控制及辦公設備中。Semiconductor components perform a wide range of functions, such as high speed computing, transmitting and receiving electromagnetic signals, controlling electronic components, converting light into electricity, and producing visual projections of television displays. Semiconductor components are found in the entertainment, communications, power conversion, networking, computer and consumer products sectors. Semiconductor components are also found in military applications, aerospace, automotive, industrial control and office equipment.
半導體元件利用半導體材料之電特性。半導體材料之原子結構讓它的導電性可受到施加電場或透過摻雜製程來操控。摻雜技術將雜質引入該半導體材料內以操控該半導體元件之導電性。Semiconductor components utilize the electrical properties of semiconductor materials. The atomic structure of a semiconductor material allows its conductivity to be manipulated by the application of an electric field or by a doping process. A doping technique introduces impurities into the semiconductor material to manipulate the conductivity of the semiconductor component.
一半導體元件包含主動及被動電性結構。包含二極體及場效電晶體之主動結構控制電流流動。藉由改變摻雜位準及施加電場或基極電流，該電晶體不是增加就是限制該電流流動。包含電阻器、電容器及電感器之被動結構在執行各種電性功能所需電壓與電流間產生某種關係。該些被動及主動結構被電性連接以執行高速計算和其它有用功能。A semiconductor component includes active and passive electrical structures. An active structure comprising a diode and a field effect transistor controls current flow. By changing the doping level and applying an electric or base current, the transistor does not increase or limit the current flow. Passive structures containing resistors, capacitors, and inductors have a relationship between the voltage and current required to perform various electrical functions. The passive and active structures are electrically connected to perform high speed calculations and other useful functions.
半導體元件大體上為使用二複合製程，也就是前端製程和後端製程來製造之，每一個製程可能涉及數百個步驟。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。每一個晶粒典型地一模一樣且內含電性連接之主動及被動構件所形成之電路。後端製程涉及單粒化來自該已完成晶圓之個別晶粒並構裝該晶粒以提供結構支撐及環境隔離。Semiconductor components are generally fabricated using two composite processes, namely front-end processes and back-end processes, each of which can involve hundreds of steps. The front end process involves forming a plurality of dies on a surface of a semiconductor wafer. Each die typically has the same pattern and contains circuitry formed by electrically connected active and passive components. The back end process involves singulating individual dies from the finished wafer and constructing the dies to provide structural support and environmental isolation.
半導體製程之一目標為製造較小的半導體元件。較小的元件典型地消耗較少電力、具有較高執行效率且可更有效率地被製造。此外，較小的半導體元件具有一較小佔用空間，其可期待提供較小的終端產品。一較小晶粒尺寸可經由改善該前端製程以產生內含較小、較高密度主動和被動構件之晶粒而得。後端製程可經由改善電性連接和構裝材料而產生具有一較小佔用空間之半導體元件構裝。One of the goals of semiconductor manufacturing is to make smaller semiconductor components. Smaller components typically consume less power, have higher execution efficiency, and can be manufactured more efficiently. In addition, smaller semiconductor components have a smaller footprint, which can be expected to provide smaller end products. A smaller grain size can be obtained by improving the front end process to produce grains containing smaller, higher density active and passive components. The backend process can produce a semiconductor component package with a small footprint by improving electrical connections and packaging materials.
在形成晶圓級晶片尺寸構裝(WLCSP)時，常需要在該些構裝內形成頂部及底部互連結構。該頂部及底部互連結構有助於將該些晶圓級晶片尺寸構裝安裝至主機板及其它印刷電路板(PCB)或基板上。經由在該構裝之頂部及底部表面上形成該些互連結構，多個晶圓級晶片尺寸構裝可被放置於彼此上以形成堆疊式構裝而於一小構裝體積內提供複雜功能。該頂部及底部互連結構通常包含導電直通矽晶穿孔(TSV)或導電貫穿導通孔(THV)。為了形成直通矽晶穿孔或導電通孔，一通孔被切割以貫穿該半導體材料或該半導體晶粒周邊區域。該些通孔接著例如透過一電鍍製程之銅沉積作用而被一導電材料填滿。然而，該半導體晶粒在晶粒黏接期間難以調準且在該封膠製程期間會移位，其導致元件失敗及較低的製造良率。When forming wafer level wafer size packages (WLCSP), it is often desirable to form top and bottom interconnect structures within the packages. The top and bottom interconnect structures facilitate the mounting of the wafer level wafers to motherboards and other printed circuit boards (PCBs) or substrates. By forming the interconnect structures on the top and bottom surfaces of the package, a plurality of wafer level wafer size packages can be placed on each other to form a stacked package to provide complex functionality within a small package volume. The top and bottom interconnect structures typically comprise conductive through-silicon vias (TSVs) or conductive through vias (THVs). To form a through-silicon via or a conductive via, a via is cut through the semiconductor material or the peripheral region of the semiconductor die. The vias are then filled with a conductive material, for example, by copper deposition of an electroplating process. However, the semiconductor die is difficult to align during die bonding and can shift during the encapsulation process, which results in component failure and lower manufacturing yield.
現存有在垂直互連結構間進行半導體晶粒安裝和調準而不使該晶粒移位之需求。有鑑於此，在一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一暫時載體、在該暫時載體上形成一第一導電層、及在該暫時載體上形成一凸塊下金屬化層。該凸塊下金屬化層為固定於該第一導電層的相對位置。該方法進一步包含之步驟為在該第一導電層上形成一導電柱、將一半導體晶粒安裝至該凸塊下金屬化層以將該半導體晶粒調準對應至該導電柱並在該半導體晶粒上和該導電柱四周沉積一封膠劑。該凸塊下金屬化層在沉積該封膠劑期間阻止該半導體晶粒移位。該方法進一步包含之步驟為移除該暫時載體、在該封膠劑第一表面上形成一第一互連結構及在與該第一互連結構相對之封膠劑第二表面上形成一第二互連結構。該第一及第二互連結構為透過該導電柱進行電性連接。There is a need for semiconductor die mounting and alignment between vertical interconnect structures without displacing the die. In view of the above, in one embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of providing a temporary carrier, forming a first conductive layer on the temporary carrier, and forming a bump on the temporary carrier. Under the block metallization layer. The under bump metallization layer is at a relative position fixed to the first conductive layer. The method further includes the steps of forming a conductive pillar on the first conductive layer, mounting a semiconductor die to the under bump metallization layer to align the semiconductor die to the conductive pillar and at the semiconductor A glue is deposited on the die and around the conductive pillar. The under bump metallization layer prevents displacement of the semiconductor grains during deposition of the encapsulant. The method further includes the steps of removing the temporary carrier, forming a first interconnect structure on the first surface of the sealant, and forming a first surface on the second surface of the sealant opposite the first interconnect structure Two interconnect structures. The first and second interconnect structures are electrically connected through the conductive pillars.
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一暫時載體、在該暫時載體上形成一第一導電層及在該暫時載體上形成一凸塊下金屬化層。該凸塊下金屬化層固定於該第一導電層的相對位置。該方法進一步包含之步驟為在該第一導電層上形成一導電柱、將一半導體晶粒安裝至該凸塊下金屬化層以將該半導體晶粒調準對應至該導電柱、在該半導體晶粒上和該導電柱四周沉積一封膠劑、移除該暫時載體、在該封膠劑第一表面上形成一第一互連結構及在與該第一互連結構相對之封膠劑第二表面上形成一第二互連結構。該第一及第二互連結構為透過該導電柱進行電性連接。In another embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of providing a temporary carrier, forming a first conductive layer on the temporary carrier, and forming a bump under metallization on the temporary carrier. Floor. The under bump metallization layer is fixed at a relative position of the first conductive layer. The method further includes the steps of forming a conductive pillar on the first conductive layer, mounting a semiconductor die to the under bump metallization layer to align the semiconductor die to the conductive pillar, and the semiconductor Depositing a glue on the die and surrounding the conductive pillar, removing the temporary carrier, forming a first interconnect structure on the first surface of the sealant, and a sealant opposite to the first interconnect structure A second interconnect structure is formed on the second surface. The first and second interconnect structures are electrically connected through the conductive pillars.
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為形成包含可濕潤接觸墊片和固定於該些接觸墊片的相對位置之凸塊下金屬化層之一第一互連結構、在該第一互連結構之可濕潤接觸墊片上形成一導電柱、將一第一半導體構件安裝至該凸塊下金屬化層以將該半導體構件調準對應至該導電柱、在該半導體構件上和該導電柱四周沉積一封膠劑及在與該第一互連結構相對之封膠劑第二表面上形成一第二互連結構。該第一及第二互連結構為透過該導電柱進行電性連接。In another embodiment, the invention is a method of fabricating a semiconductor device, comprising the steps of forming a first under bump metallization layer comprising a wettable contact pad and a relative position fixed to the contact pads. An interconnect structure, a conductive pillar is formed on the wettable contact pad of the first interconnect structure, and a first semiconductor component is mounted to the under bump metallization layer to align the semiconductor component to the conductive pillar Depositing a glue on the semiconductor member and around the conductive pillar and forming a second interconnect structure on the second surface of the sealant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillars.
在另一實施例中，本發明為一種半導體元件，包括一第一導電層和固定於該第一導電層的相對位置之凸塊下金屬化層。一導電柱形成於該第一導電層上。一半導體構件安裝至該導電柱。一半導體構件安裝至該凸塊下金屬化層以將該半導體晶粒調準對應至該導電柱。一封膠劑沉積於該半導體晶粒上和該導電柱四周。一第一互連結構形成於該封膠劑第一表面上。一第二互連結構形成於與該第一互連結構相對之封膠劑第二表面上。該第一及第二互連結構為透過該導電柱進行電性連接。In another embodiment, the invention is a semiconductor device comprising a first conductive layer and an under bump metallization layer affixed to the first conductive layer. A conductive pillar is formed on the first conductive layer. A semiconductor component is mounted to the conductive post. A semiconductor component is mounted to the under bump metallization layer to align the semiconductor die to the conductive pillar. A glue is deposited on the semiconductor die and around the conductive pillar. A first interconnect structure is formed on the first surface of the encapsulant. A second interconnect structure is formed on the second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillars.
本發明參考圖形描述於下列說明之一或更多實施例中，其中類似編號代表相同或類似構件。雖然本發明以最佳模式來描述以達成本發明目的，然而那些熟知此項技術之人士應理解到本發明要涵蓋下列揭示及圖式所支持附上之申請專利範圍及它們等效例所定義之本發明精神及範圍所包含之替代例、修改例、和等效例。The present invention is described in the following description in one or more embodiments, wherein like reference numerals represent the same or the like. While the present invention has been described in its preferred embodiments, the embodiments of the invention are intended to Alternatives, modifications, and equivalents are included in the spirit and scope of the invention.
半導體元件大體上為使用二複合製程：前端製程和後端製程來製造之。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。在該晶圓上之每一個晶粒內含主動及被動電性構件，其為電性連接以形成功能性電性電路。例如電晶體之主動電性構件具有控制電流流動之能力。例如電容器、電感器、電阻器和變壓器之被動電性構件產生用以執行電性電路功能所需之電壓和電流間的關係。Semiconductor components are generally fabricated using a two-composite process: a front end process and a back end process. The front end process involves forming a plurality of dies on a surface of a semiconductor wafer. Each of the dies on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. For example, an active electrical component of a transistor has the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers create the relationship between voltage and current required to perform electrical circuit functions.
被動及主動構件為經由包含摻雜、沉積、微影成像、蝕刻及平坦化之一系列製程而形成於該半導體晶圓表面上。摻雜技術經由例如離子植入或熱擴散類之技術將雜質引入該半導體材料中。該摻雜製程改變主動元件內部半導體材料之導電性，以轉換該半導體材料成為一絕緣體、導體，或動態地改變該半導體材料導電性以回應一電場或基極電流。電晶體內含依需求安排之各種摻雜類型與程度之區域以使該電晶體可依據該電場或基極電流來增進或限制電流流動。The passive and active components are formed on the surface of the semiconductor wafer via a series of processes including doping, deposition, lithography, etching, and planarization. Doping techniques introduce impurities into the semiconductor material via techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material within the active device to convert the semiconductor material into an insulator, a conductor, or dynamically change the conductivity of the semiconductor material in response to an electric or base current. The transistor contains regions of various doping types and degrees as desired to enable the transistor to promote or limit current flow depending on the electric field or base current.
主動及被動構件為由具有不同電特性之材料層所形成。該些材料層可由欲沉積之材料類型所部分決定之各類沉積技術來形成之。例如，薄膜沉積技術可包含化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍及無電鍍各製程。每一層大體上經由圖案化而形成主動構件、被動構件或構件間之電性連接部分。Active and passive components are formed from layers of material having different electrical properties. The layers of material may be formed by various deposition techniques that are determined in part by the type of material to be deposited. For example, thin film deposition techniques may include chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. Each layer forms an active member, a passive member, or an electrically connected portion between the members, substantially via patterning.
該些材料層可使用微影成像技術來圖案化之，其包含將例如光阻劑之感光性材料沉積於欲圖案化之材料層上。使用光將一圖案自一光罩轉印至該光阻劑。該光阻劑圖案中遇到光的部分為使用一溶劑來移除之，以露出下層中欲圖案化的部分。該光阻劑其餘部分被移除，留下一圖案化層。替代性地，一些材料類型為經由直接沉積材料於使用例如無電鍍及電鍍類技術之先前沉積/蝕刻製程所形成之區域或孔隙中而進行圖案化。The layers of material may be patterned using lithographic imaging techniques comprising depositing a photosensitive material such as a photoresist onto a layer of material to be patterned. Light is used to transfer a pattern from a mask to the photoresist. The portion of the photoresist pattern that encounters light is removed using a solvent to expose portions of the underlying layer to be patterned. The remainder of the photoresist is removed leaving a patterned layer. Alternatively, some material types are patterned via direct deposition of materials in regions or voids formed using previous deposition/etch processes such as electroless plating and electroplating techniques.
將一薄膜材料沉積於一現成圖案上可擴大該下層圖案並產生一不均勻平坦表面。一均勻平坦表面被需要以產生較小且更密集封裝之主動及被動構件。平坦化技術可被使用以移除該晶圓表面之材料並產生一均勻平坦表面。平坦化技術涉及以一拋光墊片來拋光該晶圓表面。一研磨材料及腐蝕性化學藥品於拋光期間被添加至該晶圓表面。結合研磨之機械性動作及化學藥品之腐蝕性動作可移除任何不規則拓樸，產生一均勻平坦表面。Depositing a thin film material onto a ready-made pattern expands the underlying pattern and creates a non-uniform flat surface. A uniform flat surface is needed to create a smaller and denser package of active and passive components. A planarization technique can be used to remove the material of the wafer surface and create a uniform flat surface. The planarization technique involves polishing the wafer surface with a polishing pad. An abrasive material and corrosive chemicals are added to the wafer surface during polishing. Combined with the mechanical action of the grinding and the corrosive action of the chemical, any irregular topography can be removed, resulting in a uniform flat surface.
後端製程指切割或單粒化該已完成晶圓成為該個別晶粒並接著構裝該晶粒以提供結構支撐及環境隔離。為了單粒化該晶粒，將該晶圓沿著所謂割鋸道或劃線之晶圓無功能區域做記號並切開。使用一雷射切割工具或鋸片切割該晶圓成晶粒。單粒化後，個別晶粒被安裝至包含接腳或接觸墊片以與其它系統構件互相連接之構裝基板上。該半導體晶粒上所形成之接觸墊片接著被連接至該構裝內之接觸墊片。該電性連接可搭配錫球凸塊、短柱凸塊、導電膏或接線來進行之。一封膠劑或其它封膠材料被沉積在該構裝上以提供實體支撐及電性隔離。該已完成構裝接著被***一電性系統中，且該半導體元件功能對於其它系統構件是有用的。The back end process refers to cutting or singulating the finished wafer into the individual dies and then constructing the dies to provide structural support and environmental isolation. In order to singulate the grain, the wafer is marked and cut along the non-functional area of the so-called cut saw or scribe line. The wafer is cut into grains using a laser cutting tool or saw blade. After singulation, individual dies are mounted to a mounting substrate that includes pins or contact pads to interconnect with other system components. Contact pads formed on the semiconductor die are then connected to contact pads in the package. The electrical connection can be made with solder ball bumps, short stud bumps, conductive paste or wiring. A glue or other sealant material is deposited on the structure to provide physical support and electrical isolation. The completed assembly is then inserted into an electrical system and the semiconductor component functionality is useful for other system components.
圖1說明具有在表面上安裝有複數個半導體構裝之晶片載體基板或印刷電路板52之電子元件50。電子元件50可具有某半導體構裝類型或多種半導體構裝類型，視應用而定。基於說明目的，不同半導體構裝類型示於圖1中。1 illustrates an electronic component 50 having a wafer carrier substrate or printed circuit board 52 having a plurality of semiconductor packages mounted thereon. Electronic component 50 can be of a certain semiconductor construction type or a plurality of semiconductor fabrication types, depending on the application. Different semiconductor package types are shown in Figure 1 for illustrative purposes.
電子元件50可為使用該些半導體構裝來執行一或更多電性功能之獨立系統。替代性地，電子元件50可為一較大型系統之子構件。例如，電子元件50可為能夠***一電腦內之繪圖卡、網路界面卡或其它訊號處理卡。該半導體構裝可包含微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散元件或其它半導體晶粒或電性構件。Electronic component 50 can be a stand-alone system that uses the semiconductor structures to perform one or more electrical functions. Alternatively, electronic component 50 can be a subcomponent of a larger system. For example, electronic component 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an application specific integrated circuit (ASIC), logic, analog circuits, radio frequency circuits, discrete components, or other semiconductor die or electrical components.
在圖1中，為了安裝在該印刷電路板上之半導體構裝之結構支撐及電性互連，印刷電路板52提供一總基板。傳導訊號軌跡線54使用蒸鍍製程、電鍍製程、無電鍍製程、網印製程或其它合適金屬沉積製程來形成於印刷電路板52之某一表面上或多層內。訊號軌跡線54提供該些半導體構裝、安裝構件及其它外部系統構件中每一個間之電性通訊。軌跡線54也提供至該些半導體構裝中每一個之電力及接地連接。In FIG. 1, a printed circuit board 52 provides a total substrate for structural support and electrical interconnection of semiconductor structures mounted on the printed circuit board. The conductive signal traces 54 are formed on one surface or multiple layers of the printed circuit board 52 using an evaporation process, an electroplating process, an electroless plating process, a screen printing process, or other suitable metal deposition process. Signal trace 54 provides electrical communication between each of the semiconductor components, mounting components, and other external system components. Trace line 54 also provides power and ground connections to each of the semiconductor packages.
在一些實施例中，一半導體元件具有二構裝級。第一級構裝為用以機械性和電性地黏結該半導體晶粒至一中介載體之技術。第二級構裝涉及機械性和電性地黏結該中介載體至該印刷電路板。在其它實施例中，一半導體元件可以只具有該第一級構裝，其中，該晶粒經由機械性和電性方式直接安裝至該印刷電路板。In some embodiments, a semiconductor component has a two-construction stage. The first stage of fabrication is a technique for mechanically and electrically bonding the semiconductor die to an intermediate carrier. The second level of assembly involves mechanically and electrically bonding the intermediate carrier to the printed circuit board. In other embodiments, a semiconductor component can have only the first level of construction, wherein the die is mounted directly to the printed circuit board via mechanical and electrical means.
基於說明目的，包含打線接合構裝56及覆晶構裝58之一些第一級構裝類型被示於印刷電路板52上。此外，包含錫球陣列(BGA)構裝60、凸塊晶片載體(BCC)62、雙列式構裝(DIP)、平面陣列(LGA)構裝66、多晶片模組(MCM)構裝68、四邊扁平無引腳構裝(QFN)70及四邊扁平構裝72之一些第二級構裝類型顯示安裝於印刷電路板52上。依據該些系統需求，搭配第一及第二級構裝型式之任意結合以及其它電子構件所建構之半導體構裝之任意結合可被連接至印刷電路板52。在一些實施例中，電子元件50包含一單黏結半導體構裝，而其它實施例需要多個連接構裝。經由結合單一基板上之一或更多半導體構裝，製造商可整合預製構件至電子元件及系統中。因為該些半導體構裝包含複雜功能，故可使用較便宜構件及一現代化製程來製造電子元件。所產元件較不可能失敗，且對於消費者而言製造成本較低而使所產元件較便宜。Some first stage construction types including wire bond assembly 56 and flip chip assembly 58 are shown on printed circuit board 52 for illustrative purposes. In addition, a solder ball array (BGA) package 60, a bump wafer carrier (BCC) 62, a dual array package (DIP), a planar array (LGA) package 66, and a multi-chip module (MCM) package 68 are included. Some of the second stage configuration types of the four-sided flat leadless package (QFN) 70 and the four-sided flat package 72 are mounted on the printed circuit board 52. Any combination of any combination of the first and second stage configurations and the semiconductor components constructed by other electronic components can be coupled to the printed circuit board 52, depending on the requirements of the system. In some embodiments, electronic component 50 includes a single bonded semiconductor package, while other embodiments require multiple connection configurations. By incorporating one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic components and systems. Because these semiconductor packages contain complex functions, electronic components can be fabricated using less expensive components and a modern process. The components produced are less likely to fail, and the manufacturing costs are lower for the consumer and the components produced are less expensive.
圖2a-2c顯示示範性半導體構裝。圖2a說明安裝在印刷電路板52上之雙列式構裝64之進一部細部。半導體晶粒74包含一內含類比或數位電路之作用區域，該些電路被配置為形成於該晶粒內並根據該晶粒之電性設計進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器和形成於該半導體晶粒74之作用區域內之其它電路構件。接觸墊片76為例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)中之一或更多導電材料層，且被電性連接至形成於半導體晶粒74內之電路構件。在組合雙列式構裝64期間，半導體晶粒74為使用一金矽合金層或例如熱環氧樹脂類之黏接材料來安裝至一中介載體78。該構裝主體包含例如聚合物或陶瓷類之絕緣構裝材料。導線80及接線82提供半導體晶粒74及印刷電路板52間之電性互連。封膠劑84被沉積在該構裝上以阻止濕氣和微粒進入該構裝並污染晶粒74或接線82而提供環境保護。Figures 2a-2c show an exemplary semiconductor package. FIG. 2a illustrates a further detail of the dual array assembly 64 mounted on the printed circuit board 52. The semiconductor die 74 includes an active region containing an analog or digital circuit. The circuits are configured to be formed in the die and electrically interconnected according to the electrical design of the die. Layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed within the active region of the semiconductor die 74. The contact pad 76 is, for example, one or more layers of conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected To the circuit components formed in the semiconductor die 74. During the combined dual array configuration 64, the semiconductor die 74 is mounted to an interposer carrier 78 using a layer of gold alloy or a bonding material such as a thermal epoxy. The body of the package comprises an insulating material such as a polymer or ceramic. Conductor 80 and wiring 82 provide electrical interconnection between semiconductor die 74 and printed circuit board 52. A sealant 84 is deposited on the structure to prevent moisture and particulates from entering the structure and contaminating the die 74 or the wires 82 to provide environmental protection.
圖2b說明安裝於印刷電路板52上之凸塊晶片載體62之進一步細部。半導體晶粒88為使用一底部填膠或環氧樹脂黏接材料92來安裝於載體90上。接線94提供接觸墊片96及98間之第一級封裝互連。封膠化合物或封膠劑100被沉積於半導體晶粒88及接線94上以提供該元件實體支撐和電性隔離。接觸墊片102使用例如電鍍或無電鍍之合適金屬沉積製程來形成於印刷電路板52之表面上以阻止氧化作用。接觸墊片102被電性連接至印刷電路板52之傳導訊號軌跡線54。焊料凸塊沉積於凸塊晶片載體62之接觸墊片98及印刷電路板52之接觸墊片102之間並被回焊以形成凸塊104，其於凸塊晶片載體62及印刷電路板52之間形成一機械和電性連接。Figure 2b illustrates a further detail of the bump wafer carrier 62 mounted on the printed circuit board 52. The semiconductor die 88 is mounted to the carrier 90 using an underfill or epoxy bonding material 92. Wiring 94 provides a first level package interconnection between contact pads 96 and 98. A sealant compound or sealant 100 is deposited over the semiconductor die 88 and the wiring 94 to provide physical support and electrical isolation of the component. Contact pads 102 are formed on the surface of printed circuit board 52 using a suitable metal deposition process such as electroplating or electroless plating to prevent oxidation. Contact pad 102 is electrically coupled to conductive signal trace 54 of printed circuit board 52. The solder bumps are deposited between the contact pads 98 of the bump wafer carrier 62 and the contact pads 102 of the printed circuit board 52 and are soldered back to form bumps 104 on the bump wafer carrier 62 and the printed circuit board 52. A mechanical and electrical connection is formed.
在圖2c中，半導體晶粒58為面向下安裝至具有一覆晶式第一級構裝之中介載體106。半導體晶粒58之作用區域108包含根據該晶粒電性設計所形成做為主動元件、被動元件、導電層和介電層而配置之類比或數位電路。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器及作用區域108內之其它電路構件。半導體晶粒58為透過焊料凸塊或圓球110電性及機械性地連接至載體106。In Figure 2c, the semiconductor die 58 is mounted face down to the interposer carrier 106 having a flip-chip first stage configuration. The active region 108 of the semiconductor die 58 includes an analog or digital circuit configured as an active device, a passive component, a conductive layer, and a dielectric layer in accordance with the die electrical design. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within the active region 108. The semiconductor die 58 is electrically and mechanically coupled to the carrier 106 through solder bumps or spheres 110.
錫球陣列構裝60使用焊料凸塊或圓球112以電性及機械性地連接至具有一錫球陣列式第二級構裝之印刷電路板52。半導體晶粒58透過焊料凸塊110、訊號線114和焊料凸塊112來電性連接至印刷電路板52之傳導訊號軌跡線54。一封膠化合物或封膠劑116被沉積於半導體晶粒58及載體106上以提供該元件實體支撐和電性隔離。該覆晶半導體元件提供自半導體晶粒58上之主動元件至印刷電路板52上之傳導軌跡線之一短導電路徑，用以減少訊號傳送距離、降低電容、並改進整體電路執行效率。在另一實施例中，可不用中介載體106而使用覆晶式第一級構裝方式將該半導體晶粒58機械性及電性地直接連接至印刷電路板52。The solder ball array assembly 60 is electrically and mechanically connected to the printed circuit board 52 having a solder ball array second stage configuration using solder bumps or balls 112. The semiconductor die 58 is electrically coupled to the conductive signal traces 54 of the printed circuit board 52 through the solder bumps 110, the signal lines 114, and the solder bumps 112. A glue compound or sealant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation of the component. The flip-chip semiconductor component provides a short conductive path from the active component on the semiconductor die 58 to the conductive traces on the printed circuit board 52 for reducing signal transfer distance, reducing capacitance, and improving overall circuit execution efficiency. In another embodiment, the semiconductor die 58 can be mechanically and electrically connected directly to the printed circuit board 52 using a flip-chip first stage configuration without the interposer carrier 106.
圖3a-3h說明一種形成具有導電柱和基於該半導體晶粒調準而與互連結構相對固定之凸塊下金屬化(UMB)層之垂直互連結構之方法。在圖3a中，一暫時或犧牲基板或載體120包含例如矽、聚合物、聚合物複合材料、金屬薄片、陶瓷、玻璃、玻璃環氧化物、氧化鈹、卷帶或用於結構支撐之其它合適低成本硬式材料之底材。一選擇性晶種層122可形成於載體120上以供後續電鍍製程。一導電層124使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於載體120上。導電層124可為鋁、銅、錫、鎳、金、銀、鎢、多晶矽或其它合適導電材料中其中一層或更多層。導電層124包含用於稍後形成導電柱之可濕潤接觸墊片。在一實施例中，導電層124之可濕潤接觸墊片為預先電鍍於載體120上。3a-3h illustrate a method of forming a vertical interconnect structure having a conductive pillar and an under bump metallization (UMB) layer that is relatively fixed to the interconnect structure based on the semiconductor die alignment. In Figure 3a, a temporary or sacrificial substrate or carrier 120 comprises, for example, tantalum, a polymer, a polymer composite, a foil, a ceramic, a glass, a glass epoxy, a tantalum oxide, a tape or other suitable structure for structural support. Substrate for low cost hard materials. A selective seed layer 122 can be formed on the carrier 120 for subsequent electroplating processes. A conductive layer 124 is patterned on the carrier 120 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 124 can be one or more of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. Conductive layer 124 includes a wettable contact pad for later forming a conductive post. In one embodiment, the wettable contact pads of conductive layer 124 are pre-plated onto carrier 120.
一導電層126使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於晶種層122上。導電層126可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層126與導電層124共平面。導電層126為一固定於導電層124的相對位置之凸塊下金屬化層。凸塊下金屬化層126可為具有黏接層、阻障層及晶種或濕潤層之多金屬堆疊。該黏接層可為鈦、氮化鈦(TiN)、鈦鎢(TiW)、鋁或鉻(Cr)。該阻障層為形成於該黏接層上且可由鎳、鎳釩(NiV)、鉑(Pt)、鈀(Pd)、鈦鎢或鉻銅(CrCu)所構成。該阻障層禁止銅擴散進入該晶粒作用區域內。該晶種層可為銅、鎳、鎳釩、金或鋁。該晶種層形成於該阻障層上。凸塊下金屬化層126提供一低電阻互連以及對焊料擴散和提供焊料濕潤能力之晶種層之阻障。A conductive layer 126 is patterned on the seed layer 122 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 126 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. Conductive layer 126 is coplanar with conductive layer 124. The conductive layer 126 is an under bump metallization layer fixed at a relative position of the conductive layer 124. The under bump metallization layer 126 can be a multi-metal stack having an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer can be titanium, titanium nitride (TiN), titanium tungsten (TiW), aluminum or chromium (Cr). The barrier layer is formed on the adhesive layer and may be composed of nickel, nickel vanadium (NiV), platinum (Pt), palladium (Pd), titanium tungsten or chromium copper (CrCu). The barrier layer inhibits diffusion of copper into the grain active region. The seed layer can be copper, nickel, nickel vanadium, gold or aluminum. The seed layer is formed on the barrier layer. The under bump metallization layer 126 provides a low resistance interconnect and a barrier to the solder diffusion and the seed layer providing solder wetting capability.
在圖3b中，複數個導電柱或杆128形成於導電層124之可濕潤接觸墊片上。在一實施例中，導電柱128為藉由將一或更多光阻層沉積於晶種層122或載體120上而形成。導電層124上的部分光阻層為經由一蝕刻顯影製程而被露出並移除。導電材料使用一選擇性電鍍製程來沉積於該光阻層之移除部分內。該光阻層被剝除而留下各個導電柱128。導電柱128可為銅、鋁、鎢(W)、金、焊錫或其它合適導電材料。導電柱128具有2-120微米(μm)範圍之高度。在另一實施例中，形成之導電柱128可為短柱凸塊或堆疊凸塊。在任何例子中，導電柱128具有以焊料或內含銅、銀、鉍或錫之介金屬化合物(IMC)所產生之一至凸塊下金屬化層126之堅固又緊密金屬至金屬黏結。In Figure 3b, a plurality of conductive posts or rods 128 are formed on the wettable contact pads of conductive layer 124. In one embodiment, the conductive pillars 128 are formed by depositing one or more photoresist layers on the seed layer 122 or the carrier 120. A portion of the photoresist layer on the conductive layer 124 is exposed and removed via an etch developing process. The conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped leaving the respective conductive pillars 128. Conductive post 128 can be copper, aluminum, tungsten (W), gold, solder, or other suitable electrically conductive material. The conductive pillars 128 have a height in the range of 2 to 120 micrometers (μm). In another embodiment, the formed conductive pillars 128 can be short stud bumps or stacked bumps. In any example, the conductive pillars 128 have a strong and tight metal-to-metal bond formed by solder or one of the intermetallic compound layers 126 produced by the intermetallic compound (IMC) containing copper, silver, antimony or tin.
在圖3c中，複數個半導體晶粒或構件130為以金屬凸塊134朝下定位在載體120上方之覆晶安排方式來安裝至凸塊下金屬化層126。半導體晶粒130包含一內含類比或數位電路之作用區域136，該些電路為配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用表面126內之其它電路構件以配置例如數位訊號處理器(DSP)、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。半導體晶粒122也可包含用於射頻訊號處理之整合被動元件，例如電感器、電容器和電阻器。在另一實施例中，一分立式半導體構件可被安裝至載體120上。In FIG. 3c, a plurality of semiconductor dies or members 130 are mounted to the under bump metallization layer 126 in a flip chip arrangement in which metal bumps 134 are positioned downwardly over the carrier 120. The semiconductor die 130 includes an active region 136 including an analog or digital circuit. The circuits are active components and passively configured to be electrically formed in the die and electrically interconnected according to the electrical design and function of the die. Element, conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 126 to configure, for example, a digital signal processor (DSP), special purpose integrated circuit, memory, or other signal processing. The fundamental frequency analog circuit or digital circuit of the circuit. Semiconductor die 122 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors. In another embodiment, a discrete semiconductor component can be mounted to the carrier 120.
凸塊下金屬化層126固定於導電層124的相對位置。導電柱128安裝在半導體晶粒130四周之導電層124上。據此，凸塊下金屬化層126固定於導電柱128的相對位置。藉由配對金屬凸塊134與凸塊下金屬化層126，半導體晶粒130自我調準至導電柱128。The under bump metallization layer 126 is fixed to the opposite position of the conductive layer 124. Conductive posts 128 are mounted on conductive layer 124 around semiconductor die 130. Accordingly, the under bump metallization layer 126 is fixed to the opposite position of the conductive pillars 128. The semiconductor die 130 self-aligns to the conductive pillars 128 by mating the metal bumps 134 with the under bump metallization layer 126.
第3d圖顯示使用一錫膏印刷、壓縮成型、轉注成型、液體封膠成型、真空疊合或其它合適塗抹器來沉積於半導體晶粒130和導電柱128上之封膠劑或封膠化合物138。封膠劑138可為聚合物複合材料，例如，具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酯或具有正確填充劑之聚合物。封膠劑138為無導電性且在環境上保護該半導體元件隔離外部構件及污染。利用牢牢安裝至固定凸塊下金屬化層126之半導體晶粒130之金屬凸塊134，該晶粒在該封膠製程期間為對準著導電柱128並未移位。Figure 3d shows the encapsulant or sealant compound 138 deposited on the semiconductor die 130 and the conductive pillars 128 using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. . The sealant 138 can be a polymer composite such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a correct filler. The encapsulant 138 is non-conductive and environmentally protects the semiconductor component from external components and contamination. The metal bumps 134 of the semiconductor die 130 that are firmly mounted to the under bump metallization layer 126 are not displaced during alignment of the conductive pillars 128 during the encapsulation process.
在圖3e中，封膠劑138進行研磨或電漿蝕刻以平坦化該表面而形成一頂側增層式互連結構。在一實施例中，研磨器139露出導電柱128頂部表面及半導體晶粒130背部表面。替代性地，研磨器139露出導電柱128頂部表面並保留內嵌於封膠劑138中之半導體晶粒130。In Figure 3e, encapsulant 138 is ground or plasma etched to planarize the surface to form a top side build-up interconnect structure. In one embodiment, the grinder 139 exposes the top surface of the conductive pillars 128 and the back surface of the semiconductor die 130. Alternatively, the grinder 139 exposes the top surface of the conductive pillar 128 and retains the semiconductor die 130 embedded in the encapsulant 138.
在圖3f中，一頂側增層式互連結構140形成於導電柱128、封膠劑138第一表面和半導體晶粒130背部表面上。一絕緣或保護層142使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程形成之。該保護層142可為二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除部分保護層142而露出導電柱128。In FIG. 3f, a top side build-up interconnect structure 140 is formed over the conductive pillars 128, the first surface of the encapsulant 138, and the back surface of the semiconductor die 130. An insulating or protective layer 142 is formed using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 142 may be cerium oxide (SiO 2 ), cerium nitride (Si 3 N 4 ), cerium oxynitride (SiON), tantalum pentoxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ). Or one or more of the other materials having similar insulating and structural properties. The portion of the protective layer 142 is removed by an etching process to expose the conductive pillars 128.
一導電層144為使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於保護層142及導電柱128上。導電層144可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。一部分導電層144為電性連接至導電柱128。導電層144中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A conductive layer 144 is formed over the protective layer 142 and the conductive pillars 128 by patterning using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 144 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 144 is electrically connected to the conductive pillars 128. Other portions of conductive layer 144 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一絕緣或保護層146使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於保護層142及導電層144上。該保護層146可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除部分保護層146而露出導電層144。An insulating or protective layer 146 is formed over the protective layer 142 and the conductive layer 144 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering, or thermal oxidation processes. The protective layer 146 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. The portion of the protective layer 146 is removed by an etching process to expose the conductive layer 144.
在圖3g中，載體120經由化學濕式蝕刻、電漿乾式蝕刻、機械脫落、化學機械拋光、機械研磨、熱烘烤、雷射掃描或濕式剝離移除之。在載體120移除後，封膠劑138提供半導體晶粒130結構支撐。載體120移除後接著露出導電層124及凸塊下金屬化層126。In Figure 3g, the carrier 120 is removed via chemical wet etching, plasma dry etching, mechanical shedding, chemical mechanical polishing, mechanical polishing, thermal baking, laser scanning, or wet stripping. After the carrier 120 is removed, the encapsulant 138 provides structural support for the semiconductor die 130. After the carrier 120 is removed, the conductive layer 124 and the under bump metallization layer 126 are exposed.
在圖3h中，一底側增層式互連結構150形成於與頂側增層式互連結構140相對之導電柱128和封膠劑第二表面上。一導電層152使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於導電層124及凸塊下金屬化層126上。導電層152可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。部分導電層152為電性連接至導電柱128、導電層124及凸塊下金屬化層126。導電層152中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。In FIG. 3h, a bottom side build-up interconnect structure 150 is formed on the conductive pillars 128 and the sealant second surface opposite the top side build-up interconnect structure 140. A conductive layer 152 is patterned over the conductive layer 124 and the under bump metallization layer 126 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 152 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The portion of the conductive layer 152 is electrically connected to the conductive pillar 128, the conductive layer 124, and the under bump metallization layer 126. Other portions of conductive layer 152 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一絕緣或保護層154使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於導電層152和封膠劑138第二表面上。該保護層154可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除部分保護層154而露出導電層152。An insulating or protective layer 154 is formed on the second surface of the conductive layer 152 and the encapsulant 138 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 154 can be one or more of ceria, tantalum nitride, hafnium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. The portion of the protective layer 154 is removed by an etching process to expose the conductive layer 152.
一導電凸塊材料為使用蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於導電層152上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至導電層152。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊156。在一些應用中，凸塊156被回焊一第二時間以改進對導電層152之電性接觸。該些凸塊也可被壓縮黏結至導電層152。凸塊156代表可被形成於導電層152上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。A conductive bump material is deposited on the conductive layer 152 using an evaporation, electroplating, electroless plating, solder ball dropping or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, lead, antimony, copper, solder, and combinations thereof, plus a selective flux material. For example, the bump material can be eutectic tin/lead, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 152 using a suitable bonding or bonding process. In an embodiment, the bump material is reflowed to form a sphere or bump 156 by heating the material beyond its melting point. In some applications, bumps 156 are reflowed for a second time to improve electrical contact to conductive layer 152. The bumps can also be compression bonded to the conductive layer 152. Bumps 156 represent some type of interconnect structure that can be formed on conductive layer 152. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects.
該半導體晶粒130利用鋸片或雷射切割工具164進行單粒化而成為個別半導體元件160。單粒化後，該些個別半導體元件160可如圖4所示地進行堆疊。導電柱128在頂側增層式互連層140及底側增層式互連層150之間提供垂直z方向互連。導電層144為透過導電柱128電性連接至每一個半導體元件160之導電層152及金屬凸塊134。The semiconductor die 130 is singulated by a saw blade or a laser cutting tool 164 to form individual semiconductor elements 160. After singulation, the individual semiconductor components 160 can be stacked as shown in FIG. Conductive pillars 128 provide vertical z-directional interconnects between topside build-up interconnect layer 140 and bottomside build-up interconnect layer 150. The conductive layer 144 is electrically connected to the conductive layer 152 and the metal bumps 134 of each of the semiconductor elements 160 through the conductive pillars 128.
圖5具有形成於該頂側互連結構中之多個整合被動元件之垂直互連結構。類似於圖3a-3h所述方法，半導體元件162使用具有一選擇性晶種層之犧牲或暫時基板或載體。一導電層164使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於該載體上。導電層164可為鋁、銅、錫、鎳、金、銀、鎢、多晶矽或其它合適導電材料中其中一層或更多層。導電層164包含用於稍後形成導電柱之可濕潤接觸墊片。Figure 5 has a vertical interconnect structure of a plurality of integrated passive components formed in the topside interconnect structure. Similar to the method described in Figures 3a-3h, the semiconductor component 162 uses a sacrificial or temporary substrate or carrier having a selective seed layer. A conductive layer 164 is patterned on the carrier using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 164 can be one or more of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. Conductive layer 164 includes a wettable contact pad for later forming a conductive post.
一導電層166使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於絯晶種層或載體上。導電層166可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層166為與導電層164共平面。導電層166為一固定於導電層164的相對位置之凸塊下金屬化層。A conductive layer 166 is patterned on the seed layer or carrier using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 166 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. Conductive layer 166 is coplanar with conductive layer 164. The conductive layer 166 is an under bump metallization layer fixed at a relative position of the conductive layer 164.
複數個導電柱或杆168形成於導電層164之可濕潤接觸墊片上。在一實施例中，導電柱168藉由將一或更多光阻層沉積於晶種層或載體上而形成。導電層164上的部分光阻層為經由一蝕刻顯影製程而被露出並移除。導電材料使用一選擇性電鍍製程來沉積於該光阻層之移除部分內。該光阻層被剝除而留下各個導電柱168。導電柱168可為銅、鋁、鎢、金、焊錫或其它合適導電材料。導電柱168具有2-120微米範圍之高度。在另一實施例中，形成之導電柱168可為短柱凸塊或堆疊凸塊。在任何例子中，導電柱168具有以焊料或內含銅、銀、鉍或錫之介金屬化合物所產生之一至凸塊下金屬化層166之堅固又緊密金屬至金屬黏結。A plurality of conductive posts or rods 168 are formed on the wettable contact pads of the conductive layer 164. In one embodiment, the conductive pillars 168 are formed by depositing one or more photoresist layers on a seed layer or carrier. A portion of the photoresist layer on conductive layer 164 is exposed and removed via an etch developing process. The conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped leaving the respective conductive pillars 168. Conductive post 168 can be copper, aluminum, tungsten, gold, solder, or other suitable electrically conductive material. Conductive post 168 has a height in the range of 2-120 microns. In another embodiment, the formed conductive pillars 168 can be short stud bumps or stacked bumps. In any example, the conductive pillars 168 have a strong and tight metal-to-metal bond with one of the solder or a metal-containing compound containing copper, silver, antimony or tin to the under bump metallization layer 166.
複數個半導體晶粒或構件170為以金屬凸塊174朝下定位在該載體上方之覆晶安排方式來安裝至凸塊下金屬化層166。半導體晶粒170包含一內含類比或數位電路之作用區域176，該些電路配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用表面176內之其它電路構件以配置例如數位訊號處理器、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。半導體晶粒170也可包含用於射頻訊號處理之整合被動元件，例如電感器、電容器和電阻器。A plurality of semiconductor dies or members 170 are mounted to the under bump metallization layer 166 in a flip chip arrangement in which the metal bumps 174 are positioned downwardly over the carrier. The semiconductor die 170 includes an active region 176 having an analog or digital circuit configured to be formed in the die and electrically interconnected according to the electrical design and function of the die. , conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 176 to configure, for example, a digital signal processor, special purpose integrated circuit, memory, or other signal processing circuit. Frequency analog circuit or digital circuit. Semiconductor die 170 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors.
凸塊下金屬化層166固定於導電層164的相對位置。導電柱168安裝在半導體晶粒170四周之導電層164上。據此，凸塊下金屬化層166固定於導電柱168的相對位置。藉由配對金屬凸塊174與凸塊下金屬化層166，半導體晶粒170自我調準至導電柱168。The under bump metallization layer 166 is fixed to the opposite position of the conductive layer 164. Conductive posts 168 are mounted on conductive layer 164 around semiconductor die 170. Accordingly, the under bump metallization layer 166 is fixed to the opposite position of the conductive pillars 168. The semiconductor die 170 self-aligns to the conductive pillars 168 by pairing the metal bumps 174 with the under bump metallization layer 166.
一封膠劑或封膠化合物178使用一錫膏印刷、壓縮成型、轉注成型、液體封膠成型、真空疊合或其它合適塗抹器來沉積於半導體晶粒170和導電柱168上。封膠劑178可為聚合物複合材料，例如，具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酯或具有正確填充劑之聚合物。封膠劑178為無導電性且在環境上保護該半導體元件隔離外部構件及污染。利用牢牢安裝至固定凸塊下金屬化層166之半導體晶粒170之金屬凸塊174，該晶粒在該封膠製程期間對準著導電柱168並未移位。A glue or sealant compound 178 is deposited onto the semiconductor die 170 and the conductive posts 168 using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. The sealant 178 can be a polymer composite such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a correct filler. The sealant 178 is non-conductive and environmentally protects the semiconductor component from external components and contamination. The metal bumps 174, which are firmly mounted to the semiconductor die 170 of the under bump metallization layer 166, are not displaced during alignment of the conductive pillars 168 during the encapsulation process.
該封膠劑178進行研磨或電漿蝕刻以平坦化該表面而形成一頂側增層式互連結構。該研磨操作露出導電柱168頂部表面及半導體晶粒170背部表面。該頂側增層式互連結構180形成於導電柱168、封膠劑178第一表面和半導體晶粒170背部表面上。一絕緣或保護層182使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程形成之。該保護層182可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除部分保護層182而露出導電柱168。The encapsulant 178 is ground or plasma etched to planarize the surface to form a top side build-up interconnect structure. The polishing operation exposes the top surface of the conductive pillar 168 and the back surface of the semiconductor die 170. The top side build-up interconnect structure 180 is formed on the conductive pillars 168, the first surface of the sealant 178, and the back surface of the semiconductor die 170. An insulating or protective layer 182 is formed using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 182 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. The portion of the protective layer 182 is removed by an etching process to expose the conductive pillars 168.
一導電層184使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於保護層182及導電柱168上。導電層184可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。一部分導電層184為電性連接至導電柱168。導電層184中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A conductive layer 184 is patterned on the protective layer 182 and the conductive pillars 168 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 184 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 184 is electrically connected to the conductive pillars 168. Other portions of conductive layer 184 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一電阻層186a-186b為使用物理氣相沉積或化學氣相沉積來分別圖案化並沉積於導電層184和絕緣層182上。電阻層186為TaxSiy或其它金屬矽化物、氮化鉭、鎳鉻、鈦、氮化鈦、鈦鎢或具有5至100歐姆/平方電阻率之摻雜多晶矽。一絕緣層188使用物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程進行圖案化來形成於導電層186a上。該絕緣層188可為氮化矽、二氧化矽、氮氧化矽、五氧化二鉭、氧化鋅、氧化鋯、氧化鋁、聚醯亞胺、苯環丁烯、聚苯噁唑或其它合適介電材料中其中一層或更多層。電阻層186及絕緣層188可以相同遮罩形成並同時進行蝕刻。替代性地，電阻層186及絕緣層188可以不同遮罩進行圖案化及蝕刻。A resistive layer 186a-186b is separately patterned and deposited on conductive layer 184 and insulating layer 182 using physical vapor deposition or chemical vapor deposition. The resistive layer 186 is Ta x Si y or other metal germanide, tantalum nitride, nickel chromium, titanium, titanium nitride, titanium tungsten or doped polysilicon having a resistivity of 5 to 100 ohms/square. An insulating layer 188 is patterned on the conductive layer 186a using physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation processes. The insulating layer 188 may be tantalum nitride, hafnium oxide, hafnium oxynitride, tantalum pentoxide, zinc oxide, zirconium oxide, aluminum oxide, polyimine, benzocyclobutene, polybenzoxazole or other suitable medium. One or more layers of the electrical material. The resistive layer 186 and the insulating layer 188 can be formed in the same mask and etched simultaneously. Alternatively, the resistive layer 186 and the insulating layer 188 can be patterned and etched with different masks.
一絕緣或保護層190使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於保護層182、導電層184、電阻層186及絕緣層188上。該保護層190可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。部分保護層190被移除而露出導電層184、電阻層186及絕緣層188。An insulating or protective layer 190 is formed over the protective layer 182, the conductive layer 184, the resistive layer 186, and the insulating layer 188 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 190 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, antimony pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 190 is removed to expose the conductive layer 184, the resistive layer 186, and the insulating layer 188.
一導電層192使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化並沉積於保護層190、導電層184、電阻層186及絕緣層188上以形成個別部分或區段以供進一步互連性。導電層192中之個別部分可依據該個別半導體晶粒之連接性而為共電性或電性隔離。導電層192可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。A conductive layer 192 is patterned and deposited on the protective layer 190, the conductive layer 184, the resistive layer 186, and the insulating layer 188 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Upper to form individual sections or sections for further interconnectivity. Individual portions of conductive layer 192 may be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. Conductive layer 192 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.
一絕緣或保護層194使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層192和保護層190上。該保護層194可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。一部分保護層194被移除而露出導電層192。An insulating or protective layer 194 is formed on the conductive layer 192 and the protective layer 190 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 194 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, antimony pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 194 is removed to expose the conductive layer 192.
增層式互連結構180中所述結構構成一或更多被動電路構件或整合被動元件。在一實施例中，導電層184、電阻層186a、絕緣層188及導電層192為一金屬層-絕緣層-金屬層(MIM)電容器。電阻層186b為該被動電路中之電阻器構件。導電層192中之個別區段在平面視野上可被捲繞或盤繞以產生或展示想要之電感器特性。The structure described in the build-up interconnect structure 180 constitutes one or more passive circuit components or integrated passive components. In one embodiment, the conductive layer 184, the resistive layer 186a, the insulating layer 188, and the conductive layer 192 are a metal-insulator-metal layer (MIM) capacitor. The resistive layer 186b is a resistor member in the passive circuit. Individual segments of conductive layer 192 can be wound or coiled in a planar field of view to create or exhibit desired inductor characteristics.
該整合被動元件結構提供例如共振器、高通濾波器、低通濾波器、帶通濾波器、對稱性高品質因數共振變壓器、匹配網路及調諧電容器般之高頻應用所需之電性特徵曲線。該些整合被動元件可充當前端無線射頻構件使用，其可被定位在該天線及收發器之間。該電感器可為一以高達100千兆赫操作之高品質因數平衡-不平衡變換器、變壓器或線圈。在一些應用中，多個平衡-不平衡變換器為形成於同一基板上以進行多頻段操作。例如，二或更多平衡-不平衡變換器被使用於行動電話或其它全球行動通訊系統(GSM)之四頻段中，每一個平衡-不平衡變換器專門提供該四頻元件中之一頻段操作。一典型射頻系統在一或更多半導體構裝中需要多個整合被動元件及其它高頻電路以執行所需之電性功能。The integrated passive component structure provides electrical characteristics required for high frequency applications such as resonators, high pass filters, low pass filters, band pass filters, symmetrical high quality factor resonant transformers, matching networks, and tuning capacitors. . The integrated passive components can function as a front end radio frequency component that can be positioned between the antenna and the transceiver. The inductor can be a high quality factor balun, transformer or coil operating at up to 100 GHz. In some applications, multiple baluns are formed on the same substrate for multi-band operation. For example, two or more baluns are used in the four bands of mobile phones or other Global System for Mobile Communications (GSM), each of which is dedicated to providing one of the four frequency components. A typical RF system requires multiple integrated passive components and other high frequency circuitry to perform the desired electrical functions in one or more semiconductor packages.
該載體經由化學濕式蝕刻、電漿乾式蝕刻、機械脫落、化學機械拋光、機械研磨、熱烘烤、雷射掃描或濕式剝離移除之。在該載體移除後，封膠劑178提供半導體晶粒170結構支撐。該載體移除後接著露出導電層164及凸塊下金屬化層166。The support is removed by chemical wet etching, plasma dry etching, mechanical shedding, chemical mechanical polishing, mechanical grinding, hot baking, laser scanning or wet stripping. After the carrier is removed, the encapsulant 178 provides structural support for the semiconductor die 170. The carrier is removed and the conductive layer 164 and the under bump metallization layer 166 are then exposed.
一底側增層式互連結構200形成於與頂側增層式互連結構180相對之導電柱168和封膠劑178第二表面上。一導電層202使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於導電層164及凸塊下金屬化層166上。導電層202可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。部分導電層202為電性連接至導電柱168、導電層164及凸塊下金屬化層166。導電層202中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A bottom side build-up interconnect structure 200 is formed on the second surface of the conductive pillars 168 and encapsulant 178 opposite the top side build-up interconnect structure 180. A conductive layer 202 is patterned on the conductive layer 164 and the under bump metallization layer 166 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 202 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The portion of the conductive layer 202 is electrically connected to the conductive pillar 168, the conductive layer 164, and the under bump metallization layer 166. Other portions of conductive layer 202 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一絕緣或保護層204使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於導電層202和封膠劑178第二表面上。該保護層204可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層204而露出導電層202。An insulating or protective layer 204 is formed on the second surface of the conductive layer 202 and the encapsulant 178 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 204 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. A portion of the protective layer 204 is removed by an etching process to expose the conductive layer 202.
一導電凸塊材料使用蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於導電層202上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至導電層202。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊206。在一些應用中，凸塊206被回焊一第二時間以改進對導電層202之電性接觸。該些凸塊也可被壓縮黏結至導電層202。凸塊206代表可被形成於導電層202上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。A conductive bump material is deposited on the conductive layer 202 using evaporation, electroplating, electroless plating, solder ball dropping or screen printing processes. The bump material can be aluminum, tin, nickel, gold, silver, lead, antimony, copper, solder, and combinations thereof, plus a selective flux material. For example, the bump material can be eutectic tin/lead, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 202 using a suitable bonding or bonding process. In an embodiment, the bump material is reflowed to form a sphere or bump 206 by heating the material beyond its melting point. In some applications, bumps 206 are reflowed for a second time to improve electrical contact to conductive layer 202. The bumps can also be compression bonded to the conductive layer 202. Bumps 206 represent some type of interconnect structure that can be formed on conductive layer 202. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects.
導電柱168在頂側增層式互連層180及底側增層式互連層200之間提供垂直z方向互連。導電層184為透過導電柱168電性連接至導電層202及半導體晶粒170之金屬凸塊174。Conductive pillars 168 provide vertical z-direction interconnections between topside build-up interconnect layer 180 and bottomside build-up interconnect layer 200. The conductive layer 184 is a metal bump 174 electrically connected to the conductive layer 202 and the semiconductor die 170 through the conductive pillars 168.
圖6說明具有形成於底側互連結構中之多個整合被動元件之垂直互連結構實施例。類似於圖3a-3h所述方法，半導體元件212使用具有一選擇性晶種層之犧牲或暫時基板或載體。一導電層214使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於該載體上。導電層214可為鋁、銅、錫、鎳、金、銀、鎢、多晶矽或其它合適導電材料中其中一層或更多層。導電層214包含用於稍後形成導電柱之可濕潤接觸墊片。Figure 6 illustrates an embodiment of a vertical interconnect structure having a plurality of integrated passive components formed in a bottom side interconnect structure. Similar to the method described in Figures 3a-3h, the semiconductor component 212 uses a sacrificial or temporary substrate or carrier having a selective seed layer. A conductive layer 214 is patterned on the carrier using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 214 can be one or more of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. Conductive layer 214 includes a wettable contact pad for later forming a conductive post.
一導電層216使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於絯晶種層或載體上。導電層216可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層216為與導電層214共平面。導電層216為一固定於導電層214的相對位置之凸塊下金屬化層。A conductive layer 216 is patterned on the seed layer or carrier using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 216 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. Conductive layer 216 is coplanar with conductive layer 214. The conductive layer 216 is an under bump metallization layer fixed at a relative position of the conductive layer 214.
複數個導電柱或杆218形成於導電層214之可濕潤接觸墊片上。在一實施例中，導電柱218為藉由將一或更多光阻層沉積於晶種層或載體上而形成。導電層214上的部分光阻層為經由一蝕刻顯影製程而被露出並移除。導電材料使用一選擇性電鍍製程來沉積於該光阻層之移除部分內。該光阻層被剝除而留下各個導電柱218。導電柱218可為銅、鋁、鎢、金、焊錫或其它合適導電材料。導電柱218具有2-120微米範圍之高度。在另一實施例中，形成之導電柱218可為短柱凸塊或堆疊凸塊。在任何例子中，導電柱218具有以焊料或內含銅、銀、鉍或錫之介金屬化合物所產生之一至凸塊下金屬化層216之堅固又緊密金屬至金屬黏結。A plurality of conductive posts or rods 218 are formed on the wettable contact pads of the conductive layer 214. In one embodiment, the conductive pillars 218 are formed by depositing one or more photoresist layers on the seed layer or carrier. A portion of the photoresist layer on the conductive layer 214 is exposed and removed via an etch developing process. The conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped leaving the respective conductive pillars 218. Conductive post 218 can be copper, aluminum, tungsten, gold, solder, or other suitable electrically conductive material. Conductive post 218 has a height in the range of 2-120 microns. In another embodiment, the formed conductive pillars 218 can be short stud bumps or stacked bumps. In any example, the conductive posts 218 have a strong and tight metal-to-metal bond with one of the solder or a metal-containing compound containing copper, silver, antimony or tin to the under-bump metallization layer 216.
複數個半導體晶粒或構件220為以金屬凸塊224朝下定位在該載體上方之覆晶安排方式來安裝至凸塊下金屬化層216。半導體晶粒220包含一內含類比或數位電路之作用區域226，該些電路配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用表面226內之其它電路構件以配置例如數位訊號處理器、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。半導體晶粒220也可包含用於射頻訊號處理之整合被動元件，例如電感器、電容器和電阻器。A plurality of semiconductor dies or features 220 are mounted to the under bump metallization layer 216 in a flip chip arrangement in which the metal bumps 224 are positioned downwardly over the carrier. The semiconductor die 220 includes an active region 226 including an analog or digital circuit configured to be actively and passively formed in the die and electrically interconnected according to the electrical design and function of the die. , conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed within the active surface 226 to configure, for example, a digital signal processor, special purpose integrated circuit, memory, or other signal processing circuit. Frequency analog circuit or digital circuit. Semiconductor die 220 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors.
凸塊下金屬化層216固定於導電層214的相對位置。導電柱218安裝在半導體晶粒220四周之導電層214上。據此，凸塊下金屬化層216固定於導電柱218的相對位置。藉由配對金屬凸塊224與凸塊下金屬化層216，半導體晶粒220自我調準至導電柱218。The under bump metallization layer 216 is fixed to the opposite position of the conductive layer 214. Conductive posts 218 are mounted on conductive layer 214 around semiconductor die 220. Accordingly, the under bump metallization layer 216 is fixed to the opposite position of the conductive pillars 218. The semiconductor die 220 self-aligns to the conductive pillars 218 by pairing the metal bumps 224 with the under bump metallization layers 216.
一封膠劑或封膠化合物228使用一錫膏印刷、壓縮成型、轉注成型、液體封膠成型、真空疊合或其它合適塗抹器來沉積於半導體晶粒220和導電柱218上。封膠劑228可為聚合物複合材料，例如，具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酯或具有正確填充劑之聚合物。封膠劑228為無導電性且在環境上保護該半導體元件隔離外部構件及污染。利用牢牢安裝至固定凸塊下金屬化層216之半導體晶粒220之金屬凸塊224，該晶粒在該封膠製程期間對準著導電柱218並未移位。A glue or sealant compound 228 is deposited onto the semiconductor die 220 and the conductive posts 218 using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. The sealant 228 can be a polymer composite such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a correct filler. The encapsulant 228 is non-conductive and environmentally protects the semiconductor component from external components and contamination. With the metal bumps 224 of the semiconductor die 220 firmly attached to the under bump metallization layer 216, the die is aligned with the conductive posts 218 during the encapsulation process.
該封膠劑228進行研磨或電漿蝕刻以平坦化該表面而形成一頂側增層式互連結構。該研磨操作露出導電柱218頂部表面及半導體晶粒220背部表面。該頂側增層式互連結構230形成於導電柱218、封膠劑228第一表面、和半導體晶粒220背部表面上。一絕緣或保護層232使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程形成之。該保護層232可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層232而露出導電柱218。The encapsulant 228 is ground or plasma etched to planarize the surface to form a top side build-up interconnect structure. The polishing operation exposes the top surface of the conductive pillar 218 and the back surface of the semiconductor die 220. The top side build-up interconnect structure 230 is formed on the conductive pillars 218, the first surface of the sealant 228, and the back surface of the semiconductor die 220. An insulating or protective layer 232 is formed using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 232 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. A portion of the protective layer 232 is removed by an etching process to expose the conductive pillars 218.
一導電層234使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於保護層232及導電柱218上。導電層234可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。一部分導電層234為電性連接至導電柱218。導電層234中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A conductive layer 234 is patterned on the protective layer 232 and the conductive pillars 218 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 234 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 234 is electrically connected to the conductive pillars 218. Other portions of conductive layer 234 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一絕緣或保護層236使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於絕緣層232及導電層234上。該保護層236可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層236而露出導電層234。An insulating or protective layer 236 is formed over the insulating layer 232 and the conductive layer 234 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering, or thermal oxidation processes. The protective layer 236 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, antimony pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 236 is removed by an etching process to expose the conductive layer 234.
該載體經由化學濕式蝕刻、電漿乾式蝕刻、機械脫落、化學機械拋光、機械研磨、熱烘烤、雷射掃描或濕式剝離移除之。在該載體移除後，封膠劑228提供半導體晶粒220結構支撐。該載體移除後接著露出導電層214及凸塊下金屬化層216。The support is removed by chemical wet etching, plasma dry etching, mechanical shedding, chemical mechanical polishing, mechanical grinding, hot baking, laser scanning or wet stripping. After the carrier is removed, the encapsulant 228 provides structural support for the semiconductor die 220. After the carrier is removed, the conductive layer 214 and the under bump metallization layer 216 are exposed.
一底側增層式互連結構240形成於與頂側增層式互連結構230相對之導電柱218和封膠劑228第二表面上。一導電層242使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於導電層214及凸塊下金屬化層216上。導電層242可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。部分導電層242為電性連接至導電柱218、導電層214及凸塊下金屬化層216。導電層242中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A bottom side build-up interconnect structure 240 is formed on the second surface of the conductive pillar 218 and encapsulant 228 opposite the top side build-up interconnect structure 230. A conductive layer 242 is patterned on the conductive layer 214 and the under bump metallization layer 216 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 242 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The portion of the conductive layer 242 is electrically connected to the conductive pillar 218, the conductive layer 214, and the under bump metallization layer 216. Other portions of conductive layer 242 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一電阻層244使用物理氣相沉積或化學氣相沉積進行圖案化及沉積。電阻層244TaxSiy或其它金屬矽化物、氮化鉭、鎳鉻、氮化鈦或具有5至100歐姆/平方電阻率之摻雜多晶矽。一絕緣層246使用物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層242上。該絕緣層246可為氮化矽、二氧化矽、氮氧化矽、五氧化二鉭、氧化鋅、氧化鋯、氧化鋁、聚醯亞胺、苯環丁烯、聚苯噁唑或其它合適介電材料中其中一層或更多層。電阻層244及絕緣層246可以相同遮罩形成並同時進行蝕刻。替代性地，電阻層244及絕緣層246可以不同遮罩進行圖案化及蝕刻。A resistive layer 244 is patterned and deposited using physical vapor deposition or chemical vapor deposition. Resistive layer 244Ta x Si y or other metal germanide, tantalum nitride, nickel chromium, titanium nitride or doped polysilicon having a resistivity of 5 to 100 ohms/square. An insulating layer 246 is formed on the conductive layer 242 using physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The insulating layer 246 may be tantalum nitride, hafnium oxide, hafnium oxynitride, antimony pentoxide, zinc oxide, zirconium oxide, aluminum oxide, polyimine, benzocyclobutene, polybenzoxazole or other suitable medium. One or more layers of the electrical material. The resistive layer 244 and the insulating layer 246 may be formed in the same mask and etched simultaneously. Alternatively, the resistive layer 244 and the insulating layer 246 can be patterned and etched with different masks.
一絕緣或保護層248使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層242、電阻層244及絕緣層246上。該保護層248可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。一部分保護層248被移除而露出導電層242、電阻層244及絕緣層246。An insulating or protective layer 248 is formed on the conductive layer 242, the resistive layer 244, and the insulating layer 246 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 248 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 248 is removed to expose the conductive layer 242, the resistive layer 244, and the insulating layer 246.
一導電層250使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化並沉積於保護層248、導電層242、電阻層244及絕緣層246上以形成個別部分或區段以供進一步互連性。導電層250中之個別部分可依據個別半導體晶粒之連接性而為共電性或電性隔離。導電層250可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。A conductive layer 250 is patterned and deposited on the protective layer 248, the conductive layer 242, the resistive layer 244, and the insulating layer 246 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Upper to form individual sections or sections for further interconnectivity. Individual portions of conductive layer 250 may be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. Conductive layer 250 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.
一絕緣或保護層252使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層250和保護層248上。該保護層252可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。一部分保護層252被移除而露出導電層250。An insulating or protective layer 252 is formed over conductive layer 250 and protective layer 248 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 252 can be one or more of cerium oxide, tantalum nitride, hafnium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 252 is removed to expose the conductive layer 250.
增層式互連結構240中所述結構構成一或更多被動電路構件或整合被動元件。在一實施例中，導電層242、絕緣層246及導電層250為一金屬層-絕緣層-金屬層電容器。電阻層244為該被動電路中之電阻器構件。導電層250中之個別區段在平面視野上可被捲繞或盤繞以產生或展示想要之電感器特性。The structure described in the build-up interconnect structure 240 constitutes one or more passive circuit components or integrated passive components. In one embodiment, the conductive layer 242, the insulating layer 246, and the conductive layer 250 are a metal layer-insulation layer-metal layer capacitor. The resistive layer 244 is a resistor member in the passive circuit. Individual segments of conductive layer 250 can be wound or coiled in a planar field of view to create or exhibit desired inductor characteristics.
一導電凸塊材料使用蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於導電層250上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至導電層250。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊254。在一些應用中，凸塊254被回焊一第二時間以改進對導電層250之電性接觸。該些凸塊也可被壓縮黏結至導電層250。凸塊254代表可被形成於導電層250上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。A conductive bump material is deposited on the conductive layer 250 using evaporation, electroplating, electroless plating, solder ball dropping or screen printing processes. The bump material can be aluminum, tin, nickel, gold, silver, lead, antimony, copper, solder, and combinations thereof, plus a selective flux material. For example, the bump material can be eutectic tin/lead, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 250 using a suitable bonding or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 254. In some applications, bumps 254 are reflowed for a second time to improve electrical contact to conductive layer 250. The bumps can also be compression bonded to the conductive layer 250. Bumps 254 represent some type of interconnect structure that can be formed on conductive layer 250. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects.
導電柱218在頂側增層式互連層230及底側增層式互連層240之間提供垂直z方向互連。導電層234為透過導電柱218電性連接至導電層242和250及半導體晶粒220之金屬凸塊224。Conductive pillars 218 provide vertical z-direction interconnections between topside build-up interconnect layer 230 and bottom side build-up interconnect layer 240. The conductive layer 234 is a metal bump 224 electrically connected to the conductive layers 242 and 250 and the semiconductor die 220 through the conductive pillars 218.
圖7說明具有形成於該底側互連結構中之多個整合被動元件之垂直互連結構之實施例。半導體元件260使用具有一犧牲或暫時基板或載體。一底側互連結構形成於該載體上。一導電層264使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化而得以形成個別部分或區段264a-264h。導電層264可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。部分導電層264為電性連接至導電柱168。導電層184中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。Figure 7 illustrates an embodiment of a vertical interconnect structure having a plurality of integrated passive components formed in the bottom side interconnect structure. The semiconductor component 260 is used with a sacrificial or temporary substrate or carrier. A bottom side interconnect structure is formed on the carrier. A conductive layer 264 is patterned using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process to form individual portions or sections 264a-264h. Conductive layer 264 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 264 is electrically connected to the conductive pillars 168. Other portions of conductive layer 184 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一電阻層266a-266b使用物理氣相沉積或化學氣相沉積來分別圖案化並沉積於導電層264和該載體上。電阻層266為TaxSiy或其它金屬矽化物、氮化鉭、鎳鉻、氮化鈦或具有5至100歐姆/平方電阻率之摻雜多晶矽。一絕緣層268使用物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層266a上。該絕緣層268可為氮化矽、二氧化矽、氮氧化矽、五氧化二鉭、氧化鋅、氧化鋯、氧化鋁、聚醯亞胺、苯環丁烯、聚苯噁唑或其它合適介電材料中其中一層或更多層。A resistive layer 266a-266b is separately patterned and deposited on the conductive layer 264 and the carrier using physical vapor deposition or chemical vapor deposition. The resistive layer 266 is Ta x Si y or other metal germanide, tantalum nitride, nickel chromium, titanium nitride or doped polysilicon having a resistivity of 5 to 100 ohms/square. An insulating layer 268 is formed on the conductive layer 266a using physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation processes. The insulating layer 268 may be tantalum nitride, hafnium oxide, hafnium oxynitride, antimony pentoxide, zinc oxide, zirconium oxide, aluminum oxide, polyimine, benzocyclobutene, polybenzoxazole or other suitable medium. One or more layers of the electrical material.
一絕緣或保護層270使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層264、電阻層266及絕緣層268上。該保護層270可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。一部分保護層270被移除而露出導電層264、電阻層266及絕緣層268。An insulating or protective layer 270 is formed on the conductive layer 264, the resistive layer 266, and the insulating layer 268 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 270 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, antimony pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 270 is removed to expose the conductive layer 264, the resistive layer 266, and the insulating layer 268.
一導電層272使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化並沉積於保護層270、導電層264、電阻層266及絕緣層268上以形成個別部分或區段以供進一步互連性。導電層272中之個別部分可依據個別半導體晶粒之連接性而為共電性或電性隔離。導電層272可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。導電層272包含用於稍後形成導電柱之可濕潤接觸墊片以及基於該半導體晶粒調準而與該些導電柱相對固定之凸塊下金屬化層。A conductive layer 272 is patterned and deposited on the protective layer 270, the conductive layer 264, the resistive layer 266, and the insulating layer 268 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Upper to form individual sections or sections for further interconnectivity. Individual portions of conductive layer 272 may be electrically or electrically isolated depending on the connectivity of the individual semiconductor dies. Conductive layer 272 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The conductive layer 272 includes a wettable contact pad for later forming a conductive pillar and an under bump metallization layer that is fixed relative to the conductive pillars based on the semiconductor die alignment.
一絕緣或保護層274使用旋塗、物理氣相沉積、化學氣相沉積、印刷、燒結或熱氧化製程來形成於導電層272和保護層270上。該保護層274可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有合適絕緣特性之其它材料中其中一層或更多層。一部分保護層274被移除而露出導電層272。An insulating or protective layer 274 is formed on the conductive layer 272 and the protective layer 270 using spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation processes. The protective layer 274 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, antimony pentoxide, aluminum oxide, or other materials having suitable insulating properties. A portion of the protective layer 274 is removed to expose the conductive layer 272.
增層式互連結構262中所述結構構成一或更多被動電路構件或整合被動元件。在一實施例中，導電層264b、電阻層266a、絕緣層268及導電層272為一金屬層-絕緣層-金屬層電容器。電阻層266b為該被動電路中之電阻器構件。導電層272中之其它個別區段在平面視野上可被捲繞或盤繞以產生或展示想要之電感器特性。The structure described in the build-up interconnect structure 262 constitutes one or more passive circuit components or integrated passive components. In one embodiment, the conductive layer 264b, the resistive layer 266a, the insulating layer 268, and the conductive layer 272 are a metal layer-insulating layer-metal layer capacitor. The resistive layer 266b is a resistor member in the passive circuit. Other individual segments in conductive layer 272 may be wound or coiled in a planar field of view to create or exhibit desired inductor characteristics.
複數個導電柱或杆278形成於導電層272之可濕潤接觸墊片上。在一實施例中，導電柱278為藉由將一或更多光阻層沉積於互連結構262上而形成。導電層272上的部分光阻層為經由一蝕刻顯影製程而被露出並移除。導電材料使用一選擇性電鍍製程來沉積於該光阻層之移除部分內。該光阻層被剝除而留下各個導電柱278。導電柱278可為銅、鋁、鎢、金、焊錫或其它合適導電材料。導電柱278具有2-120微米範圍之高度。在另一實施例中，形成之導電柱278可為短柱凸塊或堆疊凸塊。在任何例子中，導電柱278具有以焊料或內含銅、銀、鉍或錫之介金屬化合物所產生之一至凸塊下金屬化層126之堅固又緊密金屬至金屬黏結。A plurality of conductive posts or rods 278 are formed on the wettable contact pads of conductive layer 272. In one embodiment, the conductive pillars 278 are formed by depositing one or more photoresist layers on the interconnect structure 262. A portion of the photoresist layer on conductive layer 272 is exposed and removed via an etch developing process. The conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped leaving the respective conductive pillars 278. Conductive post 278 can be copper, aluminum, tungsten, gold, solder, or other suitable electrically conductive material. Conductive post 278 has a height in the range of 2-120 microns. In another embodiment, the formed conductive pillars 278 can be short stud bumps or stacked bumps. In any example, the conductive posts 278 have a strong and tight metal-to-metal bond with one of the solder or a metal-containing compound containing copper, silver, antimony or tin to the under bump metallization layer 126.
複數個半導體晶粒或構件280為以金屬凸塊284朝下定位在互連結構262上方之覆晶安排方式來安裝至導電層272。半導體晶粒280包含一內含類比或數位電路之作用區域136，該些電路配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用表面126內之其它電路構件以配置例如數位訊號處理器、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。半導體晶粒280也可包含用於射頻訊號處理之整合被動元件，例如電感器、電容器和電阻器。A plurality of semiconductor dies or members 280 are mounted to the conductive layer 272 in a flip chip arrangement in which the metal bumps 284 are positioned downwardly over the interconnect structure 262. The semiconductor die 280 includes an active region 136 including an analog or digital circuit configured to be actively and passively formed in the die and electrically interconnected according to the electrical design and function of the die. , conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed within the active surface 126 to configure, for example, a digital signal processor, special purpose integrated circuit, memory, or other signal processing circuit. Frequency analog circuit or digital circuit. Semiconductor die 280 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors.
一封膠劑或封膠化合物288使用一錫膏印刷、壓縮成型、轉注成型、液體封膠成型、真空疊合或其它合適塗抹器來沉積於半導體晶粒280和導電柱278上。封膠劑288可為聚合物複合材料，例如，具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酯或具有正確填充劑之聚合物。封膠劑288為無導電性且在環境上保護該半導體元件隔離外部構件及污染。利用牢牢安裝至導電層272之半導體晶粒280之金屬凸塊284，該晶粒在該封膠製程期間為對準著導電柱278並未移位。A glue or sealant compound 288 is deposited onto the semiconductor die 280 and the conductive posts 278 using a solder paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination or other suitable applicator. The sealant 288 can be a polymer composite such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a correct filler. The encapsulant 288 is non-conductive and environmentally protects the semiconductor component from external components and contamination. With the metal bumps 284 of the semiconductor die 280 firmly mounted to the conductive layer 272, the die is not displaced during alignment of the conductive posts 278 during the encapsulation process.
該封膠劑288進行研磨或電漿蝕刻以平坦化該表面而形成一頂側增層式互連結構。在一實施例中，該研磨操作露出導電柱278頂部表面及半導體晶粒280背部表面。替代性地，該研磨操作露出導電柱278頂部表面並保留內嵌於封膠劑288之半導體晶粒280。該頂側增層式互連結構290形成於導電柱278、封膠劑288第一表面和半導體晶粒280背部表面上。一絕緣或保護層292使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程形成之。該保護層292可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層292而露出導電柱278。The encapsulant 288 is ground or plasma etched to planarize the surface to form a top side build-up interconnect structure. In one embodiment, the polishing operation exposes the top surface of the conductive pillar 278 and the back surface of the semiconductor die 280. Alternatively, the polishing operation exposes the top surface of the conductive pillar 278 and retains the semiconductor die 280 embedded in the encapsulant 288. The top side build-up interconnect structure 290 is formed on the conductive pillars 278, the first surface of the sealant 288, and the back surface of the semiconductor die 280. An insulating or protective layer 292 is formed using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 292 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. A portion of the protective layer 292 is removed by an etching process to expose the conductive pillars 278.
一導電層294使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於保護層292及導電柱278上。導電層294可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。一部分導電層294為電性連接至導電柱278。導電層294中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A conductive layer 294 is patterned on the protective layer 292 and the conductive pillars 278 by physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 294 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 294 is electrically connected to the conductive pillars 278. Other portions of conductive layer 294 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一絕緣或保護層296使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於絕緣層292和導電層294上。該保護層296可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層296而露出導電層294。An insulating or protective layer 296 is formed over the insulating layer 292 and the conductive layer 294 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 296 can be one or more of ceria, tantalum nitride, hafnium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. A portion of the protective layer 296 is removed by an etching process to expose the conductive layer 294.
該暫時載體經由化學濕式蝕刻、電漿乾式蝕刻、機械脫落、化學機械拋光、機械研磨、熱烘烤、雷射掃描或濕式剝離移除之。在該載體移除後，封膠劑288提供半導體晶粒260結構支撐。該載體移除後接著露出導電層264。The temporary carrier is removed by chemical wet etching, plasma dry etching, mechanical shedding, chemical mechanical polishing, mechanical grinding, hot baking, laser scanning or wet stripping. Sealant 288 provides structural support for semiconductor die 260 after the carrier is removed. The carrier is removed and the conductive layer 264 is then exposed.
一絕緣或保護層300使用物理氣相沉積、化學氣相沉積、印刷、旋塗、噴塗、燒結或熱氧化製程來形成於導電層272和絕緣層274上。該保護層300可為二氧化矽、氮化矽、氮氧化矽、五氧化二鉭、氧化鋁或具有類似絕緣和結構特性之其它材料中其中一層或更多層。以一蝕刻製程移除一部分保護層300而露出導電層272。An insulating or protective layer 300 is formed on the conductive layer 272 and the insulating layer 274 using physical vapor deposition, chemical vapor deposition, printing, spin coating, spray coating, sintering or thermal oxidation processes. The protective layer 300 can be one or more of cerium oxide, cerium nitride, cerium oxynitride, tantalum pentoxide, aluminum oxide, or other materials having similar insulating and structural properties. A portion of the protective layer 300 is removed by an etching process to expose the conductive layer 272.
一導電層298使用物理氣相沉積、化學氣相沉積、濺鍍、電鍍、無電鍍製程或其它合適金屬沉積製程進行圖案化來形成於導電層272上。導電層298可為鋁、銅、錫、鎳、金、銀或其它合適導電材料中其中一層或更多層。部分導電層298為電性連接至導電柱278及導電層272。導電層298中的其它部分可依據該半導體元件之設計和功能而為共電性或電性隔離。A conductive layer 298 is patterned on the conductive layer 272 using physical vapor deposition, chemical vapor deposition, sputtering, electroplating, electroless plating, or other suitable metal deposition process. Conductive layer 298 can be one or more of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The portion of the conductive layer 298 is electrically connected to the conductive pillar 278 and the conductive layer 272. Other portions of conductive layer 298 may be electrically or electrically isolated depending on the design and function of the semiconductor component.
一導電凸塊材料使用蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於導電層298上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至導電層298。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊302。在一些應用中，凸塊302被回焊一第二時間以改進對導電層298之電性接觸。該些凸塊也可被壓縮黏結至導電層298。凸塊302代表可被形成於導電層298上之某類型互連結構。該互連結構也可使用接線、導電膏、短柱凸塊、微小凸塊或其它電性互連。A conductive bump material is deposited on conductive layer 298 using evaporation, electroplating, electroless plating, solder ball dropping or screen printing processes. The bump material can be aluminum, tin, nickel, gold, silver, lead, antimony, copper, solder, and combinations thereof, plus a selective flux material. For example, the bump material can be eutectic tin/lead, high lead solder, or lead free solder. The bump material is bonded to conductive layer 298 using a suitable bonding or bonding process. In one embodiment, the bump material is reflowed to form a sphere or bump 302 by heating the material beyond its melting point. In some applications, bumps 302 are reflowed for a second time to improve electrical contact to conductive layer 298. The bumps can also be compression bonded to the conductive layer 298. Bumps 302 represent some type of interconnect structure that can be formed on conductive layer 298. The interconnect structure can also use wiring, conductive paste, stud bumps, tiny bumps, or other electrical interconnects.
一半導體晶粒或構件304為以金屬凸塊306電性連接至導電層298之覆晶安排方式來安裝至半導體元件260背面。半導體晶粒304包含一內含類比或數位電路之作用表面，該些電路配置為形成於該晶粒內並根據該晶粒之電性設計及功能進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體和形成於作用表面226內之其它電路構件以配置例如數位訊號處理器、特殊用途積體電路、記憶體或其它訊號處理電路之基頻類比電路或數位電路。半導體晶粒304也可包含用於射頻訊號處理之整合被動元件，例如電感器、電容器和電阻器。一底部填膠材料308被沉積於半導體晶粒304下。A semiconductor die or member 304 is mounted to the back side of the semiconductor device 260 in a flip chip arrangement in which the metal bumps 306 are electrically connected to the conductive layer 298. The semiconductor die 304 includes an active surface containing an analog or digital circuit configured to be active in the die and electrically interconnected according to the electrical design and function of the die. Conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed within the active surface 226 to configure, for example, a digital signal processor, special purpose integrated circuit, memory, or other signal processing circuit. Frequency analog circuit or digital circuit. Semiconductor die 304 may also include integrated passive components for RF signal processing, such as inductors, capacitors, and resistors. An underfill material 308 is deposited under the semiconductor die 304.
導電柱278在底側增層式互連層262及頂側增層式互連層290之間提供垂直z方向互連。導電層294為透過導電柱278電性連接至導電層272和半導體晶粒280之金屬凸塊284，以及導電層264、半導體晶粒304之金屬凸塊306和互連層262中的整合被動元件。Conductive pillars 278 provide vertical z-direction interconnections between bottom side build-up interconnect layer 262 and top side build-up interconnect layer 290. The conductive layer 294 is a metal bump 284 electrically connected to the conductive layer 272 and the semiconductor die 280 through the conductive pillar 278, and the integrated passive component in the conductive layer 264, the metal bump 306 of the semiconductor die 304, and the interconnect layer 262. .
如上所述，該整合被動元件結構可被形成於該頂側增層式互連層和底側增層式互連層中之任一者或兩者。此外，二或更多半導體晶粒可被堆疊或一起安裝於該些導電柱之間。其它半導體晶粒、分立式構件及構裝可使用二級互連來安裝至該頂側增層式互連層和底側增層式互連層。As described above, the integrated passive component structure can be formed in either or both of the top side buildup interconnect layer and the bottom side buildup interconnect layer. Additionally, two or more semiconductor dies may be stacked or mounted together between the conductive pillars. Other semiconductor dies, discrete components, and structures can be mounted to the topside buildup interconnect layer and the bottom side buildup interconnect layer using a second level interconnect.
儘管本發明一或更多實施例已被詳加說明，熟知此項技術之人士會理解到對那些實施例之修正和改寫可被進行而不偏離下列申請專利範圍所提之本發明範圍。Although one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations to those embodiments can be made without departing from the scope of the invention as set forth in the appended claims.
50．．．電子元件50. . . Electronic component
52．．．印刷電路板52. . . A printed circuit board
54．．．軌跡線54. . . Trajectory
56．．．打線接合構裝56. . . Wire bonding
58．．．覆晶構裝58. . . Cladding
60．．．錫球陣列構裝60. . . Tin ball array
62．．．凸塊晶片載體62. . . Bump wafer carrier
64．．．雙列式構裝64. . . Double row construction
66．．．平面陣列構裝66. . . Planar array assembly
68．．．多晶片模組構裝68. . . Multi-chip module assembly
70．．．四邊扁平無引腳構裝70. . . Four-sided flat leadless assembly
72．．．四邊扁平構裝72. . . Four-sided flat construction
74．．．半導體晶粒74. . . Semiconductor grain
76．．．接觸墊片76. . . Contact gasket
78．．．中介載體78. . . Mediation carrier
80．．．導線80. . . wire
82．．．接線82. . . wiring
84．．．封膠劑84. . . Sealant
88．．．半導體晶粒88. . . Semiconductor grain
90．．．載體90. . . Carrier
92．．．底部填膠或環氧樹脂黏接材料92. . . Bottom glue or epoxy bonding material
94．．．接線94. . . wiring
96．．．接觸墊片96. . . Contact gasket
98．．．接觸墊片98. . . Contact gasket
100．．．封膠化合物或封膠劑100. . . Sealing compound or sealant
102．．．接觸墊片102. . . Contact gasket
104．．．凸塊104. . . Bump
106．．．載體106. . . Carrier
108．．．作用區域108. . . Action area
110．．．焊料凸塊或圓球110. . . Solder bump or ball
112．．．焊料凸塊或圓球112. . . Solder bump or ball
114．．．訊號線114. . . Signal line
116．．．封膠化合物或封膠劑116. . . Sealing compound or sealant
120．．．載體120. . . Carrier
122．．．晶種層122. . . Seed layer
124．．．導電層124. . . Conductive layer
126．．．凸塊下金屬化層126. . . Under bump metallization
128．．．導電柱或杆128. . . Conductive column or rod
130．．．半導體晶粒或構件130. . . Semiconductor die or member
134．．．金屬凸塊134. . . Metal bump
136．．．作用表面136. . . Surface
138．．．封膠劑或封膠化合物138. . . Sealant or sealant
139．．．研磨器139. . . abrader
140．．．頂側增層式互連結構140. . . Top side build-up interconnect structure
142．．．絕緣或保護層142. . . Insulation or protective layer
144．．．導電層144. . . Conductive layer
146．．．絕緣或保護層146. . . Insulation or protective layer
150．．．底側增層式互連結構150. . . Bottom side build-up interconnect structure
152．．．導電層152. . . Conductive layer
154．．．絕緣或保護層154. . . Insulation or protective layer
156．．．圓球或凸塊156. . . Ball or bump
160．．．半導體元件160. . . Semiconductor component
162．．．半導體元件162. . . Semiconductor component
164．．．導電層164. . . Conductive layer
166．．．導電層166. . . Conductive layer
168．．．導電柱168. . . Conductive column
170．．．半導體晶粒或構件170. . . Semiconductor die or member
174．．．金屬凸塊174. . . Metal bump
176．．．作用表面176. . . Surface
178．．．封膠劑或封膠化合物178. . . Sealant or sealant
180．．．頂側增層式互連結構180. . . Top side build-up interconnect structure
182．．．絕緣或保護層182. . . Insulation or protective layer
184．．．導電層184. . . Conductive layer
186．．．電阻層186. . . Resistance layer
188．．．絕緣層188. . . Insulation
190．．．絕緣或保護層190. . . Insulation or protective layer
192．．．導電層192. . . Conductive layer
194．．．絕緣或保護層194. . . Insulation or protective layer
200．．．底側增層式互連結構200. . . Bottom side build-up interconnect structure
202．．．導電層202. . . Conductive layer
204．．．絕緣或保護層204. . . Insulation or protective layer
206．．．圓球或凸塊206. . . Ball or bump
212．．．半導體元件212. . . Semiconductor component
214．．．導電層214. . . Conductive layer
216．．．導電層216. . . Conductive layer
218．．．導電柱218. . . Conductive column
220．．．半導體晶粒或構件220. . . Semiconductor die or member
224．．．金屬凸塊224. . . Metal bump
226．．．作用表面226. . . Surface
228．．．封膠劑或封膠化合物228. . . Sealant or sealant
230．．．頂側增層式互連結構230. . . Top side build-up interconnect structure
232．．．絕緣或保護層232. . . Insulation or protective layer
234．．．導電層234. . . Conductive layer
236．．．絕緣或保護層236. . . Insulation or protective layer
240．．．底側增層式互連結構240. . . Bottom side build-up interconnect structure
242．．．導電層242. . . Conductive layer
244．．．電阻層244. . . Resistance layer
246．．．絕緣層246. . . Insulation
248．．．絕緣或保護層248. . . Insulation or protective layer
250．．．導電層250. . . Conductive layer
252．．．絕緣或保護層252. . . Insulation or protective layer
254．．．圓球或凸塊254. . . Ball or bump
260．．．半導體元件260. . . Semiconductor component
262．．．底側增層式互連結構262. . . Bottom side build-up interconnect structure
264．．．導電層264. . . Conductive layer
266．．．電阻層266. . . Resistance layer
268．．．絕緣層268. . . Insulation
270．．．保護層270. . . The protective layer
272．．．導電層272. . . Conductive layer
274．．．絕緣或保護層274. . . Insulation or protective layer
278．．．導電柱或杆278. . . Conductive column or rod
280．．．半導體晶粒或構件280. . . Semiconductor die or member
284．．．金屬凸塊284. . . Metal bump
288．．．封膠劑或封膠化合物288. . . Sealant or sealant
290．．．頂側增層式互連結構290. . . Top side build-up interconnect structure
292．．．絕緣或保護層292. . . Insulation or protective layer
294．．．導電層294. . . Conductive layer
296．．．絕緣或保護層296. . . Insulation or protective layer
298．．．導電層298. . . Conductive layer
300．．．絕緣或保護層300. . . Insulation or protective layer
302．．．圓球或凸塊302. . . Ball or bump
304．．．半導體晶粒或構件304. . . Semiconductor die or member
306．．．金屬凸塊306. . . Metal bump
308．．．底部填膠材料308. . . Bottom filling material
圖1說明在表面上安裝有各類型構裝之印刷電路板。Figure 1 illustrates a printed circuit board having various types of mountings mounted on a surface.
圖2a-2c說明安裝至該印刷電路板之代表性半導體構裝之進一步細部。Figures 2a-2c illustrate further details of a representative semiconductor package mounted to the printed circuit board.
圖3a-3h說明一種使用導電柱和基於該半導體晶粒調準而與該些導電柱相對固定之凸塊下金屬化層來形成一垂直互連結構之方法。3a-3h illustrate a method of forming a vertical interconnect structure using conductive pillars and an under bump metallization layer that is fixed relative to the conductive pillars based on the alignment of the semiconductor grains.
圖4說明利用該些導電柱進行電性互連之堆疊半導體元件。Figure 4 illustrates a stacked semiconductor component electrically interconnected using the conductive pillars.
圖5說明具有形成於一頂側互連結構中之整合被動元件之半導體元件。Figure 5 illustrates a semiconductor component having integrated passive components formed in a topside interconnect structure.
圖6說明具有形成於一底側互連結構中之整合被動元件之半導體元件。Figure 6 illustrates a semiconductor component having integrated passive components formed in a bottom side interconnect structure.
圖7說明具有形成於一底側互連結構中之整合被動元件之半導體元件之另一實施例。Figure 7 illustrates another embodiment of a semiconductor component having integrated passive components formed in a bottom side interconnect structure.
124．．．導電層124. . . Conductive layer
126．．．凸塊下金屬化層126. . . Under bump metallization
128．．．導電柱或杆128. . . Conductive column or rod
130．．．半導體晶粒或構件130. . . Semiconductor die or member
134．．．金屬凸塊134. . . Metal bump
136．．．作用表面136. . . Surface
138．．．封膠劑或封膠化合物138. . . Sealant or sealant
140．．．頂側增層式互連結構140. . . Top side build-up interconnect structure
142．．．絕緣或保護層142. . . Insulation or protective layer
144．．．導電層144. . . Conductive layer
146．．．絕緣或保護層146. . . Insulation or protective layer
150．．．底側增層式互連結構150. . . Bottom side build-up interconnect structure
152．．．導電層152. . . Conductive layer
154．．．絕緣或保護層154. . . Insulation or protective layer
156．．．圓球或凸塊156. . . Ball or bump
160．．．半導體元件160. . . Semiconductor component
Claims (15)
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| US12/476,447 US8072059B2 (en) | 2006-04-19 | 2009-06-02 | Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die |
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