TWI517161B - Supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array - Google Patents
Supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array Download PDFInfo
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Description
本發明是有關於資料儲存技術之領域,且特別是有關於一種電源電壓產生電路與用於記憶陣列之電源電壓產生電路的操作方法。 The present invention relates to the field of data storage technology, and more particularly to a method of operating a power supply voltage generating circuit and a power supply voltage generating circuit for a memory array.
非揮發性(non-volatile)記憶體是一種即使在無外部電源供電的情況下,也能夠保存其儲存資料的一種記憶體。由於這種記憶體本身不需要浪費電力在資料的記憶上,因此特別適合使用在攜帶式的裝置上。 A non-volatile memory is a type of memory that retains stored data even when it is not powered by an external power source. Since the memory itself does not need to waste power on the memory of the data, it is particularly suitable for use on a portable device.
非揮發性記憶體有三種操作方式:讀取(read)、寫入(write)與抹除(erase)。其中,寫入操作即所謂的程式化(program)操作。一般而言,非揮發性記憶體在執行這三種操作時所需要的電壓都不一樣。而由於非揮發性記憶體對於其執行程式化操作時所需之程式化電壓的位準精確度要求越來越嚴格,因此其所需之程式化電壓必須非常精準。 Non-volatile memory has three modes of operation: read, write, and erase. Among them, the write operation is a so-called program operation. In general, non-volatile memory requires different voltages to perform these three operations. Since the non-volatile memory requires more and more stringent precision for the stylized voltages required to perform the stylized operation, the required stylized voltage must be very accurate.
本發明提供一種電源電壓產生電路,其適用於一記憶陣列。此電源電壓產生電路可提供較精準的一電源電壓來當作程式化電壓使用。 The present invention provides a power supply voltage generating circuit that is suitable for use in a memory array. This supply voltage generation circuit provides a more accurate supply voltage for use as a stylized voltage.
本發明另提供一種對應於上述電源電壓產生電路之操作 方法。 The present invention further provides an operation corresponding to the above-described power supply voltage generating circuit method.
本發明再提供一種記憶體,其內部所產生之一電源電壓可當作程式化電壓使用,且此種記憶體改善了程式化電壓之傳輸路徑上的元件的溫度、製程變異對程式化電壓的影響。 The present invention further provides a memory in which a power supply voltage is generated as a stylized voltage, and the memory improves the temperature of the component on the transmission path of the stylized voltage, and the variation of the process to the programmed voltage influences.
本發明提出一種電源電壓產生電路,其適用於一記憶陣列,其中此記憶陣列包括有多個記憶單元。此電源電壓產生電路包括一比較單元、一電壓位準控制單元與一穩壓電路。所述之比較單元用以對上述記憶陣列的一輸入資料與一輸出資料進行比較,以產生一比較結果,其中上述之輸出資料係記憶陣列中已依上述輸入資料進行過一程式化操作之多個記憶單元所存有的一儲存資料,而比較結果係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的。所述之電壓位準控制單元用以依據比較結果產生一控制訊號。而所述之穩壓電路用以提供上述記憶陣列所需之一電源電壓,並依據控制訊號來改變電源電壓的大小。 The present invention provides a power supply voltage generating circuit suitable for use in a memory array wherein the memory array includes a plurality of memory cells. The power voltage generating circuit includes a comparing unit, a voltage level control unit and a voltage stabilizing circuit. The comparing unit is configured to compare an input data of the memory array with an output data to generate a comparison result, wherein the output data is in a memory array and has been subjected to a stylized operation according to the input data. A stored data stored in the memory unit, and the comparison result shows that the output data is different from the number of bits of the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage stabilizing circuit is configured to provide a power supply voltage required by the memory array, and change the power supply voltage according to the control signal.
本發明另提出一種用於記憶陣列之電源電壓產生電路的操作方法。所述之記憶陣列包括有多個記憶單元,且此記憶陣列電性耦接一解碼器。所述之解碼器包括有一輸入端與多個輸出端,且每一輸出端電性耦接上述記憶單元的其中一部分。所述之操作方法包括有下列步驟:依據上述記憶陣列之一輸入資料來提供一電源電壓至上述解碼器的輸入端;對上述輸入資料與記憶陣列之一輸出資料進行比較,以產生一比較結果,其中上述之輸出資料係記憶陣列中已依上述輸入資料進行過一程式化操作之多個記憶單元所存有的一儲存資料,而比較結果係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的;以及當比較結果顯示出至少有一個位元的資料 是不同的時候,便依據比較結果來改變電源電壓的大小。 The present invention further provides an operational method for a power supply voltage generating circuit of a memory array. The memory array includes a plurality of memory units, and the memory array is electrically coupled to a decoder. The decoder includes an input end and a plurality of output ends, and each output end is electrically coupled to a part of the memory unit. The operation method includes the following steps: providing a power voltage to an input end of the decoder according to one of the input data of the memory array; comparing the input data with an output data of the memory array to generate a comparison result The output data is a stored data stored in a plurality of memory cells of the memory array that have been subjected to a stylized operation according to the input data, and the comparison result shows how much of the output data is relative to the input data. The information of one bit is different; and when the comparison shows at least one bit of data When it is different, the power supply voltage is changed according to the comparison result.
本發明再提出一種記憶體,其包括一記憶陣列、一解碼器與一穩壓電路。所述之記憶陣列包括有多條源極線與多個記憶單元,且每一源極線電性耦接該些記憶單元的其中一部分。所述之解碼器包括有一輸入端與多個輸出端,且解碼器之該些輸出端分別電性耦接該些源極線。而所述之穩壓電路用以提供一電源電壓至解碼器之輸入端,且穩壓電路電性耦接解碼器之該些輸出端,以依據解碼器之其中一輸出端所輸出的訊號與一控制訊號來對應產生一回授訊號,進而依據此回授訊號來改變上述電源電壓的大小。 The invention further provides a memory comprising a memory array, a decoder and a voltage stabilizing circuit. The memory array includes a plurality of source lines and a plurality of memory cells, and each of the source lines is electrically coupled to a portion of the memory cells. The decoder includes an input end and a plurality of output ends, and the output ends of the decoder are electrically coupled to the source lines respectively. The voltage stabilizing circuit is configured to provide a power supply voltage to the input end of the decoder, and the voltage stabilizing circuit is electrically coupled to the output ends of the decoder to output signals according to one of the output ends of the decoder. A control signal is correspondingly generated to generate a feedback signal, and the size of the power supply voltage is changed according to the feedback signal.
在本發明之電源電壓產生電路與電源電壓產生電路的操作方法中,係先對記憶陣列的一輸入資料與一輸出資料進行比較,以產生一比較結果,所述輸出資料係記憶陣列中已依上述輸入資料進行過一程式化操作之多個記憶單元所存有的一儲存資料,而所述比較結果係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的。因此,當比較結果顯示出至少有一個位元的資料是不同的時候,便可依據比較結果來改變電源電壓的大小。據此,本發明之電源電壓產生電路與電源電壓產生電路的操作方法便可提供較精準的電源電壓來當作程式化電壓使用。 In the method for operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention, an input data of the memory array is first compared with an output data to generate a comparison result, and the output data is in the memory array. The input data carries a stored data stored in a plurality of memory units of a stylized operation, and the comparison result indicates that the output data has different data relative to the input data. Therefore, when the comparison result shows that the data of at least one bit is different, the magnitude of the power supply voltage can be changed according to the comparison result. Accordingly, the method of operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention can provide a relatively accurate power supply voltage for use as a stylized voltage.
此外,在本發明之記憶體中,穩壓電路所產生的電源電壓可當作程式化電壓使用。而由於此穩壓電路更電性耦接解碼器所具有之多個輸出端,且此穩壓電路可依據解碼器之其中一輸出端所輸出的訊號與一控制訊號來對應產生一回授訊號,進而依據此回授訊號來改變上述電源電壓的大小,因此這種記憶體改善了程式化電壓之傳輸路徑上的元件的溫度、製程變異對程 式化電壓的影響。 Further, in the memory of the present invention, the power supply voltage generated by the voltage stabilizing circuit can be used as a stylized voltage. The voltage-stabilizing circuit is electrically coupled to the plurality of outputs of the decoder, and the voltage-stabilizing circuit can generate a feedback signal according to the signal outputted by one of the output ends of the decoder and a control signal. And further changing the magnitude of the power supply voltage according to the feedback signal, so the memory improves the temperature and process variation of the component on the transmission path of the stylized voltage. The effect of the voltage.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。 The above and other objects, features and advantages of the present invention will become more <RTIgt;
圖1為依照本發明一實施例之記憶體的示意圖,其僅繪示記憶體中與本發明相關的電路架構。請參照圖1,此記憶體100包括有資料輸入/輸出介面110、電源電壓產生電路120、電源電壓切換開關160、解碼器170與記憶陣列180。所述之記憶陣列180包括有多條源極線(如標示181所示)與多個記憶單元(如標示182所示),且每一源極線181電性耦接該些記憶單元182的其中一部分。而所述之解碼器170包括有一輸入端171與多個輸出端(如標示172所示)。在此例中,解碼器170之該些輸出端172分別電性耦接記憶陣列180之該些源極線181。從以上說明可知,解碼器170乃是一源極線解碼器。 1 is a schematic diagram of a memory device in accordance with an embodiment of the invention, showing only the circuit architecture associated with the present invention in memory. Referring to FIG. 1 , the memory 100 includes a data input/output interface 110 , a power voltage generating circuit 120 , a power voltage switching switch 160 , a decoder 170 , and a memory array 180 . The memory array 180 includes a plurality of source lines (as indicated by the numeral 181) and a plurality of memory cells (shown by the numeral 182), and each of the source lines 181 is electrically coupled to the memory units 182. Part of it. The decoder 170 includes an input 171 and a plurality of outputs (as indicated by reference numeral 172). In this example, the output terminals 172 of the decoder 170 are electrically coupled to the source lines 181 of the memory array 180, respectively. As can be seen from the above description, the decoder 170 is a source line decoder.
電源電壓切換開關160電性耦接於電源電壓產生電路120之輸出端與解碼器170之輸入端171之間,並用以接收電源電壓PV1與預設電壓PV2,進而依據控制命令CM來選擇輸出電源電壓PV1或預設電壓PV2至解碼器170之輸入端171。在此例中,電源電壓PV1是用來當作程式化電壓使用,而預設電壓PV2則例如是用來當作讀取電壓使用。 The power supply voltage switching switch 160 is electrically coupled between the output end of the power supply voltage generating circuit 120 and the input end 171 of the decoder 170, and is configured to receive the power supply voltage PV1 and the preset voltage PV2, and then select the output power according to the control command CM. The voltage PV1 or the preset voltage PV2 is input to the input terminal 171 of the decoder 170. In this example, the supply voltage PV1 is used as a stylized voltage, and the preset voltage PV2 is used, for example, as a read voltage.
電源電壓產生電路120包括比較單元130、電壓位準控制單元140與穩壓電路150。所述之比較單元130用以對記憶陣列180的一輸入資料與一輸出資料進行比較,以產生一比較結果CR。上述之輸出資料係記憶陣列180中已依上述輸入資料進行 過一程式化操作之多個記憶單元182所存有的一儲存資料,而比較結果CR係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的。此外,所述之電壓位準控制單元140用以依據比較結果CR產生控制訊號CS。而所述之穩壓電路150用以提供記憶陣列180所需之電源電壓PV1,並依據控制訊號CS來改變電源電壓PV1的大小。 The power supply voltage generating circuit 120 includes a comparing unit 130, a voltage level control unit 140, and a voltage stabilizing circuit 150. The comparing unit 130 is configured to compare an input data of the memory array 180 with an output data to generate a comparison result CR. The above output data is stored in the memory array 180 according to the above input data. A stored data stored in the plurality of memory units 182 of a stylized operation, and the comparison result CR indicates that the output data is different from the number of bits of the input data. In addition, the voltage level control unit 140 is configured to generate the control signal CS according to the comparison result CR. The voltage stabilizing circuit 150 is configured to provide a power supply voltage PV1 required by the memory array 180, and change the magnitude of the power supply voltage PV1 according to the control signal CS.
此外,為了取得上述之輸入資料與上述之輸出資料,比較單元130更電性耦接資料輸入/輸出介面110,以接收資料輸入/輸出介面110所傳輸之該輸入資料與該輸出資料。其中,資料輸入/輸出介面110還用以閂鎖上述之輸入資料。在此例中,資料輸入/輸出介面110更包括有輸入資料傳輸單元112與輸出資料傳輸單元114,其中輸入資料傳輸單元112用以傳輸並閂鎖上述之輸入資料,而輸出資料傳輸單元114用以傳輸上述之輸出資料。 In addition, in order to obtain the input data and the output data, the comparison unit 130 is further electrically coupled to the data input/output interface 110 to receive the input data and the output data transmitted by the data input/output interface 110. The data input/output interface 110 is also used to latch the input data. In this example, the data input/output interface 110 further includes an input data transmission unit 112 and an output data transmission unit 114, wherein the input data transmission unit 112 is configured to transmit and latch the input data, and the output data transmission unit 114 To transmit the above output data.
以下將說明電源電壓產生電路120之一實際操作方式,並以對四個記憶單元182進行程式化操作為例。請繼續參照圖1。電源電壓產生電路120可以是先依據記憶陣列180之一輸入資料來提供電源電壓PV1,以便將此電源電壓PV1當作程式化電壓來傳送至解碼器170的輸入端171。因此,記憶陣列180中之四個記憶單元182便可依據此時之程式化電壓的大小來進行一程式化操作,進而各自儲存一個位元的資料。接著,記憶體100便可將上述四個已依前述輸入資料進行過一程式化操作的四個記憶單元182所存有的一儲存資料(其包含四個位元的資料)傳送至資料輸入/輸出介面110,以當作記憶陣列180之一輸出資料。 An actual operation mode of one of the power supply voltage generating circuits 120 will be described below, and an example of the stylization operation of the four memory cells 182 will be described. Please continue to refer to Figure 1. The power supply voltage generating circuit 120 may first supply the power supply voltage PV1 according to one of the input data of the memory array 180 to transmit the power supply voltage PV1 as a stylized voltage to the input terminal 171 of the decoder 170. Therefore, the four memory cells 182 in the memory array 180 can perform a stylization operation according to the size of the stylized voltage at this time, thereby storing one bit of data respectively. Then, the memory 100 can transfer a stored data (including four-bit data) stored in the four memory units 182 that have been subjected to a stylization operation according to the input data to the data input/output. The interface 110 outputs data as one of the memory arrays 180.
因此,電源電壓產生電路120便可從資料輸入/輸出介面 110取得先前閂鎖的輸入資料與傳送至資料輸入/輸出介面110的輸出資料,並對取得的輸入資料與輸出資料進行比較,以產生比較結果CR。當比較結果CR顯示出上述輸出資料相對於上述輸入資料至少有一個位元的資料是不同的時候,電源電壓產生電路120便會依據比較結果CR來改變電源電壓PV1的大小。這是因為四個以下(不含四個)之記憶單元182所需要的程式化電壓大小係不同於四個記憶單元182所需要的程式化電壓大小所致。 Therefore, the power supply voltage generating circuit 120 can be accessed from the data input/output interface. 110 obtains the previously latched input data and the output data transmitted to the data input/output interface 110, and compares the obtained input data with the output data to generate a comparison result CR. When the comparison result CR indicates that the data of the output data is different from the input data by at least one bit, the power supply voltage generating circuit 120 changes the magnitude of the power supply voltage PV1 according to the comparison result CR. This is because the stylized voltage levels required for the four or fewer (excluding four) memory cells 182 are different from the stylized voltage levels required for the four memory cells 182.
假設比較結果CR顯示出上述輸出資料相對於上述輸入資料有二個位元的資料是不同的時候,電源電壓產生電路120便會將電源電壓PV1調低,以使調低後之電源電壓PV1的大小能符合二個記憶單元182所需要的程式化電壓大小。因此,上述二個儲存錯誤的記憶單元182便可依據此時之程式化電壓的大小來再次進行一程式化操作,以便儲存正確的資料。換句話說,越多位元的資料是不同的時候,電源電壓PV1就越大;而越少位元的資料是不同的時候,電源電壓PV1就越小。當然,上述輸入資料與輸出資料的比較操作可以重覆地進行,直到輸入資料與輸出資料吻合為止。此外,電壓位準控制單元140並非僅限於接收比較單元130所產生的比較結果CR,其也可以是直接接收來自記憶體100外部之比較結果CR’。也就是說,比較結果CR’係來自記憶陣列180所屬記憶體100之外部。 Assuming that the comparison result CR shows that the data of the output data has two bits relative to the input data, the power supply voltage generating circuit 120 lowers the power supply voltage PV1 to lower the power supply voltage PV1. The size can match the stylized voltage required by the two memory cells 182. Therefore, the two memory cells 182 that are incorrectly stored can perform a stylization operation again according to the size of the stylized voltage at this time to store the correct data. In other words, the more the bit data is different, the larger the power supply voltage PV1; and the less the bit data is different, the smaller the power supply voltage PV1. Of course, the comparison operation of the above input data and output data can be repeated until the input data and the output data match. Further, the voltage level control unit 140 is not limited to receiving the comparison result CR generated by the comparison unit 130, and may also directly receive the comparison result CR' from the outside of the memory 100. That is, the comparison result CR' is from the outside of the memory 100 to which the memory array 180 belongs.
由上述的說明可知,電源電壓產生電路120係可依照負載的大小(即所需驅動的記憶單元182的個數)來動態調整電源電壓PV1的大小。因此,電源電壓產生電路120可提供較精準的電源電壓PV1來當作程式化電壓使用。 As apparent from the above description, the power supply voltage generating circuit 120 can dynamically adjust the magnitude of the power supply voltage PV1 in accordance with the magnitude of the load (i.e., the number of memory cells 182 to be driven). Therefore, the power supply voltage generating circuit 120 can provide a more accurate power supply voltage PV1 for use as a stylized voltage.
以下將進一步說明電源電壓產生電路120中各構件的實際設計方式。圖1中之比較單元130可以採用數位式的資料比較方式、類比式的電流比較方式或類比式的電壓比較方式來比較前述之輸入資料與輸出資料。以數位式的資料比較方式而言,比較單元130可以是採用圖2所示之設計。 The actual design of each component in the power supply voltage generating circuit 120 will be further explained below. The comparing unit 130 in FIG. 1 can compare the input data and the output data by using a digital data comparison method, an analog current comparison method or an analog voltage comparison method. In the digital data comparison manner, the comparison unit 130 may adopt the design shown in FIG. 2.
圖2為圖1之比較單元的其中一種電路架構。請參照圖2,比較單元130包括有多個反閘(如標示132所示)、多個反及閘(如標示134所示)與多個D型正反器(如標示136所示)。這些反閘132之輸入端係互相電性耦接,並用以接收記憶陣列180之輸入資料DIN[0:N],其中N為自然數。每一反及閘134之其中一輸入端用以接收其中一反閘132的輸出訊號,每一反及閘134之另一輸入端係與其他反及閘134之另一輸入端互相電性耦接,並用以接收記憶陣列180之輸出資料DOUT[0:N]。 2 is a circuit diagram of one of the comparison units of FIG. 1. Referring to FIG. 2, the comparison unit 130 includes a plurality of reverse gates (as indicated by the numeral 132), a plurality of inverse gates (as indicated by the numeral 134), and a plurality of D-type flip-flops (as indicated by the numeral 136). The inputs of the reverse gates 132 are electrically coupled to each other and are used to receive input data DIN[0:N] of the memory array 180, where N is a natural number. One of the inputs of each of the anti-gates 134 is configured to receive an output signal of one of the anti-gates 132, and the other input of each of the anti-gates 134 is electrically coupled to the other input of the other of the anti-gates 134. Connected and used to receive the output data DOUT[0:N] of the memory array 180.
每一D型正反器136具有一資料輸入端D、一時脈訊號輸入端CLK、一重置訊號輸入端R與一資料輸出端Q。每一D型正反器136之資料輸入端D用以接收其中一反及閘134的輸出訊號。這些D型正反器136之該些時脈訊號輸入端CLK皆用以接收一時脈訊號CK,而此時脈訊號CK在前述輸入資料與前述輸出資料這二者需被比較時才會被產生。此外,這些D型正反器136之該些重置訊號輸入端R皆用以接收一重置訊號RS。而每一D型正反器136之資料輸出端Q用以提供一輸出訊號(如訊號Q1~Q4所示),且這些D型正反器136之該些輸出訊號用以形成比較結果CR。由圖2可知,這種比較單元130係以多級的電路來呈現,每級電路係可包括一個反閘132、一個反及閘134與一個D型正反器136。 Each D-type flip-flop 136 has a data input terminal D, a clock signal input terminal CLK, a reset signal input terminal R and a data output terminal Q. The data input terminal D of each D-type flip-flop 136 is configured to receive an output signal of one of the anti-gates 134. The clock signal input terminals CLK of the D-type flip-flops 136 are used to receive a clock signal CK, and the pulse signal CK is generated when the input data and the output data need to be compared. . In addition, the reset signal input terminals R of the D-type flip-flops 136 are used to receive a reset signal RS. The data output terminal Q of each D-type flip-flop 136 is used to provide an output signal (as shown by signals Q1 to Q4), and the output signals of the D-type flip-flops 136 are used to form a comparison result CR. As can be seen from FIG. 2, the comparison unit 130 is presented in a multi-stage circuit. Each stage of the circuit can include a reverse gate 132, a reverse gate 134 and a D-type flip-flop 136.
此外,圖1中之電壓位準控制單元140可以是儲存有一對照 表。此對照表係記錄欲進行程式化操作之記憶單元182的數目與欲提供之電源電壓PV1的大小的對應關係。如此一來,電壓位準控制單元140便可依據比較單元130所輸出的比較結果CR來查找此對照表,以依據一查找結果來產生控制訊號CS。 In addition, the voltage level control unit 140 in FIG. 1 may store a control. table. This comparison table records the correspondence between the number of memory cells 182 to be programmed and the magnitude of the power supply voltage PV1 to be supplied. In this way, the voltage level control unit 140 can search the comparison table according to the comparison result CR output by the comparison unit 130 to generate the control signal CS according to a search result.
至於圖1中之穩壓電路150,其可以是採用一低壓差穩壓器(Low Dropout Regulator)來實現。圖3即為圖1之穩壓電路的其中一種電路架構。請參照圖3,此穩壓電路150包括P型電晶體151、分壓電路152、多個開關(如標示153所示)、開關控制電路154與電壓比較器155。P型電晶體151的其中一源/汲極用以電性耦接操作電源VDD,而另一源/汲極用以提供電源電壓PV1。分壓電路152具有串聯之多個電阻(如標示152-1所示)。此分壓電路152的其中一端用以電性耦接P型電晶體151的另一源/汲極,而分壓電路152的另一端則用以電性耦接一參考電壓,例如是一接地電壓GND。 As for the voltage stabilizing circuit 150 of FIG. 1, it can be implemented by a Low Dropout Regulator. FIG. 3 is one of the circuit architectures of the voltage regulator circuit of FIG. 1. Referring to FIG. 3, the voltage stabilizing circuit 150 includes a P-type transistor 151, a voltage dividing circuit 152, a plurality of switches (as indicated by reference numeral 153), a switch control circuit 154, and a voltage comparator 155. One source/drain of the P-type transistor 151 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. The voltage divider circuit 152 has a plurality of resistors in series (as indicated by reference numeral 152-1). One end of the voltage dividing circuit 152 is electrically coupled to another source/drain of the P-type transistor 151, and the other end of the voltage dividing circuit 152 is electrically coupled to a reference voltage, for example, A ground voltage GND.
此外,每一開關153皆具有第一端(如標示153-1所示)、第二端(如標示153-2所示)與控制端(如標示153-3所示)。每一開關153之第一端153-1與第二端153-2分別電性耦接分壓電路152之其中一電阻152-1的二端,且每一開關153依據其控制端153-3所接收到的訊號而決定是否導通。開關控制電路154電性耦接該些開關153之該些控制端153-3,並用以依據電壓位準控制單元140所輸出的控制訊號CS來決定要導通哪些開關153。至於電壓比較器155,其具有正輸入端(以+號來標示)、負輸入端(以-號來標示)與輸出端。電壓比較器155之正輸入端用以接收另一參考電壓VREF,電壓比較器155之負輸入端電性耦接至分壓電路152之其中二個電阻152-1的相互電性耦接處,此相互電性耦接處用以提供一回授訊號FB,而 電壓比較器155之輸出端係電性耦接P型電晶體151的閘極。 In addition, each switch 153 has a first end (as indicated by reference numeral 153-1), a second end (as indicated by reference numeral 153-2) and a control end (as indicated by reference numeral 153-3). The first end 153-1 and the second end 153-2 of each switch 153 are electrically coupled to the two ends of one of the resistors 152-1 of the voltage dividing circuit 152, and each switch 153 is based on its control end 153- 3 received signals to determine whether to turn on. The switch control circuit 154 is electrically coupled to the control terminals 153-3 of the switches 153, and is configured to determine which switches 153 to be turned on according to the control signal CS output by the voltage level control unit 140. As for the voltage comparator 155, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 155 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 155 is electrically coupled to the mutual electrical coupling of the two resistors 152-1 of the voltage dividing circuit 152. The mutual electrical coupling is used to provide a feedback signal FB, and The output of the voltage comparator 155 is electrically coupled to the gate of the P-type transistor 151.
另外,為了改善了程式化電壓之傳輸路徑上的元件的溫度、製程變異對程式化電壓的影響,電源電壓產生電路中的穩壓電路係可採用不同的回授方式,例如以圖4或圖6所示方式來設計。請先參照圖4,其為依照本發明另一實施例之記憶體的示意圖,且其僅繪示記憶體中與本發明相關的電路架構。此記憶體400與前述記憶體100的不同之處,在於此記憶體400之電源電壓產生電路420中的穩壓電路450更電性耦接解碼器170所包括有之輸入端171,且此穩壓電路450還用以依據前述輸入端171所接收到的訊號與控制訊號CS而對應產生一回授訊號,進而依據此回授訊號來改變電源電壓PV1的大小。 In addition, in order to improve the influence of the temperature of the components on the transmission path of the stylized voltage and the variation of the process on the stylized voltage, the voltage regulator circuit in the power supply voltage generating circuit can adopt different feedback methods, for example, as shown in FIG. 4 or 6 is designed to be designed. Please refer to FIG. 4, which is a schematic diagram of a memory according to another embodiment of the present invention, and only shows the circuit architecture related to the present invention in the memory. The memory 400 differs from the memory 100 in that the voltage regulator circuit 450 in the power voltage generating circuit 420 of the memory 400 is more electrically coupled to the input terminal 171 included in the decoder 170, and is stable. The voltage circuit 450 is further configured to generate a feedback signal according to the signal received by the input terminal 171 and the control signal CS, and then change the magnitude of the power supply voltage PV1 according to the feedback signal.
圖5即繪有圖4之穩壓電路的其中一種電路架構。請參照圖5,此穩壓電路450包括P型電晶體451、分壓電路452、多個開關(如標示453所示)、開關控制電路454與電壓比較器455。P型電晶體451之其中一源/汲極用以電性耦接操作電源VDD,而另一源/汲極用以提供電源電壓PV1。分壓電路452具有串聯之多個電阻(如標示452-1所示)。此分壓電路452的其中一端用以電性耦接解碼器170之輸入端171,而分壓電路452的另一端則用以電性耦接一參考電壓,例如是一接地電壓GND。 FIG. 5 depicts one of the circuit architectures of the voltage regulator circuit of FIG. Referring to FIG. 5, the voltage stabilizing circuit 450 includes a P-type transistor 451, a voltage dividing circuit 452, a plurality of switches (as indicated by reference numeral 453), a switch control circuit 454, and a voltage comparator 455. One of the source/drain electrodes of the P-type transistor 451 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. Voltage divider circuit 452 has a plurality of resistors in series (as indicated by reference 452-1). One end of the voltage dividing circuit 452 is electrically coupled to the input end 171 of the decoder 170, and the other end of the voltage dividing circuit 452 is electrically coupled to a reference voltage, such as a ground voltage GND.
此外,每一開關453具有第一端(如標示453-1所示)、第二端(如標示453-2所示)與控制端(如標示453-3所示),且每一開關453之第一端453-1與第二端453-2分別電性耦接分壓電路452之其中一電阻452-1的二端。開關控制電路454電性耦接該些開關453之該些控制端453-3,並用以依據電壓位準控制單元140所輸出的控制訊號CS來決定要導通哪些開關 453。至於電壓比較器455,其具有正輸入端(以+號來標示)、負輸入端(以-號來標示)與輸出端。電壓比較器455之正輸入端用以接收另一參考電壓VREF,電壓比較器455之負輸入端電性耦接至分壓電路452之其中二個電阻452-1的相互電性耦接處,所述之相互電性耦接處用以提供前述之回授訊號(以FB來標示),而電壓比較器455之輸出端係電性耦接P型電晶體451之閘極。 In addition, each switch 453 has a first end (as indicated by the reference 453-1), a second end (as indicated by the reference 453-2) and a control end (as indicated by the reference 453-3), and each switch 453 The first end 453-1 and the second end 453-2 are electrically coupled to the two ends of one of the resistors 452-1 of the voltage dividing circuit 452, respectively. The switch control circuit 454 is electrically coupled to the control terminals 453-3 of the switches 453, and is configured to determine which switches to be turned on according to the control signal CS output by the voltage level control unit 140. 453. As for the voltage comparator 455, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 455 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 455 is electrically coupled to the mutual electrical coupling of the two resistors 452-1 of the voltage dividing circuit 452. The electrical coupling is used to provide the aforementioned feedback signal (indicated by FB), and the output of the voltage comparator 455 is electrically coupled to the gate of the P-type transistor 451.
圖6為依照本發明再一實施例之記憶體的示意圖,且其僅繪示記憶體中與本發明相關的電路架構。此記憶體600與前述記憶體100的不同之處,在於此記憶體600之電源電壓產生電路620中的穩壓電路650更電性耦接解碼器170所包括有之多個輸出端172中的每一個輸出端172,並用以依據其中一輸出端172所輸出的訊號與控制訊號CS而對應產生一回授訊號,進而依據此回授訊號來改變電源電壓PV1的大小。 FIG. 6 is a schematic diagram of a memory according to still another embodiment of the present invention, and only shows a circuit architecture related to the present invention in a memory. The difference between the memory 600 and the memory 100 is that the voltage regulator circuit 650 in the power voltage generating circuit 620 of the memory 600 is more electrically coupled to the plurality of outputs 172 included in the decoder 170. Each of the output terminals 172 is configured to generate a feedback signal according to the signal outputted by one of the output terminals 172 and the control signal CS, and then change the magnitude of the power supply voltage PV1 according to the feedback signal.
圖7即繪有圖6之穩壓電路的其中一種電路架構。請參照圖7,此穩壓電路650包括P型電晶體651、分壓電路652、多個開關(如標示653所示)、開關控制電路654、電壓比較器655與選擇電路656。P型電晶體651之其中一源/汲極用以電性耦接操作電源VDD,而另一源/汲極用以提供電源電壓PV1。選擇電路656具有多個輸入端(如標示656-1所示)與一輸出端656-2。此選擇電路656之該些輸入端656-1分別電性耦接解碼器170之該些輸出端172,且選擇電路656用以依據選擇訊號SL來選擇該些輸入端656-1的其中之一,以將選定之輸入端656-1所接收到的訊號自選擇電路656之輸出端656-2輸出。 FIG. 7 is a circuit diagram of one of the voltage regulator circuits of FIG. Referring to FIG. 7, the voltage stabilizing circuit 650 includes a P-type transistor 651, a voltage dividing circuit 652, a plurality of switches (as indicated by reference numeral 653), a switch control circuit 654, a voltage comparator 655, and a selection circuit 656. One of the source/drain electrodes of the P-type transistor 651 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. Selection circuit 656 has a plurality of inputs (as indicated by reference 656-1) and an output 656-2. The input terminals 656-1 of the selection circuit 656 are electrically coupled to the output terminals 172 of the decoder 170, respectively, and the selection circuit 656 is configured to select one of the input terminals 656-1 according to the selection signal SL. The signal received by the selected input terminal 656-1 is output from the output terminal 656-2 of the selection circuit 656.
此外,分壓電路652具有串聯之多個電阻(如標示652-1 所示)。此分壓電路652的其中一端用以電性耦接選擇電路656之輸出端656-2,而分壓電路656的另一端則用以電性耦接一參考電壓,例如是一接地電壓GND。每一開關653具有第一端(如標示653-1所示)、第二端(如標示653-2所示)與控制端(如標示653-3所示),且每一開關653之第一端653-1與第二端653-2分別電性耦接分壓電路652之其中一電阻652-1的二端。開關控制電路654電性耦接該些開關653之該些控制端653-3,並用以依據控制訊號CS來決定要導通哪些開關653。 In addition, the voltage dividing circuit 652 has a plurality of resistors connected in series (eg, 652-1) Shown). One end of the voltage dividing circuit 652 is electrically coupled to the output end 656-2 of the selecting circuit 656, and the other end of the voltage dividing circuit 656 is electrically coupled to a reference voltage, such as a ground voltage. GND. Each switch 653 has a first end (as indicated by reference 653-1), a second end (as indicated by reference 653-2) and a control end (as indicated by reference 653-3), and each switch 653 The one end 653-1 and the second end 653-2 are electrically coupled to the two ends of one of the resistors 652-1 of the voltage dividing circuit 652, respectively. The switch control circuit 654 is electrically coupled to the control terminals 653-3 of the switches 653 and configured to determine which switches 653 to be turned on according to the control signal CS.
至於電壓比較器655,其具有正輸入端(以+號來標示)、負輸入端(以-號來標示)與輸出端。電壓比較器655之正輸入端用以接收另一參考電壓VREF,電壓比較器655之負輸入端電性耦接至分壓電路652之其中二個電阻652-1的相互電性耦接處,所述之相互電性耦接處用以提供前述之回授訊號(以FB來標示),而電壓比較器655之輸出端係電性耦接P型電晶體651之閘極。 As for the voltage comparator 655, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 655 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 655 is electrically coupled to the mutual electrical coupling of the two resistors 652-1 of the voltage dividing circuit 652. The electrical coupling is used to provide the aforementioned feedback signal (indicated by FB), and the output of the voltage comparator 655 is electrically coupled to the gate of the P-type transistor 651.
根據上述各實施例之教示,本領域具有通常知識者當可歸納出前述各電源電壓產生電路的基本操作方式,其步驟一如圖8所示。圖8為依照本發明一實施例之用於記憶陣列之電源電壓產生電路的操作方法的流程圖。所述之記憶陣列包括有多個記憶單元,且此記憶陣列電性耦接一解碼器。所述之解碼器包括有一輸入端與多個輸出端,且其每一輸出端電性耦接上述記憶單元的其中一部分。此操作方法之步驟包括:依據上述記憶陣列之一輸入資料來提供一電源電壓至上述解碼器的輸入端(如步驟S802所示);對上述輸入資料與記憶陣列之一輸出資料進行比較,以產生一比較結果,其中上述輸出資料係記憶陣列中已依上述輸入資料進行過一程式化操作之多個記憶單元 所存有的一儲存資料,而比較結果係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的(如步驟S804所示);以及當比較結果顯示出至少有一個位元的資料是不同的時候,便依據比較結果來改變電源電壓的大小(如步驟S806所示)。 According to the teachings of the above embodiments, those skilled in the art can generalize the basic operation modes of the foregoing power supply voltage generating circuits, and the first step is as shown in FIG. FIG. 8 is a flow chart showing an operation method of a power supply voltage generating circuit for a memory array in accordance with an embodiment of the present invention. The memory array includes a plurality of memory units, and the memory array is electrically coupled to a decoder. The decoder includes an input end and a plurality of output ends, and each of the output ends is electrically coupled to a portion of the memory unit. The method includes the following steps: providing a power voltage to the input end of the decoder according to one of the input data of the memory array (as shown in step S802); comparing the input data with the output data of one of the memory arrays, Generating a comparison result, wherein the output data is a plurality of memory cells in the memory array that have been subjected to a stylization operation according to the input data a stored data stored, and the comparison result shows that the output data is different from the number of bits of the input data (as shown in step S804); and when the comparison result shows at least one bit When the data of the meta is different, the magnitude of the power supply voltage is changed according to the comparison result (as shown in step S806).
綜上所述,在本發明之電源電壓產生電路與電源電壓產生電路的操作方法中,係先對記憶陣列的一輸入資料與一輸出資料進行比較,以產生一比較結果,所述輸出資料係記憶陣列中已依上述輸入資料進行過一程式化操作之多個記憶單元所存有的一儲存資料,而所述比較結果係顯示出上述輸出資料相對於上述輸入資料尚有多少個位元的資料是不同的。因此,當比較結果顯示出至少有一個位元的資料是不同的時候,便可依據比較結果來改變電源電壓的大小。據此,本發明之電源電壓產生電路與電源電壓產生電路的操作方法便可提供較精準的電源電壓來當作程式化電壓使用。 In summary, in the operating method of the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention, an input data of the memory array is first compared with an output data to generate a comparison result, and the output data is a stored data stored in a plurality of memory cells of the memory array that have been subjected to a stylized operation according to the input data, and the comparison result shows how many bits of the output data are relative to the input data. It is different. Therefore, when the comparison result shows that the data of at least one bit is different, the magnitude of the power supply voltage can be changed according to the comparison result. Accordingly, the method of operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention can provide a relatively accurate power supply voltage for use as a stylized voltage.
此外,在本發明之記憶體中,穩壓電路所產生的電源電壓可當作程式化電壓使用。而由於此穩壓電路更電性耦接解碼器所具有之多個輸出端,且此穩壓電路可依據解碼器之其中一輸出端所輸出的訊號與一控制訊號來對應產生一回授訊號,進而依據此回授訊號來改變上述電源電壓的大小,因此這種記憶體改善了程式化電壓之傳輸路徑上的元件的溫度、製程變異對程式化電壓的影響。 Further, in the memory of the present invention, the power supply voltage generated by the voltage stabilizing circuit can be used as a stylized voltage. The voltage-stabilizing circuit is electrically coupled to the plurality of outputs of the decoder, and the voltage-stabilizing circuit can generate a feedback signal according to the signal outputted by one of the output ends of the decoder and a control signal. Then, according to the feedback signal, the magnitude of the power supply voltage is changed. Therefore, the memory improves the influence of the temperature of the component on the transmission path of the stylized voltage and the variation of the process on the stylized voltage.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100、400、600‧‧‧記憶體 100, 400, 600‧‧‧ memory
110‧‧‧資料輸入/輸出介面 110‧‧‧Data input/output interface
112‧‧‧輸入資料傳輸單元 112‧‧‧Input data transmission unit
114‧‧‧輸出資料傳輸單元 114‧‧‧Output data transmission unit
120、420、620‧‧‧電源電壓產生電路 120, 420, 620‧‧‧ power supply voltage generating circuit
130‧‧‧比較單元 130‧‧‧Comparative unit
132‧‧‧反閘 132‧‧‧Backgate
134‧‧‧反及閘 134‧‧‧Anti-gate
136‧‧‧D型正反器 136‧‧‧D type flip-flop
140‧‧‧電壓位準控制單元 140‧‧‧Voltage level control unit
150、450、650‧‧‧穩壓電路 150, 450, 650‧‧‧ voltage regulator circuit
151、451、651‧‧‧P型電晶體 151, 451, 651‧‧‧P type transistor
152、452、652‧‧‧分壓電路 152, 452, 652‧‧ ‧ voltage divider circuit
152-1、452-1、652-1‧‧‧電阻 152-1, 452-1, 652-1‧‧‧ resistance
153、453、653‧‧‧開關 153, 453, 653‧ ‧ switch
153-1、453-1、653-1‧‧‧第一端 153-1, 453-1, 653-1‧‧‧ first end
153-2、453-2、653-2‧‧‧第二端 153-2, 453-2, 653-2‧‧‧ second end
153-3、453-3、653-3‧‧‧控制端 153-3, 453-3, 653-3‧‧‧ control terminal
154、454、654‧‧‧開關控制電路 154, 454, 654‧‧ ‧ switch control circuit
155、455、655‧‧‧電壓比較器 155, 455, 655‧‧‧ voltage comparator
160‧‧‧電源電壓切換開關 160‧‧‧Power supply voltage switch
170‧‧‧解碼器 170‧‧‧Decoder
171、656-1‧‧‧輸入端 171,656-1‧‧‧ input
172、656-2‧‧‧輸出端 172, 656-2‧‧‧ output
180‧‧‧記憶陣列 180‧‧‧ memory array
181‧‧‧源極線 181‧‧‧ source line
182‧‧‧記憶單元 182‧‧‧ memory unit
656‧‧‧選擇電路 656‧‧‧Selection circuit
CK‧‧‧時脈訊號 CK‧‧‧ clock signal
CLK‧‧‧時脈訊號輸入端 CLK‧‧‧ clock signal input
CM‧‧‧控制命令 CM‧‧‧ control order
CR‧‧‧比較結果 CR‧‧‧ comparison results
CR’‧‧‧比較結果 CR’‧‧‧ comparison results
CS‧‧‧控制訊號 CS‧‧‧Control signal
D‧‧‧資料輸入端 D‧‧‧ data input
DIN[0:N]‧‧‧輸入資料 DIN[0:N]‧‧‧ Input data
DOUT[0:N]‧‧‧輸出資料 DOUT[0:N]‧‧‧Output data
FB‧‧‧回授訊號 FB‧‧‧ feedback signal
GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage
PV1‧‧‧電源電壓 PV1‧‧‧Power supply voltage
PV2‧‧‧預設電壓 PV2‧‧‧Preset voltage
Q‧‧‧資料輸出端 Q‧‧‧ data output
Q1~Q4‧‧‧輸出訊號 Q1~Q4‧‧‧ output signal
R‧‧‧重置訊號輸入端 R‧‧‧Reset signal input
RS‧‧‧重置訊號 RS‧‧‧Reset signal
SL‧‧‧選擇訊號 SL‧‧‧Select signal
VDD‧‧‧操作電源 VDD‧‧‧Operating power supply
VREF‧‧‧參考電壓 VREF‧‧‧reference voltage
S802~S806‧‧‧步驟 S802~S806‧‧‧Steps
+‧‧‧正輸入端 +‧‧‧正Input
-‧‧‧負輸入端 -‧‧‧negative input
圖1為依照本發明一實施例之記憶陣列的示意圖。 1 is a schematic diagram of a memory array in accordance with an embodiment of the present invention.
圖2為圖1之比較單元的其中一種電路架構。 2 is a circuit diagram of one of the comparison units of FIG. 1.
圖3為圖1之穩壓電路的其中一種電路架構。 FIG. 3 is one of the circuit architectures of the voltage regulator circuit of FIG. 1.
圖4為依照本發明另一實施例之記憶陣列的示意圖。 4 is a schematic diagram of a memory array in accordance with another embodiment of the present invention.
圖5繪有圖4之穩壓電路的其中一種電路架構。 FIG. 5 depicts one of the circuit architectures of the voltage regulator circuit of FIG.
圖6為依照本發明再一實施例之記憶陣列的示意圖。 6 is a schematic diagram of a memory array in accordance with still another embodiment of the present invention.
圖7繪有圖6之穩壓電路的其中一種電路架構。 Figure 7 depicts one of the circuit architectures of the voltage regulator circuit of Figure 6.
圖8為依照本發明一實施例之用於記憶陣列之電源電壓產生電路的操作方法的流程圖。 FIG. 8 is a flow chart showing an operation method of a power supply voltage generating circuit for a memory array in accordance with an embodiment of the present invention.
S802~S806‧‧‧步驟 S802~S806‧‧‧Steps
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