TWI514530B - 線路基板、半導體封裝結構及線路基板製程 - Google Patents

線路基板、半導體封裝結構及線路基板製程 Download PDF

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TWI514530B
TWI514530B TW102130846A TW102130846A TWI514530B TW I514530 B TWI514530 B TW I514530B TW 102130846 A TW102130846 A TW 102130846A TW 102130846 A TW102130846 A TW 102130846A TW I514530 B TWI514530 B TW I514530B
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plating
openings
circuit substrate
bonding
layer
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TW102130846A
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TW201508879A (zh
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Chen Yueh Kung
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Via Tech Inc
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Priority to TW102130846A priority Critical patent/TWI514530B/zh
Priority to US14/054,850 priority patent/US10103115B2/en
Priority to CN201310484756.3A priority patent/CN103545286B/zh
Publication of TW201508879A publication Critical patent/TW201508879A/zh
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Publication of TWI514530B publication Critical patent/TWI514530B/zh
Priority to US16/121,654 priority patent/US10573614B2/en

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Description

線路基板、半導體封裝結構及線路基板製程
本發明是有關於應用於半導體封裝領域的線路基板、半導體封裝結構及線路基板製程。
在半導體封裝技術領域中，晶片載體(chip carrier)是一種用以將積體電路晶片(IC chip)連接至下一層級的電子元件，例如主機板或模組板等。具有高佈線密度的線路基板(circuit board)經常作為高接點數的晶片載體。線路基板主要由多個圖案化導體層(patterned conductive layer)及多個介電層(dielectric layer)交替疊合而成，而兩圖案化導體層之間可透過導體孔(conductive via)來彼此電性連接。
覆晶接合(flip-chip bonding)是一種應用於高接點數(high pin count)的晶片封裝技術，其通常採用線路基板作為晶片載體，並透過多個以面陣列方式排列的導電凸塊(conductive bump)，以將晶片電連接至線路基板的多個接墊。為了減少接墊之 間的間距來提高接墊的密度，一種習知的作法是利用線路基板上的防銲層的大型開口來完全暴露出線路基板上的晶片接合區，並藉由線路基板上的走線(trace)位在晶片接合區內的一接合區段(bonding segment)來銲接至對應的導體凸塊。
承上所述，當兩個相鄰的接合區段之間存在另一條走線的一過渡區段(transitional segment)時，為了減少這兩相鄰的接合區段之間的距離，需窄化上述的過渡區段。然而，為了確保過渡區段能提供電性傳輸的功能，過渡區段的窄化有其限制，這將不利於相鄰二接合區段之間距的減少。此外，接合區段的接合面積取決於走線的寬度及厚度。為了確保接合區段具有足夠的接合面積，走線的窄化也有其限制，這也不利於相鄰二接合區段之間距的減少。
本發明提供一種線路基板，應用於半導體封裝技術。
本發明提供一種半導體封裝結構，以應用於封裝半導體積體電路晶片。
本發明提供一種線路基板製程，用以製作出應用於半導體封裝領域的線路基板。
本發明的一種線路基板，其包括一線路疊構、一圖案化導體層、一介電層及多個增厚導體層。線路疊構具有一表面。圖案化導體層配置在表面上並具有多個走線。各走線具有一接合區 段。介電層配置在表面上且覆蓋圖案化導體層。介電層具有多個接合開口，各接合開口暴露出對應的接合區段。各增厚導體層配置在對應的接合區段上。
本發明的一種半導體封裝結構，包括一線路基板及一晶片。線路基板包括一線路疊構、一圖案化導體層、一介電層及多個增厚導體層。線路疊構具有一表面。圖案化導體層配置在表面上並具有多個走線。各走線具有一接合區段。介電層配置在表面上且覆蓋圖案化導體層。介電層具有多個接合開口，各接合開口暴露出對應的接合區段。各增厚導體層配置在對應的接合區段上。晶片連接這些增厚導體層。
本發明的一種線路基板製程，包括下列步驟。提供一線路疊構及一圖案化導體層，其中線路疊構具有一表面，圖案化導體層配置在表面上且具有多個走線，且各走線具有一接合區段及一電鍍區段。形成一介電層覆蓋表面及圖案化導體層，其中介電層具有多個接合開口及多個電鍍開口，各接合開口暴露出對應的接合區段，且各電鍍開口暴露出對應的電鍍區段。形成一電鍍種子層覆蓋表面、這些接合區段、這些電鍍區段及介電層。形成一罩幕覆蓋電鍍種子層，其中罩幕具有多個罩幕開口，且各罩幕開口暴露出電鍍種子層在對應的接合區段上的一部分。以罩幕為蝕刻罩幕蝕刻電鍍種子層，以移除電鍍種子層在這些接合區段上的這些部分而暴露出這些接合區段。在蝕刻電鍍種子層以後，以罩幕為電鍍罩幕並經由電鍍種子層及這些走線，在各接合區段上電 鍍一增厚導體層。在電鍍這些增厚導體層以後，移除罩幕及電鍍種子層。
基於上述，本發明藉由在接合區段上形成增厚導體層，以增加接合區段的寬度及高度，因而增加接合面積。另外，在本發明的線路基板製程中，利用介電層之電鍍開口暴露出走線的電鍍區段，以藉此作為電流路徑在走線的接合區段上電鍍增厚導體層。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧半導體封裝結構
12‧‧‧晶片
14‧‧‧導電凸塊
14a‧‧‧銲料
16‧‧‧底膠
18‧‧‧導電球
100‧‧‧線路基板
110‧‧‧線路疊構
110a、110b、202a‧‧‧表面
120、180、204‧‧‧圖案化導體層
122、206‧‧‧走線
122a、206a‧‧‧接合區段
122a-1、206a-1‧‧‧頂面
122a-2、206a-2‧‧‧側面
122b、206b‧‧‧電鍍區段
130、190、208‧‧‧介電層
132a、208a‧‧‧接合開口
132b、208b‧‧‧電鍍開口
140、214‧‧‧增厚導體層
182‧‧‧接墊
202‧‧‧線路疊構
210‧‧‧電鍍種子層
212‧‧‧罩幕
212a‧‧‧罩幕開口
B‧‧‧晶片接合區
P‧‧‧晶片投影區
X、Y‧‧‧部位
圖1為本發明的一實施例的一種線路基板的俯視圖。
圖2為圖1之線路基板的X部位的放大圖。
圖3A為圖2之局部的線路基板沿線3A-3A的剖視圖。
圖3B為圖2之局部的線路基板沿線3B-3B的剖視圖。
圖3C為圖2之局部的線路基板沿線3C-3C的剖視圖。
圖4A為圖2之局部的線路基板的圖案化導體層的走線的局部的立體圖。
圖4B為圖2之局部的線路基板的圖案化導體層的走線的局部及增厚導體層的立體圖。
圖5為本發明的一實施例的一種半導體封裝結構的俯視圖。
圖6為圖5之半導體封裝結構沿線6-6的剖面圖。
圖7為圖5之線路基板的Y部位的放大圖。
圖8A為圖7之局部的線路基板沿線8A-8A的剖視圖。
圖8B為圖7之局部的線路基板沿線8B-8B的剖視圖。
圖8C為圖7之局部的線路基板沿線8C-8C的剖視圖。
圖9A至圖9G為本發明之另一實施例的一種線路基板製程的局部俯視圖。
圖10A至圖10G分別為圖9A至圖9G之線路基板沿著線I-I的上半部剖面圖。
圖11A至圖11G分別為圖9A至圖9G之線路基板沿著線II-II的上半部剖面圖。
圖1為本發明的一實施例的一種線路基板的俯視圖，圖2為圖1之線路基板的X部位的放大圖，圖3A為圖2之局部的線路基板沿線3A-3A的剖視圖，圖3B為圖2之局部的線路基板沿線3B-3B的剖視圖，而圖3C為圖2之局部的線路基板沿線3C-3C的剖視圖。請參考圖1、圖2及圖3A至圖3C，本實施例之線路基板100包括一線路疊構110。線路疊構110具有一表面110a。在本實施例中，線路疊構110由多個圖案化導體層及一或多個介電層交替疊合而成，而這些圖案化導體層之間可透過這些導體孔而彼此電性連接。然而，本發明不以此為限。在其他未繪示實施例 中，線路疊構110亦可由其他數量的圖案化導體層及介電層交替疊合而成。在另一未繪示實施例中，線路疊構110也可僅由單一介電層所構成。
請再參考圖1、圖2及圖3A至圖3C，本實施例之線路基板100更包括一圖案化導體層120、一介電層130及多個增厚導體層140。圖案化導體層120配置在表面110a上並具有多個走線122。各走線122具有一接合區段122a。介電層130(例如防銲層)配置在表面110a上且覆蓋圖案化導體層120，且介電層130具有多個接合開口132a，各接合開口132a暴露出對應的接合區段122a。各增厚導體層140配置在對應的接合區段122a上。
值得注意的是，在一般已知的利用走線配置接合區段的技術中，走線的接合區段僅為走線的一小線段，故已知的接合區段的寬度及厚度與構成此已知的接合區段的走線的寬度及厚度分別是相同的。然而，在本發明的實施例中，由於走線122的接合區段122a上配置有增厚導體層140，因此接合區段122a及增厚導體層140的寬度總和將大於構成接合區段122a的走線122的寬度，且接合區段122a及增厚導體層140的厚度總和將大於構成接合區段122a的走線122的厚度。因此，在本發明中，在接合區段上形成增厚導體層，以增加接合區段的寬度及高度，因而增加接合面積。
圖4A為圖2之局部的線路基板的圖案化導體層的走線的局部的立體圖，而圖4B為圖2之局部的線路基板的圖案化導體層 的走線的局部及增厚導體層的立體圖。請參考圖3A、圖3B、圖4A及圖4B，各接合區段122a具有遠離表面110a的一頂面122a-1及分別從頂面122a-1兩側延伸至表面110a的兩側面122a-2，且各增厚導體層140配置在對應的接合區段122a的頂面122a-1及這些側面122a-2上。
請再參考圖1、圖2、圖3B及圖3C，各走線122具有一電鍍區段122b，介電層具有多個電鍍開口132b，且各電鍍開口132b暴露出對應的電鍍區段122b。此外，線路疊構110具有一晶片接合區B，且這些接合開口132a及這些電鍍開口132b位於晶片接合區B內。另外，線路疊構110更具有一晶片投影區P，而這些接合開口132a位於晶片接合區B內。在另一未繪示的實施例中，當相鄰的走線122之間的間距縮小時，上述的多個電鍍開口132b可以一較大的電鍍開口取代。換言之，此較大電鍍開口同時暴露出多條走線122以及對應的多個電鍍區段122b。
值得注意的是，這些電鍍區段122b的用途在下文所介紹的線路基板製程的實施例進行更詳細地說明。
請再參考圖1及圖3A至圖3C，線路基板100還包括另一圖案化導體層180及另一介電層190，且線路疊構110還包括另一表面110b。圖案化導體層180配置在表面110b上，並具有多個接墊182。介電層190(例如防銲層)配置在表面110a上且覆蓋圖案化導體層180，但暴露出圖案化導體層180的多個接墊182。因此，圖案化導體層120經由線路疊構110電性連接至圖案化導 體層180，並經由這些接墊182電性連接至下一層級的電子裝置(未繪示)。
圖5為本發明的一實施例的一種半導體封裝結構的俯視圖，而圖6為圖5之半導體封裝結構沿線6-6的剖面圖。請參考圖5及圖6，本實施例的半導體封裝結構10包含一晶片12及上述實施例的線路基板100，其中晶片12以覆晶接合的方式連接至線路基板100。
圖7為圖5之線路基板的Y部位的放大圖，圖8A為圖7之局部的線路基板沿線8A-8A的剖視圖，圖8B為圖7之局部的線路基板沿線8B-8B的剖視圖，而圖8C為圖7之局部的線路基板沿線8C-8C的剖視圖。請參考圖7及圖8A至圖8C，在本實施例中，半導體封裝結構10具有多個導電凸塊14，其配置於晶片12與線路基板100之間，以將晶片12連接至這些增厚導體層140。在本實施例中，藉由銲料14a將各導電凸塊14連接至對應的增厚導體層140。
請再參考圖7及圖8A至圖8C，半導體封裝結構10更包括一底膠16，其配置於晶片12及線路基板100之間，並填入這些電鍍開口132b以覆蓋這些電鍍區段122b，因而達到絕緣包覆這些電鍍區段122b的目的。在本實施例中，底膠160的分布範圍在晶片接合區B(如圖1所繪示)，其邊界略大於晶片12的邊界。此外，在本實施例中，半導體封裝結構10更包括多個導電球18，其分別連接至這些接墊182，以連接至下一層級的電子裝置，例如主 機板或模組板等。
圖9A至圖9G為本發明之另一實施例的一種線路基板製程的局部俯視圖，其類似於圖1之線路基板的X部位的放大(即圖2)，圖10A至圖10G分別為圖9A至圖9G之線路基板沿著線I-I的上半部剖面圖，而圖11A至圖11G分別為圖9A至圖9G之線路基板沿著線II-II的上半部剖面圖。在本實施例中，僅以線路基板的上半部進行說明。請參考圖9A、10A及圖11A，首先，提供一線路疊構202及一圖案化導體層204，其中線路疊構202具有一表面202a，圖案化導體層204配置在表面202a上且具有多個走線206，且各走線206具有一接合區段206a及一電鍍區段206b。
接著，請參考圖9B、10B及圖11B，形成一介電層208(例如防銲層)覆蓋表面202a及圖案化導體層204，其中介電層208具有多個接合開口208a及多個電鍍開口208b，各接合開口208a暴露出對應的接合區段206a，且各電鍍開口208b暴露出對應的電鍍區段206b。在本實施例中，線路疊構202具有一晶片接合區B，且這些接合開口208a及這些電鍍開口208b位於晶片接合區B內。在另一未繪示的實施例中，當相鄰的走線206之間的間距縮小時，上述的多個電鍍開口208b可以一較大的電鍍開口取代。換言之，此較大電鍍開口同時暴露出多條走線206以及對應的多個電鍍區段206b。
接著，請參考圖9C、10C及圖11C，形成一電鍍種子層210覆蓋表面202a、這些接合區段206a、這些電鍍區段206b及介 電層208。接著，請參考圖9D、10D及圖11D，形成一罩幕212覆蓋電鍍種子層210，其中罩幕212具有多個罩幕開口212a，且各罩幕開口212a暴露出電鍍種子層210在對應的接合區段206a上的一部分。接著，請參考圖9E、10E及圖11E，以罩幕212為蝕刻罩幕蝕刻電鍍種子層210，以移除電鍍種子層210在這些接合區段206a上的這些部分而暴露出這些接合區段206a。
接著，請參考圖9F、10F及圖11F，在蝕刻電鍍種子層210以後，以罩幕212為電鍍罩幕並經由電鍍種子層210及這些走線206，在各接合區段206a上電鍍一增厚導體層214。類似於圖4A的接合區段122a，各接合區段206a具有遠離表面202a的一頂面206a-1及分別從頂面206a-1的兩側延伸至表面202a的兩側面206a-2，而對應的增厚導體層214則配置在接合區段206a的頂面206a-1及這兩側面206a-2上。
最後，請參考圖9G、10G及圖11G，在電鍍這些增厚導體層214以後，移除罩幕212及電鍍種子層210。
綜上所述，本發明藉由介電層(例如防銲層)覆蓋配置在線路疊構上的圖案化導體層，但暴露出圖案化導體層的走線的接合區段，使得相鄰的接合區段的間距可以減少，特別是相鄰的接合區段之間存在其他走線，且相鄰的接合區段彼此不易橋接(Bridging)。此外，本發明在接合區段上形成增厚導體層，以增加接合區段的寬度及高度，因而增加接合面積。
除此之外，在本發明的線路基板製程中，利用介電層之 電鍍開口暴露出走線的電鍍區段，以藉此作為電流路徑在走線的接合區段上電鍍增厚導體層。同時，更可藉由底膠來填充電鍍開口以包覆走線的電鍍區段，以達到絕緣包覆電鍍區段的目的。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
110‧‧‧線路疊構
110a‧‧‧表面
110b‧‧‧表面
122‧‧‧走線
122a‧‧‧接合區段
122a-1‧‧‧頂面
122a-2‧‧‧側面
130‧‧‧介電層
132a‧‧‧接合開口
140‧‧‧增厚導體層
180‧‧‧圖案化導體層
182‧‧‧接墊
190‧‧‧介電層

Claims (18)

  1. 一種線路基板，包括：一線路疊構，具有一表面；一圖案化導體層，配置在該表面上並具有多個走線，各該走線具有一接合區段及一電鍍區段；一介電層，配置在該表面上且覆蓋該圖案化導體層，且該介電層具有多個接合開口及多個電鍍開口，各該接合開口暴露出對應的該接合區段，各該電鍍開口暴露出對應的該電鍍區段；以及多個增厚導體層，各該增厚導體層配置在對應的該接合區段上。
  2. 如申請專利範圍第1項所述的線路基板，其中各該接合區段具有遠離該表面的一頂面及分別從該頂面兩側延伸至該表面的兩側面，且各該增厚導體層配置在對應的該接合區段的該頂面及該些側面上。
  3. 如申請專利範圍第1項所述的線路基板，其中該線路基板適於藉由一底膠與一晶片連接，而該底膠適於配置於該晶片與該線路基板之間，並填入該些電鍍開口以覆蓋該些電鍍區段。
  4. 如申請專利範圍第1項所述的線路基板，其中該線路疊構具有一晶片接合區，且該些接合開口及該些電鍍開口位於該晶片接合區內。
  5. 如申請專利範圍第1項所述的線路基板，其中該介電層為一防銲層。
  6. 如申請專利範圍第1項所述的線路基板，其中各該接合區段與對應的該增厚導體層的寬度總和大於對應的該走線的寬度，且各該接合區段與對應的該增厚導體層的厚度總和大於對應的該走線的厚度。
  7. 一種半導體封裝結構，包括：一線路基板，包括：一線路疊構，具有一表面；一圖案化導體層，配置在該表面上並具有多個走線，各該走線具有一接合區段及一電鍍區段；一介電層，配置在該表面上且覆蓋該圖案化導體層，且該介電層具有多個接合開口及多個電鍍開口，各該接合開口暴露出對應的該接合區段，各該電鍍開口暴露出對應的該電鍍區段；以及多個增厚導體層，各該增厚導體層配置在對應的該接合區段上；以及一晶片，連接該些增厚導體層。
  8. 如申請專利範圍第7項所述的半導體封裝結構，其中各該接合區段具有遠離該表面的一頂面及分別從該頂面兩側延伸至該表面的兩側面，且各該增厚導體層配置在對應的該接合區段的該頂面及該些側面上。
  9. 如申請專利範圍第7項所述的半導體封裝結構，更包括：一底膠，配置於該晶片與該線路基板之間，並填入該些電鍍 開口以覆蓋該些電鍍區段。
  10. 如申請專利範圍第7項所述的半導體封裝結構，其中該線路疊構具有一晶片接合區，且該些接合開口及該些電鍍開口位於該晶片接合區內。
  11. 如申請專利範圍第7項所述的半導體封裝結構，其中該線路疊構具有一晶片投影區，且該些接合開口位於該晶片投影區內。
  12. 如申請專利範圍第7項所述的半導體封裝結構，其中該介電層為一防銲層。
  13. 如申請專利範圍第7項所述的半導體封裝結構，更包括：多個導電凸塊，配置於該晶片與該線路基板之間，以將該晶片連接至該些增厚導體層。
  14. 一種線路基板製程，包括：提供一線路疊構及一圖案化導體層，其中該線路疊構具有一表面，該圖案化導體層配置在該表面上且具有多個走線，且各該走線具有一接合區段及一電鍍區段；形成一介電層覆蓋該表面及該圖案化導體層，其中該介電層具有多個接合開口及多個電鍍開口，各該接合開口暴露出對應的該接合區段，且各該電鍍開口暴露出對應的該電鍍區段；形成一電鍍種子層覆蓋該表面、該些接合區段、該些電鍍區段及該介電層；形成一罩幕覆蓋該電鍍種子層，其中該罩幕具有多個罩幕開 口，且各該罩幕開口暴露出該電鍍種子層在對應的該接合區段上的一部分；以該罩幕為蝕刻罩幕蝕刻該電鍍種子層，以移除該電鍍種子層在該些接合區段上的該些部分而暴露出該些接合區段；在蝕刻該電鍍種子層以後，以該罩幕為電鍍罩幕並經由該電鍍種子層及該些走線，在各該接合區段上電鍍一增厚導體層；以及在電鍍該些增厚導體層以後，移除該罩幕及該電鍍種子層。
  15. 如申請專利範圍第14項所述的線路基板製程，其中各該接合區段具有遠離該表面的一頂面及分別從該頂面兩側延伸至該表面的兩側面，且各該增厚導體層配置在對應的該接合區段的該頂面及該些側面上。
  16. 如申請專利範圍第14項所述的線路基板製程，其中該線路疊構具有一晶片接合區，且該些接合開口及該些電鍍開口位於該晶片接合區內。
  17. 如申請專利範圍第14項所述的線路基板製程，其中該介電層為一防銲層。
  18. 如申請專利範圍第14項所述的線路基板製程，其中各該接合區段與對應的該增厚導體層的寬度總和大於對應的該走線的寬度，且各該接合區段與對應的該增厚導體層的厚度總和大於對應的該走線的厚度。
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