TWI513011B - Differential varactor device - Google Patents
Differential varactor device Download PDFInfo
- Publication number
- TWI513011B TWI513011B TW100123829A TW100123829A TWI513011B TW I513011 B TWI513011 B TW I513011B TW 100123829 A TW100123829 A TW 100123829A TW 100123829 A TW100123829 A TW 100123829A TW I513011 B TWI513011 B TW I513011B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- variable capacitance
- differential variable
- electrically connected
- well region
- Prior art date
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
本發明係關於一種差動可變電容元件。The present invention relates to a differential variable capacitance element.
在現代化資訊產業中，各種數據、資料、訊息、影像等都是以電子訊號的形式來傳遞，而用來處理電子訊號的處理電路，也就成為現代資訊產業中最重要的基礎。而電路中之震盪器(oscillator)則是現代數位系統中不可或缺的重要電路構築方塊之一。例如，在一般的資訊系統(例如：個人電腦)中，需要一總體時脈(global clock)以協調數位系統中的各個數位電路一起運作，而時脈則是由震盪器所產生的。此外，要協調不同的時脈同步(譬如說在傳輸訊號的通訊系統中)，還需要使用鎖相(phase loop lock，PLL)電路；而鎖相電路中則需要精密的壓控震盪器(voltage-controlled oscillators，VCOs)，以電壓來控制壓控震盪器震盪出頻率不同的震盪訊號，以協調各時脈同步。此外，像是在某些精密的濾波器中，尚須使用能調整濾波頻率的電阻-電容(RC)濾波器。In the modern information industry, various data, materials, messages, and images are transmitted in the form of electronic signals, and the processing circuits used to process electronic signals become the most important foundation in the modern information industry. The oscillator in the circuit is one of the important circuit building blocks in modern digital systems. For example, in a general information system (eg, a personal computer), a global clock is needed to coordinate the various digital circuits in the digital system, and the clock is generated by the oscillator. In addition, to coordinate different clock synchronization (such as in the communication system for transmitting signals), a phase loop lock (PLL) circuit is also required; in the phase-locked circuit, a precision voltage-controlled oscillator is required. -controlled oscillators (VCOs), which control the voltage-controlled oscillator to oscillate different oscillation signals with different voltages to coordinate the clock synchronization. In addition, as in some sophisticated filters, a resistor-capacitor (RC) filter that adjusts the filter frequency is required.
不論是電阻-電容(RC)濾波器的濾波特性(像是濾波器的通帶頻寬)，或是電感-電容(LC)壓控震盪器的震盪特性(像是震盪訊號的頻率)，都可以用改變電容值的方法來加以調整。因此，具有可調整電容值之電容，亦即可變電容，已被運用於具有該些特性之元件中。而在可變電容之操作範圍內，其電容值係隨加諸其上之電壓而減少。目前已發展出多種可應用於積體電路元件中之可變電容，而其中以PN接面可變電容(PN junction varactor)以及金氧半導體(metal-oxide semiconductor，MOS)可變電容兩種結構最常為常見。Whether it is the filter characteristics of a resistor-capacitor (RC) filter (such as the passband bandwidth of a filter) or the oscillatory characteristics of an inductor-capacitor (LC) voltage-controlled oscillator (like the frequency of a oscillating signal), It can be adjusted by changing the value of the capacitor. Therefore, a capacitor having an adjustable capacitance value, that is, a variable capacitance, has been used in an element having such characteristics. In the operating range of the variable capacitor, the capacitance value decreases with the voltage applied to it. A variety of variable capacitors have been developed for use in integrated circuit components, among which are PN junction varactors and metal-oxide semiconductor (MOS) variable capacitors. Most often it is common.
然而，以MOS可變電容而言，其調諧比值，定義為可變電容之最大電容與最小電容之比值，在操作頻率為10GHz的情況下僅能達到3。換句話說，MOS可變電容可調整的電容值的變化範圍係受限於其調諧比值。有鑑於此，提升可變電容之調諧比值實為業界努力之目標。However, in the case of a MOS variable capacitor, the tuning ratio is defined as the ratio of the maximum capacitance to the minimum capacitance of the variable capacitor, which can only reach 3 at an operating frequency of 10 GHz. In other words, the range of variation of the MOS variable capacitance adjustable capacitance value is limited by its tuning ratio. In view of this, increasing the tuning ratio of the variable capacitor is an industry goal.
本發明之主要目的之一在於提供一種差動可變電容元件，以提升調諧比值。One of the main objects of the present invention is to provide a differential variable capacitance element to increase the tuning ratio.
為達上述之目的，本發明提供一種差動可變電容元件，其包括一基底、一井區、五第一摻雜區、四第一絕緣層以及一第一閘極、一第二閘極、一第三閘極與一第四閘極。基底具有一第一導電類型。井區設於基底中，且井區具有一第二導電類型。五第一摻雜區設於井區中，並沿著一第一方向排列，且第一摻雜區具有第二導電類型。四第一絕緣層設於井區上，且各第一絕緣層分別設於任兩相鄰之第一摻雜區之間。第一閘極、第二閘極、第三閘極與第四閘極分別設於各第一絕緣層上，且依序沿著第一方向排列。To achieve the above objective, the present invention provides a differential variable capacitance element including a substrate, a well region, five first doped regions, four first insulating layers, and a first gate and a second gate. a third gate and a fourth gate. The substrate has a first conductivity type. The well zone is disposed in the substrate and the well zone has a second conductivity type. The fifth first doped regions are disposed in the well region and aligned along a first direction, and the first doped regions have a second conductivity type. The first insulating layer is disposed on the well region, and each of the first insulating layers is disposed between any two adjacent first doped regions. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the first insulating layers, and are sequentially arranged along the first direction.
為達上述之目的，本發明另提供一種差動可變電容元件，其包括一基底、一第一井區與一第二井區、三第三摻雜區、三第四摻雜區、二第四絕緣層、一第一閘極與一第二閘極以及一第三閘極與一第四閘極。基底具有一第一導電類型。第一井區與第二井區設於基底中，並沿著一第一方向排列，且第一井區與第二井區具有一第二導電類型。第三摻雜區設於第一井區中，並沿著第一方向排列，且第三摻雜區具有第二導電類型。第四摻雜區設於第二井區中，並沿著第一方向排列，且第四摻雜區具有第二導電類型。第三絕緣層設於第一井區上，且各第三絕緣層分別位於任兩相鄰之第三摻雜區之間。第四絕緣層設於第二井區上，且各第四絕緣層分別位於任兩相鄰之第四摻雜區之間。第一閘極與第二閘極分別設於各第三絕緣層上，且依序沿著第一方向排列。第三閘極與第四閘極分別設於各第四絕緣層上，且依序沿著第一方向排列。To achieve the above objective, the present invention further provides a differential variable capacitance element including a substrate, a first well region and a second well region, three third doped regions, three fourth doped regions, and two a fourth insulating layer, a first gate and a second gate, and a third gate and a fourth gate. The substrate has a first conductivity type. The first well region and the second well region are disposed in the substrate and arranged along a first direction, and the first well region and the second well region have a second conductivity type. The third doped region is disposed in the first well region and arranged along the first direction, and the third doped region has the second conductivity type. The fourth doped region is disposed in the second well region and arranged along the first direction, and the fourth doped region has the second conductivity type. The third insulating layer is disposed on the first well region, and each of the third insulating layers is respectively located between any two adjacent third doped regions. The fourth insulating layer is disposed on the second well region, and each of the fourth insulating layers is respectively located between any two adjacent fourth doping regions. The first gate and the second gate are respectively disposed on the third insulating layers, and are sequentially arranged along the first direction. The third gate and the fourth gate are respectively disposed on the fourth insulating layers, and are sequentially arranged along the first direction.
為達上述之目的，本發明另提供一種差動可變電容元件，其包括複數個差動可變電容單元。各差動可變電容單元分別具有二閘極，分別電性連接至一第一輸出端與一第二輸出端，其中差動可變電容單元具有一調諧比值，且調諧比值大於4。To achieve the above object, the present invention further provides a differential variable capacitance element including a plurality of differential variable capacitance units. Each of the differential variable capacitor units has two gates respectively electrically connected to a first output end and a second output end, wherein the differential variable capacitor unit has a tuning ratio and the tuning ratio is greater than 4.
本發明之差動可變電容元件藉由將電性連接至不同閘極電壓之閘極沿著第一方向交錯設置，以及將不同之差動可變電容單元設於同一井區中，使調諧比值大於4，進而有效提升其可調整之電容範 圍。The differential variable capacitance element of the present invention is tuned by arranging gates electrically connected to different gate voltages in a first direction, and different differential variable capacitance units in the same well region. The ratio is greater than 4, which effectively increases its adjustable capacitance Wai.
請參考第1圖至第3圖，第1圖為本發明一第一較佳實施例之差動可變電容元件的上視示意圖，第2圖為沿著第1圖之剖面線AA’之剖面示意圖，且第3圖為沿著第1圖之剖面線BB’之剖面示意圖。如第1圖與第2圖所示，差動可變電容元件100係製作於一基底102上，例如矽基底，且基底102具有一第一導電類型。並且，差動可變電容元件100包含有一井區104、五第一摻雜區106以及四第一閘極結構108。井區104設於基底102中，且具有與第一導電類型不同之一第二導電類型。第一摻雜區106設於井區104中，並沿著一第一方向110排列，且第一摻雜區106具有第二導電類型。於本實施例中，第一導電類型係為P型，且第二導電類型為N型，但不限於此，本發明之第一導電類型與第二導電類型亦可互換。Please refer to FIG. 1 to FIG. 3 . FIG. 1 is a top view of a differential variable capacitance element according to a first preferred embodiment of the present invention, and FIG. 2 is a cross-sectional line AA′ along FIG. 1 . A schematic cross-sectional view, and Fig. 3 is a schematic cross-sectional view taken along line BB' of Fig. 1. As shown in FIGS. 1 and 2, the differential variable capacitance element 100 is fabricated on a substrate 102, such as a germanium substrate, and the substrate 102 has a first conductivity type. Moreover, the differential variable capacitance element 100 includes a well region 104, five first doping regions 106, and four first gate structures 108. The well region 104 is disposed in the substrate 102 and has a second conductivity type that is different from the first conductivity type. The first doped regions 106 are disposed in the well region 104 and are aligned along a first direction 110, and the first doped regions 106 have a second conductivity type. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type, but is not limited thereto, and the first conductive type and the second conductive type of the present invention may also be interchanged.
於本實施例中，第一閘極結構108分別設於任兩相鄰之N型第一摻雜區106之間的N型井區104上。並且，各第一閘極結構108包含有一第一絕緣層112、一閘極以及二第一側壁子116，其中各閘極分別設於各第一絕緣層112上，且第一側壁子116分別設於各閘極與各第一絕緣層112之兩側。在第一方向110上沿著任兩相鄰之第一摻雜區106之間僅設置有閘極之其中單一者。由此可知，N型井區104、任兩相鄰之N型第一摻雜區106以及位於任兩相鄰之N型第一摻雜區106之間的各第一閘極結構108可構成一第一可變電 容117，第2圖例式為4組，且兩相鄰之第一可變電容117係共用同一N型第一摻雜區106。此外，本實施例之各閘極係由一多晶矽層所構成，但不限於此，本發明之閘極亦可為一金屬閘極(metal gate)。In the present embodiment, the first gate structures 108 are respectively disposed on the N-type well regions 104 between any two adjacent N-type first doping regions 106. The first gate structure 108 includes a first insulating layer 112, a gate, and two first sidewalls 116. The gates are respectively disposed on the first insulating layers 112, and the first sidewalls 116 are respectively It is disposed on each side of each gate and each of the first insulating layers 112. Only a single one of the gates is disposed between the two adjacent first doped regions 106 in the first direction 110. It can be seen that the N-type well region 104, any two adjacent N-type first doped regions 106, and the respective first gate structures 108 between any two adjacent N-type first doped regions 106 may constitute First variable electric The second pattern is a group of four, and the two adjacent first variable capacitors 117 share the same N-type first doping region 106. In addition, each of the gates of the present embodiment is composed of a polysilicon layer, but is not limited thereto, and the gate of the present invention may also be a metal gate.
於本實施例中，第一閘極結構108之閘極可區分為一第一閘極114a、一第二閘極114b、一第三閘極114c與一第四閘極114d，沿著第一方向110依序排列。並且，差動可變電容元件100另包括複數個P型摻雜區118、複數個接觸插塞120、複數個導電層、一第一輸出端122、一第二輸出端124以及一第三輸出端126。P型摻雜區118設於P型基底102中，且用於將P型基底102電性連接至外界。接觸插塞120、導電層、第一輸出端122、第二輸出端124以及第三輸出端126設於P型基底102上，且接觸插塞120分別設於P型摻雜區118、第一閘極114a、第二閘極114b、第三閘極114c、第四閘極114d以及部分N型第一摻雜區106上。導電層包括一第一導電層128a、一第二導電層128b、一第三導電層128c以及一第四導電層128d，分別設於第一閘極114a、第二閘極114b、第三閘極114c與第四閘極114d上，且第一導電層128a、第二導電層128b、第三導電層128c與第四導電層128d藉由接觸插塞120分別電性連接第一閘極114a、第二閘極114b、第三閘極114c與第四閘極114d。並且，第一導電層128a與第三導電層128c係電性連接至第一輸出端122，使第一閘極114a與第三閘極114c可藉由第一導電層128a、第三導電層128c與相對應之接觸插塞120電性連接至第一輸出端 122；且第二導電層128b與第四導電層128d係電性連接至第二輸出端124，使第二閘極114b與第四閘極114d可藉由第二導電層128b、第四導電層128d與相對應之接觸插塞120電性連接至第二輸出端124。而N型第一摻雜區106則可藉由接觸插塞120電性連接至第三輸出端126，例如本實施例中，位於第一閘極114a與第二閘極114b之間以及位於第三閘極114c與第四閘極114d之間的N型第一摻雜區106係與相對應之接觸插塞120相接觸，而電性連接至第三輸出端126。第一輸出端122與第二輸出端124可分別作為差動可變電容元件100之不同閘極輸出端，以用於電性連接至二不同閘極電壓，且第三輸出端126則作為差動可變電容元件100之控制端，以用於電性連接至一控制電壓。由此可知，電性連接至不同閘極電壓之任二第一可變電容117可構成一第一差動可變電容(differential varactor)單元119，其中一第一差動可變電容單元119僅具有第一閘極114a與第二閘極114b，另一第一差動可變電容單元119僅具有第三閘極114c與第四閘極114d，且本實施例之差動可變電容元件100係具有兩個互相並聯且沿著第一方向100排列之第一差動可變電容單元119。於本發明之其他實施例中，差動可變電容元件100另可包括一第四輸出端，藉由接觸插塞120電性連接至P型摻雜區118，以用於作為P型基底102之輸出端。並且，本發明第一閘極114a與第三閘極114b電性連接至第一輸出端122之方式、第二閘極114b與第四閘極114d電性連接至第二輸出端124之方式、N型第一摻雜區106電性連接至第三輸出端126之方式與P型摻雜區118電性連接至第四輸出端之方式並不限於上述方式，亦可利用其他金 屬內連線或埋設導線(buried line)結構來達成。In this embodiment, the gate of the first gate structure 108 can be divided into a first gate 114a, a second gate 114b, a third gate 114c and a fourth gate 114d, along the first The directions 110 are arranged in order. Moreover, the differential variable capacitance element 100 further includes a plurality of P-type doping regions 118, a plurality of contact plugs 120, a plurality of conductive layers, a first output terminal 122, a second output terminal 124, and a third output. End 126. The P-type doping region 118 is disposed in the P-type substrate 102 and is used to electrically connect the P-type substrate 102 to the outside. The contact plug 120, the conductive layer, the first output end 122, the second output end 124, and the third output end 126 are disposed on the P-type substrate 102, and the contact plugs 120 are respectively disposed in the P-type doping region 118, first The gate 114a, the second gate 114b, the third gate 114c, the fourth gate 114d, and a portion of the N-type first doping region 106. The conductive layer includes a first conductive layer 128a, a second conductive layer 128b, a third conductive layer 128c, and a fourth conductive layer 128d, respectively disposed on the first gate 114a, the second gate 114b, and the third gate. The first conductive layer 128a, the second conductive layer 128b, the third conductive layer 128c and the fourth conductive layer 128d are electrically connected to the first gate 114a by the contact plug 120, respectively. The second gate 114b, the third gate 114c and the fourth gate 114d. The first conductive layer 128a and the third conductive layer 128c are electrically connected to the first output end 122, so that the first gate 114a and the third gate 114c can pass through the first conductive layer 128a and the third conductive layer 128c. Electrically connecting to the corresponding contact plug 120 to the first output end The second conductive layer 128b and the fourth conductive layer 128d are electrically connected to the second output end 124, so that the second gate 114b and the fourth gate 114d can pass through the second conductive layer 128b and the fourth conductive layer. 128d and the corresponding contact plug 120 are electrically connected to the second output end 124. The N-type first doping region 106 can be electrically connected to the third output terminal 126 by the contact plug 120. For example, in the embodiment, the first gate electrode 114a and the second gate electrode 114b are located between the first gate electrode 114a and the second gate electrode 114b. The N-type first doping region 106 between the third gate 114c and the fourth gate 114d is in contact with the corresponding contact plug 120 and is electrically connected to the third output terminal 126. The first output terminal 122 and the second output terminal 124 can be respectively used as different gate outputs of the differential variable capacitance element 100 for electrically connecting to two different gate voltages, and the third output terminal 126 is used as a difference. The control terminal of the variable capacitance element 100 is electrically connected to a control voltage. Therefore, any two first variable capacitors 117 electrically connected to different gate voltages may constitute a first differential variable varactor unit 119, wherein a first differential variable capacitor unit 119 is only The first gate variable 114a and the second gate 114b have the third gate 114c and the fourth gate 114d, and the differential variable capacitance element 100 of the present embodiment There is two first differential variable capacitance units 119 arranged in parallel with each other and arranged along the first direction 100. In other embodiments of the present invention, the differential variable capacitance element 100 further includes a fourth output terminal electrically connected to the P-type doping region 118 by the contact plug 120 for use as the P-type substrate 102. The output. Moreover, the manner in which the first gate 114a and the third gate 114b of the present invention are electrically connected to the first output terminal 122, and the second gate 114b and the fourth gate 114d are electrically connected to the second output terminal 124, The manner in which the N-type first doping region 106 is electrically connected to the third output terminal 126 and the P-type doping region 118 are electrically connected to the fourth output terminal is not limited to the above manner, and other gold may be utilized. It is achieved by an internal wiring or a buried line structure.
如第3圖所示，差動可變電容元件100另可包括四第二閘極結構130以及五N型第二摻雜區132，其中第二閘極結構130設於相鄰於第一閘極結構108之N型井區104上，並分別位於任兩相鄰之N型第二摻雜區132之間，且第二閘極結構130與第一閘極結構108沿著一第二方向134排列。各第二閘極結構130包含有一第二絕緣層136、一閘極以及二第二側壁子138，其中各閘極分別設於各第二絕緣層136上，且第二側壁子138分別設於各閘極與各第二絕緣層136之兩側。因此，N型井區104、任兩相鄰之N型第二摻雜區132以及位於任兩相鄰之N型第二摻雜區132之間的各第二閘極結構130可構成一第二可變電容139，且兩相鄰之第二可變電容係共用同一N型第二摻雜區132。於本實施例中，第二閘極結構130之閘極可區分為一第五閘極140a、一第六閘極140b、一第七閘極140c與一第八閘極140d。第五閘極140a、第六閘極140b、第七閘極140c與第八閘極140d係沿著第一方向110依序排列。並且，導電層另包括一第五導電層128e、一第六導電層128f、一第七導電層128g以及一第八導電層128h，分別設於第五閘極140a、第六閘極140b、第七閘極140c與第八閘極140d上，且第五導電層128e、第六導電層128f、第七導電層128g與第八導電層128h藉由相對應之接觸插塞120分別電性連接第五閘極140a、第六閘極140b、第七閘極140c與第八閘極140d。此外，第五導電層128e與第七導電層128g係電性連接至第一輸出端122，使第五閘極140a與第七閘極140c可藉 由第五導電層128e、第七導電層128g與相對應之接觸插塞120電性連接至第一輸出端122，且第六導電層128f與第八導電層128h係電性連接至第二輸出端124，使第六閘極140b與第八閘極140d可藉由第六導電層128f、第八導電層128h與相對應之接觸插塞120電性連接至第二輸出端124。位於第五閘極140a與第六閘極140b之間以及位於第七閘極140c與第八閘極140d之間的N型第二摻雜區132係與相對應之接觸插塞120相接觸，而電性連接至第三輸出端126。As shown in FIG. 3, the differential variable capacitance element 100 further includes four second gate structures 130 and five N-type second doping regions 132, wherein the second gate structure 130 is disposed adjacent to the first gate. The N-type well region 104 of the pole structure 108 is located between any two adjacent N-type second doping regions 132, and the second gate structure 130 and the first gate structure 108 are along a second direction. 134 arranged. Each of the second gate structures 130 includes a second insulating layer 136, a gate, and two second sidewalls 138. The gates are respectively disposed on the second insulating layers 136, and the second sidewalls 138 are respectively disposed on the second gate layer 138. Each of the gates and each of the second insulating layers 136 are on both sides. Therefore, the N-type well region 104, any two adjacent N-type second doped regions 132, and each of the second gate structures 130 between any two adjacent N-type second doped regions 132 may constitute a first Two variable capacitors 139, and two adjacent second variable capacitors share the same N-type second doping region 132. In this embodiment, the gate of the second gate structure 130 can be divided into a fifth gate 140a, a sixth gate 140b, a seventh gate 140c and an eighth gate 140d. The fifth gate 140a, the sixth gate 140b, the seventh gate 140c, and the eighth gate 140d are sequentially arranged along the first direction 110. The conductive layer further includes a fifth conductive layer 128e, a sixth conductive layer 128f, a seventh conductive layer 128g, and an eighth conductive layer 128h, respectively disposed on the fifth gate 140a and the sixth gate 140b. The seventh gate 140c and the eighth gate 140d, and the fifth conductive layer 128e, the sixth conductive layer 128f, the seventh conductive layer 128g and the eighth conductive layer 128h are respectively electrically connected by the corresponding contact plugs 120. The five gates 140a, the sixth gate 140b, the seventh gate 140c, and the eighth gate 140d. In addition, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the first output end 122, so that the fifth gate 140a and the seventh gate 140c can be borrowed. The fifth conductive layer 128e, the seventh conductive layer 128g and the corresponding contact plug 120 are electrically connected to the first output end 122, and the sixth conductive layer 128f and the eighth conductive layer 128h are electrically connected to the second output. The second terminal 140b and the eighth gate 140d are electrically connected to the second output end 124 by the sixth conductive layer 128f, the eighth conductive layer 128h and the corresponding contact plug 120. An N-type second doping region 132 between the fifth gate 140a and the sixth gate 140b and between the seventh gate 140c and the eighth gate 140d is in contact with the corresponding contact plug 120. It is electrically connected to the third output terminal 126.
由此可知，電性連接至不同閘極電壓之任二第二可變電容139可構成一第二差動可變電容單元141，且本實施例之差動可變電容元件100係具有兩個互相並聯且沿著第一方向110排列之第二差動可變電容單元141。並且，第一差動可變電容單元119之第一閘極114a與第三閘極114c係與第二差動可變電容單元141之第五閘極140a與第七閘極140c並聯至第一輸出端122，且第一差動可變電容單元119之第二閘極114b與第四閘極114d以及第二差動可變電容單元141之第六閘極140b與第八閘極140d並聯至第二輸出端124，而第一差動可變電容單元119與第二差動可變電容單元141沿著第二方向134排列設置於同一N型井區104上，使第一差動可變電容單元119與第二差動可變電容單元141彼此相互並聯。值得注意的是，本實施例之差動可變電容元件100將電性連接至不同閘極電壓之閘極沿著第一方向110交錯設置，且將不同之第一差動可變電容單元119與第二差動可變電容單元141設於同一N型井區104中， 使差動可變電容元件100之調諧比值大於4，以有效提升其可調整之電容範圍。Therefore, it can be seen that any two second variable capacitors 139 electrically connected to different gate voltages can constitute a second differential variable capacitance unit 141, and the differential variable capacitance element 100 of the embodiment has two A second differential variable capacitance unit 141 that is parallel to each other and arranged along the first direction 110. The first gate 114a and the third gate 114c of the first differential variable capacitor unit 119 are connected in parallel with the fifth gate 140a and the seventh gate 140c of the second differential variable capacitor unit 141. The output terminal 122, and the second gate 114b and the fourth gate 114d of the first differential variable capacitor unit 119 and the sixth gate 140b of the second differential variable capacitor unit 141 are connected in parallel with the eighth gate 140d to The second output terminal 124, and the first differential variable capacitor unit 119 and the second differential variable capacitor unit 141 are arranged along the second direction 134 on the same N-type well region 104, so that the first differential variable The capacitor unit 119 and the second differential variable capacitor unit 141 are connected to each other in parallel. It should be noted that the differential variable capacitance element 100 of the present embodiment has the gates electrically connected to different gate voltages staggered along the first direction 110, and the first differential variable capacitance unit 119 is different. And the second differential variable capacitor unit 141 is disposed in the same N-type well region 104, The tuning ratio of the differential variable capacitance element 100 is made greater than 4 to effectively increase its adjustable capacitance range.
於本發明之其他實施例中，差動可變電容元件100亦可具有複數個第一差動可變電容單元119沿著第一方向110排列。並且，差動可變電容元件100亦可具有複數個第二差動可變電容單元141沿著第一方向110排列。此外，本發明之差動可變電容元件100不限於僅具有第一差動可變電容單元119與第二差動可變電容單元141排列於第二方向134上，亦可具有複數個差動可變電容單元排列於第二方向134上。In other embodiments of the present invention, the differential variable capacitance element 100 may also have a plurality of first differential variable capacitance units 119 arranged along the first direction 110. Further, the differential variable capacitance element 100 may have a plurality of second differential variable capacitance units 141 arranged along the first direction 110. In addition, the differential variable capacitance element 100 of the present invention is not limited to having only the first differential variable capacitance unit 119 and the second differential variable capacitance unit 141 arranged in the second direction 134, and may have a plurality of differentials. The variable capacitance units are arranged in the second direction 134.
本發明之差動可變電容元件並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形，然為了簡化說明並突顯各實施例或變化形之間的差異，下文中使用相同標號標注相同元件，並不再對重覆部分作贅述。The differential variable capacitance element of the present invention is not limited to the above embodiment. The other embodiments and variations of the present invention are described in the following, and the same reference numerals will be used to refer to the same elements, and the repeated parts will not be described again.
請參考第4圖，第4圖為本發明第一較佳實施例之另一變化形的差動可變電容元件之上視示意圖。如第4圖所示，相較於上述實施例，本變化形之N型第二摻雜區132可為延伸N型第一摻雜區106之一部分，因此第二閘極結構130分別設於任兩相鄰之N型第一摻雜區106之間。Please refer to FIG. 4, which is a top view of another variation of the differential variable capacitance element according to the first preferred embodiment of the present invention. As shown in FIG. 4, compared with the above embodiment, the N-type second doping region 132 of the modified shape may be a portion of the extended N-type first doping region 106, so the second gate structure 130 is respectively disposed on Between two adjacent N-type first doped regions 106.
請參考第5圖，第5圖為本發明一第二較佳實施例之差動可變電 容元件之上視示意圖。如第5圖所示，相較於第一實施例，於本實施例之差動可變電容元件200中，第五導電層128e與第七導電層128g係電性連接至第二輸出端124，使第五閘極140a與第七閘極140c電性連接至第二輸出端124，且第六導電層128f與第八導電層128h係電性連接至第一輸出端122，使第六閘極140b與第八閘極140d電性連接至第一輸出端122。Please refer to FIG. 5, which is a differential variable power according to a second preferred embodiment of the present invention. The top view of the component is shown. As shown in FIG. 5, in the differential variable capacitance element 200 of the present embodiment, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the second output end 124. The fifth gate 140a and the seventh gate 140c are electrically connected to the second output terminal 124, and the sixth conductive layer 128f and the eighth conductive layer 128h are electrically connected to the first output terminal 122, so that the sixth gate The pole 140b and the eighth gate 140d are electrically connected to the first output end 122.
請參考第6圖，第6圖為本發明一第三較佳實施例之差動可變電容元件之上視示意圖。如第6圖所示，相較於第一實施例，於本實施例之差動可變電容元件250中，第一導電層128a、第二導電層128b、第五導電層128e與第六導電層128f係電性連接至第一輸出端122，使第一閘極114a、第二閘極114b、第五閘極140a與第六閘極140b電性連接至第一輸出端122，且第三導電層128c、第四導電層128d、第七導電層128g與第八導電層128h係電性連接至第二輸出端124，使第三閘極114c、第四閘極114d、第七閘極140c與第八閘極140d電性連接至第二輸出端124。於本實施例中，相鄰之第一閘極114a與第二閘極114b以及相鄰之第五閘極140a與第六閘極140b係電性連接至相同的第一輸出端122，而相鄰之第三閘極114c與第四閘極114d以及相鄰之第七閘極140c與第八閘極140d係電性連接至相同的第二輸出端124，使電性連接至第一輸出端122之第一閘極114a與第二閘極114b以及電性連接至第二輸出端124之第三閘極114c與第四閘極114d以兩兩交錯的方式排列於第一方向110上。同理，電性連接至第一輸出端122之第五閘極140a與第 六閘極140b以及電性連接至第二輸出端124之第七閘極140c與第八閘極140d亦以兩兩交錯的方式排列於第一方向110上。Please refer to FIG. 6. FIG. 6 is a top view of a differential variable capacitance element according to a third preferred embodiment of the present invention. As shown in FIG. 6, in the differential variable capacitance element 250 of the present embodiment, the first conductive layer 128a, the second conductive layer 128b, the fifth conductive layer 128e, and the sixth conductive portion are compared with the first embodiment. The layer 128f is electrically connected to the first output end 122, and electrically connects the first gate 114a, the second gate 114b, the fifth gate 140a and the sixth gate 140b to the first output terminal 122, and the third The conductive layer 128c, the fourth conductive layer 128d, the seventh conductive layer 128g and the eighth conductive layer 128h are electrically connected to the second output terminal 124, so that the third gate 114c, the fourth gate 114d, and the seventh gate 140c The eighth gate 140d is electrically connected to the second output terminal 124. In this embodiment, the adjacent first gate 114a and second gate 114b and the adjacent fifth gate 140a and sixth gate 140b are electrically connected to the same first output terminal 122, and the phase The adjacent third gate 114c and the fourth gate 114d and the adjacent seventh gate 140c and the eighth gate 140d are electrically connected to the same second output terminal 124 to be electrically connected to the first output end. The first gate 114a and the second gate 114b of the second gate 114b and the third gate 114c and the fourth gate 114d electrically connected to the second output terminal 124 are arranged in the first direction 110 in a staggered manner. Similarly, the fifth gate 140a and the first electrode electrically connected to the first output terminal 122 The sixth gate 140b and the seventh gate 140c and the eighth gate 140d electrically connected to the second output terminal 124 are also arranged in the first direction 110 in a staggered manner.
請參考第7圖至第9圖，第7圖為本發明一第四較佳實施例之差動可變電容元件之上視示意圖，第8圖為沿著第7圖之剖面線CC’之剖面示意圖，且第9圖為沿著第7圖之剖面線DD’之剖面示意圖。如第7圖與第8圖所示，相較於第一實施例，本實施例之差動可變電容元件300的各差動可變電容單元係分別設於不同井區中。本實施例之差動可變電容元件300包含有一N型第一井區302、一N型第二井區304、三N型第三摻雜區306、三N型第四摻雜區308、二第三閘極結構310以及二第四閘極結構312。N型第一井區302與N型第二井區304設於P型基底102中，且沿著第一方向110排列。N型第三摻雜區306設於N型第一井區302中，且沿著第一方向110排列。N型第四摻雜區308設於N型第二井區304中，且沿著第一方向110排列。Please refer to FIG. 7 to FIG. 9 . FIG. 7 is a top view of a differential variable capacitance element according to a fourth preferred embodiment of the present invention, and FIG. 8 is a cross-sectional line CC′ along FIG. 7 . A schematic cross-sectional view, and Fig. 9 is a schematic cross-sectional view taken along line DD' of Fig. 7. As shown in FIGS. 7 and 8, the differential variable capacitance units of the differential variable capacitance element 300 of the present embodiment are respectively disposed in different well regions as compared with the first embodiment. The differential variable capacitance element 300 of the present embodiment includes an N-type first well region 302, an N-type second well region 304, a three-N-type third doping region 306, and a three-N-type fourth doping region 308. Two third gate structures 310 and two fourth gate structures 312. The N-type first well region 302 and the N-type second well region 304 are disposed in the P-type substrate 102 and are arranged along the first direction 110. N-type third doped regions 306 are disposed in the N-type first well region 302 and are aligned along the first direction 110. The N-type fourth doped regions 308 are disposed in the N-type second well region 304 and are aligned along the first direction 110.
並且，各第三閘極結構310設於N型第一井區302上，且分別位於任兩相鄰之N型第三摻雜區306之間。各第三閘極結構310包含有一第三絕緣層314、一閘極以及二第三側壁子316，其中各閘極分別設於各第三絕緣層314上，且第三側壁子316分別設於各閘極與各第三絕緣層314之兩側。此外，第三閘極結構310之閘極可區分為第一閘極318a與第二閘極318b，分別電性連接至第一輸出端122與第二輸出端124。兩相鄰之N型第三摻雜區306之間僅設置 有第一閘極318a與第二閘極318b之其中單一者。並且，N型第一井區302係藉由位於第一閘極318a與第二閘極318b之間的N型第三摻雜區306係電性連接至第三輸出端126。藉此，N型第一井區302、N型第三摻雜區306以及第三閘極結構310可構成一第三差動可變電容單元319。Moreover, each of the third gate structures 310 is disposed on the N-type first well region 302 and is respectively located between any two adjacent N-type third doping regions 306. Each of the third gate structures 310 includes a third insulating layer 314, a gate, and two third sidewalls 316. The gates are respectively disposed on the third insulating layers 314, and the third sidewalls 316 are respectively disposed on the third gate layer 316. Each of the gates and each of the third insulating layers 314 are on both sides. In addition, the gate of the third gate structure 310 can be divided into a first gate 318a and a second gate 318b, which are electrically connected to the first output terminal 122 and the second output terminal 124, respectively. Only two adjacent N-type third doping regions 306 are disposed between There is a single one of the first gate 318a and the second gate 318b. Moreover, the N-type first well region 302 is electrically connected to the third output terminal 126 by an N-type third doping region 306 between the first gate 318a and the second gate 318b. Thereby, the N-type first well region 302, the N-type third doping region 306, and the third gate structure 310 can constitute a third differential variable capacitance unit 319.
各第四閘極結構312設於N型第二井區304上，且分別位於任兩相鄰之N型第四摻雜區308之間。各第四閘極結構312包含有一第四絕緣層320、一閘極以及二第四側壁子322，其中各閘極分別設於各第四絕緣層320上，且第四側壁子322分別設於各閘極與各第四絕緣層320之兩側。此外，第四閘極結構312之閘極可區分為第三閘極324a與第四閘極324b，且第一閘極318a、第二閘極318b、第三閘極324a與第四閘極324b依序沿著第一方向110排列。兩相鄰之N型第四摻雜區308之間僅設置有第三閘極324a與第四閘極324b之其中單一者。第三閘極324a電性連接至第一輸出端122，且第四閘極324b電性連接至第二輸出端124。並且，N型第二井區304係藉由位於第三閘極324a與第四閘極324b之間的N型第四摻雜區308係電性連接至第三輸出端126。藉此，N型第二井區304、N型第四摻雜區308以及第四閘極結構312可構成一第四差動可變電容單元325。Each of the fourth gate structures 312 is disposed on the N-type second well region 304 and is respectively located between any two adjacent N-type fourth doped regions 308. Each of the fourth gate structures 312 includes a fourth insulating layer 320, a gate, and two fourth sidewalls 322. The gates are respectively disposed on the fourth insulating layers 320, and the fourth sidewalls 322 are respectively disposed on the fourth gate layer 322. Each of the gates and each of the fourth insulating layers 320 are on both sides. In addition, the gate of the fourth gate structure 312 can be divided into a third gate 324a and a fourth gate 324b, and the first gate 318a, the second gate 318b, the third gate 324a and the fourth gate 324b Arranged in the first direction 110 in sequence. Only one of the third gate 324a and the fourth gate 324b is disposed between the two adjacent N-type fourth doping regions 308. The third gate 324a is electrically connected to the first output terminal 122, and the fourth gate 324b is electrically connected to the second output terminal 124. Moreover, the N-type second well region 304 is electrically connected to the third output terminal 126 by an N-type fourth doping region 308 between the third gate 324a and the fourth gate 324b. Thereby, the N-type second well region 304, the N-type fourth doping region 308, and the fourth gate structure 312 can constitute a fourth differential variable capacitance unit 325.
另外，如第9圖所示，本實施例之差動可變電容元件300另包括一N型第三井區326、一N型第四井區328、三N型第五摻雜區330、 三N型第六摻雜區332、二第五閘極結構334以及二第六閘極結構336。N型第三井區326與N型第四井區328設於P型基底102中，並沿著第一方向110排列。N型第五摻雜區330設於N型第三井區326中，且沿著第一方向110排列。N型第六摻雜區332設於N型第四井區328中，且沿著第一方向110排列。第五閘極結構334設於N型第三井區326上，且分別位於任兩相鄰之N型第五摻雜區330之間，並與第三閘極結構310沿著第二方向134排列。各第五閘極結構334包含有一第五絕緣層338以及設於第五絕緣層338上之一閘極。並且，第五閘極結構334之閘極可區分為第五閘極340a與第六閘極340b。第六閘極結構336設於N型第四井區328上，且分別位於任兩相鄰之N型第六摻雜區332之間，並與第四閘極結構312沿著第二方向134排列。各第六閘極結構336包含有一第六絕緣層342以及設於第六絕緣層342上之一閘極。並且，第六閘極結構336之閘極可區分為第七閘極344a與第八閘極344b。第五閘極340a、第六閘極340b、第七閘極344a與第八閘極344b係依序沿著第一方向110排列。於本實施例中，第五閘極340a與第七閘極344a電性連接至第一輸出端122，且第六閘極340b與第八閘極344b電性連接至第二輸出端124。並且，N型第三井區326與N型第四井區328分別藉由位於第五閘極340a與第六閘極340b之間的N型第五摻雜區330以及位於第七閘極344a與第八閘極344b之間的N型第六摻雜區332係電性連接至第三輸出端126。藉此，N型第三井區326、N型第五摻雜區330以及第五閘極結構334可構成一第五差動可變電容單元345，且N型第四井區328、N型第六摻雜區332 以及第六閘極結構336可構成一第六差動可變電容單元346。In addition, as shown in FIG. 9, the differential variable capacitance element 300 of the present embodiment further includes an N-type third well region 326, an N-type fourth well region 328, and a three-N-type fifth doping region 330. Three N-type sixth doped regions 332, two fifth gate structures 334, and two sixth gate structures 336. The N-type third well region 326 and the N-type fourth well region 328 are disposed in the P-type substrate 102 and are arranged along the first direction 110. The N-type fifth doped regions 330 are disposed in the N-type third well region 326 and are aligned along the first direction 110. The N-type sixth doped regions 332 are disposed in the N-type fourth well region 328 and are aligned along the first direction 110. The fifth gate structure 334 is disposed on the N-type third well region 326 and is respectively located between any two adjacent N-type fifth doping regions 330 and along the third gate structure 310 along the second direction 134. arrangement. Each of the fifth gate structures 334 includes a fifth insulating layer 338 and a gate disposed on the fifth insulating layer 338. Moreover, the gate of the fifth gate structure 334 can be divided into a fifth gate 340a and a sixth gate 340b. The sixth gate structure 336 is disposed on the N-type fourth well region 328 and is respectively located between any two adjacent N-type sixth doping regions 332 and along the fourth gate structure 312 along the second direction 134. arrangement. Each of the sixth gate structures 336 includes a sixth insulating layer 342 and a gate disposed on the sixth insulating layer 342. Moreover, the gate of the sixth gate structure 336 can be divided into a seventh gate 344a and an eighth gate 344b. The fifth gate 340a, the sixth gate 340b, the seventh gate 344a, and the eighth gate 344b are sequentially arranged along the first direction 110. In this embodiment, the fifth gate 340a and the seventh gate 344a are electrically connected to the first output end 122, and the sixth gate 340b and the eighth gate 344b are electrically connected to the second output end 124. Moreover, the N-type third well region 326 and the N-type fourth well region 328 are respectively disposed by the N-type fifth doping region 330 between the fifth gate 340a and the sixth gate 340b and at the seventh gate 344a. The N-type sixth doping region 332 between the eighth gate 344b and the eighth gate 344b is electrically connected to the third output terminal 126. Thereby, the N-type third well region 326, the N-type fifth doping region 330, and the fifth gate structure 334 can constitute a fifth differential variable capacitance unit 345, and the N-type fourth well region 328, N-type Sixth doping region 332 And the sixth gate structure 336 can constitute a sixth differential variable capacitance unit 346.
請參考第10圖與第11圖，第10圖為本發明一第五較佳實施例之差動可變電容元件之上視示意圖，且第11圖為本發明一第六較佳實施例之差動可變電容元件之上視示意圖。如第10圖所示，相較於第四實施例，第五導電層128e與第七導電層128g係電性連接至第二輸出端124，使第五閘極340a與第七閘極344a可電性連接至第二輸出端124，且第六導電層128f與第八導電層128h係電性連接至第一輸出端122，使第六閘極340b與第八閘極344b可電性連接至第一輸出端122。如第11圖所示，相較於第四實施例，第一導電層128a、第二導電層128b、第五導電層128e與第六導電層128f係電性連接至第一輸出端122，使第一閘極318a、第二閘極318b、第五閘極340a與第六閘極340b電性連接至第一輸出端122，且第三導電層128c、第四導電層128d、第七導電層128g與第八導電層128h係電性連接至第二輸出端124，使第三閘極324a、第四閘極324b、第七閘極344a與第八閘極344b電性連接至第二輸出端124。Please refer to FIG. 10 and FIG. 11 , FIG. 10 is a top view of a differential variable capacitance element according to a fifth preferred embodiment of the present invention, and FIG. 11 is a sixth preferred embodiment of the present invention. The top view of the differential variable capacitance element is shown. As shown in FIG. 10, the fifth conductive layer 128e and the seventh conductive layer 128g are electrically connected to the second output end 124, so that the fifth gate 340a and the seventh gate 344a are The second conductive layer 128f is electrically connected to the first output end 122, and the sixth gate 340b and the eighth gate 344b are electrically connected to the sixth gate 344b. The first output terminal 122. As shown in FIG. 11 , the first conductive layer 128 a , the second conductive layer 128 b , the fifth conductive layer 128 e and the sixth conductive layer 128 f are electrically connected to the first output end 122 , so that The first gate 318a, the second gate 318b, the fifth gate 340a and the sixth gate 340b are electrically connected to the first output end 122, and the third conductive layer 128c, the fourth conductive layer 128d, and the seventh conductive layer 128g and the eighth conductive layer 128h are electrically connected to the second output end 124, and the third gate 324a, the fourth gate 324b, the seventh gate 344a and the eighth gate 344b are electrically connected to the second output end. 124.
以下將進一步說明本發明各較佳實施例之差動可變電容元件之功效。請參閱表1。表1係列舉了當差動可變電容元件運作在10GHz的操作頻率下各實施例之差動可變電元件的最大電容值與最小電容值以及其調諧比值，亦即最大電容值與最小電容值之比值。如表1所示，當電性連接至一閘極電壓之兩閘極與電性連接至另一閘極電壓之兩閘極係沿著第一方向兩兩交錯排列時，差動可變電容元件之 調諧比值可大於3.68。將電性連接至不同閘極電壓之閘極沿著第一方向交錯設置，且同時將不同之差動可變電容單元設於不同N型井區中，差動可變電容元件之調諧比值係大於4.13。並且，電性連接至不同閘極電壓之閘極沿著第一方向交錯設置，且同時將不同之差動可變電容單元設於同一N型井區中，差動可變電容元件之調諧比值係大於4.83。因此，本發明之差動可變電容元件可有效地提升調諧比值，且增加差動可變電容元件之可調整電容範圍。The effects of the differential variable capacitance element of each of the preferred embodiments of the present invention will be further described below. Please refer to Table 1. Table 1 series shows the maximum capacitance value and minimum capacitance value of the differential variable element of each embodiment when the differential variable capacitance element operates at an operating frequency of 10 GHz, and the tuning ratio thereof, that is, the maximum capacitance value and the minimum capacitance. The ratio of values. As shown in Table 1, when two gates electrically connected to one gate voltage and two gates electrically connected to another gate voltage are staggered in the first direction, the differential variable capacitor Component The tuning ratio can be greater than 3.68. The gates electrically connected to different gate voltages are staggered along the first direction, and at the same time, different differential variable capacitor units are disposed in different N-type well regions, and the tuning ratio of the differential variable capacitance elements is Greater than 4.13. Moreover, the gates electrically connected to different gate voltages are staggered along the first direction, and at the same time, different differential variable capacitor units are disposed in the same N-type well region, and the tuning ratio of the differential variable capacitance component is The system is greater than 4.83. Therefore, the differential variable capacitance element of the present invention can effectively increase the tuning ratio and increase the adjustable capacitance range of the differential variable capacitance element.
綜上所述，本發明之差動可變電容元件藉由將電性連接至不同閘極電壓之閘極沿著一方向交錯排列，以及將不同之差動可變電容單元設於同一井區中，使調諧比值大於4，進而有效提升其可調整之電容範圍。In summary, the differential variable capacitance device of the present invention is staggered in one direction by gates electrically connected to different gate voltages, and different differential variable capacitance units are disposed in the same well region. In the middle, the tuning ratio is greater than 4, thereby effectively increasing the adjustable capacitance range.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above description is only a preferred embodiment of the present invention, and the patent application scope according to the present invention Equivalent changes and modifications made are intended to be within the scope of the present invention.
100‧‧‧差動可變電容元件100‧‧‧Differential variable capacitance element
102‧‧‧基底102‧‧‧Base
104‧‧‧井區104‧‧‧ Well Area
106‧‧‧第一摻雜區106‧‧‧First doped area
108‧‧‧第一閘極結構108‧‧‧First gate structure
110‧‧‧第一方向110‧‧‧First direction
112‧‧‧第一絕緣層112‧‧‧First insulation
114a‧‧‧第一閘極114a‧‧‧first gate
114b‧‧‧第二閘極114b‧‧‧second gate
114c‧‧‧第三閘極114c‧‧‧third gate
114d‧‧‧第四閘極114d‧‧‧fourth gate
116‧‧‧第一側壁子116‧‧‧First side wall
117‧‧‧第一可變電容117‧‧‧First variable capacitor
118‧‧‧摻雜區118‧‧‧Doped area
119‧‧‧第一差動可變電容單元119‧‧‧First Differential Variable Capacitor Unit
120‧‧‧接觸插塞120‧‧‧Contact plug
122‧‧‧第一輸出端122‧‧‧ first output
124‧‧‧第二輸出端124‧‧‧second output
126‧‧‧第三輸出端126‧‧‧ third output
128a‧‧‧第一導電層128a‧‧‧First conductive layer
128b‧‧‧第二導電層128b‧‧‧Second conductive layer
128c‧‧‧第三導電層128c‧‧‧ third conductive layer
128d‧‧‧第四導電層128d‧‧‧fourth conductive layer
128e‧‧‧第五導電層128e‧‧‧ fifth conductive layer
128f‧‧‧第六導電層128f‧‧‧ sixth conductive layer
128g‧‧‧第七導電層128g‧‧‧ seventh conductive layer
128h‧‧‧第八導電層128h‧‧‧8th conductive layer
130‧‧‧第二閘極結構130‧‧‧Second gate structure
132‧‧‧第二摻雜區132‧‧‧Second doped area
134‧‧‧第二方向134‧‧‧second direction
136‧‧‧第二絕緣層136‧‧‧Second insulation
138‧‧‧第二側壁子138‧‧‧Second side wall
139‧‧‧第二可變電容139‧‧‧Second variable capacitor
140a‧‧‧第五閘極140a‧‧‧ fifth gate
140b‧‧‧第六閘極140b‧‧‧ sixth gate
140c‧‧‧第七閘極140c‧‧‧ seventh gate
140d‧‧‧第八閘極140d‧‧‧eightth gate
141‧‧‧第二差動可變電容單元141‧‧‧Second differential variable capacitor unit
200‧‧‧差動可變電容元件200‧‧‧Differential variable capacitance element
250‧‧‧差動可變電容元件250‧‧‧Differential variable capacitance components
300‧‧‧差動可變電容元件300‧‧‧Differential variable capacitance components
302‧‧‧第一井區302‧‧‧First Well Area
304‧‧‧第二井區304‧‧‧Second well area
306‧‧‧第三摻雜區306‧‧‧ Third doped area
308‧‧‧第四摻雜區308‧‧‧fourth doping zone
310‧‧‧第三閘極結構310‧‧‧ Third Gate Structure
312‧‧‧第四閘極結構312‧‧‧fourth gate structure
314‧‧‧第三絕緣層314‧‧‧ Third insulation layer
316‧‧‧第三側壁子316‧‧‧ third side wall
318a‧‧‧第一閘極318a‧‧‧first gate
318b‧‧‧第二閘極318b‧‧‧second gate
319‧‧‧第三差動可變電容單元319‧‧‧3rd differential variable capacitor unit
320‧‧‧第四絕緣層320‧‧‧fourth insulation
322‧‧‧第四側壁子322‧‧‧fourth side wall
324a‧‧‧第三閘極324a‧‧‧third gate
324b‧‧‧第四閘極324b‧‧‧fourth gate
325‧‧‧第四差動可變電容單元325‧‧‧fourth differential variable capacitor unit
326‧‧‧第三井區326‧‧‧ Third Well Area
328‧‧‧第四井區328‧‧‧Four Well Area
330‧‧‧第五摻雜區330‧‧‧ fifth doping area
332‧‧‧第六摻雜區332‧‧‧ sixth doping area
334‧‧‧第五閘極結構334‧‧‧ fifth gate structure
336‧‧‧第六閘極結構336‧‧‧ sixth gate structure
338‧‧‧第五絕緣層338‧‧‧ fifth insulation
340a‧‧‧第五閘極340a‧‧‧ fifth gate
340b‧‧‧第六閘極340b‧‧‧ sixth gate
342‧‧‧第六絕緣層342‧‧‧ sixth insulation layer
344a‧‧‧第七閘極344a‧‧‧ seventh gate
344b‧‧‧第八閘極344b‧‧‧ eighth gate
345‧‧‧第五差動可變電容單元345‧‧‧ fifth differential variable capacitor unit
346‧‧‧第六差動可變電容單元346‧‧‧ sixth differential variable capacitor unit
第1圖為本發明一第一較佳實施例之差動可變電容元件的上視示意圖。Fig. 1 is a top plan view showing a differential variable capacitance element according to a first preferred embodiment of the present invention.
第2圖為沿著第1圖之剖面線AA’之剖面示意圖。Fig. 2 is a schematic cross-sectional view taken along line AA' of Fig. 1.
第3圖為沿著第1圖之剖面線BB’之剖面示意圖。Fig. 3 is a schematic cross-sectional view taken along line BB' of Fig. 1.
第4圖為本發明第一較佳實施例之另一變化形的差動可變電容元件之上視示意圖。Fig. 4 is a top plan view showing another variation of the differential variable capacitance element according to the first preferred embodiment of the present invention.
第5圖為本發明一第二較佳實施例之差動可變電容元件之上視示意圖。Figure 5 is a top plan view of a differential variable capacitance element according to a second preferred embodiment of the present invention.
第6圖為本發明一第三較佳實施例之差動可變電容元件之上視示意圖。Figure 6 is a top plan view of a differential variable capacitance element according to a third preferred embodiment of the present invention.
第7圖為本發明一第四較佳實施例之差動可變電容元件之上視示意圖。Figure 7 is a top plan view of a differential variable capacitance element according to a fourth preferred embodiment of the present invention.
第8圖為沿著第7圖之剖面線CC’之剖面示意圖。Fig. 8 is a schematic cross-sectional view taken along line CC' of Fig. 7.
第9圖為沿著第7圖之剖面線DD’之剖面示意圖。Fig. 9 is a schematic cross-sectional view taken along line DD' of Fig. 7.
第10圖為本發明一第五較佳實施例之差動可變電容元件之上視示意圖。Figure 10 is a top plan view of a differential variable capacitance element according to a fifth preferred embodiment of the present invention.
第11圖為本發明一第六較佳實施例之差動可變電容元件之上視示意圖。Figure 11 is a top plan view of a differential variable capacitance element according to a sixth preferred embodiment of the present invention.
102．．．基底102. . . Base
104．．．井區104. . . Well area
106．．．第一摻雜區106. . . First doped region
108．．．第一閘極結構108. . . First gate structure
112．．．第一絕緣層112. . . First insulating layer
114a．．．第一閘極114a. . . First gate
114b．．．第二閘極114b. . . Second gate
114c．．．第三閘極114c. . . Third gate
114d．．．第四閘極114d. . . Fourth gate
116．．．第一側壁子116. . . First side wall
117．．．第一可變電容117. . . First variable capacitor
118．．．摻雜區118. . . Doped region
119．．．第一差動可變電容單元119. . . First differential variable capacitance unit
120．．．接觸插塞120. . . Contact plug
128a．．．第一導電層128a. . . First conductive layer
128b．．．第二導電層128b. . . Second conductive layer
128c．．．第三導電層128c. . . Third conductive layer
128d．．．第四導電層128d. . . Fourth conductive layer
Claims (22)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100123829A TWI513011B (en) | 2011-07-06 | 2011-07-06 | Differential varactor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100123829A TWI513011B (en) | 2011-07-06 | 2011-07-06 | Differential varactor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201304151A TW201304151A (en) | 2013-01-16 |
| TWI513011B true TWI513011B (en) | 2015-12-11 |
Family
ID=48138210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100123829A TWI513011B (en) | 2011-07-06 | 2011-07-06 | Differential varactor device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI513011B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW587302B (en) * | 2001-03-07 | 2004-05-11 | United Microelectronics Corp | Manufacturing method for MOS capacitor |
| TW200532813A (en) * | 2004-03-30 | 2005-10-01 | United Microelectronics Corp | Varactor and differential varactor |
| TW200610103A (en) * | 2004-08-27 | 2006-03-16 | Ibm | MOS varactor using isolation well |
| TW200715576A (en) * | 2005-10-07 | 2007-04-16 | Integrated Digital Tech Inc | Photo detector array |
| TW200950059A (en) * | 2008-01-16 | 2009-12-01 | Renesas Tech Corp | Semiconductor device |
-
2011
- 2011-07-06 TW TW100123829A patent/TWI513011B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW587302B (en) * | 2001-03-07 | 2004-05-11 | United Microelectronics Corp | Manufacturing method for MOS capacitor |
| TW200532813A (en) * | 2004-03-30 | 2005-10-01 | United Microelectronics Corp | Varactor and differential varactor |
| TW200610103A (en) * | 2004-08-27 | 2006-03-16 | Ibm | MOS varactor using isolation well |
| TW200715576A (en) * | 2005-10-07 | 2007-04-16 | Integrated Digital Tech Inc | Photo detector array |
| TW200950059A (en) * | 2008-01-16 | 2009-12-01 | Renesas Tech Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201304151A (en) | 2013-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10367514B2 (en) | Passive phased injection locked circuit | |
| JP3877597B2 (en) | Multi-terminal MOS varactor | |
| US8624683B2 (en) | Semiconductor device | |
| US11495382B2 (en) | High Q-factor inductor | |
| KR102451528B1 (en) | Cmos varactor with increased tuning range | |
| US10115835B2 (en) | Variable capacitor based on buried oxide process | |
| US10181533B2 (en) | Transcap manufacturing techniques without a silicide-blocking mask | |
| US9159718B2 (en) | Switched capacitor structure | |
| US20140184346A1 (en) | Voltage-Controlled Oscillator Circuit Structure | |
| US8502348B2 (en) | Differential varactor device | |
| TWI536742B (en) | Time-to-digital converter, forming method thereof and delay unit structure | |
| TWI513011B (en) | Differential varactor device | |
| JP4110792B2 (en) | Capacitor element and semiconductor integrated circuit using capacitor element | |
| US9847433B2 (en) | Integrated MOS varicap, and voltage controlled oscillator and filter having same | |
| TW201840008A (en) | Variable capacitor structures with reduced channel resistance | |
| US10319866B2 (en) | Layout techniques for transcap area optimization | |
| CN102891144A (en) | Differential variable capacitor element | |
| TWI536730B (en) | Quadrature phase relaxation oscillator | |
| US20060012009A1 (en) | Semiconductor device | |
| US20190305143A1 (en) | Apparatuses and methods for a variable capacitor | |
| US20180240915A1 (en) | Advanced techniques to manipulate the c-v characteristics of variable capacitors | |
| JP2005101295A (en) | Differential voltage controlled oscillator |