TWI513004B - Tft and method for manufacturing the same - Google Patents
Tft and method for manufacturing the same Download PDFInfo
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Description
本發明涉及一種薄膜電晶體及其製造方法。 The present invention relates to a thin film transistor and a method of manufacturing the same.
傳統之底柵式薄膜電晶體一般包括基板、依次形成在該基板上之柵極、柵極絕緣層、半導體層以及源極電極和漏極電極，源極電極和漏極電極之間形成有溝道。通常，如果該溝道之寬度太寬，會造成薄膜電晶體之整體尺寸過大，從而影響畫素之開口率，因此為了提高開口率，需要減小薄膜電晶體之尺寸，所以也必須將溝道之寬度做小。 A conventional bottom-gate thin film transistor generally includes a substrate, a gate electrode sequentially formed on the substrate, a gate insulating layer, a semiconductor layer, and source and drain electrodes, and a trench is formed between the source electrode and the drain electrode. Road. Generally, if the width of the channel is too wide, the overall size of the thin film transistor is too large, thereby affecting the aperture ratio of the pixel. Therefore, in order to increase the aperture ratio, it is necessary to reduce the size of the thin film transistor, so the channel must also be The width is small.
一般情況下，源極電極和漏極電極是採用同樣之金屬層構造，然後利用一道光刻製程加工該金屬層形成所述源極電極、漏極電極以及溝道。但是由於所形成之溝道之寬度會受到光刻製程中之掩模之圖案加工精度之制約，會具有一定之寬度而無法做到更短，所以無法提高開口率。 In general, the source electrode and the drain electrode are constructed using the same metal layer, and then the metal layer is processed by a photolithography process to form the source electrode, the drain electrode, and the channel. However, since the width of the formed channel is limited by the pattern processing precision of the mask in the photolithography process, it has a certain width and cannot be made shorter, so the aperture ratio cannot be improved.
有鑑於此，有必要提供一種不受光刻加工精度制約，溝道寬度較小之薄膜電晶體及其製造方法。 In view of the above, it is necessary to provide a thin film transistor which is not restricted by the precision of photolithography processing and has a small channel width, and a method of manufacturing the same.
一種薄膜電晶體，其包括基板以及形成在基板上之柵極、半導體層、源極電極和漏極電極。所述源極電極與漏極電極分別在不同之光刻製程中形成。 A thin film transistor comprising a substrate and a gate, a semiconductor layer, a source electrode, and a drain electrode formed on the substrate. The source electrode and the drain electrode are respectively formed in different photolithography processes.
一種薄膜電晶體之製造方法，其包括以下幾個步驟：提供一個基板，並在該基板上形成柵極以及半導體層；利用一道光刻製程形成漏極電極；利用另一道光刻製程形成源極電極。 A method for manufacturing a thin film transistor, comprising the steps of: providing a substrate, forming a gate electrode and a semiconductor layer on the substrate; forming a drain electrode by using a photolithography process; and forming a source by another photolithography process electrode.
上述之薄膜電晶體及其製造方法中，漏極電極以及源極電極是採用兩道光刻製程分別形成，而傳統工藝中，漏極電極和源極電極是極採用同一光刻製程加工同一金屬層而形成，因此相對於傳統工藝，本發明之漏極電極和源極電極之間之溝道之寬度主要由漏極電極和源極電極之間之間隙所決定，不會受到同一光刻製程中之掩模之圖案加工精度之制約，因此可以做之更小。 In the above thin film transistor and the manufacturing method thereof, the drain electrode and the source electrode are respectively formed by two photolithography processes, and in the conventional process, the drain electrode and the source electrode are processed by the same photolithography process to process the same metal. The layer is formed, so the width of the channel between the drain electrode and the source electrode of the present invention is mainly determined by the gap between the drain electrode and the source electrode, and is not subjected to the same photolithography process. The mask processing in the mask is limited by the processing precision, so it can be made smaller.
100、200、300‧‧‧薄膜電晶體 100, 200, 300‧‧‧ film transistors
10‧‧‧基板 10‧‧‧Substrate
20‧‧‧柵極 20‧‧‧Gate
30‧‧‧柵極絕緣層 30‧‧‧Gate insulation
40‧‧‧半導體層 40‧‧‧Semiconductor layer
50‧‧‧蝕刻阻擋層 50‧‧‧ etching barrier
60‧‧‧漏極電極 60‧‧‧Drain electrode
70‧‧‧源極電極 70‧‧‧Source electrode
80‧‧‧保護層 80‧‧ ‧ protective layer
90‧‧‧溝道 90‧‧‧Channel
60a‧‧‧透明導電膜層 60a‧‧‧Transparent conductive film layer
60b‧‧‧金屬層 60b‧‧‧metal layer
圖1為本發明第一實施方式中之薄膜電晶體之截面示意圖。 1 is a schematic cross-sectional view showing a thin film transistor in a first embodiment of the present invention.
圖2為本發明第二實施方式中之薄膜電晶體之截面示意圖。 2 is a schematic cross-sectional view showing a thin film transistor in a second embodiment of the present invention.
圖3為本發明第三實施方式中之薄膜電晶體之截面示意圖。 3 is a schematic cross-sectional view showing a thin film transistor in a third embodiment of the present invention.
請參閱圖1，本發明第一實施方式提供之一種薄膜電晶體100包括基板10以及形成在該基板10上之柵極20、柵極絕緣層30、半導體層40、蝕刻阻擋層50、漏極電極60、源極電極70、保護層80。 Referring to FIG. 1 , a thin film transistor 100 according to a first embodiment of the present invention includes a substrate 10 , a gate electrode 20 formed on the substrate 10 , a gate insulating layer 30 , a semiconductor layer 40 , an etch stop layer 50 , and a drain electrode . Electrode 60, source electrode 70, and protective layer 80.
所述基板10為絕緣基板，其可以為玻璃、石英或者陶瓷等絕緣材料。在本實施例中，該基板10為玻璃基板。 The substrate 10 is an insulating substrate, which may be an insulating material such as glass, quartz or ceramic. In the present embodiment, the substrate 10 is a glass substrate.
所述柵極20形成在基板10之表面，所述柵極絕緣層30覆蓋柵極20 形成在基板10之表面，該柵極絕緣層30包括氮化矽及/或氧化矽。 The gate electrode 20 is formed on a surface of the substrate 10, and the gate insulating layer 30 covers the gate electrode 20. Formed on the surface of the substrate 10, the gate insulating layer 30 includes tantalum nitride and/or hafnium oxide.
所述半導體層40形成在柵極絕緣層30上並位於柵極20之正上方，該半導體層40採用非晶質氧化半導體材料(Amorphous Oxide Semiconductor,AOS)，在本實施方式中，該半導體層40是採用IGZO系氧化物材料。所述蝕刻阻擋層50形成在半導體層40上。 The semiconductor layer 40 is formed on the gate insulating layer 30 and directly above the gate electrode 20. The semiconductor layer 40 is made of an amorphous oxide semiconductor material (AOS). In the embodiment, the semiconductor layer is used. 40 is an IGZO-based oxide material. The etch stop layer 50 is formed on the semiconductor layer 40.
所述漏極電極60形成在柵極絕緣層30上並且延伸覆蓋在半導體層40以及蝕刻阻擋層50之一側表面上。該漏極電極60採用Mo、Al、Cu、Ti等金屬材料構成。 The drain electrode 60 is formed on the gate insulating layer 30 and extends over one side surface of the semiconductor layer 40 and the etch barrier layer 50. The drain electrode 60 is made of a metal material such as Mo, Al, Cu, or Ti.
所述源極電極70形成在柵極絕緣層30上並且延伸覆蓋在半導體層40以及蝕刻阻擋層50之另一側表面上。源極電極70與漏極電極60之間形成一溝道90。該源極電極70採用銦錫氧化物薄膜(Indium Tin Oxide,ITO)等透明導電膜，同時還作為所述薄膜電晶體100之畫素電極。漏極電極60與源極電極70分別在不同之光刻製程中形成。 The source electrode 70 is formed on the gate insulating layer 30 and extends over the other side surface of the semiconductor layer 40 and the etch barrier layer 50. A channel 90 is formed between the source electrode 70 and the drain electrode 60. The source electrode 70 is made of a transparent conductive film such as an indium tin oxide film (ITO), and also serves as a pixel electrode of the thin film transistor 100. The drain electrode 60 and the source electrode 70 are respectively formed in different photolithography processes.
在本實施方式中，半導體層40因為是非晶質氧化半導體結構，所以其可直接與形成其上之源極電極70形成電連接。傳統之薄膜電晶體一般是採用非晶矽(a-si)半導體結構，在非晶矽半導體結構上層積ITO時，ITO主要成分之氧化銦中之氧會和非晶矽反應，生成矽氧化物，因矽氧化物電阻高，非晶矽和ITO不能夠電連接，因此需要在兩者之間設置一金屬層。而本發明之半導體層40採用IGZO這樣之非晶質氧化半導體材料，因為其本身為氧化物，因此與ITO之性質比較接近，所以可以直接與ITO構成之源極電極70形成電連接。 In the present embodiment, since the semiconductor layer 40 is an amorphous oxide semiconductor structure, it can be electrically connected directly to the source electrode 70 formed thereon. Conventional thin film transistors generally use an amorphous germanium (a-si) semiconductor structure. When ITO is laminated on an amorphous germanium semiconductor structure, oxygen in the indium oxide of the main component of ITO reacts with amorphous germanium to form germanium oxide. Since the oxide resistance is high, the amorphous germanium and the ITO cannot be electrically connected, so it is necessary to provide a metal layer between the two. On the other hand, the semiconductor layer 40 of the present invention uses an amorphous oxidized semiconductor material such as IGZO. Since it is an oxide itself, it is relatively close to the nature of ITO, so that it can be directly electrically connected to the source electrode 70 made of ITO.
所述保護層80覆蓋所述柵極絕緣層30、蝕刻阻擋層50、漏極電極60以及源極電極70。 The protective layer 80 covers the gate insulating layer 30, the etch stop layer 50, the drain electrode 60, and the source electrode 70.
本發明第一實施方式提供之薄膜電晶體100之製造方法包括以下幾個步驟： The manufacturing method of the thin film transistor 100 provided by the first embodiment of the present invention includes the following steps:
步驟一：提供一個基板10，並在該基板上形成柵極20、柵極絕緣層30、半導體層40。在本實施方式中，形成柵極20、柵極絕緣層30、半導體層40可分別採用兩道光刻製程。具體方法為：第一道光刻製程用於形成柵極金屬層，即，在該基板10上依序形成一柵極金屬層和一第一光致抗蝕劑層；再以第一道光罩之圖案對該第一光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該柵極金屬層進行蝕刻，然後移除第一光致抗蝕劑層，形成柵極20。第二道光刻製程用於形成柵極絕緣層30和半導體層40，即，在具有該柵極20之基板10上形成一柵極絕緣層30、一非晶質氧化半導體層和一第二光致抗蝕劑層；再以第二道光罩之圖案對該第二光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該非晶質氧化半導體層進行蝕刻，然後移除第二光致抗蝕劑層，形成一具有預定圖案之半導體層40。 Step 1: A substrate 10 is provided, and a gate electrode 20, a gate insulating layer 30, and a semiconductor layer 40 are formed on the substrate. In the present embodiment, the gate electrode 20, the gate insulating layer 30, and the semiconductor layer 40 can be formed by two photolithography processes, respectively. The specific method is as follows: a first photolithography process is used to form a gate metal layer, that is, a gate metal layer and a first photoresist layer are sequentially formed on the substrate 10; The first photoresist layer is exposed and developed to form a predetermined pattern, the gate metal layer is etched, and then the first photoresist layer is removed to form the gate electrode 20. The second photolithography process is used to form the gate insulating layer 30 and the semiconductor layer 40, that is, a gate insulating layer 30, an amorphous oxide semiconductor layer, and a second are formed on the substrate 10 having the gate 20. a photoresist layer; exposure and development of the second photoresist layer in a pattern of a second mask to form a predetermined pattern, etching the amorphous oxide semiconductor layer, and then removing the second The photoresist layer forms a semiconductor layer 40 having a predetermined pattern.
步驟二：在半導體層40上形成一蝕刻阻擋層50。 Step 2: Forming an etch stop layer 50 on the semiconductor layer 40.
步驟三：利用一道光刻製程形成漏極電極60。所述漏極電極60為金屬材料構成。在本實施方式中，形成漏極電極60之具體方法為：在形成有柵極20、柵極絕緣層30和半導體層40之基板10上形成一金屬層和一第三光致抗蝕劑層；再以第三道光罩之圖案對該第三光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該金屬層進行蝕刻，然後移除第三光致抗蝕劑層，形成漏極電極60。 Step 3: The drain electrode 60 is formed by a photolithography process. The drain electrode 60 is made of a metal material. In the present embodiment, a specific method of forming the drain electrode 60 is to form a metal layer and a third photoresist layer on the substrate 10 on which the gate electrode 20, the gate insulating layer 30, and the semiconductor layer 40 are formed. And then exposing and developing the third photoresist layer in a pattern of a third mask to form a predetermined pattern, etching the metal layer, and then removing the third photoresist layer to form a drain Polar electrode 60.
步驟四：利用另一道光刻製程形成源極電極70。所述源極電極70採用銦錫氧化物薄膜(Indium Tin Oxide,ITO)等透明導電膜。在本實施方式中，形成源極電極70之具體方法為：在形成有柵極20、柵極絕緣層30、半導體層40和漏極電極60之基板10上形成一透明導電膜和一第四光致抗蝕劑層；再以第四道光罩之圖案對該第四光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該透明導電膜進行蝕刻，然後移除第四光致抗蝕劑層，形成源極電極70。 Step 4: The source electrode 70 is formed by another photolithography process. The source electrode 70 is made of a transparent conductive film such as an indium tin oxide film (ITO). In the present embodiment, a specific method of forming the source electrode 70 is to form a transparent conductive film and a fourth on the substrate 10 on which the gate electrode 20, the gate insulating layer 30, the semiconductor layer 40, and the drain electrode 60 are formed. a photoresist layer; the fourth photoresist layer is exposed and developed in a pattern of a fourth mask to form a predetermined pattern, the transparent conductive film is etched, and then the fourth photo is removed The resist layer forms the source electrode 70.
步驟五：在基板10上形成保護層80。在本實施方式中，形成保護層80之具體方法為：在形成有柵極20、柵極絕緣層30、半導體層40、漏極電極60和源極電極70之基板10上沉積一鈍化層和一第五光致抗蝕劑層；再以第五道光罩之圖案對該第五光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該鈍化層進行蝕刻，然後移除第五光致抗蝕劑層，形成保護層80。 Step 5: A protective layer 80 is formed on the substrate 10. In the present embodiment, a specific method of forming the protective layer 80 is to deposit a passivation layer on the substrate 10 on which the gate electrode 20, the gate insulating layer 30, the semiconductor layer 40, the drain electrode 60, and the source electrode 70 are formed. a fifth photoresist layer; the fifth photoresist layer is exposed and developed in a pattern of a fifth mask to form a predetermined pattern, the passivation layer is etched, and then the fifth layer is removed The photoresist layer forms a protective layer 80.
可以理解之是，在本發明之薄膜電晶體100之製造方法中，也可以先形成源極電極70，而後形成漏極電極60，即步驟三和步驟四順序可以顛倒。 It can be understood that, in the manufacturing method of the thin film transistor 100 of the present invention, the source electrode 70 may be formed first, and then the drain electrode 60 may be formed, that is, the steps 3 and 4 may be reversed.
在本發明之薄膜電晶體100中，所述漏極電極60以及所述源極電極70是採用兩道光刻製程分別形成，相對於傳統工藝中漏極電極和源極電極採用同一光刻製程加工，本發明之漏極電極60和源極電極70之間之溝道90之寬度主要由漏極電極60和源極電極70之間之間隙所決定，不會受到同一光刻製程中之掩模之圖案加工精度之制約，因此可以做之更小。另外，源極電極70是採用和畫素電極相同之ＩTO等透明導電膜材料形成，因此源極電極70也能夠貢 獻一部分透過率，所以能夠大大提高開口率。 In the thin film transistor 100 of the present invention, the drain electrode 60 and the source electrode 70 are respectively formed by two photolithography processes, and the same photolithography process is used as compared with the drain electrode and the source electrode in the conventional process. The width of the channel 90 between the drain electrode 60 and the source electrode 70 of the present invention is mainly determined by the gap between the drain electrode 60 and the source electrode 70, and is not masked by the same photolithography process. The pattern processing precision of the mold is limited, so it can be made smaller. Further, since the source electrode 70 is formed of a transparent conductive film material such as ITO which is the same as the pixel electrode, the source electrode 70 can also be tributed. A part of the transmission rate is provided, so the aperture ratio can be greatly improved.
請參閱圖2，本發明第二實施方式提供之薄膜電晶體200與第一實施方式中之薄膜電晶體100之區別在於：薄膜電晶體200之漏極電極60是由透明導電膜層60a以及積層在透明導電膜層60a上之金屬層60b構成。在本實施方式中，所述透明導電膜層60a為ITO層。 Referring to FIG. 2, the thin film transistor 200 according to the second embodiment of the present invention is different from the thin film transistor 100 of the first embodiment in that the drain electrode 60 of the thin film transistor 200 is composed of a transparent conductive film layer 60a and a laminate. The metal layer 60b is formed on the transparent conductive film layer 60a. In the present embodiment, the transparent conductive film layer 60a is an ITO layer.
本發明第二實施方式提供之薄膜電晶體200之製造方法包括以下幾個步驟： The manufacturing method of the thin film transistor 200 provided by the second embodiment of the present invention includes the following steps:
步驟一：提供一個基板10，並在該基板上形成柵極20、柵極絕緣層30、半導體層40。形成柵極20、柵極絕緣層30以及半導體層40之方法同上。 Step 1: A substrate 10 is provided, and a gate electrode 20, a gate insulating layer 30, and a semiconductor layer 40 are formed on the substrate. The method of forming the gate electrode 20, the gate insulating layer 30, and the semiconductor layer 40 is the same as above.
步驟二：在半導體層40上形成一蝕刻阻擋層50。 Step 2: Forming an etch stop layer 50 on the semiconductor layer 40.
步驟三：在形成有柵極20、柵極絕緣層30、半導體層40以及蝕刻阻擋層50之基板10上形成一透明導電膜。所述透明導電膜為銦錫氧化物薄膜(Indium Tin Oxide,ITO)等。 Step 3: Forming a transparent conductive film on the substrate 10 on which the gate electrode 20, the gate insulating layer 30, the semiconductor layer 40, and the etch barrier layer 50 are formed. The transparent conductive film is an indium tin oxide film (ITO) or the like.
步驟四：利用一道光刻製程形成漏極電極60。在本實施方式中，形成漏極電極60之具體方法為：在透明導電膜上形成一金屬層和一光致抗蝕劑層；再以一道光罩之圖案對該光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該金屬層進行蝕刻，然後移除光致抗蝕劑層，形成漏極電極60。由此形成之漏極電極60是由透明導電膜和金屬材料構成。 Step 4: The drain electrode 60 is formed by a photolithography process. In this embodiment, a specific method of forming the drain electrode 60 is: forming a metal layer and a photoresist layer on the transparent conductive film; and performing the photoresist layer in a pattern of a mask. Exposure is developed to form a predetermined pattern, the metal layer is etched, and then the photoresist layer is removed to form the drain electrode 60. The drain electrode 60 thus formed is composed of a transparent conductive film and a metal material.
步驟五：利用另一道光刻製程對所述透明導電膜進行加工，形成 源極電極70。在本實施方式中，形成源極電極70之具體方法為：在透明導電膜上形成一光致抗蝕劑層；再以一道光罩之圖案對該光致抗蝕劑層進行曝光顯影，從而形成一預定圖案，對該透明導電膜進行蝕刻，然後移除光致抗蝕劑層，形成源極電極70。 Step 5: processing the transparent conductive film by another photolithography process to form Source electrode 70. In this embodiment, a specific method of forming the source electrode 70 is: forming a photoresist layer on the transparent conductive film; and exposing and developing the photoresist layer in a pattern of a mask, thereby A predetermined pattern is formed, the transparent conductive film is etched, and then the photoresist layer is removed to form the source electrode 70.
步驟六：在基板10上形成保護層80。 Step 6: A protective layer 80 is formed on the substrate 10.
請參閱圖3，本發明第三實施方式提供之薄膜電晶體300與第一實施方式中之薄膜電晶體100之區別在於：所述薄膜電晶體300之半導體層40形成在漏極電極60和源極電極70之間之溝道90中，並且分別延伸至漏極電極60和源極電極70之上表面。 Referring to FIG. 3, the thin film transistor 300 according to the third embodiment of the present invention is different from the thin film transistor 100 of the first embodiment in that the semiconductor layer 40 of the thin film transistor 300 is formed on the drain electrode 60 and the source. The channel 90 between the electrode electrodes 70 extends into the upper surfaces of the drain electrode 60 and the source electrode 70, respectively.
本發明第三實施方式提供之薄膜電晶體300之製造方法包括以下幾個步驟： The manufacturing method of the thin film transistor 300 provided by the third embodiment of the present invention includes the following steps:
步驟一：提供一個基板10，並在該基板上形成柵極20以及柵極絕緣層30。 Step 1: A substrate 10 is provided, and a gate electrode 20 and a gate insulating layer 30 are formed on the substrate.
步驟二：利用一道光刻製程在柵極絕緣層30上形成漏極電極60。所述漏極電極60由金屬材料構成。 Step 2: A drain electrode 60 is formed on the gate insulating layer 30 by a photolithography process. The drain electrode 60 is made of a metal material.
步驟三：利用另一道光刻製程柵極絕緣層30上形成源極電極70。所述源極電極70由ITO等透明導電膜材料構成。 Step 3: The source electrode 70 is formed on the gate insulating layer 30 by another photolithography process. The source electrode 70 is made of a transparent conductive film material such as ITO.
步驟四：在漏極電極60與源極電極70之間之溝道90中形成半導體層40，並且半導體層40分別延伸至漏極電極60和源極電極70之上表面。 Step 4: A semiconductor layer 40 is formed in the channel 90 between the drain electrode 60 and the source electrode 70, and the semiconductor layer 40 extends to the upper surfaces of the drain electrode 60 and the source electrode 70, respectively.
100‧‧‧薄膜電晶體 100‧‧‧film transistor
10‧‧‧基板 10‧‧‧Substrate
20‧‧‧柵極 20‧‧‧Gate
30‧‧‧柵極絕緣層 30‧‧‧Gate insulation
40‧‧‧半導體層 40‧‧‧Semiconductor layer
50‧‧‧蝕刻阻擋層 50‧‧‧ etching barrier
60‧‧‧漏極電極 60‧‧‧Drain electrode
70‧‧‧源極電極 70‧‧‧Source electrode
80‧‧‧保護層 80‧‧ ‧ protective layer
90‧‧‧溝道 90‧‧‧Channel
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| TW200802883A (en) * | 2006-06-12 | 2008-01-01 | Lg Philips Lcd Co Ltd | Tunneling-effect thin film transistor, method of manufacturing the same, and organic light-emitting diode display using the same |
| US20110215331A1 (en) * | 2010-03-05 | 2011-09-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| TW201135932A (en) * | 2009-11-06 | 2011-10-16 | Semiconductor Energy Lab | Semiconductor device |
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| TW200802883A (en) * | 2006-06-12 | 2008-01-01 | Lg Philips Lcd Co Ltd | Tunneling-effect thin film transistor, method of manufacturing the same, and organic light-emitting diode display using the same |
| TW201135932A (en) * | 2009-11-06 | 2011-10-16 | Semiconductor Energy Lab | Semiconductor device |
| US20110215331A1 (en) * | 2010-03-05 | 2011-09-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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