TWI512851B - Molded wlcsp with thick metal bonded and top exposed - Google Patents
Molded wlcsp with thick metal bonded and top exposed Download PDFInfo
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- TWI512851B TWI512851B TW102116599A TW102116599A TWI512851B TW I512851 B TWI512851 B TW I512851B TW 102116599 A TW102116599 A TW 102116599A TW 102116599 A TW102116599 A TW 102116599A TW I512851 B TWI512851 B TW I512851B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本發明一般涉及一種半導體器件的封裝體及其製備方法，更確切的說，本發明涉及在一種晶圓級封裝器件中，將晶片進行整體封裝而使其無裸露在塑封體之外的部分，並在晶片的底部設有一較厚的金屬底部基座。The present invention generally relates to a package of a semiconductor device and a method of fabricating the same, and more particularly to a wafer-level package device in which a wafer is integrally packaged so that it is not exposed outside the molded body. A thick metal bottom pedestal is placed on the bottom of the wafer.
在晶圓級封裝WLCSP中，先行在整片晶圓上進行封裝和測試，然後才將其切割成單顆的IC封裝體，所獲得的封裝體的體積即幾乎等同於裸晶片的原尺寸，從而使該封裝體具備良好的散熱及電氣性能。In the wafer-level package WLCSP, the package is first packaged and tested on a single wafer, and then cut into individual IC packages. The volume of the package obtained is almost equal to the original size of the bare wafer. Therefore, the package has good heat dissipation and electrical properties.
在這種封裝方式中，無論是基於降低襯底電阻還是縮小晶片尺寸的目地，晶片最終都要被減薄至一定的厚度。而晶片愈薄愈容易碎裂，這就要求極力避免對晶片造成任何形態的損傷。公開號為US2009/0032871的美國專利揭露了一種晶圓級封裝的方法，其中晶片完成塑封並被從晶圓上分割下來之後，晶片正面的一部分電極通過位於晶片側面的導電結構與晶片背面的電極進行連接，然而晶片背面的電極仍然是裸露在塑封料之外，其不良影響是導致晶片抗濕能力差及塑封體無法提供全方位的機械保護。專利號為6107164的美國專利同樣也公開了一種晶圓級封裝的方法，通過先在晶圓的正面進行切割並進行塑封，再從晶圓的背面減薄晶圓，之後將晶片從晶圓上分割下來，所獲得的完成塑封的晶片的背面仍然還是裸露在塑封料之外。類似的，還有專利號分別為US6420244和6852607的美國專利案，這些申請均沒有很好解決如何在減薄晶圓的同時還能將晶片進行完全密封保護的問題，並且其散熱效果也不佳。In this package, the wafer is ultimately thinned to a certain thickness, whether based on the purpose of reducing the substrate resistance or reducing the size of the wafer. The thinner the wafer, the easier it is to break, which requires that any damage to the wafer be avoided. US Patent Publication No. US2009/0032871 discloses a wafer level package method in which a portion of an electrode on the front side of a wafer passes through a conductive structure on the side of the wafer and an electrode on the back side of the wafer after the wafer is plastically encapsulated and separated from the wafer. The connection is made, however, the electrodes on the back side of the wafer are still exposed outside the molding compound, and the adverse effect is that the wafer has poor moisture resistance and the plastic body cannot provide comprehensive mechanical protection. U.S. Patent No. 6,107,164 also discloses a wafer-level packaging method in which a wafer is first cut and molded on the front side of the wafer, and then the wafer is thinned from the back side of the wafer, and then the wafer is removed from the wafer. After being divided, the back side of the obtained finished plastic wafer is still exposed outside the molding compound. Similarly, there are US patents with patent numbers US6420244 and 6852607, respectively. These applications do not solve the problem of how to completely seal the wafer while thinning the wafer, and the heat dissipation effect is not good. .
本發明提供一種帶有底部基座的晶圓級封裝器件，包括：一晶片及設置在晶片正面的各焊墊上的金屬互連結構；一覆蓋在晶片背面的底部金屬層；一通過導電粘合層焊接在底部金屬層上的底部基座；一覆蓋在晶片正面的並包覆在各金屬互連結構側壁周圍的頂部塑封層；以及包覆在頂部塑封層、晶片、底部金屬層、導電粘合層和底部基座各自周邊外側的一橫截面呈環形框狀的塑封體。The invention provides a wafer level package device with a bottom pedestal, comprising: a wafer and a metal interconnection structure disposed on each of the pads on the front side of the wafer; a bottom metal layer covering the back surface of the wafer; a bottom pedestal soldered to the bottom metal layer; a top plastic overlayer covering the front side of the wafer and surrounding the sidewalls of the metal interconnect structures; and a top plastic encapsulant, a wafer, a bottom metal layer, and a conductive paste A sealing body having a circular frame shape in a cross section on the outer side of each of the respective layers and the bottom base is formed.
上述的帶有底部基座的晶圓級封裝器件，所述焊墊包括第一類、第二類焊墊；並且在所述晶片內設置有對準第二類焊墊並貫穿晶片厚度的通孔，所述底部金屬層通過填充在通孔內的導電材料而電性連接到所述第二類焊墊上。The above wafer-level package device with a bottom pedestal, the pad includes a first type and a second type of pad; and a pass aligning the second type of pad and extending through the thickness of the wafer is disposed in the wafer a hole, the bottom metal layer being electrically connected to the second type of pad by a conductive material filled in the via hole.
在一些實施方式中，上述的帶有底部基座的晶圓級封裝器件，所述金屬互連結構的頂端與頂部塑封層的上表面處於同一平面。In some embodiments, the above-described wafer-level package device with a bottom pedestal, the top end of the metal interconnect structure being in the same plane as the upper surface of the top mold layer.
上述的帶有底部基座的晶圓級封裝器件，還包括設置在頂部塑封層上的被分割成多個獨立區域的圖案化金屬層；並且其每個獨立區域均具有與一個或多個焊墊交疊的部分，以保障每個焊墊能通過金屬互連結構而電性連接到一個相應的獨立區域上。The above wafer-level package device with a bottom pedestal further comprising a patterned metal layer disposed on the top plastic encapsulation layer and divided into a plurality of independent regions; and each of the individual regions has one or more soldering The overlapping portions of the pads ensure that each pad can be electrically connected to a corresponding separate area through the metal interconnect structure.
上述的帶有底部基座的晶圓級封裝器件，部分獨立區域帶有從頂部塑封層的上表面沿水準方向延伸至塑封體的外側壁處的引腳。The above wafer-level package device with a bottom pedestal has a separate region with pins extending from the upper surface of the top molding layer in the horizontal direction to the outer sidewall of the molding body.
上述的帶有底部基座的晶圓級封裝器件，所述底部基座的平面面積小於晶片的橫截面面積；以及所述塑封體還包含有環繞在底部基座周邊外側的增大了厚度的部分。The above wafer-level package device with a bottom pedestal having a planar area smaller than a cross-sectional area of the wafer; and the molding body further comprising an increased thickness surrounding the periphery of the bottom pedestal periphery section.
本發明提供一種帶有底部基座的晶圓級封裝器件，包括：一晶片及設置在晶片正面的各焊墊上的金屬互連結構；一覆蓋在晶片背面的底部金屬層；一通過導電粘合層焊接在底部金屬層上的底部基座；一覆蓋在晶片正面的並包覆在各金屬互連結構側壁周圍的頂部塑封層；以及包覆在晶片、底部金屬層、導電粘合層和底部基座各自周邊外側的一橫截面呈環形框狀的塑封體。The invention provides a wafer level package device with a bottom pedestal, comprising: a wafer and a metal interconnection structure disposed on each of the pads on the front side of the wafer; a bottom metal layer covering the back surface of the wafer; a bottom pedestal soldered to the bottom metal layer; a top plastic overlayer covering the front side of the wafer and surrounding the sidewalls of the metal interconnect structures; and a wafer, a bottom metal layer, a conductive adhesive layer, and a bottom layer A cross-section of the outer periphery of each of the bases is a ring-shaped molding body.
上述的帶有底部基座的晶圓級封裝器件，所述塑封體包括包覆在一部分厚度的晶片、底部金屬層、導電粘合層、底部基座的各自周邊外側的第一塑封體；及包括包覆在另一部分厚度的晶片的周邊外側的第二塑封體。The above wafer-level package device with a bottom pedestal comprising a first molding body coated on a part of the thickness of the wafer, the bottom metal layer, the conductive adhesive layer, and the outer periphery of the bottom pedestal; A second molding comprising a periphery of the periphery of the wafer of another thickness is included.
上述的帶有底部基座的晶圓級封裝器件，所述焊墊包括第一類、第二類焊墊；並且在所述晶片內設置有對準第二類焊墊並貫穿晶片厚度的通孔，所述底部金屬層通過填充在通孔內的導電材料而電性連接到所述第二類焊墊上。The above wafer-level package device with a bottom pedestal, the pad includes a first type and a second type of pad; and a pass aligning the second type of pad and extending through the thickness of the wafer is disposed in the wafer a hole, the bottom metal layer being electrically connected to the second type of pad by a conductive material filled in the via hole.
上述的帶有底部基座的晶圓級封裝器件，所述金屬互連結構的頂端凸出於頂部塑封層的上表面。In the above wafer level package device with a bottom pedestal, the top end of the metal interconnection structure protrudes from the upper surface of the top molding layer.
上述的帶有底部基座的晶圓級封裝器件，所述底部基座的平面面積小於晶片的橫截面面積；並且所述第一塑封體還包括環繞在所述底部基座周邊外側的增大了厚度的部分。The above wafer-level package device with a bottom pedestal having a planar area smaller than a cross-sectional area of the wafer; and the first molding body further includes an increase surrounding the periphery of the bottom pedestal The part of the thickness.
本發明還提供一種帶有底部基座的晶圓級封裝器件的製備方法，提供一包含有多個晶片的晶圓並在每個晶片的正面均設置有多個焊墊，包括以下步驟：在每個焊墊上焊接一個金屬互連結構；形成一覆蓋在晶圓正面的並將各金屬互連結構予以包覆的塑封層；在晶圓的背面進行研磨以減薄晶圓並沉積一金屬層覆蓋在晶圓的減薄背面；利用塗覆在金屬層上的一層導電的粘合材料將一帶有底部基座陣列的引線框架粘貼在金屬層上，並在金屬層覆蓋在每個晶片背面的區域上相應粘貼一個底部基座；形成貫穿粘合材料、金屬層、晶圓各自厚度的並將相鄰晶片分割開的多條第一切割槽，第一切割槽具有延伸至部分厚度的塑封層中的深度；在所述第一切割槽中和相鄰底部基座之間的間隙中填充塑封料；研磨減薄塑封層直至金屬互連結構予以外露；沿第一切割槽對所述塑封料進行切割。The present invention also provides a method of fabricating a wafer level package device with a bottom pedestal, providing a wafer including a plurality of wafers and having a plurality of pads on each front surface of the wafer, including the following steps: Soldering a metal interconnect structure on each pad; forming a plastic layer covering the front side of the wafer and covering each metal interconnect structure; grinding on the back side of the wafer to thin the wafer and deposit a metal layer Covering the thinned back side of the wafer; bonding a lead frame with a bottom pedestal array to the metal layer using a layer of electrically conductive adhesive material coated on the metal layer, and covering the back side of each wafer with a metal layer Correspondingly, a bottom pedestal is adhered to the region; a plurality of first cutting grooves are formed through the respective thicknesses of the bonding material, the metal layer and the wafer, and the adjacent wafers are divided, and the first cutting groove has a plastic sealing layer extending to a partial thickness a depth in the gap between the first cutting groove and the adjacent bottom base; filling the thinned plastic sealing layer until the metal interconnect structure is exposed; Plastic material to be cut.
上述的方法，形成第一切割槽的步驟中，一層所述的粘合材料、金屬層經切割後分別形成多個導電粘合層、多個底部金屬層，以使覆蓋在每個晶片背面的一底部金屬層通過一導電粘合層粘附有一個底部基座。In the above method, in the step of forming the first cutting groove, a layer of the adhesive material and the metal layer are respectively cut to form a plurality of conductive adhesive layers and a plurality of bottom metal layers so as to cover the back surface of each wafer. A bottom metal layer is adhered to a bottom pedestal through a conductive adhesive layer.
上述的方法，研磨減薄塑封層的步驟中，減薄的塑封層被填充在多條第一切割槽中的塑封料分割成多個頂部塑封層，每個晶片的正面相應覆蓋有一個頂部塑封層。In the above method, in the step of grinding the thinned plastic sealing layer, the thinned plastic sealing layer is divided into a plurality of top plastic sealing layers by the molding compound filled in the plurality of first cutting grooves, and the front surface of each wafer is correspondingly covered with a top plastic sealing layer. Floor.
上述的方法，對塑封料實施切割的步驟中，每個晶片四周的第一切割槽內的塑封料和粘附在該晶片背面的底部金屬層上的底部基座周圍的塑封料經切割後，形成包覆在該晶片及其頂部塑封層、底部金屬層、導電粘合層和底部基座各自周邊外側的一橫截面呈環形框狀的塑封體。In the above method, in the step of cutting the molding compound, the molding compound in the first cutting groove around each wafer and the molding compound around the bottom base adhered to the bottom metal layer on the back surface of the wafer are cut, A molding body having a ring-shaped frame shape in cross section is formed on the outer periphery of each of the wafer and its top plastic sealing layer, the bottom metal layer, the conductive adhesive layer and the bottom base.
上述的方法，所述焊墊包括第一類焊墊和第二類焊墊，並且形成第二類焊墊的步驟包括：先在晶圓的每個晶片內形成深度小於晶圓厚度的通孔，然後再在該通孔內填充導電材料，之後再在晶片正面形成與通孔有交疊部分的並與通孔內的導電材料保持電接觸的第二類焊墊。In the above method, the solder pad comprises a first type of pad and a second type of pad, and the step of forming the second type of pad comprises: first forming a via having a depth less than a thickness of the wafer in each of the wafers Then, the via hole is filled with a conductive material, and then a second type of pad having an overlapping portion with the via hole and maintaining electrical contact with the conductive material in the via hole is formed on the front surface of the wafer.
上述的方法，在對晶圓研磨減薄的步驟中，填充在通孔內的導電材料從其減薄背面予以外露。In the above method, in the step of polishing and thinning the wafer, the conductive material filled in the through hole is exposed from the thinned back surface thereof.
上述的方法，所述焊墊包括第一類焊墊和第二類焊墊，並且在減薄所述晶圓之後，先在其減薄背面進行鑽孔以在晶圓的每個晶片內形成對準第二類焊墊的通孔，然後再在通孔內填充導電材料，之後再在減薄背面沉積金屬層。In the above method, the pad includes a first type of pad and a second type of pad, and after thinning the wafer, drilling is performed on the thinned back side to form in each wafer of the wafer. The via holes of the second type of pad are aligned, and then the via holes are filled with a conductive material, and then the metal layer is deposited on the thinned back side.
上述的方法，在對所述塑封料進行切割之前，先在每個頂部塑封層上覆蓋一層具有分割成多個獨立區域的圖案化的金屬層，其每個獨立區域均具有與一個或多個焊墊相交疊的部分，以保障每個焊墊能通過金屬互連結構而電性連接到一個相應的獨立區域上。In the above method, before cutting the molding compound, each of the top molding layers is covered with a patterned metal layer having a plurality of independent regions, each of which has one or more independent regions. The portions of the pads that overlap each other to ensure that each pad can be electrically connected to a corresponding independent area through the metal interconnect structure.
上述的方法，部分獨立區域具有的引腳沿水準方向延伸至覆蓋在該頂部塑封層附近的一部分塑封料上，以便在對塑封料進行切割的步驟中，使塑封料的每個切割形成面與延伸到該切割形成面處的引腳的沿平行於切割方向的邊緣對齊。In the above method, a part of the independent area has a pin extending in the horizontal direction to cover a part of the molding compound in the vicinity of the top molding layer, so that in the step of cutting the molding compound, each cutting forming surface of the molding compound is The pins extending to the cutting forming face are aligned along edges parallel to the cutting direction.
上述方法，將引線框架粘貼在金屬層上的步驟包括：提供一支撐晶圓，利用一粘貼膜將引線框架粘貼在支撐晶圓的正面；將晶圓的減薄背面朝向支撐晶圓的正面，並利用塗覆在金屬層上的一層導電的粘合材料將引線框架粘貼在金屬層上，以將晶圓和支撐晶圓鍵合在一起；其中金屬層覆蓋在每個晶片背面的區域對準一個底部基座，以便將該對準的底部基座粘貼在金屬層的覆蓋在晶片背面的該區域；之後移除粘貼膜和支撐晶圓。In the above method, the step of attaching the lead frame to the metal layer comprises: providing a supporting wafer, bonding the lead frame to the front surface of the supporting wafer by using an adhesive film; and facing the thinned back surface of the wafer toward the front surface of the supporting wafer, And bonding the lead frame to the metal layer by using a conductive adhesive material coated on the metal layer to bond the wafer and the supporting wafer together; wherein the metal layer covers the area alignment on the back surface of each wafer A bottom pedestal is attached to the aligned bottom pedestal to the area of the metal layer overlying the back side of the wafer; the affixing film and the supporting wafer are then removed.
本發明還提供一種帶有底部基座的晶圓級封裝器件的製備方法，提供一包含有多個晶片的晶圓並在每個晶片的正面均設置有多個焊墊，包括以下步驟：在每個焊墊上焊接一個金屬互連結構；在晶圓的正面切割出界定每個晶片邊界的多條第二切割槽；形成一覆蓋在晶圓正面的並包覆在各金屬互連結構側壁周圍的塑封層，且形成塑封層的塑封料同時還填充在第二切割槽中；在晶圓的背面進行研磨以減薄晶圓並沉積一金屬層覆蓋在晶圓的減薄背面；利用塗覆在金屬層上的一層導電的粘合材料將一帶有底部基座陣列的引線框架粘貼在金屬層上，並在金屬層覆蓋在每個晶片背面的區域上相應粘貼一個底部基座；在減薄背面形成貫穿粘合材料、金屬層並與多條第二切割槽在垂直於晶圓所在平面的方向上分別對準重合的多條第一切割槽，彼此接觸的第一切割槽和第二切割槽將相鄰的晶片分隔開；在第一切割槽中和相鄰底部基座之間的間隙中填充塑封料；沿第一或第二切割槽對填充在第一或第二切割槽中、相鄰底部基座之間的間隙中的塑封料和塑封層實施切割。The present invention also provides a method of fabricating a wafer level package device with a bottom pedestal, providing a wafer including a plurality of wafers and having a plurality of pads on each front surface of the wafer, including the following steps: Soldering a metal interconnect structure on each of the pads; cutting a plurality of second cutting grooves defining a boundary of each of the wafers on a front surface of the wafer; forming a cover on the front surface of the wafer and surrounding the sidewalls of the metal interconnect structures a molding layer, and the molding compound forming the plastic sealing layer is also filled in the second cutting groove; grinding is performed on the back side of the wafer to thin the wafer and depositing a metal layer covering the thinned back surface of the wafer; a conductive bonding material on the metal layer adheres a lead frame with a bottom pedestal array to the metal layer, and pastes a bottom pedestal on the area of the metal layer covering the back surface of each wafer; Forming, by the back surface, a plurality of first cutting grooves penetrating through the bonding material, the metal layer and respectively aligned with the plurality of second cutting grooves in a direction perpendicular to a plane of the wafer, the first cutting grooves contacting each other and The two cutting grooves separate adjacent wafers; filling the gap between the first cutting groove and the adjacent bottom base; filling the first or second cutting along the first or second cutting groove pair The molding compound and the plastic seal layer in the gap between the adjacent bottom bases in the groove are cut.
上述的方法，形成第一切割槽的切割步驟中，所述粘合材料、金屬層經切割後分別形成多個導電粘合層、多個底部金屬層，以使覆蓋在每個晶片背面的底部金屬層通過一導電粘合層粘附有一個底部基座。In the above method, in the cutting step of forming the first cutting groove, the bonding material and the metal layer are respectively cut to form a plurality of conductive adhesive layers and a plurality of bottom metal layers so as to cover the bottom of each wafer back surface. The metal layer is adhered to a bottom pedestal through a conductive adhesive layer.
上述的方法，對塑封層實施切割的步驟中，塑封層被切割成多個頂部塑封層，每個晶片的正面相應覆蓋有一個頂部塑封層。In the above method, in the step of cutting the plastic sealing layer, the plastic sealing layer is cut into a plurality of top plastic sealing layers, and the front surface of each wafer is correspondingly covered with a top plastic sealing layer.
上述的方法，位於第二切割槽內的塑封料經切割後形成包覆在一部分厚度的晶片的周邊外側的第二塑封料；以及位於第一切割槽內和相鄰底部基座之間的間隙中的塑封料經切割後形成包覆在底部金屬層、導電粘合層、底部基座和另一部分厚度的晶片的各自周邊外側的第一塑封體。In the above method, the molding compound located in the second cutting groove is cut to form a second molding compound covering the outer periphery of the wafer of a part of the thickness; and a gap between the first cutting groove and the adjacent bottom base The molding compound is cut to form a first molding body covering the outer periphery of the bottom metal layer, the conductive bonding layer, the bottom base, and another portion of the thickness of the wafer.
上述的方法，所述焊墊包括第一類焊墊和第二類焊墊，並且形成第二類焊墊的步驟包括：先在晶圓的每個晶片內形成深度小於晶圓厚度的通孔，然後再在該通孔內填充導電材料，之後再在晶片正面形成與通孔有交疊部分的並與通孔內的導電材料保持電接觸的第二類焊墊。In the above method, the solder pad comprises a first type of pad and a second type of pad, and the step of forming the second type of pad comprises: first forming a via having a depth less than a thickness of the wafer in each of the wafers Then, the via hole is filled with a conductive material, and then a second type of pad having an overlapping portion with the via hole and maintaining electrical contact with the conductive material in the via hole is formed on the front surface of the wafer.
上述的方法，在對晶圓研磨減薄的步驟中，填充在通孔內的導電材料從其減薄背面予以外露。In the above method, in the step of polishing and thinning the wafer, the conductive material filled in the through hole is exposed from the thinned back surface thereof.
上述的方法，所述焊墊包括第一類焊墊和第二類焊墊，並且在減薄所述晶圓之後，先在其減薄背面進行鑽孔以在晶圓的每個晶片內形成對準第二類焊墊的通孔，然後再在通孔內填充導電材料，之後再在減薄背面沉積金屬層。In the above method, the pad includes a first type of pad and a second type of pad, and after thinning the wafer, drilling is performed on the thinned back side to form in each wafer of the wafer. The via holes of the second type of pad are aligned, and then the via holes are filled with a conductive material, and then the metal layer is deposited on the thinned back side.
上述的方法，將引線框架粘貼在金屬層上的步驟包括：提供一支撐晶圓，並利用一粘貼膜將引線框架粘貼在支撐晶圓的正面；將晶圓的減薄背面朝向支撐晶圓的正面，並利用塗覆在金屬層上的一層導電的粘合材料將引線框架粘貼在金屬層上，以將晶圓和支撐晶圓鍵合在一起；其中，金屬層覆蓋在每個晶片背面的區域對準一個底部基座，以便將該對準的底部基座粘貼在金屬層的覆蓋在晶片背面的該區域；之後移除粘貼膜和支撐晶圓。In the above method, the step of attaching the lead frame to the metal layer comprises: providing a supporting wafer, and bonding the lead frame to the front surface of the supporting wafer by using a bonding film; and facing the thinned back surface of the wafer toward the supporting wafer Front side, and bonding a lead frame to the metal layer by using a conductive adhesive material coated on the metal layer to bond the wafer and the support wafer together; wherein the metal layer covers the back of each wafer The area is aligned with a bottom pedestal to adhere the aligned bottom pedestal to the area of the metal layer overlying the back side of the wafer; the affixing film and the supporting wafer are then removed.
在一些實施方式中，上述方法中金屬互連結構的頂端凸出于塑封層。In some embodiments, the top end of the metal interconnect structure in the above method protrudes from the plastic seal layer.
本領域的技術人員閱讀以下較佳實施例的詳細說明，並參照附圖之後，本發明的這些和其他方面的優勢無疑將顯而易見。These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;
100．．．晶圓100. . . Wafer
110a、110b．．．焊墊110a, 110b. . . Solder pad
115．．．第二切割槽115. . . Second cutting slot
115a．．．第二塑封體115a. . . Second plastic body
116．．．塑封料116. . . Molding compound
121．．．通孔121. . . Through hole
122．．．導電材料122. . . Conductive material
130．．．金屬互連結構130. . . Metal interconnect structure
140．．．塑封層140. . . Plastic layer
151．．．金屬層151. . . Metal layer
153．．．基座153. . . Pedestal
1530．．．引線框架1530. . . Lead frame
1531．．．連筋1531. . . Continuous reinforcement
1532．．．圓形框1532. . . Round frame
101．．．晶圓101. . . Wafer
154．．．粘貼膜154. . . Adhesive film
152．．．粘合材料152. . . Adhesive material
101'．．．晶片101'. . . Wafer
160．．．第一切割槽160. . . First cutting slot
152'．．．導電粘合層152'. . . Conductive adhesive layer
170．．．粘貼膜170. . . Adhesive film
161．．．塑封料161. . . Molding compound
141．．．塑封層141. . . Plastic layer
100A．．．晶圓級封裝器件100A. . . Wafer level package device
161a．．．塑封體161a. . . Plastic body
161a-1．．．外側壁161a-1. . . Outer side wall
161b．．．部分161b. . . section
180．．．金屬層180. . . Metal layer
180a、180b、180c．．．獨立區域180a, 180b, 180c. . . Independent area
110a-1、110a-2．．．第一類焊墊110a-1, 110a-2. . . First type of pad
180b-1、180c-1．．．引腳180b-1, 180c-1. . . Pin
100'A．．．封裝器件100'A. . . Packaged device
151'．．．金屬層151'. . . Metal layer
152'．．．導電粘合層152'. . . Conductive adhesive layer
161'a．．．第一塑封體161'a. . . First plastic body
161'b．．．部分161'b. . . section
101"．．．晶片101"...chip
參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
圖1A-1O是本發明製備帶有厚底部基座的晶圓級封裝器件的流程示意圖。1A-1O are schematic flow diagrams of a wafer level package device having a thick bottom pedestal in accordance with the present invention.
圖2A-2G是本發明製備另一種結構稍有變化的帶有厚底部基座的晶圓級封裝器件的流程示意圖。2A-2G are flow diagrams showing the fabrication of another wafer-level packaged device with a thick bottom pedestal having a slightly modified structure.
圖3A-3D是減薄晶圓後才在晶圓內形成通孔的流程示意圖。3A-3D are schematic flow diagrams of forming vias in a wafer after thinning the wafer.
圖4A-4E是在晶圓的正面形成切割槽並覆蓋一層塑封層，然後再在減薄的晶圓的背面形成通孔和沉積金屬層的步驟。4A-4E are steps of forming a dicing groove on the front side of the wafer and covering a layer of plastic, and then forming via holes and depositing a metal layer on the back side of the thinned wafer.
圖5A-5E是製備不需要在晶圓內形成電性連接晶片正面的焊墊和其背面電極的通孔的晶圓級封裝器件的流程示意圖。5A-5E are schematic flow diagrams of wafer-level package devices that do not require the formation of vias in the wafer that electrically connect the pads on the front side of the wafer and the backside electrodes thereof.
圖6A-6D是製備另一種不需要在晶圓內形成電性連接晶片正面的焊墊和其背面電極的通孔的晶圓級封裝器件的流程示意圖。6A-6D are flow diagrams showing another wafer level package device that does not require the formation of vias in the wafer that electrically connect the pads on the front side of the wafer and the back electrodes thereof.
參見圖1A，晶圓100包含有多個未標記出的晶片，此時眾多晶片皆鑄造連接在一起，以設置在晶圓100的正面的多條劃片道來界定每個晶片的邊界，因這些技術特徵已為本領域的技術人員所熟知，所以附圖中不再詳細描述。其中，每個晶片正面均設置有焊墊110a、110b，定義焊墊110a為第一類焊墊、焊墊110b為第二類焊墊。如圖所示，在晶圓100所含的每個晶片內均設置有對準第二類焊墊110b的通孔121，並在通孔121內填充有導電材料122，導電材料122和與其接觸的第二類焊墊110b保持電性連接。Referring to FIG. 1A, the wafer 100 includes a plurality of unmarked wafers, in which case a plurality of wafers are cast and joined together to define a plurality of scribe lanes on the front side of the wafer 100 to define boundaries of each wafer. The technical features are well known to those skilled in the art and will not be described in detail in the drawings. Wherein, the front surface of each wafer is provided with solder pads 110a, 110b, the defining pads 110a are the first type of pads, and the pads 110b are the second type of pads. As shown, a via 121 that is aligned with the second type of pad 110b is disposed in each of the wafers included in the wafer 100, and the via 121 is filled with a conductive material 122, and the conductive material 122 is in contact therewith. The second type of pad 110b remains electrically connected.
基於簡潔性的考慮，覆蓋在通孔121側壁和底部的隔離層並未在圖中示意出，用來絕緣隔離晶片位於通孔121周圍的區域和導電材料122的隔離層可以是具有一定厚度的氧化物層，也可以一個複合層。作為一種可選方式，複合層可包括先行覆蓋在通孔121側壁和底部的一氮化物層（如SiN），及覆蓋在氮化物層上的一氧化物層（如SiO2）和覆蓋在氧化物層上的一金屬擴散阻擋層（如Ti、TiN、TiXSiYNZ或Ta、TaN、TaXSiYNZ 或W、WN、WN2等）。導電材料122可採用鎢、鋁、銅等金屬或其他合金，充當擴散阻擋層的氮化物層用於防止導電材料122擴散到晶片位於通孔121周圍的區域中，而氧化物層可作為一個電絕緣層，金屬擴散阻擋層則進一步阻擋導電材料122的擴散。For the sake of simplicity, the isolation layer covering the sidewalls and the bottom of the via 121 is not illustrated in the drawing, and the isolation layer for insulating the isolation wafer around the via 121 and the isolation layer of the conductive material 122 may have a certain thickness. The oxide layer can also be a composite layer. As an alternative, the composite layer may include a nitride layer (such as SiN) covering the sidewalls and the bottom of the via 121, and an oxide layer (such as SiO2) covering the nitride layer and covering the oxide. A metal diffusion barrier layer on the layer (such as Ti, TiN, TiXSiYNZ or Ta, TaN, TaXSiYNZ or W, WN, WN2, etc.). The conductive material 122 may be made of a metal such as tungsten, aluminum, copper or the like, or other alloy, and a nitride layer serving as a diffusion barrier layer is used to prevent the conductive material 122 from diffusing into the region of the wafer around the through hole 121, and the oxide layer can be used as an electric The insulating layer, the metal diffusion barrier further blocks the diffusion of the conductive material 122.
參見圖1B，在每個焊墊110a、110b上焊接一個金屬互連結構130，金屬互連結構130可以是焊錫球也可以是金屬凸塊，其形狀不受限制，如圓球形、橢球形、楔形、正（長）方體、圓柱形等。然後如圖1C所述，利用環氧樹脂類的塑封料形成一覆蓋在晶圓100正面的並將各金屬互連結構130予以包覆的塑封層140，因塑封層140的物理支撐作用，極大的增強了晶圓100的機械強度，所以晶圓100可被研磨的足夠薄，如圖1D所示，在其背面實施研磨以獲得預期厚度的晶圓，研磨持續到導電材料122從減薄背面外露出來。之後沉積一金屬層151覆蓋在晶圓100的減薄背面，此時每個通孔121內的導電材料122均與金屬層151保持電性連接，如圖1E所示。在大部分情況下，在形成金屬層151之前還需要在該減薄背面注入重摻雜的摻雜物。Referring to FIG. 1B, a metal interconnection structure 130 is soldered on each of the pads 110a, 110b. The metal interconnection structure 130 may be a solder ball or a metal bump, and the shape thereof is not limited, such as a spherical shape or an ellipsoidal shape. Wedge, positive (long) square, cylindrical, etc. Then, as shown in FIG. 1C, a plastic sealing layer 140 covering the front surface of the wafer 100 and covering the metal interconnection structures 130 is formed by using an epoxy resin molding compound, which is greatly supported by the physical support of the plastic sealing layer 140. The mechanical strength of the wafer 100 is enhanced, so the wafer 100 can be ground sufficiently thin, as shown in FIG. 1D, to be ground on the back side to obtain a wafer of a desired thickness, and the polishing continues until the conductive material 122 is thinned from the back. It’s exposed. A metal layer 151 is then deposited over the thinned back side of the wafer 100, and the conductive material 122 in each via 121 is electrically connected to the metal layer 151, as shown in FIG. 1E. In most cases, it is also necessary to implant heavily doped dopants on the thinned back side prior to forming the metal layer 151.
之後如圖1F-1至圖1F-2所示，利用塗覆在金屬層151上的粘合材料152將一帶有底部基座153陣列的圓形引線框架1530粘貼在金屬層151上，且金屬層151覆蓋在每個晶片背面的區域上相應粘貼一個底部基座153。圖1F-2的俯視圖詳細描述了圓形引線框架1530的大致結構，其包含了多個金屬材質的底部基座153，這些底部基座153呈陣列式佈置，相鄰的底部基座153通過彼此間的連筋1531相互連接，靠近引線框架1530周邊處的圓形框1532的底部基座153也通過連筋1531連接在圓形框1532上。為了最大限度的保持良率，底部基座153的數量可與晶圓100上完整的晶片（即非晶圓邊緣處缺角的晶片）的數量一致。Thereafter, as shown in FIG. 1F-1 to FIG. 1F-2, a circular lead frame 1530 having an array of bottom pedestals 153 is pasted on the metal layer 151 by the adhesive material 152 coated on the metal layer 151, and the metal Layer 151 covers a region of the back of each wafer and a bottom pedestal 153 is attached thereto. The top view of FIG. 1F-2 details the general structure of a circular lead frame 1530 that includes a plurality of metal bottom pedestals 153 that are arranged in an array with adjacent bottom pedestals 153 passing each other. The intermediate ribs 1531 are connected to each other, and the bottom pedestal 153 of the circular frame 1532 near the periphery of the lead frame 1530 is also connected to the circular frame 1532 via the ribs 1531. To maximize yield retention, the number of bottom pedestals 153 can be consistent with the number of complete wafers on the wafer 100 (ie, wafers that are not angled at the edges of the wafer).
圖1F-3至圖1F-6是將引線框架1530粘貼在金屬層151上的一種可選實施方式，引入了一支撐晶圓101，並利用一粘貼膜154將圓形的引線框架1530粘貼在支撐晶圓101的正面。如圖1F-4所示，先將引線框架1530中各連筋1531截斷，圖1F-5即是各連筋1531被截斷後的被粘貼在支撐晶圓101上的引線框架1530的豎截面示意圖。1F-3 to 1F-6 are an alternative embodiment of attaching the lead frame 1530 to the metal layer 151, introducing a support wafer 101, and pasting the circular lead frame 1530 with an adhesive film 154 The front side of the wafer 101 is supported. As shown in FIG. 1F-4, the connecting ribs 1531 in the lead frame 1530 are first cut off. FIG. 1F-5 is a vertical cross-sectional view of the lead frame 1530 pasted on the supporting wafer 101 after the connecting ribs 1531 are cut off. .
如圖1F-6，使晶圓100的減薄背面面向對支撐晶圓101的正面，並將帶有塑封層140的晶圓100鍵合在支撐晶圓101上。在圖1G中，利用塗覆在金屬層151上的一層導電的粘合材料152（典型的如焊錫膏）將引線框架1530粘貼在金屬層151上，該鍵合步驟中，金屬層151覆蓋在任意一個晶片背面的一個區域均對準一個底部基座153，以便使該被對準的底部基座153粘貼在金屬層151覆蓋在該晶片背面的該區域，從而實現在金屬層151覆蓋在每個晶片背面的區域上均相應粘貼一個底部基座153。之後移除粘貼膜154、支撐晶圓101，以便將引線框架1530從粘貼膜154上剝離。粘貼膜154應當具備易於從引線框架1530上脫落的特性，如熱釋膜或受紫外照射易失去粘性的釋放膜等。1F-6, the thinned back side of the wafer 100 faces the front side of the support wafer 101, and the wafer 100 with the mold layer 140 is bonded to the support wafer 101. In FIG. 1G, a lead frame 1530 is pasted on a metal layer 151 by a layer of electrically conductive adhesive material 152 (typically solder paste) coated on a metal layer 151. In the bonding step, the metal layer 151 is covered. An area of the back surface of any one of the wafers is aligned with a bottom base 153 so that the aligned bottom base 153 is adhered to the metal layer 151 covering the area of the back surface of the wafer, thereby achieving coverage in the metal layer 151. A bottom base 153 is attached to each of the areas on the back side of the wafer. Thereafter, the adhesive film 154 and the support wafer 101 are removed to peel the lead frame 1530 from the adhesive film 154. The adhesive film 154 should have a property of being easily detached from the lead frame 1530, such as a heat release film or a release film which is susceptible to loss of viscosity by ultraviolet irradiation.
如圖1H，在晶圓100的減薄背面實施切割，形成貫穿粘合材料152、金屬層151和晶圓100各自厚度的並將多個晶片101'彼此分割開的多條第一切割槽160，切割停留在塑封層140中，即第一切割槽160具有延伸至部分厚度的塑封層140中的深度。應該認識到，儘管圖中僅僅示意出了垂直於紙面的縱向切割槽，但如果從垂直於晶圓100所在平面的方向上觀察，每條橫向的第一切割槽160應當和晶圓100正面的一條與其相對應的橫向劃片道重合，每條縱向的第一切割槽160應當和晶圓100正面的一條與其相對應的縱向劃片道重合。此切割步驟中，粘合材料152經切割後分別形成多個導電粘合層152'、金屬層151經切割後分別形成多個底部金屬層151'，以使得覆蓋在每個晶片101'背面的一個底部金屬層151'通過一個導電粘合層152'而粘附有一個底部基座153。儘管此時多條橫向和縱向的第一切割槽160將多個晶片101'彼此分割開，但這些晶片101'依然固定在塑封層140上。As shown in FIG. 1H, a dicing is performed on the thinned back side of the wafer 100 to form a plurality of first dicing grooves 160 that penetrate the respective thicknesses of the bonding material 152, the metal layer 151, and the wafer 100 and separate the plurality of wafers 101' from each other. The cut remains in the plastic seal layer 140, that is, the first cut groove 160 has a depth extending into the partial thickness of the mold layer 140. It should be appreciated that although only longitudinal slits perpendicular to the paper surface are illustrated, each lateral first cut groove 160 should be front of wafer 100 if viewed from a direction perpendicular to the plane of wafer 100. A transverse scribe line coincides with its corresponding first dicing groove 160, and each longitudinal first dicing groove 160 should coincide with a corresponding longitudinal scribe line on the front side of the wafer 100. In the cutting step, the bonding material 152 is separately formed to form a plurality of conductive adhesive layers 152', and the metal layer 151 is cut to form a plurality of bottom metal layers 151', respectively, so as to cover the back of each wafer 101'. A bottom metal layer 151' is adhered to a bottom base 153 by a conductive adhesive layer 152'. Although a plurality of lateral and longitudinal first cutting grooves 160 separate the plurality of wafers 101' from each other at this time, the wafers 101' are still fixed on the plastic sealing layer 140.
如圖1I所示，將一擴展張開的粘貼膜170覆蓋在各底部基座153上，其實，耐高溫的粘貼膜170是平鋪在塑封模腔（未示意出）的頂腔壁上，帶有塑封層140的晶圓100置於模腔之中，各底部基座153的與粘貼到底部金屬層151'上的一面相對的另一面緊貼該粘貼膜170，然後在第一切割槽160內和相鄰的底部基座153之間的間隙中填充塑封料161，待塑封料161固化之後便可揭去粘貼膜170，如圖1J-1K所示。之後如圖1L，研磨減薄塑封層140直至金屬互連結構130在減薄的塑封層140中予以外露，此研磨步驟帶來的另一效果是，減薄的塑封層140被填充在多條第一切割槽160中的塑封料161分割成多個頂部塑封層141，而且每個晶片101'的正面皆相應覆蓋有一個頂部塑封層141，此時每個金屬互連結構130的頂端均與頂部塑封層141的上表面處於同一平面。As shown in FIG. 1I, an extended opening adhesive film 170 is covered on each of the bottom bases 153. In fact, the high temperature resistant adhesive film 170 is laid on the top cavity wall of the plastic molding cavity (not shown). The wafer 100 with the plastic sealing layer 140 is placed in the cavity, and the other surface of each of the bottom bases 153 opposite to the surface pasted to the bottom metal layer 151' is in close contact with the adhesive film 170, and then in the first cutting groove. The gap between the inner portion 160 and the adjacent bottom base 153 is filled with a molding compound 161. After the molding compound 161 is cured, the adhesive film 170 can be removed, as shown in Figs. 1J-1K. Thereafter, as shown in FIG. 1L, the thinned plastic encapsulation layer 140 is ground until the metal interconnection structure 130 is exposed in the thinned plastic encapsulation layer 140. Another effect of this polishing step is that the thinned plastic encapsulation layer 140 is filled in a plurality of strips. The molding compound 161 in the first cutting groove 160 is divided into a plurality of top molding layers 141, and the front surface of each wafer 101' is covered with a top molding layer 141, and the top end of each metal interconnection structure 130 is The upper surfaces of the top molding layer 141 are in the same plane.
然後沿第一切割槽160對塑封料161實施切割以獲得多個晶圓級封裝器件100A，此步驟中，每個晶片101'四周的第一切割槽160內的塑封料161和粘附在該晶片101'背面的底部金屬層151'上的底部基座153周圍的塑封料161經切割後，形成包覆在該晶片101'及其頂部塑封層141、底部金屬層151'、導電粘合層152'和底部基座153各自周邊外側的一塑封體161a，塑封體161a的大體形狀為一個沒有頂蓋和底蓋的正方體或長方體的外殼，其橫截面呈環形框狀，而且該環形框為長方形或正方形。基於對完成封裝工藝的晶片的可靠性考慮，例如防止分層，可以設計底部基座153的平面面積略小於晶片101'的橫截面面積，使得塑封體161a還包含有圍繞在底部基座153周邊外側的增大了厚度的部分161b。Then, the molding compound 161 is cut along the first cutting groove 160 to obtain a plurality of wafer-level package devices 100A. In this step, the molding compound 161 in the first cutting groove 160 around each wafer 101' is adhered thereto. The molding compound 161 around the bottom pedestal 153 on the bottom metal layer 151' on the back side of the wafer 101' is cut to form a coating on the wafer 101' and its top molding layer 141, the bottom metal layer 151', and a conductive adhesive layer. a molding body 161a on the outer side of each of the 152' and the bottom base 153. The general shape of the molding body 161a is a rectangular or rectangular parallelepiped casing having no top cover and bottom cover, and the cross section is in the shape of a ring frame, and the ring frame is Rectangular or square. Based on the reliability considerations of the wafer that completes the packaging process, such as preventing delamination, the planar area of the bottom pedestal 153 may be designed to be slightly smaller than the cross-sectional area of the wafer 101' such that the hull body 161a further includes a periphery surrounding the bottom pedestal 153. The outer portion of the thickness portion 161b is increased.
圖1M-1O是針對封裝器件100A作進一步的改進而獲得的另一封裝器件100'A，主要是在對塑封料161進行切割之前，先在每個頂部塑封層141上形成一層圖案化的金屬層180，金屬層180具有分割成多個獨立區域180a、180b、180c，其每個獨立區域均具有與一個或多個焊墊相交疊的部分，例如獨立區域180a具有與第一類焊墊110a-1交疊的部分，獨立區域180b具有與第一類焊墊110a-2交疊的部分，獨立區域180c具有與第二類焊墊110b交疊的部分，從而保障每個焊墊能通過至少一個金屬互連結構130而電性連接到一個相應的獨立區域上。例如第一類焊墊110a-1、110a-2分別通過金屬互連結構130電性連接到獨立區域180a、180b上，第二類焊墊110b通過金屬互連結構130電性連接到獨立區域180c上。此外，獨立區域180b、180c各自具有的引腳180b-1、180c-1還分別在水準方向上延伸，直至覆蓋在該頂部塑封層141附近的一部分塑封料161上，以便在對塑封料161進行切割的步驟中，使塑封料161的每個切割形成面與延伸到該切割形成面處的引腳180b-1（或180c-1）的沿平行於切割方向的邊緣對齊（如圖1O），該切割方向是指用於形成該切割形成面的切割刀所移動的方向，且這些切割形成面最終即為塑封體161a四周的外側壁161a-1。在圖1M的實施例中，任何一個頂部塑封層141之上的獨立區域並未與相鄰一個頂部塑封層141之上的另一個獨立區域連接在一起，但在另一些可選實施方式中，針對分別位於相鄰的兩個頂部塑封層141之上的彼此靠近的兩個獨立區域而言，如果它們各自的引腳朝著向對方靠近的方向延伸直至該兩個獨立區域連接在一起，僅需要在圖1O所示的切割步驟中，將該兩個獨立區域各自的引腳從對方的引腳上切割分開即可。此時因延伸到切割形成面處的引腳也受到切割，其沿平行於切割方向的邊緣其實也即一個切割形成邊，它自然和切割形成面對齊。顯然，封裝器件100'A相容傳統的QFN封裝，但較之後者具有更佳的散熱性能和電氣性能。1M-1O is another package device 100'A obtained by further improvement of the package device 100A, mainly forming a patterned metal on each of the top molding layers 141 before cutting the molding compound 161. The layer 180, the metal layer 180 has a plurality of independent regions 180a, 180b, 180c each having a portion overlapping one or more pads, for example, the individual regions 180a having a first type of pads 110a -1 overlapping portion, the independent region 180b has a portion overlapping the first type of pad 110a-2, and the independent region 180c has a portion overlapping the second type of pad 110b, thereby ensuring that each pad can pass at least A metal interconnect structure 130 is electrically connected to a corresponding separate area. For example, the first type of pads 110a-1, 110a-2 are electrically connected to the individual regions 180a, 180b through the metal interconnection structure 130, and the second type of pads 110b are electrically connected to the independent region 180c through the metal interconnection structure 130. on. In addition, the pins 180b-1, 180c-1 each having the independent regions 180b, 180c also extend in the horizontal direction until a portion of the molding compound 161 is disposed near the top molding layer 141 for performing the molding compound 161. In the step of cutting, each of the cut forming faces of the molding compound 161 is aligned with the edge of the pin 180b-1 (or 180c-1) extending to the cutting forming face in a direction parallel to the cutting direction (Fig. 10). The cutting direction refers to the direction in which the cutting blades for forming the cutting forming faces are moved, and these cutting forming faces are finally the outer side walls 161a-1 around the molded body 161a. In the embodiment of FIG. 1M, the individual regions above any of the top molding layers 141 are not joined to another separate region above the adjacent one of the top molding layers 141, but in other alternative embodiments, For two separate regions that are located close to each other on the adjacent two top molding layers 141, respectively, if their respective pins extend in a direction toward the other side until the two independent regions are connected together, only It is necessary to cut and separate the respective pins of the two independent regions from the counterpart pins in the cutting step shown in FIG. At this time, the pin extending to the cutting forming surface is also cut, and its edge parallel to the cutting direction is actually a cutting forming edge, which is naturally aligned with the cutting forming face. Obviously, the packaged device 100'A is compatible with the conventional QFN package, but has better heat dissipation performance and electrical performance than the latter.
作為一種選擇，晶片101'可以是一種垂直式的功率MOSFET器件，其第一類焊墊110 a包含有焊墊110a-1、110a-2，其中焊墊110a-1為柵極電極、焊墊110a-2為源極電極，而底部金屬層151'則為漏極電極。較之常規的MOSFET，晶片101'的焊墊110a是原本就具備的，但焊墊110b卻是額外添加的。參見圖1L-圖1O，在晶片101'內設置有對準第二類焊墊110b並貫穿晶片101'厚度的通孔121，底部金屬層151'通過填充在通孔121內的導電材料122而電性連接到第二類焊墊上110b。獨立區域180b帶有從頂部塑封層141的上表面沿水準方向延伸至塑封體161a的一個外側壁處161a-1的引腳180b-1，獨立區域180c帶有從頂部塑封層141的上表面沿水準方向延伸至塑封體161a的另一個相對的外側壁處161a-1的引腳180c-1。As an option, the wafer 101' may be a vertical power MOSFET device, and the first type of pads 110a includes pads 110a-1, 110a-2, wherein the pads 110a-1 are gate electrodes and pads 110a-2 is the source electrode and the bottom metal layer 151' is the drain electrode. The pad 110a of the wafer 101' is originally provided compared to a conventional MOSFET, but the pad 110b is additionally added. Referring to FIGS. 1L-10O, a via 121 is formed in the wafer 101' to align the second type of pads 110b and penetrate the thickness of the wafer 101'. The bottom metal layer 151' passes through the conductive material 122 filled in the via 121. Electrically connected to the second type of pad 110b. The individual region 180b has a pin 180b-1 extending from the upper surface of the top molding layer 141 in the horizontal direction to an outer side wall 161a-1 of the molding body 161a, and the independent region 180c is provided with an upper surface edge from the top molding layer 141. The horizontal direction extends to the pin 180c-1 of the other opposite outer side wall 161a-1 of the molded body 161a.
在圖2A-2G所示的實施方式中，先在每個焊墊110a、110b上焊接一個金屬互連結構130後，再在晶圓100的正面沿劃片道切割形成多條第二切割槽115，第二切割槽115界定了每個晶片的邊界。第二切割槽115具有延伸到部分厚度的晶圓100中的深度。然後如圖2B，形成一覆蓋在晶圓100正面的並包覆在各金屬互連結構130側壁周圍的塑封層140，此時塑封層140並未完全將金屬互連結構130包覆住，各金屬互連結構130的頂端均凸出于塑封層140的上表面。此步驟中，用於形成塑封層140的部分塑封料116同時還填充在第二切割槽115中。之後如圖2C，在晶圓100的背面進行研磨以減薄晶圓，並沉積一金屬層151覆蓋在晶圓的減薄背面，然後利用塗覆在金屬層151上的一層導電的粘合材料152將一帶有由多個底部基座153構成的陣列的圓形引線框架1530粘貼在金屬層151上，並在金屬層151覆蓋在每個晶片背面的區域上相應粘貼一個底部基座153，此點可參考圖1F-1。再如圖2E所示，在晶圓100的減薄背面形成貫穿粘合材料152、金屬層151的多條第一切割槽160，而且切割停留在晶圓100中，第一切割槽160具有延伸到部分厚度的晶圓100中的深度。值得注意的是，要求第一切割槽160接觸到第二切割槽115，並且從垂直於晶圓100所在平面的方向上觀察，多條第一切割槽160與多條第二切割槽115分別一一對準重合，而且相互接觸的第一切割槽160和第二切割槽115可將相鄰的晶片101'分割開。In the embodiment shown in FIGS. 2A-2G, after a metal interconnection structure 130 is soldered on each of the pads 110a, 110b, a plurality of second cutting grooves 115 are formed along the dicing streets on the front surface of the wafer 100. The second cutting groove 115 defines the boundary of each wafer. The second cutting groove 115 has a depth that extends into the wafer 100 of a partial thickness. Then, as shown in FIG. 2B, a plastic encapsulation layer 140 covering the front surface of the wafer 100 and surrounding the sidewalls of the metal interconnection structures 130 is formed. At this time, the plastic encapsulation layer 140 does not completely cover the metal interconnection structure 130. The top ends of the metal interconnect structures 130 are both protruded from the upper surface of the plastic encapsulation layer 140. In this step, a portion of the molding compound 116 for forming the mold layer 140 is also filled in the second cutting groove 115. Thereafter, as shown in FIG. 2C, polishing is performed on the back side of the wafer 100 to thin the wafer, and a metal layer 151 is deposited to cover the thinned back surface of the wafer, and then a conductive adhesive material coated on the metal layer 151 is utilized. 152. A circular lead frame 1530 having an array of a plurality of bottom pedestals 153 is pasted on the metal layer 151, and a bottom pedestal 153 is attached to the area of the metal layer 151 covering the back surface of each wafer. Refer to Figure 1F-1 for points. As shown in FIG. 2E, a plurality of first cutting grooves 160 penetrating the adhesive material 152 and the metal layer 151 are formed on the thinned back surface of the wafer 100, and the cutting remains in the wafer 100, and the first cutting groove 160 has an extension. The depth into the wafer 100 of partial thickness. It should be noted that the first cutting groove 160 is required to contact the second cutting groove 115, and the plurality of first cutting grooves 160 and the plurality of second cutting grooves 115 are respectively viewed from a direction perpendicular to the plane of the wafer 100. A first cutting groove 160 and a second cutting groove 115 that are coincident with each other and in contact with each other can separate adjacent wafers 101'.
形成第一切割槽160的切割步驟中，粘合材料152經切割後形成多個導電粘合層152'，金屬層151經切割後形成多個底部金屬層151'，以使覆蓋在每個晶片101'背面的一個底部金屬層151'通過一導電粘合層152'而粘附有一個底部基座153。如圖2F所示，在第一切割槽160中和相鄰的底部基座153之間的間隙中填充塑封料161（此步驟可參見圖1J），然後沿第一切割槽160、第二切割槽115，對填充在第一切割槽160中和填充在相鄰底部基座153之間的間隙中的塑封料161和對填充在第二切割槽115中的塑封料116實施切割，及對和塑封層140實施切割。In the cutting step of forming the first cutting groove 160, the bonding material 152 is cut to form a plurality of conductive adhesive layers 152', and the metal layer 151 is cut to form a plurality of bottom metal layers 151' so as to cover each wafer. A bottom metal layer 151' on the back side of 101' is adhered to a bottom base 153 by a conductive adhesive layer 152'. As shown in FIG. 2F, the molding compound 161 is filled in the gap between the first cutting groove 160 and the adjacent bottom base 153 (this step can be seen in FIG. 1J), and then along the first cutting groove 160, the second cutting. The groove 115, the molding compound 161 filled in the gap between the first cutting groove 160 and the adjacent bottom base 153, and the molding compound 116 filled in the second cutting groove 115 are cut and aligned. The plastic seal layer 140 performs cutting.
該切割步驟中，塑封層140被切割成多個頂部塑封層141，而且每個晶片101'的正面均相應覆蓋有一個頂部塑封層141。位於第二切割槽115內的塑封料116經切割後形成包覆在一部分厚度的晶片101'的周邊外側的第二塑封體115a，位於第一切割槽160內和相鄰底部基座153之間的間隙中的塑封料161經切割後形成包覆在底部金屬層151'、導電粘合層152'、底部基座153和餘下另一部分厚度的晶片101'的各自周邊外側的第一塑封體161'a，若設定底部基座153的平面面積小於晶片101'的橫截面面積，則第一塑封體161'a還包括環繞在底部基座153周邊外側的增大了厚度的部分161'b。如果第一切割槽160、第二切割槽115各自的寬度較之對方有差異，則第一塑封體161'a的厚度與第二塑封體115a的厚度也不一樣，但第一塑封體161'a和第二塑封體115a的厚度差可以通過改變第一切割槽160和第二切割槽115各自的寬度值進行調整，因此，第一塑封體161'a和第二塑封體115a的厚度既可以相等也可以稍有差異。第一塑封體161'a和第二塑封體115a構成一個整體性的塑封體，包覆在晶片101'、底部金屬層151'、導電粘合層152'和底部基座153各自周邊外側，該塑封體大致上也呈現為一個沒有頂蓋和底蓋的正方體或長方體外殼，其橫截面為正方形或長方形的環形框。In the cutting step, the plastic sealing layer 140 is cut into a plurality of top molding layers 141, and the front surface of each wafer 101' is correspondingly covered with a top molding layer 141. The molding compound 116 located in the second cutting groove 115 is cut to form a second molding body 115a coated on the outer side of the periphery of the wafer 101' of a portion of the thickness, between the first cutting groove 160 and the adjacent bottom base 153. The molding compound 161 in the gap is cut to form a first molding body 161 covering the bottom metal layer 151', the conductive bonding layer 152', the bottom base 153, and the outer periphery of the wafer 101' of the remaining thickness of the other portion. 'a, if the planar area of the bottom base 153 is set to be smaller than the cross-sectional area of the wafer 101', the first molding body 161'a further includes an enlarged thickness portion 161'b surrounding the periphery of the bottom base 153. If the widths of the first cutting groove 160 and the second cutting groove 115 are different from each other, the thickness of the first molding body 161'a is different from the thickness of the second molding body 115a, but the first molding body 161' The difference in thickness between the a and the second molding body 115a can be adjusted by changing the respective width values of the first cutting groove 160 and the second cutting groove 115, so that the thickness of the first molding body 161'a and the second molding body 115a can be Equality can also be slightly different. The first molding body 161'a and the second molding body 115a constitute a unitary molding body, which is wrapped around the periphery of each of the wafer 101', the bottom metal layer 151', the conductive adhesive layer 152' and the bottom base 153. The molded body is also substantially presented as a square or rectangular parallelepiped casing without a top cover and a bottom cover, and has a square or rectangular annular frame in cross section.
在圖2A-2G所示的實施方式中，第二切割槽115的深度小於減薄晶圓的厚度。也可以在背面進行研磨時，減薄晶圓厚度直到露出第二切割槽115和其中的塑封料116，然後沉積金屬層151覆蓋在晶圓的減薄背面和露出的塑封料116，再將底部基座153粘貼在金屬層151覆蓋在每個晶片背面的區域上，最後沿第二切割槽115切割分離塑封料116， 金屬層151以及底部基座153的連筋。這樣第一切割槽160和其中的塑封料161，就可以作為選項而非必需了。在這種實施方式中塑封層140可以厚些完全將金屬互連結構130包覆住，以便在晶圓減薄後提供足夠的機械支援，並在最後切割分離前將塑封層140減薄以露出金屬互連結構。In the embodiment illustrated in Figures 2A-2G, the depth of the second dicing trench 115 is less than the thickness of the thinned wafer. It is also possible to reduce the thickness of the wafer when the back side is ground until the second cutting groove 115 and the molding compound 116 therein are exposed, and then deposit a metal layer 151 covering the thinned back surface of the wafer and the exposed molding compound 116, and then the bottom portion The pedestal 153 is pasted on the area where the metal layer 151 covers the back surface of each wafer, and finally the detached molding material 116, the metal layer 151 and the bottom pedestal 153 are cut along the second cutting groove 115. Thus, the first cutting groove 160 and the molding compound 161 therein can be used as an option rather than being necessary. In this embodiment, the encapsulation layer 140 can be completely covered with the metal interconnect structure 130 to provide sufficient mechanical support after the wafer is thinned, and the plastic encapsulation layer 140 is thinned to be exposed before the final dicing separation. Metal interconnect structure.
製備圖1A所示的通孔121和焊墊110b的一種典型方式是，先在晶圓100的每個晶片內形成深度小於晶圓厚度的通孔121，然後在通孔121側壁和底部沉積一層隔離層（未示出），再在該通孔121內填充導電材料122，之後再在晶片正面形成與通孔121有交疊部分的第二類焊墊110b，因此第二類焊墊110b電性連接在通孔121內的導電材料122上。圖3A-3D是形成通孔121的另一種實施方式，其與圖1A-1D的主要區別是，在起始階段的晶圓100內並未形成通孔121，先形成塑封層140並減薄晶圓100後，才在減薄背面進行鑽孔以在晶圓100的每個晶片內形成對準第二類焊墊110b的通孔121，然後在通孔121側壁沉積一層隔離層（未示出），之後再在通孔121內填充導電材料122，最後再在減薄背面沉積金屬層151。A typical way of preparing the via 121 and the pad 110b shown in FIG. 1A is to first form a via 121 having a depth less than the thickness of the wafer in each wafer of the wafer 100, and then deposit a layer on the sidewall and bottom of the via 121. An isolation layer (not shown) is further filled with the conductive material 122 in the via hole 121, and then a second type of pad 110b overlapping the through hole 121 is formed on the front surface of the wafer, so that the second type of pad 110b is electrically The conductive material 122 is connected to the conductive material 122 in the through hole 121. 3A-3D are another embodiment of forming the via hole 121, and the main difference from FIG. 1A-1D is that the through hole 121 is not formed in the wafer 100 at the initial stage, and the plastic sealing layer 140 is first formed and thinned. After the wafer 100, drilling is performed on the thinned back surface to form a via 121 aligned with the second type of pad 110b in each wafer of the wafer 100, and then a spacer layer is deposited on the sidewall of the via 121 (not shown). Then, the conductive material 122 is filled in the via hole 121, and finally the metal layer 151 is deposited on the thinned back surface.
圖4A-4E是形成通孔121的又一種實施方式，與圖2A-2C所示的實施例的主要區別是，在起始階段晶圓100內並未形成有通孔121，只是在減薄晶圓100後，才在減薄背面進行鑽孔以在晶圓100的每個晶片內形成對準第二類焊墊110b的通孔121，並在通孔121側壁沉積一層隔離層（未示出），然後再在通孔121內填充導電材料122，之後再在減薄背面沉積金屬層151。4A-4E are still another embodiment of forming the via hole 121. The main difference from the embodiment shown in FIGS. 2A-2C is that the via hole 121 is not formed in the wafer 100 at the initial stage, but is thinned. After the wafer 100, drilling is performed on the thinned back surface to form a via 121 aligned with the second type of pad 110b in each wafer of the wafer 100, and a spacer layer is deposited on the sidewall of the via 121 (not shown). Then, the conductive material 122 is filled in the via hole 121, and then the metal layer 151 is deposited on the thinned back surface.
圖5A-5E所示的方法與圖1A-1O的主要區別是，無需在晶片101"內形成通孔，也無需將晶片101"背面的底部金屬層151'通過通孔內的導電材料引導到晶片101"的正面，所以該晶片101"的正面僅有第一類焊墊110a而無額外設置的第二類焊墊110b，同樣可以在頂部塑封層141上形成僅僅接觸第一類焊墊110a的圖案化金屬層。圖6A-6D所示的方法與圖2A-2G的主要區別是，無需在晶片101"內形成通孔，也無需將晶片101"背面的底部金屬層151'通過通孔內的導電材料引導到晶片101"的正面，晶片101"的正面僅有第一類焊墊110a而無需額外再設置第二類焊墊110b。晶片101"的典型應用為共漏極雙MOSFET器件。此外，在另外一些實施方式中，雖然晶片101"可以不是垂直器件而是平面型的器件，理論上其背面不設置底部金屬層151'是可行的，但鑒於直接將金屬材質的底部基座153粘貼至矽材質的晶片101"的背面會有一些困難，而且會帶來一些可靠性的問題，所以在一些優選的實施方式中還是有必要保留底部金屬層151'。The main difference between the method shown in FIGS. 5A-5E and FIGS. 1A-1O is that there is no need to form via holes in the wafer 101", nor is it necessary to guide the bottom metal layer 151' of the back side of the wafer 101 through the conductive material in the via holes. The front side of the wafer 101", so that the front side of the wafer 101" has only the first type of bonding pads 110a and no additional second type of bonding pads 110b, and the upper molding layer 141 can also be formed to contact only the first type of bonding pads 110a. The patterned metal layer. The main difference between the method shown in FIGS. 6A-6D and FIGS. 2A-2G is that there is no need to form via holes in the wafer 101", nor is it necessary to guide the bottom metal layer 151' of the back side of the wafer 101 through the conductive material in the via holes. On the front side of the wafer 101", the front side of the wafer 101" has only the first type of pads 110a without the need to additionally provide the second type of pads 110b. A typical application of the wafer 101" is a common drain dual MOSFET device. Further, in other embodiments, although the wafer 101" may not be a vertical device but a planar device, in theory, the bottom metal layer 151' is not provided on the back side. It is feasible, but in view of the difficulty in directly attaching the bottom base 153 of the metal material to the back surface of the wafer 101 of the crucible material, and there are some reliability problems, it is necessary in some preferred embodiments. The bottom metal layer 151' is retained.
以上，通過說明和附圖，給出了具體實施方式的特定結構的典型實施例，上述發明提出了現有的較佳實施例，但這些內容並不作為局限。對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍書應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍書範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.
100'A．．．封裝器件100'A. . . Packaged device
180a、180b、180c．．．獨立區域180a, 180b, 180c. . . Independent area
101'．．．晶片101'. . . Wafer
161a．．．塑封體161a. . . Plastic body
161a-1．．．外側壁161a-1. . . Outer side wall
Claims (26)
一晶片及設置在晶片正面的各焊墊上的金屬互連結構；
一覆蓋在晶片背面的底部金屬層；
一通過導電粘合層焊接在底部金屬層上的底部基座；
一覆蓋在晶片正面的並包覆在各金屬互連結構側壁周圍的頂部塑封層；以及包覆在晶片、底部金屬層、導電粘合層和底部基座各自周邊外側的一橫截面呈環形框狀的塑封體。A wafer level package device with a bottom pedestal, comprising:
a wafer and a metal interconnection structure disposed on each of the pads on the front side of the wafer;
a bottom metal layer overlying the back side of the wafer;
a bottom pedestal soldered to the bottom metal layer by a conductive adhesive layer;
a top molding layer covering the front surface of the wafer and surrounding the sidewalls of the metal interconnect structures; and a cross-section annular frame surrounding the respective periphery of the wafer, the bottom metal layer, the conductive adhesive layer and the bottom base Shaped plastic body.
在每個焊墊上焊接一個金屬互連結構；
形成一覆蓋在晶圓正面的並將各金屬互連結構予以包覆的塑封層；
在晶圓的背面進行研磨以減薄晶圓並沉積一金屬層覆蓋在晶圓的減薄背面；
利用塗覆在金屬層上的一層導電的粘合材料將帶有底部基座陣列的一引線框架粘貼在金屬層上，使金屬層覆蓋在每個晶片背面的區域上相應粘貼一個底部基座；
形成貫穿粘合材料、金屬層、晶圓各自厚度的並將相鄰晶片分割開的多條第一切割槽，第一切割槽具有延伸至部分厚度的塑封層中的深度；
在所述第一切割槽中和相鄰底部基座之間的間隙中填充塑封料；
研磨減薄塑封層直至金屬互連結構予以外露；
沿第一切割槽對所述塑封料進行切割。A method of fabricating a wafer level package device with a bottom pedestal, providing a wafer including a plurality of wafers and having a plurality of pads on each front surface of the wafer, comprising the steps of:
Soldering a metal interconnect structure on each pad;
Forming a plastic sealing layer covering the front surface of the wafer and covering each metal interconnection structure;
Grinding on the back side of the wafer to thin the wafer and deposit a metal layer overlying the thinned back side of the wafer;
Attaching a lead frame with a bottom pedestal array to the metal layer by using a layer of conductive adhesive material coated on the metal layer, and affixing a bottom pedestal correspondingly to the area of the back surface of each wafer;
Forming a plurality of first cutting grooves penetrating the respective thicknesses of the bonding material, the metal layer, and the wafer and separating the adjacent wafers, the first cutting grooves having a depth extending into the partial thickness of the plastic sealing layer;
Filling a gap between the first cutting groove and the adjacent bottom base; and filling a molding compound;
Grinding and thinning the plastic sealing layer until the metal interconnection structure is exposed;
The molding compound is cut along the first cutting groove.
提供一支撐晶圓，並利用一粘貼膜將引線框架粘貼在支撐晶圓的正面；
將晶圓的減薄背面面向支撐晶圓的正面，並利用塗覆在金屬層上的一層導電的粘合材料將引線框架粘貼在金屬層上，從而將晶圓和支撐晶圓鍵合在一起；
其中，金屬層覆蓋在每個晶片背面的區域對準一個底部基座，以便將該對準的底部基座粘貼在金屬層的覆蓋在晶片背面的該區域；
之後移除所述粘貼膜和支撐晶圓。The method of claim 10, wherein the step of attaching the lead frame to the metal layer comprises:
Providing a supporting wafer and bonding the lead frame to the front surface of the supporting wafer by using an adhesive film;
The thinned back side of the wafer faces the front side of the supporting wafer, and the lead frame is pasted on the metal layer by a conductive adhesive material coated on the metal layer, thereby bonding the wafer and the supporting wafer together ;
Wherein the metal layer covers a region of the back surface of each wafer aligned with a bottom pedestal to adhere the aligned bottom pedestal to the region of the metal layer overlying the back side of the wafer;
The adhesive film and the support wafer are then removed.
在每個焊墊上焊接一個金屬互連結構；
在所述晶圓的正面切割出界定每個晶片邊界的多條第二切割槽；
形成一覆蓋在晶圓正面的並至少包覆在各金屬互連結構側壁周圍的塑封層，且形成所述塑封層的塑封料同時還填充在所述第二切割槽中；
在晶圓的背面進行研磨以減薄晶圓並沉積一金屬層覆蓋在晶圓的減薄背面；
利用塗覆在金屬層上的一層導電的粘合材料將帶有底部基座陣列的一引線框架粘貼在金屬層上，使金屬層覆蓋在每個晶片背面的區域上相應粘貼一個底部基座；
沿第二切割槽對填充在第二切割槽中的塑封料以及對所述塑封層實施切割。A method of fabricating a wafer level package device with a bottom pedestal, providing a wafer including a plurality of wafers and having a plurality of pads on each front surface of the wafer, comprising the steps of:
Soldering a metal interconnect structure on each pad;
Cutting a plurality of second cutting grooves defining a boundary of each wafer on a front surface of the wafer;
Forming a plastic sealing layer covering the front surface of the wafer and covering at least around the sidewalls of the metal interconnect structures, and the molding compound forming the plastic sealing layer is also filled in the second cutting groove;
Grinding on the back side of the wafer to thin the wafer and deposit a metal layer overlying the thinned back side of the wafer;
Attaching a lead frame with a bottom pedestal array to the metal layer by using a layer of conductive adhesive material coated on the metal layer, and affixing a bottom pedestal correspondingly to the area of the back surface of each wafer;
The molding compound filled in the second cutting groove and the cutting of the plastic sealing layer are cut along the second cutting groove.
先在晶圓的每個晶片內形成深度小於晶圓厚度的通孔，然後再在該通孔內填充導電材料，之後再在晶片正面形成與通孔有交疊部分的並與通孔內的導電材料保持電接觸的第二類焊墊。The method of claim 18 or 20, wherein the bonding pad comprises a first type of bonding pad and a second type of bonding pad, and the step of forming the second type of bonding pad comprises:
First, a via hole having a depth smaller than a thickness of the wafer is formed in each wafer of the wafer, and then the conductive material is filled in the via hole, and then the front surface of the wafer is formed in an overlapping portion with the through hole and in the through hole. A second type of pad that holds the electrically conductive material in electrical contact.
提供一支撐晶圓，並利用一粘貼膜將引線框架粘貼在支撐晶圓的正面；
將晶圓的減薄背面面向支撐晶圓的正面，並利用塗覆在金屬層上的一層導電的粘合材料將引線框架粘貼在金屬層上，以將晶圓和支撐晶圓鍵合在一起；
其中，金屬層覆蓋在每個晶片背面的區域對準一個底部基座，以便將該對準的底部基座粘貼在金屬層的覆蓋在晶片背面的該區域；
之後移除所述粘貼膜和支撐晶圓。The method of claim 18 or 20, wherein the step of attaching the lead frame to the metal layer comprises:
Providing a supporting wafer and bonding the lead frame to the front surface of the supporting wafer by using an adhesive film;
The thinned back side of the wafer faces the front side of the supporting wafer, and the lead frame is pasted on the metal layer by a layer of conductive adhesive material coated on the metal layer to bond the wafer and the supporting wafer together ;
Wherein the metal layer covers a region of the back surface of each wafer aligned with a bottom pedestal to adhere the aligned bottom pedestal to the region of the metal layer overlying the back side of the wafer;
The adhesive film and the support wafer are then removed.
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| US13/602,144 US8853003B2 (en) | 2011-08-09 | 2012-09-01 | Wafer level chip scale package with thick bottom metal exposed and preparation method thereof |
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| TW201411743A (en) | 2014-03-16 |
| TWI529893B (en) | 2016-04-11 |
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| CN103681377A (en) | 2014-03-26 |
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