TWI512741B - System and methods to improve the performance of semiconductor based sampling system (4) - Google Patents

Description

用於增進以半導體為基礎之取樣系統之效能的系統與方法(四)System and method for improving the performance of semiconductor-based sampling systems (4) 對相關申請案的交叉引用Cross-reference to related applications

本申請案係相關於與本申請案共同申請的美國專利申請案第13/155,993 號、第13/155,922 號與第13/155,945 號，該等申請案具有共同的發明名稱、申請人且共同轉讓。The present application is related to U.S. Patent Application Serial Nos. 13/155,993 , 13/155,922 , and 13/155,945 , which are incorporated herein by reference . .

本發明係關於電子取樣系統。更特定言之，本發明係關於藉由減少訊號失真來增進電子取樣系統之效能的電路與方法，訊號失真常見地相關聯於此種系統的電子實施。The present invention is directed to an electronic sampling system. More particularly, the present invention relates to circuits and methods for enhancing the performance of electronic sampling systems by reducing signal distortion, which is commonly associated with electronic implementation of such systems.

取樣系統被廣泛地應用於電子應用中。例如，取樣系統常見於流行的電子裝置中，諸如MP3撥放器、DVD撥放器以及蜂巢式電話。其他流行的取樣系統用途，包含相關於資料獲取、測試與量測，以及控制系統應用的用途。更特定言之，取樣系統以及以取樣為基礎的科技，可見於用以建置此種裝置的電子部件中，電子部件包含類比數位轉換器、切換電容網路、訊號獲取電路系統、比較器以及其他者。Sampling systems are widely used in electronic applications. For example, sampling systems are commonly found in popular electronic devices such as MP3 players, DVD players, and cellular phones. Other popular sampling system uses include data acquisition, testing and measurement, and the use of control system applications. More specifically, sampling systems and sampling-based technologies can be found in electronic components used to build such devices, including analog digital converters, switched capacitor networks, signal acquisition circuitry, comparators, and Others.

在一些應用中，取樣系統採用取樣保持(sample and hold)電路，取樣保持電路取樣電壓，並將電壓維持在儲存裝置中，而使另一電路可量測或觀察所獲取的電壓。然而，如已知於本發明領域中，僅僅是取樣所感興趣之訊號的步驟，即會給予一些失真量至所取樣的訊號。In some applications, the sampling system uses sample and hold (sample and Hold) The circuit holds the sampled voltage and maintains the voltage in the storage device, allowing another circuit to measure or observe the acquired voltage. However, as is known in the art, only the step of sampling the signal of interest will give some amount of distortion to the sampled signal.

由取樣電路系統中的部件所產生的訊號失真，傾向於限制輸入訊號的可用電壓與頻率範圍。此種失真可由各種因素產生，諸如取樣保持電路中的開關的非線性電阻值特性、與關斷(turnoff)臨限值相關聯的效應、體效應(bulk effect)、開關比例匹配變異與製程變異等等。失真亦可由取樣電路中開關的寄生電容、取樣電路中開關所造成的訊號相依電荷注入(charge injection)、流過輸入源電阻的非線性負載電流等等造成。The distortion of the signal produced by the components in the sampling circuitry tends to limit the available voltage and frequency range of the input signal. Such distortion can be caused by various factors, such as the nonlinear resistance value characteristics of the switches in the sample and hold circuit, the effects associated with the turnoff threshold, the bulk effect, the switch ratio matching variation, and the process variation. and many more. Distortion can also be caused by the parasitic capacitance of the switches in the sampling circuit, the signal-dependent charge injection caused by the switches in the sampling circuit, the non-linear load current flowing through the input source resistance, and the like.

第1圖圖示典型的先前技術取樣保持電路100。取樣保持電路100一般而言包含開關110(諸如電晶體或傳輸閘)，開關110耦合在輸入終端115與儲存裝置(諸如取樣電容器120)之間。開關110的阻抗可透過開關阻抗控制終端135來控制，在「關閉」訊號施加至終端135時，終端135允許開關110操作為「開路」(亦即具有非常大的阻抗)，或者在「開啟」訊號施加至終端135時，終端135允許開關110操作為「短路」(亦即具有非常小的阻抗)。FIG. 1 illustrates a typical prior art sample and hold circuit 100. The sample and hold circuit 100 generally includes a switch 110 (such as a transistor or transfer gate) coupled between the input terminal 115 and a storage device, such as the sampling capacitor 120. The impedance of the switch 110 can be controlled by the switch impedance control terminal 135. When the "off" signal is applied to the terminal 135, the terminal 135 allows the switch 110 to operate as an "open circuit" (i.e., has a very large impedance), or "on" When signal is applied to terminal 135, terminal 135 allows switch 110 to operate as a "short circuit" (i.e., has a very small impedance).

在開關110(例如)被實施為N通道MOS電晶體時，在高於開關110的傳導臨限值的電壓被施加於開關110的控制節點(諸如閘極)時開關110為開啟，而在低於 開關110的傳導臨限值的電壓被施加於開關110的閘極時開關110為關閉。如已知於本發明領域，開關110被開啟或關閉的程度，係相依於施加於開關110控制節點的訊號的量值。因此(例如)，可施加恰於傳導臨限值之上的訊號至開關110的控制節點而開啟開關110，但可藉由施加較大的電壓來更完整地開啟開關110而增進傳導性特性。相反的，若控制電壓降至傳導性臨限值以下，則開關110可被關閉。When the switch 110 is implemented, for example, as an N-channel MOS transistor, the switch 110 is turned on when the voltage higher than the conduction threshold of the switch 110 is applied to the control node of the switch 110, such as the gate. to The switch 110 is turned off when a voltage of the conduction threshold of the switch 110 is applied to the gate of the switch 110. As is known in the art, the extent to which switch 110 is turned "on" or "off" depends on the magnitude of the signal applied to the control node of switch 110. Thus, for example, a signal just above the conduction threshold can be applied to the control node of switch 110 to turn on switch 110, but the conductive characteristic can be enhanced by applying a larger voltage to turn switch 110 more completely. Conversely, if the control voltage falls below the conductivity threshold, the switch 110 can be turned off.

在作業中，時變輸入訊號被施加至輸入終端115。控制電路125耦合於指令終端130與控制終端135之間。控制電路125回應於施加於指令節點130的外部保持指令訊號，將開關阻抗調變於高(關閉)與低(開啟)之間。In the operation, a time varying input signal is applied to the input terminal 115. Control circuit 125 is coupled between command terminal 130 and control terminal 135. The control circuit 125 modulates the switch impedance between high (closed) and low (turned) in response to an external hold command signal applied to the command node 130.

取樣保持電路100具有兩個個別的狀態，該兩個個別的狀態通常稱為取樣狀態與保持狀態。在取樣狀態中，開關110為開啟(亦即，在輸入終端115與取樣電容器120之間呈現低阻抗)，因此強迫取樣電容器120上的訊號跟隨輸入訊號。在保持狀態中，開關110為「關閉」(亦即，在輸入終端115與取樣電容器120之間呈現高阻抗)，因此在電容器120上的訊號被維持在訊號的先前位準，且在電容器120上的訊號實質上不相依於輸入訊號。The sample and hold circuit 100 has two individual states, commonly referred to as a sample state and a hold state. In the sampled state, switch 110 is on (i.e., exhibits a low impedance between input terminal 115 and sampling capacitor 120), thereby forcing the signal on sampling capacitor 120 to follow the input signal. In the hold state, switch 110 is "off" (i.e., exhibits a high impedance between input terminal 115 and sampling capacitor 120), so that the signal on capacitor 120 is maintained at the previous level of the signal and at capacitor 120. The signal on the signal is substantially independent of the input signal.

如已知於本發明領域，可使用各種電子與機電部件來實施開關110，包含(但不限於)繼電器、電樞開關， 以及各種形式的電晶體(包含雙極性接面電晶體(BJT)、場效電晶體(FET)等等)。As is known in the art, various electronic and electromechanical components can be used to implement switch 110, including but not limited to relays, armature switches, And various forms of transistors (including bipolar junction transistors (BJT), field effect transistors (FET), etc.).

然而，已知的取樣保持電路(類似於上文所說明者)，受到各種缺點與缺陷的不良影響。例如，因為相關聯於實體部件實施的一些性質，取樣狀態的開關阻抗時常不夠低而無法達成最佳的訊號傳輸，或開關阻抗可隨著輸入訊號的量值變化。此可(至少部分地)因為施加至開關110控制節點的訊號不夠完整地開啟電晶體，或由於輸入訊號量值的改變，訊號相對於裝置傳導臨限值的關係變化而發生。However, known sample and hold circuits (similar to those described above) are adversely affected by various shortcomings and drawbacks. For example, because of some of the properties associated with physical component implementations, the switching impedance of the sampling state is often not low enough to achieve optimal signal transmission, or the switching impedance can vary with the magnitude of the input signal. This can occur (at least in part) because the signal applied to the control node of switch 110 is not fully turned on, or due to a change in the magnitude of the input signal, the relationship of the signal relative to the device's conduction threshold changes.

所產生的在取樣狀態中的不良影響，為儲存於電容器120上的電壓訊號將不同於施加於輸入終端115的輸入訊號。再者，儲存於電容器120上的電壓訊號與輸入訊之間的差異，可為對於輸入訊號瞬時值的函數。因此，在保持狀態期間所獲取的訊號將為不精確的輸入訊號代表，且任何隨後的訊號處理方塊將被該等不精確度影響。隨著輸入訊號的最大頻率提昇，此種訊號失真變得越來越顯著，且此種訊號失真的量值變得與可用的電力供應範圍相當。The resulting adverse effect in the sampling state is that the voltage signal stored on capacitor 120 will be different from the input signal applied to input terminal 115. Moreover, the difference between the voltage signal stored on the capacitor 120 and the input signal can be a function of the instantaneous value of the input signal. Therefore, the signal acquired during the hold state will be an inaccurate input signal representation, and any subsequent signal processing blocks will be affected by such inaccuracies. As the maximum frequency of the input signal increases, such signal distortion becomes more and more significant, and the magnitude of such signal distortion becomes comparable to the available power supply range.

高速取樣資料系統(諸如類比數位轉換器)的效能，係敏感於在循序的取樣作業的時間區間之間的變異。此變異可稱為取樣抖動(jitter)。取樣抖動的成分為時間延遲的變異，該時間延遲從外部保持指令確立於指令終端130之時刻，至開關110進入保持狀態(亦即關閉) 之時刻。控制電路125通常需要有限的時間區間來產生控制訊號，控制訊號將把開關阻抗從取樣值調變成保持值。若發生此轉變的臨限值相依於輸入訊號，則會產生取樣抖動。因此，一般而言希望將輸入訊號對開關控制訊號轉變臨限值的影響最小化。The performance of high-speed sampling data systems, such as analog-like digital converters, is sensitive to variations between the time intervals of sequential sampling operations. This variation can be referred to as sample jitter. The component of the sample jitter is a variation of the time delay from the moment when the external hold command is established at the command terminal 130 until the switch 110 enters the hold state (ie, is turned off). The moment. Control circuit 125 typically requires a limited time interval to generate a control signal that will change the switching impedance from the sampled value to a hold value. If the threshold of this transition depends on the input signal, sample jitter will occur. Therefore, it is generally desirable to minimize the effects of input signals on the threshold of the switching control signal transition.

在克服取樣抖動缺點的一種方式中，使用CMOS傳輸閘來建置取樣開關。然而，使用其中輸入訊號範圍相當於可用電力供應的此實施，讓在取樣狀態期間內的等效開關阻抗變異變得顯著，並隨著輸入訊號頻率提昇而引入提昇的失真量。In one way to overcome the shortcomings of sample jitter, a CMOS transfer gate is used to build the sampling switch. However, using this implementation in which the input signal range is equivalent to the available power supply, the equivalent switching impedance variation during the sampling state becomes significant and introduces an increased amount of distortion as the input signal frequency increases.

de Wit於美國專利第5,170,075號中說明嘗試解決此問題的一種早期作法。如第2圖所圖示(為de Wit所提出之電路的一般代表)，輸入訊號215被直接連接至控制電路225並且輸入訊號215透過開關210耦合至取樣電容器220。該開關210係使用MOSFET裝置來建置。控制電路225回應於外部保持訊號230經由控制終端235控制開關阻抗，並且控制電路225使用一組推升電容器(未圖示)，推升電容器經耦合以產生預選定電壓V_P ，在取樣狀態中預選定電壓V_P 被疊加至輸入電壓上。所產生的複合電壓被用以在取樣狀態中控制開關阻抗。因此，在取樣狀態中，開關210被使用固定的閘極對通道電壓來控制，此舉減少了相依於輸入訊號的開關阻抗變異。此外，在取樣狀態與保持狀態之間的轉變臨限值係由V_P 的量值決定，且該轉變臨限值係實質上獨立於輸入 電壓。An early practice of attempting to solve this problem is described in U.S. Patent No. 5,170,075. As illustrated in FIG. 2 (which is a general representation of the circuit proposed by de Wit), input signal 215 is directly coupled to control circuit 225 and input signal 215 is coupled to sampling capacitor 220 via switch 210. The switch 210 is built using a MOSFET device. The control circuit 225 is held in response to the external terminal 235 via the control signal 230 controls switch impedance, and the control circuit 225 using a set of boosted capacitor (not shown), pushing up the capacitor is coupled to generate a preselected voltage V _P, the sampling state, The preselected voltage V _P is superimposed on the input voltage. The resulting composite voltage is used to control the switching impedance in the sampling state. Thus, in the sampled state, switch 210 is controlled using a fixed gate-to-channel voltage, which reduces the switching impedance variation that is dependent on the input signal. Further, the sampling and holding a state transition between states based threshold value is determined by the magnitude of V _P, and the transition threshold based substantially independent of the input voltage.

美國專利第5,500,612號與第6,118,326號呈現其他克服與已知取樣電路相關聯之缺陷的嘗試。此兩專利案所說明的電路包含透過額外開關耦合至敏感輸入終端的大量電路系統。所提出的該等配置的一種不良結果，為在輸入處的訊號相依負載的提昇，以及在取樣狀態與保持狀態之間轉變期間內的不良反沖(kick-back)訊號。由於外部輸入訊號驅動器的有限阻抗，額外的訊號相依負載，可轉譯成提昇的訊號失真。Other attempts to overcome the deficiencies associated with known sampling circuits are presented in U.S. Patent Nos. 5,500,612 and 6,118,326. The circuits described in the two patents contain a large number of circuitry coupled to the sensitive input terminals through additional switches. A poor result of the proposed configuration is a signal-dependent increase in load at the input, and a bad kick-back signal during the transition between the sampled state and the held state. Due to the finite impedance of the external input signal driver, additional signals can be translated into increased signal distortion depending on the load.

再者，反沖訊號在預選定V_P 電壓疊加至輸入訊號上時出現(部分因為在真實實施中呈現的各種阻抗)。該等訊號對外部輸入訊號驅動器呈現更為困難的安定時間需求，因此提昇了電力消耗與成本。此外，在閘極對通道電壓特性稍微增進的同時，通道對體極的電位仍隨著變化的輸入訊號而改變。因此，因為開關裝置的體效應，在取樣狀態期間的開關阻抗持續變化。類似的，轉變臨限值亦相依於開關裝置體效應。Moreover, recoil signal appears (in part because various impedances present in the real implementation) at preselected voltage V _P is superimposed onto the input signal. These signals present a more difficult settling time requirement for external input signal drivers, thereby increasing power consumption and cost. In addition, while the gate-to-channel voltage characteristics are slightly enhanced, the channel-to-body potential still changes with varying input signals. Therefore, the switching impedance during the sampling state continues to change due to the body effect of the switching device. Similarly, the transition threshold is also dependent on the body effect of the switching device.

Maes等人在美國專利第6,329,848號中呈現另一克服與已知取樣電路相關聯之缺陷的作法，此作法採用一些已知的隔離技術以減少輸入處的負載。更特定言之，如圖示於第3圖(為Maes等人所提出之電路的一般代表)，使用專屬緩衝放大器345來隔離控制電路325與輸入終端315。使用MOSFET裝置來實施開關310，開關310的源極與汲極終端耦合至輸入終端315與取樣電容 器320。閘極終端335與體極終端340皆由控制電路325驅動。Another approach to overcoming the deficiencies associated with known sampling circuits is presented by Maes et al. in U.S. Patent No. 6,329,848, which uses some known isolation techniques to reduce the load at the input. More specifically, as shown in Figure 3 (which is a general representation of the circuit proposed by Maes et al.), a dedicated buffer amplifier 345 is used to isolate control circuit 325 from input terminal 315. Switch 310 is implemented using a MOSFET device, the source and drain terminals of switch 310 being coupled to input terminal 315 and sampling capacitor 320. Both the gate terminal 335 and the body terminal 340 are driven by a control circuit 325.

第3圖的電路以作為由緩衝器345重製之輸入訊號的函數，來個別地控制閘極對通道電壓與通道對體極電壓，以減少在取樣狀態期間內的開關阻抗變異。此外，緩衝放大器345傾向於減少輸入終端的不良負載。然而，此作法持續受到各種缺點的不良影響。例如，儘管與其他實施相較之下減少了負載，但此實施仍在輸入終端加入一些負載，而給予一些失真量至輸入訊號。再者，此作法需要使用專屬緩衝放大器，此專屬緩衝放大器具有良好安定時間特性與可忽略之群組延遲，此放大器的製造是相當昂貴的。The circuit of Figure 3 individually controls the gate-to-channel voltage and the channel-to-body voltage as a function of the input signal reproduced by buffer 345 to reduce switching impedance variations during the sampling state. In addition, the buffer amplifier 345 tends to reduce the bad load of the input terminal. However, this practice continues to be adversely affected by various shortcomings. For example, although the load is reduced compared to other implementations, this implementation adds some load to the input terminal and gives some amount of distortion to the input signal. Furthermore, this approach requires the use of a dedicated buffer amplifier with good settling time characteristics and negligible group delay, which is quite expensive to manufacture.

因此，由上文可知，想要提供藉由減少訊號失真來增進電子取樣系統之效能的電路系統與方法，訊號失真常見地相關聯於此種系統的實體實施。Thus, from the above, it is known to provide circuitry and methods for enhancing the performance of an electronic sampling system by reducing signal distortion, which is commonly associated with the physical implementation of such systems.

本發明相關於操作於至少一取樣狀態與一保持狀態的取樣電路，包含：輸入終端，該輸入終端接收時變輸入訊號；以及半導體開關，該半導體開關如由施加至控制終端的電荷量所指示，而操作於至少一非傳導模式與一傳導模式中，該半導體開關係耦合於該輸入終端與輸出終端之間，可在體極偏壓終端存取該半導體開關的體 極；控制電路，該控制電路耦合至該控制終端，並可操作以選定該半導體開關的操作模式；以及體極偏壓電路，該體極偏壓電路耦合於該體極偏壓終端與該輸入終端或該輸出終端之間，在取樣狀態與保持狀態兩者中，該體極偏壓電路在該等終端之間維持經預定且實質上固定的體極偏壓電壓差。The present invention relates to a sampling circuit operating in at least one sampling state and a holding state, comprising: an input terminal receiving a time varying input signal; and a semiconductor switch as indicated by an amount of charge applied to the control terminal And operating in at least one non-conducting mode and a conducting mode, the semiconductor open relationship is coupled between the input terminal and the output terminal, and the body of the semiconductor switch can be accessed at the body bias terminal a control circuit coupled to the control terminal and operable to select an operational mode of the semiconductor switch; and a body bias circuit coupled to the body bias terminal and Between the input terminal or the output terminal, the body bias circuit maintains a predetermined and substantially fixed body bias voltage difference between the terminals in both the sampled state and the held state.

第4圖圖示根據本發明之原則來建置的取樣電路400。如第3圖，第4圖的取樣電路一般而言包含控制電路425、取樣開關410、電容器或其他適合的儲存部件420、指令節點430、開關控制終端435以及輸入終端415。在此範例中，儲存部件420為電容器(雖然亦可依所需使用其他適合的儲存部件)。Figure 4 illustrates a sampling circuit 400 constructed in accordance with the principles of the present invention. As shown in FIG. 3, the sampling circuit of FIG. 4 generally includes a control circuit 425, a sampling switch 410, a capacitor or other suitable storage component 420, an instruction node 430, a switch control terminal 435, and an input terminal 415. In this example, storage component 420 is a capacitor (although other suitable storage components may be used as desired).

與第1圖至第3圖所圖示的取樣電路相較之下，取樣電路400所增進的一個方面，為大量地減少或消除了所有連接至敏感輸入終端415的額外電路系統。在一些具體實施例中，耦合至輸入終端的此種剩餘電路系統在取樣模式期間(剩餘電路系統的存在在此時最為不良)可被斷開(於下文更進一步討論)。如第4圖所圖示，控制電路425係耦合於指令節點430與取樣開關410的控制終端435之間。In contrast to the sampling circuit illustrated in Figures 1 through 3, one aspect of the sampling circuit 400 enhancement is to substantially reduce or eliminate all of the additional circuitry connected to the sensitive input terminal 415. In some embodiments, such residual circuitry coupled to the input terminal can be disconnected during the sampling mode (the presence of the remaining circuitry is most undesirable at this time) (discussed further below). As illustrated in FIG. 4, control circuit 425 is coupled between command node 430 and control terminal 435 of sampling switch 410.

第4圖亦圖示取樣開關410為耦合於輸入終端415與 電容器420之間。開關410的阻抗係由控制電路425控制，如由施加至指令節點430的外部保持訊號決定。Figure 4 also illustrates sampling switch 410 coupled to input terminal 415 and Between capacitors 420. The impedance of switch 410 is controlled by control circuit 425 as determined by an external hold signal applied to command node 430.

類似於圖示說明於第1圖至第3圖中的先前技術電路，電路400可操作於至少兩個不同的模式：取樣模式與保持模式。在取樣模式中，取樣開關410的阻抗為低，且因此在節點415的輸入訊號被典型地施加至電容器420。在取樣模式中，電路400可操作如下。輸入訊號可被施加至輸入終端415。諸如保持訊號的指令訊號隨後可被施加(或切換)於指令節點430，使控制終端435上的訊號開啟取樣開關410。Similar to the prior art circuit illustrated in Figures 1 through 3, circuit 400 is operable in at least two different modes: a sampling mode and a hold mode. In the sampling mode, the impedance of the sampling switch 410 is low, and thus the input signal at node 415 is typically applied to capacitor 420. In the sampling mode, circuit 400 is operable as follows. The input signal can be applied to the input terminal 415. An instruction signal, such as a hold signal, can then be applied (or switched) to the command node 430 to cause the signal on the control terminal 435 to turn on the sampling switch 410.

一般而言，控制電路425產生預定電荷Q_P ，並將Q_P 施加至取樣開關410。此預定電荷對取樣開關410產生實質上固定的閘極對源極控制電壓，而使取樣開關的阻抗被維持在實質上固定的位準，此位準可基於開關410的開啟特性來預先決定。為了圖示說明之目的，假定Q_P 被選定為使取樣開關410中的傳輸路徑的阻抗相對於輸入訊號保持為最小化(亦即實質上固定)。此設置允許終端415的輸入訊號將電容器420充電至輸入訊號的值，而不會受到與開關阻抗變化相關聯的失真的不良影響。In general, control circuit 425 generates a predetermined charge Q _P and applies Q _P to sampling switch 410. This predetermined charge produces a substantially fixed gate-to-source control voltage to the sampling switch 410, while maintaining the impedance of the sampling switch at a substantially fixed level, which can be predetermined based on the opening characteristics of the switch 410. For purposes of illustration, assume that Q _P is selected as the sampling switch impedance of the transmission path 410 with respect to the input signal to a minimum of (i.e., substantially fixed). This setting allows the input signal from terminal 415 to charge capacitor 420 to the value of the input signal without being adversely affected by the distortion associated with the change in switch impedance.

在一些具體實施例中，可提供保持指令，而使電路400被維持在取樣狀態或保持狀態，並僅在此兩狀態中切換。例如，保持指令可為來自內部或外部源的邏輯高或邏輯低訊號，而將電路400置於此兩模式中的一者。此可被完成以防止指令節點430為「浮接」，浮接可將電路 400置於不確定狀態。In some embodiments, a hold command can be provided while the circuit 400 is maintained in a sampled state or a held state and switched only in both states. For example, the hold command can be a logic high or logic low signal from an internal or external source, and circuit 400 can be placed in one of these two modes. This can be done to prevent the instruction node 430 from being "floating", and the floating connection can be used to circuit 400 is placed in an indeterminate state.

再者，在一些具體實施例中，可考慮取樣開關410的開啟特性來選定預定電荷Q_P ，而能實質上達成並維持電路設計者所需的開關阻抗，即使相對於變化的輸入訊號。例如，可考慮輸入訊號選定Q_P 值，以在取樣模式中的同時將開關阻抗最小化，並藉以將在所獲取輸入訊號上的失真最小化或消除。Further, in some embodiments, may be considered characteristic of the sampling switch 410 is turned on to select the predetermined charge Q _P, but can substantially achieve and maintain the desired impedance of the switch circuit designer, even with respect to changes in the input signal. For example, the input signal can be considered to select the Q _P value to minimize the switching impedance while in the sampling mode, thereby minimizing or eliminating distortion on the acquired input signal.

在其他具體實施例中，控制電路425亦可包含已知電路系統(未圖示)以調整Q_P 來處理開關特性中的生產變異，或處理由於部件老化、溫度變異、電力供應變異等等所造成的改變。In other embodiments, control circuit 425 may also include known circuitry (not shown) to adjust Q _P to handle production variations in switching characteristics, or to handle aging, temperature variations, power supply variations, etc. The change caused.

在取樣開關410被開啟時，在輸入終端415的訊號被施加至電容器420，電容器420儲存代表訊號量值的值。在傳統取樣保持電路中，電容器420以集成於電容器上板之電荷的形式，來儲存任何輸入訊號的量值。儲存在電容器420上的電壓隨後可被量測，或該電壓隨後可依所需被觀察並處理。When the sampling switch 410 is turned on, the signal at the input terminal 415 is applied to the capacitor 420, which stores a value representative of the magnitude of the signal. In a conventional sample and hold circuit, capacitor 420 stores the magnitude of any input signal in the form of a charge integrated into the upper plate of the capacitor. The voltage stored on capacitor 420 can then be measured, or the voltage can then be observed and processed as desired.

在較佳的具體實施例中，取樣週期的持續時間足以讓輸入訊號安定，並確保正確地獲取輸入訊號。然而，如將從上文中瞭解，取樣開關410可保持開啟，只要保持訊號如此指示取樣開關410。在此種具體實施例中，取樣週期的持續時間可由保持訊號控制。在其他具體實施例中，取樣狀態可由電壓維持，該電壓儲存在與開關410相關聯之特定電容上，直到在轉變至保持狀態時控制終 端435被放電。In a preferred embodiment, the sampling period is long enough for the input signal to settle and to ensure that the input signal is properly acquired. However, as will be appreciated from the above, the sampling switch 410 can remain open as long as the hold signal thus indicates the sampling switch 410. In such a particular embodiment, the duration of the sampling period can be controlled by a hold signal. In other embodiments, the sampling state can be maintained by a voltage that is stored on a particular capacitor associated with switch 410 until the end of control when transitioning to the hold state Terminal 435 is discharged.

如圖所示，較佳的是輸入終端不被連接至任何負責在取樣模式期間切換取樣開關410開啟與關閉的電路系統。如此，節點415處的輸入訊號不經歷任何與電路400中電路系統相關聯的不良的負載(除了與電容器420與開關410相關聯的負載以外)，藉以減少訊號失真。再者，取樣開關410的通道阻抗被由預定電荷Q_P 維持為實質上固定，允許輸入訊號實質上不被改變而傳送，進一步增進了電容器420所獲得取樣的品質。As shown, it is preferred that the input terminal is not connected to any circuitry responsible for switching the sampling switch 410 on and off during the sampling mode. As such, the input signal at node 415 does not experience any bad load associated with circuitry in circuit 400 (other than the load associated with capacitor 420 and switch 410), thereby reducing signal distortion. Moreover, the channel impedance sampling switch 410 is maintained by the charge Q _P to a predetermined substantially constant, allowing the input signal is not changed substantially transmitted, to further enhance the quality of the capacitor 420 to obtain samples.

在已獲得取樣之後，電路400可從取樣模式切換至保持模式。達成此舉的一種方式為將施加於指令節點430的保持訊號反相。此可涉及將保持訊號從邏輯高改變成邏輯低(或相反)，取決於電路400中電路部件的特定實施。Circuit 400 can be switched from the sampling mode to the hold mode after sampling has been obtained. One way to achieve this is to invert the hold signal applied to the instruction node 430. This may involve changing the hold signal from a logic high to a logic low (or vice versa) depending on the particular implementation of the circuit components in circuit 400.

選擇一種慣例以供圖示說明目的，假定保持訊號從邏輯低(取樣模式)改變成邏輯高(保持模式)。當此發生時，開關410被關閉，而使輸入訊號與電容器420斷開。當此發生時，控制電路425可將開關410的閘極放電，並且控制電路425可將閘極連接至地或其他適合的關閉狀態控制位準。此將開關410關閉，將開關410與在節點415的輸入訊號斷開，且因此將電容器420與輸入訊號隔離，將電路400置於保持模式中。A convention is chosen for illustrative purposes, assuming that the hold signal changes from a logic low (sampling mode) to a logic high (hold mode). When this occurs, switch 410 is turned off and the input signal is disconnected from capacitor 420. When this occurs, control circuit 425 can discharge the gate of switch 410, and control circuit 425 can connect the gate to ground or other suitable off state control level. This turns off switch 410, disconnecting switch 410 from the input signal at node 415, and thus isolating capacitor 420 from the input signal, placing circuit 400 in the hold mode.

現將參照第5圖，第5圖圖示根據本發明原則所建置的一種可能的實施500。電路500在一些方面類似於第4 圖所說明的電路，且電路500一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路500包含儲存電容器520(第4圖中的電容器420)、輸入終端515(第4圖中的輸入終端415)、取樣開關510(第4圖中的取樣開關410)、控制電路525(第4圖中的控制電路425)以及指令節點530(第4圖中的指令節點430)。Reference will now be made to Fig. 5, which illustrates one possible implementation 500 constructed in accordance with the principles of the present invention. Circuit 500 is similar in some respects to the fourth The circuits illustrated in the figures, and circuit 500 generally comprise components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, the circuit 500 includes a storage capacitor 520 (capacitor 420 in FIG. 4), an input terminal 515 (input terminal 415 in FIG. 4), a sampling switch 510 (sampling switch 410 in FIG. 4), and a control circuit 525 ( Control circuit 425) in Fig. 4 and instruction node 530 (instruction node 430 in Fig. 4).

如圖所示，若必要，電路500可包含如下文所討論的電荷幫浦(charge pump)570。控制電路525可包含經控制電流源554、開關528與時序電路551。在此實例中，開關528可為MOSFET電晶體、傳輸閘或其他適合的半導體裝置。亦圖示於此具體實施例中的是，時序電路551可為單擊(one-shot)電路，然而可依所需使用其他適合的時序電路，諸如閂鎖器、正反器、比較器、暫態網路、時脈，或以上之組合。時序電路551在時序電路551的控制輸入處由高至低的訊號轉變觸發。As shown, circuit 500 can include a charge pump 570 as discussed below, if desired. Control circuit 525 can include controlled current source 554, switch 528, and timing circuit 551. In this example, switch 528 can be a MOSFET transistor, a transfer gate, or other suitable semiconductor device. Also illustrated in this particular embodiment, the timing circuit 551 can be a one-shot circuit, although other suitable timing circuits can be used as desired, such as latches, flip-flops, comparators, Transient network, clock, or a combination of the above. The timing circuit 551 is triggered by a high to low signal transition at the control input of the timing circuit 551.

類似於第4圖的電路400，電路500可操作於至少兩個模式：取樣模式與保持模式。因此，電路500可依下文所述操作。邏輯高訊號可被施加至指令節點530。此訊號開啟開關528，因此將控制節點535放電並關閉開關510。此舉將在節點515的輸入訊號與電容器520斷開，隔離電容器520並將電路500置於保持狀態中。Similar to circuit 400 of FIG. 4, circuit 500 is operable in at least two modes: a sampling mode and a hold mode. Thus, circuit 500 can operate as described below. A logic high signal can be applied to the instruction node 530. This signal turns on switch 528, thus discharging control node 535 and turning off switch 510. This disconnects the input signal at node 515 from capacitor 520, isolating capacitor 520 and placing circuit 500 in a hold state.

為了從保持狀態轉變成取樣狀態，在指令節點530處的保持訊號被從邏輯高切換成邏輯低。此舉關閉開關 528，並且此舉使單擊電路551產生時序脈衝(例如於在觸發輸入處偵測到邏輯高至低轉變時，所產生之相當短持續時間的邏輯高或邏輯低訊號)，將電流源554開啟持續時間T_p 。在開啟時，經控制電流源554產生輸出電流I_p 。In order to transition from the hold state to the sample state, the hold signal at instruction node 530 is switched from logic high to logic low. This closes switch 528 and causes click circuit 551 to generate a timing pulse (e.g., a logic high or logic low signal of a relatively short duration generated when a logic high to low transition is detected at the trigger input), the current source 554 on-duration T _p. When turned on, the output current _{Ip is} generated by the control current source 554.

因此，預定電荷Q_p =I_p ^＊ T_p 被施加至開關510的閘極。此舉使在閘極處的電壓上升，傾向於開啟開關510，將電路500從保持狀態轉變成取樣狀態。Therefore, the predetermined charge Q _p =I _p ^* T _p is applied to the gate of the switch 510. This causes the voltage at the gate to rise, tending to turn on the switch 510, transitioning the circuit 500 from the hold state to the sample state.

如已知於本發明領域，在開關510閘極處的電壓上升至超過開關510的開啟臨限值時(相對於通道電位)，與MOSFET開關510相關聯的閘極對通道電容511(以虛線繪製的電容器)開始產生。一般而言，在操作於此區域的同時，MOSFET開關510的閘極作為非線性電容器，同時閘極對通道電容511隨著閘極與通道之間的電壓差增加而提昇。電容512(代表亦可存在於控制節點535處的寄生電容)吸收由電流源554提供的電荷的一些，此舉不良地使開關510的阻抗變化。As is known in the art, when the voltage at the gate of switch 510 rises above the turn-on threshold of switch 510 (relative to the channel potential), the gate-to-channel capacitance 511 associated with MOSFET switch 510 (with a dashed line) The drawn capacitor) begins to produce. In general, while operating in this region, the gate of MOSFET switch 510 acts as a non-linear capacitor, while the gate-to-channel capacitance 511 increases as the voltage difference between the gate and the channel increases. Capacitor 512 (representing the parasitic capacitance that may also be present at control node 535) absorbs some of the charge provided by current source 554, which poorly changes the impedance of switch 510.

然而，可基於諸如製造材料與製程類型、大小與形狀等等的因素，來決定與MOSFET開關510相關聯的閘極對通道電容511的量，並依此選擇時間週期T_p 或輸出電流I_p 的值(或兩者)。因此，MOSFET開關510完全開啟所需的電荷量，可被計算為在開關510閘極與源極之間產生完全開啟電壓V_ON 所必需的電荷值Q_p 。在一些具體實施例中，亦可在計算中包含任何寄生電容512以獲 得非常精確的V_ON 值。在特定的實施中，寄生值可基於一些因素而變化，該等因素包含電路佈局、材料特異性以及任何輔助電容性接面。However, based on the manufacturing materials and processes, such as the type, size and shape and the like factors, determines the MOSFET switch 510 and the gate electrode of the amount associated with the channel capacitor 511, and so select the time period T _p or output current I _p Value (or both). Thus, the MOSFET switch 510 is fully turned on the amount of charge needed can be calculated as the switch 510 and the gate electrode between the source electrode produced entirely on voltage V _ON required charge value Q _p. In some embodiments, any parasitic capacitance 512 can also be included in the calculation to obtain a very accurate V _ON value. In particular implementations, the parasitic values may vary based on factors including circuit layout, material specificity, and any auxiliary capacitive junctions.

藉由在開啟MOSFET開關510時提供適當的電荷量以控制路徑535，係可能大量地減少或消除在電路500於取樣模式中的同時所遭遇到之與變化開關阻抗相關聯的訊號失真。可藉由確保在MOSFET開關510閘極與源極間產生電壓V_ON 時，由電流源554所傳遞的電荷量實質上等於由閘極對通道電容511(稱為Q_p )與寄生電容512所吸收的電荷，來達成此目標。By providing an appropriate amount of charge to control path 535 when MOSFET switch 510 is turned on, it is possible to substantially reduce or eliminate signal distortion associated with varying switch impedance encountered while circuit 500 is in the sampling mode. Can ensure by switch 510 when the MOSFET and the gate-source voltage generating V _ON, the amount of charge passed by the current source 554 is substantially equal to the gate capacitance of the channel 511 (referred to as Q _p) and a parasitic capacitance 512 The absorbed charge is used to achieve this goal.

因此，可達成此的一種方式為決定由電流源554(I_p )產生的瞬時電流的量，並將彼值乘上由時序電路551產生之脈衝的時間週期(T_p )，以獲得總和電荷值(Q_p )。一旦已獲得電荷值，則可調整脈衝的時間週期(T_p )或電流源554的值(或兩者)，來確保Q_p 被施加至MOSFET開關510的閘極，以在取樣狀態期間獲得實質上固定的開關阻抗。此調整可在設計時考慮所需的開關510性質與寄生電容512值來做成，或此調整可在製造時做成(使用已知的修整技術)，或此調整可在電路500作業期間內做成(使用已知的追蹤技術，諸如複製及/或比例控制電路監視器)，或由任何以上方式的結合來做成。例如，時序電路551可藉由監視裝置(實質上複製了開關510及/或控制終端585的性質)的閘極電容與寄生電容，來調整時序脈衝持續期間T_p 。Thus, this can be achieved is a way to determine the amount of instantaneous current generated by current source 554 (I _p), and the value multiplied by each other on the time period generated by the timing circuit 551 of the pulse (T _p), to obtain a sum of the charges Value (Q _p ). Once the charge value has been obtained, the pulse time period may be adjusted (T _p) or a value of a current source 554 (or both), to ensure that the Q _p is applied to the gate electrode of MOSFET switch 510, to the substance obtained during the sampling state Fixed switch impedance. This adjustment can be made by considering the desired nature of the switch 510 and the value of the parasitic capacitance 512, or this adjustment can be made at the time of manufacture (using known trimming techniques), or this adjustment can be made during the operation of the circuit 500. It is made (using known tracking techniques, such as copy and/or proportional control circuit monitors), or by a combination of any of the above. For example, the timing circuit 551 may be monitored by means (switch 510 substantially replicates the properties and / or the control terminal 585) of the gate capacitance and the parasitic capacitance to adjust the timing pulse duration T _p.

一般而言，時常需盡量快地將Q_P 施加至開關511，以加速存在輸入節點515處之輸入訊號的獲取。此舉可被完成以(例如)增進電路500的取樣率。因此在一些具體實施例中，可需配置電流源554以提供適當位準的電流，而相當快地(或盡量快地)獲得實質上固定的阻抗。例如，如已知於本發明領域中，可藉由監視裝置(實質上複製開關510及/或控制終端585之性質)的閘極電容與寄生電容，來選擇由電流源554產生的電流。In general, it is often desirable to apply Q _P to switch 511 as quickly as possible to speed up the acquisition of input signals present at input node 515. This can be done, for example, to increase the sampling rate of circuit 500. Thus, in some embodiments, current source 554 may need to be configured to provide a suitable level of current while achieving a substantially fixed impedance relatively quickly (or as quickly as possible). For example, as is known in the art, the current generated by current source 554 can be selected by the gate capacitance and parasitic capacitance of the monitoring device (which essentially replicates the nature of switch 510 and/or control terminal 585).

一旦電流源554關閉，給予控制終端535的電壓將相對於輸入訊號保持為實質上固定(直到保持訊號再次切換，而所儲存的能量透過開關528散逸)。Once current source 554 is turned off, the voltage applied to control terminal 535 will remain substantially fixed relative to the input signal (until the hold signal is switched again, and the stored energy is dissipated through switch 528).

再者，在一些情況中，在取樣週期期間內施加至電晶體510閘極的相關聯電壓，可需要大於軌電壓V_DD ，以容納較寬範圍的輸入訊號。可完成此的一種方式為採用電荷幫浦或其他已知於本發明領域中的電壓倍增電路，以將電路500中的一些能量儲存元件充電。例如，如圖示於第5圖，電荷幫浦570可耦合至電流源528。在一些具體實施例中，電荷幫浦570(可包含充電至適合電壓，並以循序的串聯與並聯配置來連接而提升總和電壓的一或多個電容器)可耦合至指令節點530。因此，在來自時序電路551的脈衝被電流源554接收時，電流源554可開啟，建立通過電流源554(及/或電荷幫浦570)的電流路徑，電流路徑將所儲存的能量傳導至開關510閘極，使開關510開啟。此設置允許開關510快速地被 開啟，且對於廣泛的輸入訊號位準範圍具有足夠的能量以將MOSFET開關511的阻抗維持在所需位準(例如實質上固定)。Moreover, in some cases, the associated voltage applied to the gate of transistor 510 during the sampling period may need to be greater than rail voltage V _DD to accommodate a wider range of input signals. One way in which this can be accomplished is to employ a charge pump or other voltage multiplying circuit known in the art to charge some of the energy storage elements in circuit 500. For example, as shown in FIG. 5, charge pump 570 can be coupled to current source 528. In some embodiments, charge pump 570 (which may include one or more capacitors that are charged to a suitable voltage and connected in a sequential series and parallel configuration to boost the sum voltage) may be coupled to instruction node 530. Thus, when a pulse from timing circuit 551 is received by current source 554, current source 554 can be turned on, establishing a current path through current source 554 (and/or charge pump 570) that conducts the stored energy to the switch. The 510 gate opens the switch 510. This setting allows switch 510 to be turned on quickly and has sufficient energy for a wide range of input signal levels to maintain the impedance of MOSFET switch 511 at a desired level (e.g., substantially fixed).

在此實施內，在電荷幫浦570中的能量儲存裝置的大小與容量可被計算，以提供至少適當的Q_P 值以實質上瞬時地完全開啟MOSFET開關510，而使開關阻抗被維持為實質上固定，在一些具體實施例中開關阻抗可為最小開關阻抗，增進取樣電路500的精確度。Within this implementation, the size and capacity of the energy storage device in charge pump 570 can be calculated to provide at least an appropriate Q _P value to substantially fully turn MOSFET switch 510 on, while maintaining the switch impedance substantially The upper fixed, in some embodiments, the switching impedance can be the minimum switching impedance, improving the accuracy of the sampling circuit 500.

將瞭解到，取決於所需輸入訊號範圍的量值、可用電力供應VDD的量值、所利用的半導體裝置的特性、所需的取樣頻率與取樣安定時間(與其他類似的因素)，電荷幫浦570可或不可必需存在於取樣電路500中。再者，在存在時，電荷幫浦570可持續地操作，獨立於取樣電路500的狀態(取樣或保持)或依所需操作，如由保持指令訊號530導引(且由第5圖的虛線連結指示)。It will be appreciated that depending on the magnitude of the desired input signal range, the amount of available power supply VDD, the characteristics of the semiconductor device utilized, the required sampling frequency, and the sampling stabilization time (and other similar factors), the charge helps The 570 may or may not be present in the sampling circuit 500. Again, when present, the charge pump 570 can operate continuously, independent of the state of the sampling circuit 500 (sampling or holding) or as desired, as guided by the hold command signal 530 (and by the dashed line of Figure 5) Link instructions).

現參照第6圖，圖示根據本發明原則所建置的另一可能的特定實施600。類似電路400，電路600亦在一些方面類似於第4圖所說明的電路，並且電路600一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路600包含指令節點630(第4圖中的指令節點430)、控制節點635(第4圖中的控制節點435)、取樣開關610(第4圖中的取樣開關410)、控制電路625(第4圖中的控制電路425)以及電容器620(第4圖中的電容器420)等等。Referring now to Figure 6, another possible particular implementation 600 constructed in accordance with the principles of the present invention is illustrated. Like circuit 400, circuit 600 is similar in some respects to the circuit illustrated in FIG. 4, and circuit 600 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, circuit 600 includes an instruction node 630 (instruction node 430 in FIG. 4), a control node 635 (control node 435 in FIG. 4), a sampling switch 610 (sampling switch 410 in FIG. 4), and a control circuit 625. (Control circuit 425 in Fig. 4) and capacitor 620 (capacitor 420 in Fig. 4) and the like.

如圖所示，控制電路625可包含電荷轉移開關631、放電開關628與電荷產生器650。額外的裝置629與632各別限制跨開關628與631的電壓且額外的裝置629與632可或不可被包含，取決於該等裝置(628與631)的操作範圍。電荷產生器電路650可包含電晶體656、657、658與659、反相器652以及時序電路651。在此實例中，時序電路651可為單擊電路，但可依所需使用其他已知的電路，諸如正反器、邏輯閘、電晶體等等來實施下文所說明的時序順序。時序電路651由在時序電路651控制輸入處的高至低訊號轉變觸發。可由另一電源或(如圖示於第6圖中)由電荷幫浦670來提供呈現在軌671上的電壓位準V_CP ，電荷幫浦670的功能性類似於第5圖的電荷幫浦570。As shown, control circuit 625 can include charge transfer switch 631, discharge switch 628, and charge generator 650. Additional devices 629 and 632 individually limit the voltage across switches 628 and 631 and additional devices 629 and 632 may or may not be included, depending on the operating range of the devices (628 and 631). The charge generator circuit 650 can include transistors 656, 657, 658, and 659, an inverter 652, and a timing circuit 651. In this example, the timing circuit 651 can be a click circuit, but other known circuits, such as flip-flops, logic gates, transistors, etc., can be used as needed to implement the timing sequence described below. The timing circuit 651 is triggered by a high to low signal transition at the control input of the timing circuit 651. The voltage level V _CP presented on rail 671 may be provided by charge pump 670 by another power source or (as illustrated in Figure 6), the functionality of charge pump 670 being similar to the charge pump of Figure 5 570.

如上文所述，電路600操作於至少兩個模式：取樣模式與保持模式，並且電路600可操作如下文所述。可施加邏輯高訊號至指令節點630的輸入處。此訊號較佳地具有足夠的量值以開啟電晶體628，而將控制節點635與開關610的閘極放電，關閉開關610。此將節點615的輸入訊號與電容器620斷開，隔離電容器620並將電路600置於保持狀態中。As described above, circuit 600 operates in at least two modes: a sampling mode and a hold mode, and circuit 600 is operable as described below. A logic high signal can be applied to the input of the instruction node 630. This signal preferably has a sufficient magnitude to turn on transistor 628, discharge control node 635 and the gate of switch 610, and turn off switch 610. This disconnects the input signal of node 615 from capacitor 620, isolating capacitor 620 and placing circuit 600 in a hold state.

單擊電路651在保持模式中的輸出為邏輯低(接近地)，此輸出使反相器652的輸出為邏輯高(接近VDD)，將開關657的閘極驅動為高(透過連接成電容器的電晶體659)。此舉開啟開關657，允許連接成電容器的電晶 體656被充電到接近軌671的電位V_CP 。跨裝置631的汲極對閘極電壓為接近零，將開關631維持在關閉狀態中。The output of the click circuit 651 in the hold mode is logic low (near ground), this output causes the output of the inverter 652 to be logic high (near VDD), and the gate of the switch 657 is driven high (through the connection to the capacitor) Transistor 659). This opens switch 657, allowing the transistor 656 connected to the capacitor to be charged to the potential V _CP near the rail 671. The gate-to-gate voltage across device 631 is near zero, maintaining switch 631 in the off state.

為了從保持狀態轉變成取樣狀態，在指令節點630處的保持訊號可被從邏輯高切換至邏輯低。此舉關閉電晶體628，並且此舉使時序電路651產生短邏輯高脈衝(例如於在觸發輸入處偵測到邏輯高至低轉變時，所產生之具有相當短持續時間的邏輯高訊號)，在反相器652輸出處產生短邏輯低脈衝。此允許連接成電容器的電晶體656透過開關631與電晶體632放電，因此將電晶體656所儲存的電荷經由控制終端635提供給開關610，開啟開關610。In order to transition from the hold state to the sample state, the hold signal at instruction node 630 can be switched from logic high to logic low. This turns off transistor 628, and this causes timing circuit 651 to generate a short logic high pulse (e.g., a logic high signal having a relatively short duration produced when a logic high to low transition is detected at the trigger input), A short logic low pulse is generated at the output of inverter 652. This allows the transistor 656 connected as a capacitor to discharge through the switch 631 and the transistor 632, thus supplying the charge stored by the transistor 656 to the switch 610 via the control terminal 635, turning on the switch 610.

提供給開關610的電荷量，可由電路設計者藉由控制連接成電容器的電晶體656與開關610的大小比例來指定。例如，可需提供經計算的電荷值Q_P 給開關610的閘極，電荷值Q_P 考慮開關610的閘極對通道電容(在第6圖中圖示為電容器611)與任何寄生電容(在第6圖中圖示為電容器612)，該寄生電容由從電容器656行進至開關610閘極的電荷所遭遇。在傳送給控制終端635時，電荷Q_P 產生自取樣開關610閘極至源極的開啟電壓V_ON ，因此設定取樣開關610的取樣模式阻抗。一旦所需提供給開關610的Q_P 值被計算出，連接成電容器的裝置656的大小可經選定以提供Q_P ，而使開關610的阻抗被最小化並被維持為實質上固定。例如，裝置656的實 體實施可複製裝置610、指令節點635以及相關聯的寄生電路元件的實體實施(或與該實體實施成比例)。The amount of charge provided to switch 610 can be specified by the circuit designer by controlling the size ratio of transistor 656 and switch 610 that are connected to the capacitor. For example, the calculated required charge value Q _P to the switching gate electrode 610, the charge switch 610 to consider the value of Q _P gate capacitance of the channel (in FIG. 6 is illustrated as a capacitor 611) and any parasitic capacitance (in Illustrated in FIG. 6 is capacitor 612), which is encountered by the charge traveling from capacitor 656 to the gate of switch 610. When transmitted to the control terminal 635, the charge Q _{P is} generated from the gate-to-source turn-on voltage V _{ON of the} sampling switch 610, thus setting the sampling mode impedance of the sampling switch 610. Once the desired value is supplied to the switch 610 Q _P is calculated, the size of the capacitor is connected to the apparatus 656 may be selected to provide a Q _P, the impedance of the switch 610 to be minimized and maintained substantially constant. For example, the entity of device 656 implements (or is proportional to) the entity of replicable device 610, instruction node 635, and associated parasitic circuit elements.

將瞭解到，雖然取樣電路600可使用將開關610阻抗最小化的Q_P 值，但可使用其他值以獲得所需之任何適合的實質上固定阻抗(無論是否被最小化)。由電路651所產生的時序脈衝應被選定為允許將所需的電荷Q_P 傳送至控制終端635。It will be appreciated, although the use of the sampling circuit 600 may switch Q _P value minimizing the impedance 610, but may be any other suitable value to obtain substantially the desired fixed impedance (whether is minimized). Timing pulse generated by the circuit 651 should be selected to allow the desired charge Q _P to the control terminal 635.

因為由連接成電容器之電晶體656所提供的電流脈衝的量值或持續期間(且代表電荷量值)不受輸入終端615處的電壓影響，取樣開關610的閘極將獲得閘極電荷，該閘極電荷實質上獨立於在輸入終端615處的電壓，而因此增進由電容器620所獲取之取樣的精確度。Because the magnitude or duration of the current pulse provided by the transistor 656 connected to the capacitor (and representing the magnitude of the charge) is not affected by the voltage at the input terminal 615, the gate of the sampling switch 610 will acquire the gate charge, which The gate charge is substantially independent of the voltage at input terminal 615, thereby increasing the accuracy of the samples taken by capacitor 620.

再者，在電流脈衝關閉時，在時序電路651脈衝的終端處，在取樣開關610閘極處的電壓相對於訊號路徑將保持實質上固定，並且該電壓將獨立於輸入電壓。因此，開關610被控制，而不需增加在取樣模式期間連接至敏感輸入終端的任何額外的電路系統。Again, at the end of the pulse of sequence circuit 651 when the current pulse is turned off, the voltage at the gate of sampling switch 610 will remain substantially fixed relative to the signal path, and the voltage will be independent of the input voltage. Thus, switch 610 is controlled without the need to add any additional circuitry connected to the sensitive input terminal during the sampling mode.

在電路600的一些實施中，相關聯於控制終端635的寄生電容612可使MOSFET 610的開啟阻抗輕微地變化，如對於施加至輸入節點610之輸入訊號的函數。此變化通常發生在MOSFET 610被開啟的當下。在控制終端635如需般安定於在輸入電壓(施加於輸入終端615)之上的電壓V_ON 處時，寄生電容612必需被充電至直接相依於輸入電壓的相同位準。因此，寄生電容612吸收 一小部分的電荷Q_P ，此小部分電荷隨著輸入電壓變化，而導致V_ON 的最終值變化。例如，若初始地在開啟MOSFET 610之前施加兩伏特的輸入訊號至輸入節點615(亦即MOSFET 610的源極)，則在MOSFET 610閘極處的電荷將被偏移兩伏特源極電位。此偏移改變MOSFET 610的開啟位準(藉由被寄生電容器612吸收的電荷量)，且因此此偏移改變MOSFET 610的阻抗，此舉可不佳地給予失真至任何被取樣的訊號。因為此偏移將如對輸入訊號之函數而變化，MOSFET 610的阻抗亦可相對於輸入訊號來變化。In some implementations of circuit 600, parasitic capacitance 612 associated with control terminal 635 can cause the turn-on impedance of MOSFET 610 to vary slightly, as a function of the input signal applied to input node 610. This change typically occurs when the MOSFET 610 is turned on. When the control terminal 635 is as stable as possible at the voltage V _ON above the input voltage (applied to the input terminal 615), the parasitic capacitance 612 must be charged to the same level directly dependent on the input voltage. Therefore, the parasitic capacitance 612 absorbs a small portion of the charge Q _P , which varies with the input voltage, resulting in a change in the final value of V _ON . For example, if a two volt input signal is initially applied to input node 615 (ie, the source of MOSFET 610) before MOSFET 610 is turned on, the charge at the gate of MOSFET 610 will be offset by two volts of source potential. This offset changes the turn-on level of MOSFET 610 (by the amount of charge absorbed by parasitic capacitor 612), and thus this offset changes the impedance of MOSFET 610, which can poorly impart distortion to any sampled signal. Because this offset will vary as a function of the input signal, the impedance of MOSFET 610 can also vary with respect to the input signal.

處理此問題的一種方式，為在透過開關631提供開啟電荷之前，提供預設閘極對源極初始化電壓給MOSFET 610(且隱含地提供給寄生電容器612)。此種初始化電壓可從輸入訊號導出，並且此種初始化電壓可在取樣模式開始時(但在訊號獲取之前，因此不影響獲取期間的輸入訊號)施加至MOSFET 610閘極。此允許MOSFET 610的閘極包含類似於(或相同於)隨後所取樣之訊號的電壓的初始化電壓，以完整或部分地偏移任何閘極對源極電壓差，並將瞬時阻抗變化最小化，藉以增進所取樣訊號的精確度。One way to address this problem is to provide a preset gate-to-source initialization voltage to MOSFET 610 (and implicitly to parasitic capacitor 612) prior to providing turn-on charge through switch 631. This initialization voltage can be derived from the input signal, and such initialization voltage can be applied to the MOSFET 610 gate at the beginning of the sampling mode (but before the signal acquisition, thus not affecting the input signal during acquisition). This allows the gate of MOSFET 610 to contain an initialization voltage similar to (or the same as) the subsequently sampled signal to completely or partially offset any gate-to-source voltage difference and minimize transient impedance variations, In order to improve the accuracy of the sampled signal.

第7圖圖示此種電路的一個較佳的具體實施例為電路700。電路700在許多方面類似於第6圖所說明的電路，並且電路700一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路700 包含控制電路725(第6圖中的控制電路625)、電荷產生器電路750(第6圖中的電荷產生器電路650)、取樣開關710(第6圖中的取樣開關610)與電容器720(第6圖中的電容器620)、電荷幫浦電路770(第6圖中的電荷幫浦電路670)等等。FIG. 7 illustrates a preferred embodiment of such a circuit as circuit 700. Circuitry 700 is similar in many respects to the circuitry illustrated in FIG. 6, and circuitry 700 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, circuit 700 A control circuit 725 (control circuit 625 in FIG. 6), a charge generator circuit 750 (charge generator circuit 650 in FIG. 6), a sampling switch 710 (sampling switch 610 in FIG. 6), and a capacitor 720 are included. Capacitor 620) in Fig. 6, charge pump circuit 770 (charge pump circuit 670 in Fig. 6), and the like.

然而，電路700進一步包含閘極初始化電晶體716與717，閘極初始化電晶體716與717由初始化控制電路726與初始化電荷產生器電路780控制(於下文詳細描述)。However, circuit 700 further includes gate initialization transistors 716 and 717, and gate initialization transistors 716 and 717 are controlled by initialization control circuit 726 and initialization charge generator circuit 780 (described in detail below).

如圖所示，控制電路725可包含電荷傳送開關731、放電開關728以及電荷產生器750。額外裝置729與732各別限制跨開關728與731的電壓，且額外裝置729與732可(或不可)被包含，取決於該等裝置(728與731)的操作範圍。電荷產生器電路750可包含電晶體756、757、758與759、反相器752與時序電路751。時序電路751係由低至高訊號轉變在時序電路751的控制輸入處被觸發。控制電路725與脈衝產生電路750的操作可相同於(或類似於)上文所說明的電路625與650。As shown, control circuit 725 can include a charge transfer switch 731, a discharge switch 728, and a charge generator 750. Additional devices 729 and 732 individually limit the voltage across switches 728 and 731, and additional devices 729 and 732 may (or may not) be included, depending on the operating range of the devices (728 and 731). Charge generator circuit 750 can include transistors 756, 757, 758, and 759, inverter 752, and timing circuit 751. The timing circuit 751 is triggered by the low to high signal transition at the control input of the timing circuit 751. The operation of control circuit 725 and pulse generation circuit 750 can be the same as (or similar to) circuits 625 and 650 described above.

電路700進一步包含初始化控制電路726與初始化電荷產生器電路780。如圖所示，初始化控制電路726可包含電荷傳送開關741、放電開關738與電荷產生器780。額外裝置739與742各別限制跨開關738與741的電壓，且額外裝置739與742可(或不可)被包含，取決於該等裝置(738與741)的操作範圍。初始化電荷 產生器電路780可包含電晶體787與788、耦合為電容器的電晶體786與789、反相器782以及時序電路781。時序電路781係由高至低訊號轉變在時序電路781的控制輸入處被觸發。電路726與780的操作可相同於(或類似於)上文所說明的電路725與750，除了電路726與780在不同的時間產生訊號以外(例如，電路725與750在取樣模式期間在輸入訊號正被取樣電容器720獲取時提供開啟訊號至MOSFET 710，而電路726與780在獲取輸入訊號之前提供初始化訊號給電晶體716與717，以將上文所說明的瞬時阻抗變化最小化或消除)。在一些具體實施例中，初始化訊號可被提供為如下文所述之取樣模式的起始部分，或者初始化訊號可作為替代地提供於保持模式期間。Circuitry 700 further includes an initialization control circuit 726 and an initialization charge generator circuit 780. As shown, the initialization control circuit 726 can include a charge transfer switch 741, a discharge switch 738, and a charge generator 780. Additional devices 739 and 742 individually limit the voltage across switches 738 and 741, and additional devices 739 and 742 may (or may not) be included, depending on the operating range of the devices (738 and 741). Initialization charge Generator circuit 780 can include transistors 787 and 788, transistors 786 and 789 coupled as capacitors, inverter 782, and timing circuit 781. The timing circuit 781 is triggered by a high to low signal transition at the control input of the timing circuit 781. The operations of circuits 726 and 780 can be the same as (or similar to) circuits 725 and 750 described above, except that circuits 726 and 780 generate signals at different times (eg, circuits 725 and 750 are input signals during the sampling mode). The enable signal is being supplied to the MOSFET 710 while being taken by the sampling capacitor 720, and the circuits 726 and 780 provide initialization signals to the transistors 716 and 717 to minimize or eliminate the transient impedance variations described above before acquiring the input signal. In some embodiments, the initialization signal can be provided as the beginning of the sampling mode as described below, or the initialization signal can alternatively be provided during the hold mode.

如上文所述，電路700操作於至少兩個模式：取樣模式與保持模式，並且電路700可操作如下文。可施加邏輯高訊號至指令節點730的輸入。此訊號較佳地具有足夠的量值以開啟電晶體728，電晶體728將控制節點735與開關710的閘極放電，關閉開關710。此將節點715處的輸入訊號與電容器720斷開，隔離電容器720，並將電路700置於保持狀態中。As described above, circuit 700 operates in at least two modes: a sampling mode and a hold mode, and circuit 700 is operable as follows. A logic high signal can be applied to the input of the instruction node 730. This signal preferably has a magnitude sufficient to turn on transistor 728, which discharges control node 735 and the gate of switch 710, turning off switch 710. This disconnects the input signal at node 715 from capacitor 720, isolates capacitor 720, and places circuit 700 in a hold state.

單擊電路781在保持模式中的輸出為邏輯低(接近地)，邏輯低輸出使反相器782的輸出為邏輯高(接近VDD)，將開關787的閘極驅動為高(透過連接成電容器的電晶體789)。此開啟電晶體787，允許連接成電容器 的電晶體786與電晶體766的源極被充電至軌771的電位V_CP (軌771的電位V_CP 可為由電荷幫浦770產生的提昇電壓)。Clicking on the output of circuit 781 in the hold mode is logic low (near ground), the logic low output causes the output of inverter 782 to be logic high (near VDD), and the gate of switch 787 is driven high (through the connection into a capacitor) The transistor 789). This transistor 787 is turned on, allowing the source of the transistor is connected to a capacitor 786 and transistor 766 of electrode 771 is charged to the potential V _CP rail (rail voltage V _CP 771 may be a charge pump 770 to help lift the generated voltage).

類似地，在電路750中，單擊751在保持模式中的輸出為邏輯低(接近地)，邏輯低輸出使反相器752的輸出為邏輯高(接近VDD)，將開關757的閘極驅動為高(透過連接成電容器的電晶體759)。此開啟開關757，允許連接成電容器的電晶體756被充電至軌771的電位V_CP (為由電荷幫浦770產生的提昇電壓)。由反相器742在保持模式中產生的邏輯高訊號開啟開關738，將初始化電晶體716與717的閘極放電並關閉電晶體716與717。Similarly, in circuit 750, the output of 751 in the hold mode is logic low (near ground), the low logic output causes the output of inverter 752 to be logic high (near VDD), and the gate of switch 757 is driven. It is high (through the transistor 759 connected into a capacitor). This turn-on switch 757 allows the transistor 756 connected to the capacitor to be charged to the potential V _{CP of the} rail 771 (which is the boost voltage generated by the charge pump 770). The logic high signal-on switch 738 generated by the inverter 742 in the hold mode discharges the gates of the initialization transistors 716 and 717 and turns off the transistors 716 and 717.

在電路700從保持狀態轉變至取樣狀態時，在指令節點730處的保持訊號可從邏輯高切換成邏輯低。此舉關閉電晶體728，並且此舉觸發初始化控制電路726於取樣狀態的初始部分中。此使時序電路781產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯高至低轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝使反相器782輸出處產生短邏輯低脈衝。此允許連接成電容器的電晶體786透過開關741與電晶體742放電，因此將電晶體786所儲存的電荷提供給初始化電晶體716與717的閘極，並開啟電晶體716與717。所以，MOSFET 710的閘極被充電至追蹤節點715處輸入訊號的值。初始化裝置716與717的阻抗可由選擇該初始化 裝置716與717與耦合成電容器的裝置786之間的比例來控制。The hold signal at instruction node 730 can be switched from logic high to logic low as circuit 700 transitions from the hold state to the sample state. This closes the transistor 728 and this triggers the initialization control circuit 726 in the initial portion of the sampling state. This causes the timing circuit 781 to generate a short logic high pulse (e.g., a logic high signal having a relatively short duration generated when a logic high to low transition at the trigger input is detected), and a short logic high pulse causes the inverter 782 A short logic low pulse is generated at the output. This allows the transistor 786 connected as a capacitor to discharge through the switch 741 and the transistor 742, thus providing the charge stored by the transistor 786 to the gates of the initialization transistors 716 and 717, and turning on the transistors 716 and 717. Therefore, the gate of MOSFET 710 is charged to the value of the input signal at tracking node 715. The impedance of the initialization devices 716 and 717 can be selected by the initialization The ratio between devices 716 and 717 and device 786 coupled into a capacitor is controlled.

在預定時間週期之後，單擊781的輸出返回邏輯低並開啟電晶體738(透過反相器782)。此舉將初始化電晶體716與717的閘極放電，並關閉電晶體716與717，但此舉維持MOSFET 710閘極處的初始化電荷。After a predetermined period of time, the output of 781 returns to logic low and turns on transistor 738 (via inverter 782). This will initialize the gate discharge of transistors 716 and 717 and turn off transistors 716 and 717, but this maintains the initial charge at the gate of MOSFET 710.

因此，在訊號獲取程序中的此時刻，MOSFET 710的閘極包含初始化電荷，初始化電荷部分地或完整地偏移任何閘極對源極電壓差，將任何瞬時阻抗變化最小化(或實質上消除)，藉以增進所獲取訊號的精確度。Thus, at this point in the signal acquisition procedure, the gate of MOSFET 710 contains an initial charge that partially or completely offsets any gate-to-source voltage difference, minimizing (or substantially eliminating) any transient impedance variations. ) to improve the accuracy of the signals obtained.

在完成初始化電路726作業時，反相器782的輸出返回邏輯高狀態，對電路751產生上升邊緣觸發輸入，指示單擊電路751產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯低至高轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝在反相器752輸出處產生短邏輯低脈衝。此允許連接成電容器的電晶體756透過開關731與電晶體732放電，因此將電晶體756所儲存的電荷經由路徑735提供給開關710(除了已提供的初始化電荷之外)，因此開啟開關710並允許電容器720獲取輸入訊號。Upon completion of the initialization circuit 726 operation, the output of inverter 782 returns to a logic high state, generating a rising edge trigger input to circuit 751, indicating that click circuit 751 generates a short logic high pulse (eg, logic detected at the trigger input) A low logic high pulse produces a short logic low pulse at the output of inverter 752, which occurs during a low to high transition with a relatively short duration of logic high signal. This allows the transistor 756 connected as a capacitor to discharge through the switch 731 and the transistor 732, thus providing the charge stored by the transistor 756 to the switch 710 via path 735 (in addition to the initial charge provided), thus turning on the switch 710 and Capacitor 720 is allowed to acquire an input signal.

連接成電容器的裝置756的大小，可連同於裝置710的大小來選擇，以建立在取樣狀態中所需的取樣開關阻抗。再者，如已知於本發明領域，裝置756的實體實施可複製裝置710、指令節點735以及相關聯的寄生電路 元件的實體實施(或與該實體實施成比例)，以供甚至較高層級的阻抗控制與追蹤。The size of the device 756 connected to the capacitor can be selected along with the size of the device 710 to establish the desired sampling switch impedance in the sampling state. Moreover, as is known in the art, the entity of device 756 implements replicable device 710, instruction node 735, and associated parasitic circuitry. The entity implementation of the component (or proportional to the entity implementation) for even higher level impedance control and tracking.

此設置允許電路700補償相關於瞬時閘極對源極差的阻抗變化。再者，因為在節點715處的輸入訊號在訊號獲取期間內未被加載(例如驅動開關710)，在訊號取樣期間內的訊號失真被進一步減少。This setting allows circuit 700 to compensate for impedance variations associated with the instantaneous gate to source difference. Moreover, since the input signal at node 715 is not loaded during the signal acquisition period (e.g., drive switch 710), signal distortion during signal sampling is further reduced.

第8圖圖示電路700的另一具體實施例為電路800。此具體實施例藉由提供允許流動預定時間量的預定電流而產生預定電荷量，來產生所需的電荷量。電路800在許多方面類似於第7圖所說明的電路，並且電路800一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路800包含控制電路825(第7圖中的控制電路725)、電荷產生器電路850(第7圖中的電荷產生器電路750)、初始化控制電路826(第7圖中的初始化控制電路726)、初始化電荷產生器電路880(第7圖中的初始化脈衝產生電路780)、取樣開關810(第7圖中的取樣開關710)、閘極初始化電晶體816與817(第7圖中的閘極初始化電晶體716與717)、取樣電容器820(第7圖中的取樣電容器720)、電荷幫浦電路870(第7圖中的電荷幫浦電路770)等等。FIG. 8 illustrates another embodiment of circuit 700 as circuit 800. This particular embodiment produces a desired amount of charge by providing a predetermined amount of current that is allowed to flow for a predetermined amount of time. Circuit 800 is similar in many respects to the circuit illustrated in Figure 7, and circuit 800 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, the circuit 800 includes a control circuit 825 (control circuit 725 in FIG. 7), a charge generator circuit 850 (charge generator circuit 750 in FIG. 7), and an initialization control circuit 826 (the initialization control circuit in FIG. 7). 726), initialize charge generator circuit 880 (initialization pulse generation circuit 780 in FIG. 7), sampling switch 810 (sampling switch 710 in FIG. 7), gate initialization transistors 816 and 817 (in FIG. 7 The gate initializes the transistors 716 and 717), the sampling capacitor 820 (the sampling capacitor 720 in FIG. 7), the charge pump circuit 870 (the charge pump circuit 770 in FIG. 7), and the like.

如圖所示，控制電路825可包含電流鏡電晶體833與853，以及放電開關828。額外裝置829與832各別限制跨開關828與電流鏡裝置833的電壓，且額外裝置829與832可或不可被包含，取決於該等裝置(828與833) 的操作範圍。電荷產生器電路850可包含經控制電流源，經控制電流源包含MOSFET電晶體854與電阻器855與時序電路851。時序電路851係由在時序電路851控制輸入處的低至高訊號轉變來觸發。初始化控制電路826可包含電流鏡電晶體843與883以及放電開關838。額外裝置839與842各別限制跨開關838與電流鏡裝置843的電壓，且額外裝置839與842可或不可被包含，取決於該等裝置(838與843)的操作範圍。電荷產生器電路880可包含經控制電流源，經控制電流源包含MOSFET電晶體884與電阻器885、時序電路881以及反相器882。時序電路881係由在時序電路881控制輸入處的高至低訊號轉變來觸發。控制電路825與初始化控制電路826的操作可相同於(或類似於)上文所說明的電路725與726。As shown, control circuit 825 can include current mirror transistors 833 and 853, as well as discharge switch 828. Additional devices 829 and 832 individually limit the voltage across switch 828 and current mirror device 833, and additional devices 829 and 832 may or may not be included, depending on the devices (828 and 833) The scope of operation. The charge generator circuit 850 can include a controlled current source including a MOSFET transistor 854 and a resistor 855 and a timing circuit 851. The timing circuit 851 is triggered by a low to high signal transition at the control input of the timing circuit 851. Initialization control circuit 826 can include current mirror transistors 843 and 883 and discharge switch 838. Additional devices 839 and 842 each limit the voltage across switch 838 and current mirror device 843, and additional devices 839 and 842 may or may not be included, depending on the operating range of the devices (838 and 843). The charge generator circuit 880 can include a controlled current source comprising a MOSFET transistor 884 and a resistor 885, a timing circuit 881, and an inverter 882. The timing circuit 881 is triggered by a high to low signal transition at the control input of the timing circuit 881. The operation of control circuit 825 and initialization control circuit 826 may be the same as (or similar to) circuits 725 and 726 described above.

然而，電路800與電路700不同之處在於，電荷產生器電路850與初始化電荷產生器電路880將具有預定持續期間的電流脈衝作為電荷傳遞給電晶體810、816以及817，而非來自電容器所儲存能量的放電。可藉由選定由電流源所提供之電流的量值，或由時序電路所產生的脈衝的寬度，或同時選定以上兩者，來界定所傳遞的電荷量(考量類似於先前連同第5圖電路500所說明者)。如上文所述，電路800可操作於至少兩個模式中：取樣模式與保持模式。However, circuit 800 differs from circuit 700 in that charge generator circuit 850 and initialization charge generator circuit 880 pass current pulses having a predetermined duration as charge to transistors 810, 816, and 817 rather than from capacitors. Discharge. The amount of charge transferred can be defined by selecting the magnitude of the current provided by the current source, or the width of the pulse generated by the sequential circuit, or both, (the considerations are similar to those previously described in conjunction with Figure 5 500 instructors). As described above, circuit 800 is operable in at least two modes: a sampling mode and a hold mode.

在作業中，可施加邏輯高訊號至指令節點830。此訊 號較佳地具有足夠的量值以開啟電晶體828，而將控制節點835與電晶體810閘極放電，以關閉開關810。此將於節點815的輸入訊號與電容器820斷開，隔離電容器820，並將電路800置於保持狀態中。In the job, a logic high signal can be applied to the instruction node 830. This news The number preferably has a sufficient magnitude to turn on transistor 828 and discharge control node 835 and transistor 810 to turn off switch 810. This will disconnect the input signal from node 815 from capacitor 820, isolate capacitor 820, and place circuit 800 in the hold state.

單擊電路881在保持模式中的輸出為邏輯低(接近地)，邏輯低輸出使反相器882的輸出為邏輯高(接近VDD)，將開關838的閘極驅動為高。此開啟電晶體838，將初始化電晶體816與817的閘極放電，而關閉初始化電晶體816與817。在保持模式中，時序電路881與851的邏輯低輸出各別將電流源884與854的閘極放電，防止任何電荷被各別傳遞給控制終端835與初始化控制終端836。The output of circuit 881 in hold mode is logic low (near ground), the logic low output causes the output of inverter 882 to be logic high (near VDD), and the gate of switch 838 is driven high. This turns on transistor 838, which discharges the gates of initialization transistors 816 and 817, and turns off initialization transistors 816 and 817. In the hold mode, the logic low outputs of the timing circuits 881 and 851 discharge the gates of the current sources 884 and 854, respectively, preventing any charge from being separately transferred to the control terminal 835 and the initialization control terminal 836.

在電路800從保持狀態轉變至取樣狀態時，在指令節點830處的保持訊號可從邏輯高切換成邏輯低。此舉關閉電晶體828並且此舉觸發初始化控制電路826於取樣狀態的初始部分中。此使時序電路881產生短邏輯高脈衝(例如，在於觸發輸入處偵測到邏輯高至低轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝在反相器882輸出處產生短邏輯低脈衝，短邏輯低脈衝關閉電晶體838。在時序電路881輸出處的邏輯高脈衝開啟電流源884，電流源884允許電流透過由裝置883與843組成的電流鏡流入初始化電晶體816與817的閘極。因此，預定的電荷量被傳遞至初始化控制終端836，開啟初始化電晶體816與817。因此，MOSFET 810的閘 極被充電至追蹤在節點815處之輸入訊號的值。The hold signal at instruction node 830 can be switched from logic high to logic low as circuit 800 transitions from the hold state to the sample state. This closes the transistor 828 and this triggers the initialization control circuit 826 in the initial portion of the sampling state. This causes the timing circuit 881 to generate a short logic high pulse (eg, a logic high signal having a relatively short duration generated when a logic high to low transition is detected at the trigger input), and a short logic high pulse is output at the inverter 882. A short logic low pulse is generated, and a short logic low pulse turns off the transistor 838. A logic high pulse at the output of the timing circuit 881 turns on the current source 884, which allows current to flow through the current mirrors comprised of devices 883 and 843 into the gates of the initialization transistors 816 and 817. Therefore, the predetermined amount of charge is transferred to the initialization control terminal 836, and the initialization transistors 816 and 817 are turned on. Therefore, the gate of MOSFET 810 The pole is charged to track the value of the input signal at node 815.

在預定時間週期之後，單擊881的輸出返回邏輯低，而關閉電流源884並開啟電晶體838(透過反相器882)。此舉將初始化電晶體816與817的閘極放電，而關閉電晶體816與817，但此舉在MOSFET 810的閘極處維持初始化電荷。所傳遞給電晶體816與817閘極的電荷量，因此相依於由電晶體884產生的電流，連同於電阻器885與單擊881的時間常數，以上各者可由電路設計者選定以對電晶體816與817確保所需的開啟狀態阻抗。After a predetermined period of time, the output of 881 is returned to logic low, while current source 884 is turned off and transistor 838 is turned on (via inverter 882). This will initialize the gate discharge of transistors 816 and 817, and turn off transistors 816 and 817, but this maintains an initial charge at the gate of MOSFET 810. The amount of charge delivered to the gates of transistors 816 and 817, thus dependent on the current generated by transistor 884, together with the time constant of resistor 885 and click 881, may be selected by the circuit designer to oppose transistor 816. And 817 ensure the required on-state impedance.

因此，在訊號獲取程序中的此時刻，MOSFET 810的閘極包含初始化電荷，初始化電荷部分地或完整地偏移任何閘極對源極電壓差，將任何瞬時阻抗變化最小化(或實質上消除)，藉以增進所獲取訊號的精確度。Thus, at this point in the signal acquisition procedure, the gate of MOSFET 810 contains an initial charge that partially or completely offsets any gate-to-source voltage difference, minimizing (or substantially eliminating) any transient impedance variations. ) to improve the accuracy of the signals obtained.

在完成初始化電路826作業時，反相器882的輸出返回邏輯高狀態，對時序電路851產生上升邊緣觸發輸入，指示單擊電路851產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯低至高轉變時所產生之具有相當短持續期間的邏輯高訊號)。此脈衝開啟包含電晶體854與電阻器855的電流源，並且此脈衝允許電流透過由電晶體853與833組成的電流鏡，經由路徑835流入開關810的閘極。此電荷(除了已提供的初始化電荷之外)開啟開關810，允許電容器820獲取輸入訊號。Upon completion of the initialization circuit 826 operation, the output of inverter 882 returns to a logic high state, generating a rising edge trigger input to timing circuit 851, indicating that click circuit 851 generates a short logic high pulse (eg, at the trigger input) A logic high signal with a relatively short duration generated when the logic transitions from low to high). This pulse turns on a current source comprising transistor 854 and resistor 855, and this pulse allows current to flow through the current mirror consisting of transistors 853 and 833, flowing into the gate of switch 810 via path 835. This charge (in addition to the initial charge provided) turns on switch 810, allowing capacitor 820 to take the input signal.

如上文所述，傳遞至電晶體810閘極的電荷量，係取決於由電晶體854產生的電流，連同於電阻器855與單 擊851的時間常數，以上各者可由電路設計者選定，以對電晶體810確保所需的開啟狀態阻抗。再者，在一些具體實施例中，單擊851(及/或單擊881)的時間常數可由終端使用者使用已知的技術來選定(例如，藉由耦合具有電阻器及/或電容器的外部網路)。在替代性具體實施例中，單擊851(及/或單擊881)的時間常數可被決定為適應性地追蹤半導體製程參數及/或環境參數(諸如溫度、電力供應電壓等等)，藉由使用已知的複製與比例控制電路技術。再者，在一些具體實施例中，可移除單擊881(與第7圖中的781)。As described above, the amount of charge transferred to the gate of transistor 810 is dependent on the current generated by transistor 854, along with resistor 855 and The time constant of 851, which can be selected by the circuit designer, ensures the desired on-state impedance for transistor 810. Moreover, in some embodiments, the time constant of clicking 851 (and/or clicking 881) may be selected by the end user using known techniques (eg, by coupling an external with a resistor and/or capacitor) network). In an alternative embodiment, the time constant of clicking 851 (and/or clicking 881) may be determined to adaptively track semiconductor process parameters and/or environmental parameters (such as temperature, power supply voltage, etc.), By using known replication and proportional control circuit techniques. Again, in some embodiments, click 881 (and 781 in Figure 7) can be removed.

第9圖圖示具有在取樣期間增進之阻抗特性的取樣電路的另一具體實施例為電路900。電路900在許多方面類似於第8圖所說明的電路，並且電路900一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路900包含控制電路925(第8圖中的控制電路825)、電荷產生器電路950(第8圖中的電荷產生器電路850)、初始化控制電路926(第8圖中的初始化控制電路826)、初始化電荷產生器電路980(第8圖中的初始化電荷產生電路880)、取樣開關910(第8圖中的取樣開關810)、閘極初始化電晶體916與917(第8圖中的閘極初始化電晶體816與817)、電容器920(第8圖中的電容器820)、電荷幫浦電路970(第8圖中的電荷幫浦電路870)等等。Figure 9 illustrates another embodiment of a sampling circuit having improved impedance characteristics during sampling as circuit 900. Circuit 900 is similar in many respects to the circuitry illustrated in Figure 8, and circuitry 900 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, the circuit 900 includes a control circuit 925 (control circuit 825 in FIG. 8), a charge generator circuit 950 (charge generator circuit 850 in FIG. 8), and an initialization control circuit 926 (initialization control circuit in FIG. 8). 826), initialize charge generator circuit 980 (initial charge generation circuit 880 in FIG. 8), sampling switch 910 (sampling switch 810 in FIG. 8), gate initialization transistors 916 and 917 (in FIG. 8 The gate initializes the transistors 816 and 817), the capacitor 920 (the capacitor 820 in Fig. 8), the charge pump circuit 970 (the charge pump circuit 870 in Fig. 8), and the like.

如圖所示，控制電路925可包含放電開關928。初始 化控制電路926可包含放電開關938。控制電路925與初始化控制電路926的操作可類似於上文所說明的電路825與826。As shown, control circuit 925 can include a discharge switch 928. initial The control circuit 926 can include a discharge switch 938. The operation of control circuit 925 and initialization control circuit 926 can be similar to circuits 825 and 826 described above.

再者，電路900係類似於電路800，類似之處在於控制電路925與初始化控制電路926各別傳遞電荷至電晶體910以及電晶體916與917，作為具有預定時間週期的預定電流脈衝。電流值係由跨被適合地調整尺寸的MOS電晶體上施加經界定電壓來建立，同時時間週期係由修整(trimming)電路來決定。如與連同電路500所討論者類似的考量，可被應用至電流值與時段週期的選擇上。如上文所述，電路900可操作於至少兩個模式中：取樣模式與保持模式。Moreover, circuit 900 is similar to circuit 800, similar in that control circuit 925 and initialization control circuit 926 each transfer charge to transistor 910 and transistors 916 and 917 as predetermined current pulses for a predetermined period of time. The current value is established by applying a defined voltage across a suitably sized MOS transistor while the time period is determined by a trimming circuit. Considerations similar to those discussed in connection with circuit 500 can be applied to the selection of current values and period periods. As described above, circuit 900 is operable in at least two modes: a sampling mode and a hold mode.

電路900進一步包含充電電路940，充電電路940在保持模式期間跨位準移位(level shifting)電容器955與985回復電壓，該電壓約等於在電荷幫浦輸出電壓V_CP 與電力供應電壓VDD之間的電壓差，如將於下文說明。充電電路940可包含反相器941、位準移位電容器942、943與電晶體944、945與充電開關946與947。The circuit 900 further includes a charging circuit 940 that restores voltage across the level shifting capacitors 955 and 985 during the hold mode, which is approximately equal to between the charge pump output voltage V _CP and the power supply voltage VDD The voltage difference is as explained below. Charging circuit 940 can include inverter 941, level shifting capacitors 942, 943 and transistors 944, 945 and charging switches 946 and 947.

例如，在作業中，可施加邏輯高訊號至指令節點930。此訊號較佳地具有足夠的量值以開啟電晶體928，電晶體928將控制路徑935與MOSFET 910的閘極放電，而關閉開關910。此將在節點915處的輸入訊號與電容器920斷開，隔離電容器920並將電路900置於保持狀態中。For example, in the job, a logic high signal can be applied to the instruction node 930. This signal preferably has a magnitude sufficient to turn on transistor 928, which discharges control path 935 from the gate of MOSFET 910 and turns off switch 910. This disconnects the input signal at node 915 from capacitor 920, isolating capacitor 920 and placing circuit 900 in the hold state.

單擊電路981在保持模式中的輸出為邏輯低(接近地)，邏輯低輸出使反相器982的輸出為邏輯高(接近VDD)，而將開關938的閘極驅動為高。此開啟電晶體938，將初始化電晶體916與917的閘極放電，而關閉初始化電晶體916與917。在保持模式中，反相器982與952的邏輯高輸出各別將電流源984與954的閘極放電(透過各別的位準移位電容器985與955)，防止任何電荷被各別傳遞至控制終端935與初始化控制終端936。The output of the click circuit 981 in the hold mode is logic low (near ground), the logic low output causes the output of the inverter 982 to be logic high (near VDD), and the gate of the switch 938 is driven high. This turns on transistor 938, which discharges the gates of initialization transistors 916 and 917, and turns off initialization transistors 916 and 917. In the hold mode, the logic high outputs of inverters 982 and 952 respectively discharge the gates of current sources 984 and 954 (through respective level shift capacitors 985 and 955), preventing any charge from being individually transferred to The control terminal 935 and the initialization control terminal 936.

在保持狀態期間，反相器941輸入位於邏輯高位準，且反相器的輸出位於邏輯低位準。該等位準，透過位準移位電容器942與943開啟電晶體944，並關閉電晶體945。因此，跨位準移位電容器942的電壓被回復至約V_CP -VDD(因為在反相器941輸入處的電壓為接近VDD)，同時電晶體945的汲極被維持於約為電壓V_CP -VDD。因此，充電開關946與947為開啟。因此，跨位準移位電容器985與955的電壓被回復至約V_CP -VDD(因為在反相器982與952輸出處的電壓為接近VDD)。During the hold state, the inverter 941 input is at a logic high level and the output of the inverter is at a logic low level. The levels turn on the transistor 944 through the level shifting capacitors 942 and 943 and turn off the transistor 945. Therefore, the voltage across the level shift capacitor 942 is restored to about V _{CP -} VDD (because the voltage at the input of the inverter 941 is close to VDD) while the drain of the transistor 945 is maintained at approximately voltage V _{CP .} -VDD. Therefore, the charge switches 946 and 947 are turned on. Therefore, the voltage across the level shift capacitors 985 and 955 is restored to about V _CP -VDD (since the voltage at the output of inverters 982 and 952 is close to VDD).

隨著保持訊號從邏輯高切換至低，電路900轉變至取樣模式，使反相器941的輸入位於邏輯低位準，同時反相器941的輸出位於邏輯高。該等位準，透過位準移位電容器942與943，關閉電晶體944並開啟電晶體945。因此，跨位準移位電容器943的電壓被回復至約V_CP -VDD(因為在反相器941輸出處的電壓為接近VDD)，同時電晶體945的汲極被維持於約為電壓V_CP ，且充電 開關946與947被關閉。As the hold signal switches from logic high to low, circuit 900 transitions to the sample mode, with the input of inverter 941 at a logic low level while the output of inverter 941 is at a logic high. The levels, through the level shifting capacitors 942 and 943, turn off the transistor 944 and turn on the transistor 945. Therefore, the voltage across the level shift capacitor 943 is restored to about V _{CP -} VDD (because the voltage at the output of the inverter 941 is close to VDD) while the drain of the transistor 945 is maintained at approximately the voltage V _CP And the charging switches 946 and 947 are turned off.

在電路900從保持狀態轉變成取樣狀態，在指令節點930處的保持訊號可從邏輯高被切換至邏輯低。此舉關閉電晶體928，並且此舉觸發初始化控制電路926於取樣狀態的初始部分中。此使時序電路981產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯高至低轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝在反相器982輸出處產生短邏輯低脈衝，短邏輯低脈衝關閉電晶體938。在反相器982輸出處的邏輯低脈衝亦透過位準移位電容器985開啟電流源984，電流源984允許電流透過初始化控制節點936流入初始化電晶體916與917的閘極。因此，預定電荷量被傳遞至初始化控制終端936，開啟初始化電晶體916與917。因此，MOSFET 910的閘極被充電至追蹤在節點915的輸入訊號的值。Upon the transition of the circuit 900 from the hold state to the sample state, the hold signal at the command node 930 can be switched from logic high to logic low. This closes the transistor 928 and this triggers the initialization control circuit 926 in the initial portion of the sampling state. This causes the timing circuit 981 to generate a short logic high pulse (e.g., a logic high signal having a relatively short duration generated when a logic high to low transition at the trigger input is detected), and a short logic high pulse at the inverter 982 A short logic low pulse is generated at the output and a short logic low pulse turns off the transistor 938. The logic low pulse at the output of inverter 982 also turns on current source 984 through level shift capacitor 985, which allows current to flow through initialization control node 936 into the gates of initialization transistors 916 and 917. Therefore, the predetermined amount of charge is transferred to the initialization control terminal 936, and the initialization transistors 916 and 917 are turned on. Thus, the gate of MOSFET 910 is charged to track the value of the input signal at node 915.

在預定時間週期之後，單擊981的輸出返回邏輯低，因此將反相器982的輸出返回邏輯高。透過位準移位電容器985，反相器982的輸出關閉電流源984，並開啟電晶體938。此舉將初始化電晶體916與917的閘極放電，關閉電晶體916與917，但此舉在MOSFET 910閘極處維持初始化電荷。傳遞至電晶體916與917閘極的電荷量，因此相依於由電晶體984產生的電流(在約等於VDD的電壓被施加於電晶體984源極與閘極之間時)以及單擊981的時間常數，以上各者可由電路設計者選定，以 對電晶體916與917確保所需的開啟狀態阻抗。After a predetermined period of time, the output of click 981 returns to a logic low, thus returning the output of inverter 982 to a logic high. Through the level shift capacitor 985, the output of inverter 982 turns off current source 984 and turns on transistor 938. This will initialize the gate discharge of transistors 916 and 917, turning off transistors 916 and 917, but this maintains an initial charge at the gate of MOSFET 910. The amount of charge transferred to the gates of transistors 916 and 917 is thus dependent on the current generated by transistor 984 (when a voltage approximately equal to VDD is applied between the source and gate of transistor 984) and clicks on 981 Time constant, each of which can be selected by the circuit designer to The required on-state impedance is ensured for transistors 916 and 917.

因此，在訊號獲取程序中的此時刻，MOSFET 910的閘極包含初始化電荷，初始化電荷部分地或完整地偏移任何閘極對源極電壓差，將任何瞬時阻抗變化最小化(或實質上消除)，藉以增進所獲取訊號的精準度。Thus, at this point in the signal acquisition procedure, the gate of MOSFET 910 contains an initial charge that partially or completely offsets any gate-to-source voltage difference, minimizing (or substantially eliminating) any transient impedance variations. ), in order to improve the accuracy of the signals obtained.

在初始化電路926作業完成時，反相器982的輸出返回邏輯高狀態，對時序電路951產生上升邊緣觸發輸入，指示單擊電路951產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯低至高轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝在反相器952輸出處產生短邏輯低脈衝。此脈衝透過位準移位電容器955開啟電流源電晶體954，並且此脈衝允許電流經由路徑935流入開關910的閘極。此電荷(與已提供的初始化電荷一起)開啟開關910並允許電容器920獲取輸入訊號。Upon completion of the initialization circuit 926 operation, the output of the inverter 982 returns to a logic high state, and a rising edge trigger input is generated to the timing circuit 951, indicating that the click circuit 951 generates a short logic high pulse (eg, when detected at the trigger input) The logic high signal generated during the logic low to high transition has a relatively short duration, and the short logic high pulse produces a short logic low pulse at the output of inverter 952. This pulse turns on current source transistor 954 through level shift capacitor 955, and this pulse allows current to flow into the gate of switch 910 via path 935. This charge (along with the initial charge provided) turns on switch 910 and allows capacitor 920 to take an input signal.

如上文所述，傳遞至電晶體910閘極的電荷量，係取決於由電晶體954產生的電流(在約等於VDD的電壓被施加於電晶體954源極與閘極之間時)以及單擊951的時間常數，以上各者可由電路設計者選定，以對電晶體910確保所需的開啟狀態阻抗。再者，在一些具體實施例中，單擊951(及/或單擊981)的時間常數可由終端使用者使用已知技術來選定(例如藉由耦合具有電阻器及/或電容器的外部網路)。在替代性具體實施例中，單擊951(及/或單擊981)的時間常數可被決定為適應性 地追蹤半導體製程參數及/或環境參數(諸如溫度、電力供應電壓等等)，藉由使用已知的複製與比例控制電路技術。再者，在一些具體實施例中，可移除單擊981。As described above, the amount of charge transferred to the gate of transistor 910 is dependent on the current generated by transistor 954 (when a voltage approximately equal to VDD is applied between the source and gate of transistor 954) and The time constant of 951, which can be selected by the circuit designer, ensures the desired on-state impedance for transistor 910. Moreover, in some embodiments, the time constant of clicking 951 (and/or clicking 981) may be selected by the end user using known techniques (eg, by coupling an external network with resistors and/or capacitors). ). In an alternative embodiment, the time constant of clicking 951 (and/or clicking 981) can be determined as adaptive. Track semiconductor process parameters and/or environmental parameters (such as temperature, power supply voltage, etc.) by using known replication and proportional control circuit techniques. Again, in some embodiments, click 981 can be removed.

藉由控制電路925注入開關910(或第8圖中開關810，或第7圖中開關710等等)閘極的電荷，開啟開關910並致能輸入訊號915對電容器920的取樣，亦注入相依於訊號的電荷量於此訊號路徑中。此產生非常小、相依於輸入訊號的擾動，但在非常高線性度的應用中，此擾動轉譯成不可忽視的非線性度。因此，需要引入能夠減少(或實質上消除)此效應的電路。作為實例，取樣電路900可如第10圖圖示般被修改以建置電路1000。The control circuit 925 injects the charge of the gate of the switch 910 (or the switch 810 in FIG. 8 or the switch 710 in FIG. 7 , etc.), turns on the switch 910 and enables the input signal 915 to sample the capacitor 920, and also injects the dependency. The amount of charge in the signal is in this signal path. This produces very small disturbances that are dependent on the input signal, but in very high linearity applications, this perturbation translates into non-negligible nonlinearity. Therefore, it is necessary to introduce a circuit that can reduce (or substantially eliminate) this effect. As an example, sampling circuit 900 can be modified to construct circuit 1000 as illustrated in FIG.

電路1000在許多方面類似於第9圖所說明的電路，並且電路1000一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路1000包含控制電路1025(第9圖中的控制電路925)、電荷產生器電路1050(第9圖中的電荷產生器電路950)、初始化控制電路1026(第9圖中的初始化控制電路926)、初始化電荷產生器電路1080(第9圖中的初始化電荷產生電路980)、充電電路1040(在第9圖中的充電電路940)、取樣開關1010(第9圖中的取樣開關910)、閘極初始化電晶體1016與1017(第9圖中的閘極初始化電晶體916與917)、電容器1020(第9圖中的電容器920)、電荷幫浦電路1070(第9圖中的電荷幫浦電路970)等等。Circuit 1000 is similar in many respects to the circuits illustrated in Figure 9, and circuit 1000 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, the circuit 1000 includes a control circuit 1025 (control circuit 925 in FIG. 9), a charge generator circuit 1050 (charge generator circuit 950 in FIG. 9), and an initialization control circuit 1026 (initial control circuit in FIG. 9). 926), initialize the charge generator circuit 1080 (the initialization charge generation circuit 980 in FIG. 9), the charging circuit 1040 (the charging circuit 940 in FIG. 9), and the sampling switch 1010 (the sampling switch 910 in FIG. 9) Gate initialization transistors 1016 and 1017 (gate initialization transistors 916 and 917 in FIG. 9), capacitor 1020 (capacitor 920 in FIG. 9), charge pump circuit 1070 (charge diagram in FIG. 9) Pu circuit 970) and so on.

如圖所示，控制電路1025可包含放電開關1028。初始化控制電路1026可包含放電開關1038。控制電路1025、初始化控制電路1026與充電電路1040的操作可類似於上文所述的電路925、926與940。As shown, control circuit 1025 can include a discharge switch 1028. Initialization control circuit 1026 can include a discharge switch 1038. The operation of control circuit 1025, initialization control circuit 1026, and charging circuit 1040 can be similar to circuits 925, 926, and 940 described above.

再者，電路1000包含校正電路1090，校正電路1090連同控制電路1025與初始化控制電路1026，實質上消除在開啟主開關1010時注入訊號路徑之電荷對於輸入訊號的變化。校正電路1090包含連接成電容器的裝置1091與1092，裝置1091與1092用以將校正電荷注入主開關1010兩側上的訊號路徑。跨該等裝置(1091與1092)的閘極對源極電壓係由初始化電晶體1096與1097各別設定。校正電荷由電流源1094開啟而產生，如由時序電路1051所指示，並且校正電荷由平方律裝置1095(亦即所通過的電流約隨著施加至閘極之控制電壓的平方來變化的裝置)連同耦合電容器1093來塑型。在保持狀態期間，重置裝置1098施加偏壓電壓V_bias 至裝置1095的體極與源極終端，V_bias 經選定以將裝置1095維持為接近裝置1095的開啟臨限。此外，在保持狀態期間，裝置1099將連接成電容器的電晶體1091與1092的閘極放電，而關閉電晶體1091與1092。如上文所述，電路1000可操作於至少兩個模式：取樣模式與保持模式。Moreover, the circuit 1000 includes a correction circuit 1090, together with the control circuit 1025 and the initialization control circuit 1026, substantially eliminating variations in the charge injected into the signal path with respect to the input signal when the main switch 1010 is turned on. The correction circuit 1090 includes means 1091 and 1092 connected as capacitors for injecting correction charge into the signal paths on both sides of the main switch 1010. The gate-to-source voltage across the devices (1091 and 1092) is set by initialization transistors 1096 and 1097, respectively. The correction charge is generated by the current source 1094 being turned on, as indicated by the timing circuit 1051, and the charge is corrected by the square law device 1095 (i.e., the current passed by the device varies with the square of the control voltage applied to the gate) It is molded together with the coupling capacitor 1093. During the hold state, reset device 1098 applies a bias voltage _Vbias to the body and source terminals of device 1095, and _Vbias is selected to maintain device 1095 close to the turn-on threshold of device 1095. Further, during the hold state, the device 1099 discharges the gates of the transistors 1091 and 1092 connected to the capacitor, and turns off the transistors 1091 and 1092. As described above, the circuit 1000 is operable in at least two modes: a sampling mode and a hold mode.

例如，在作業中，可施加邏輯高訊號至指令節點1030。此訊號較佳地具有足夠的量值以開啟電晶體1028、1099與1098。電晶體1028將控制路徑1035與 MOSFET 1010的閘極放電，關閉開關1010。此將在節點1015處的輸入訊號與電容器1020斷開，隔離電容器1020並將電路1000置於保持狀態中。電晶體1099將電晶體1091與1092的閘極放電，關閉電晶體1091與1092。電晶體1098將裝置1095的體極與源極電位維持為接近V_bias ，且電晶體1098連同放電電晶體1099設定跨耦合電容器1093的電壓。For example, in the job, a logic high signal can be applied to the instruction node 1030. This signal preferably has a magnitude sufficient to turn on transistors 1028, 1099, and 1098. The transistor 1028 discharges the control path 1035 from the gate of the MOSFET 1010, turning off the switch 1010. This disconnects the input signal at node 1015 from capacitor 1020, isolating capacitor 1020 and placing circuit 1000 in the hold state. The transistor 1099 discharges the gates of the transistors 1091 and 1092, and turns off the transistors 1091 and 1092. The transistor 1098 maintains the body and source potentials of the device 1095 near _Vbias , and the transistor 1098, along with the discharge transistor 1099, sets the voltage across the coupling capacitor 1093.

單擊電路1081的輸出在保持模式中為邏輯低(接近地)，邏輯低輸出使反相器1082的輸出為邏輯高(接近VDD)，將開關1038的閘極驅動為高。此開啟電晶體1038，將初始化電晶體1016、1017、1096與1097的閘極放電，關閉初始化電晶體1016、1017、1096與1097。在保持模式中，反相器1082與1052的邏輯高輸出各別將電流源1084與1054的閘極放電(透過各別的位準移位電容器1085與1055)，防止任何電荷被各別傳遞至控制終端1035與初始化控制終端1036。再者，反相器1052的輸出位於邏輯高位準，將校正塑型平方律裝置1095維持於關閉狀態中。The output of the click circuit 1081 is logic low (near ground) in the hold mode, the logic low output causes the output of the inverter 1082 to be logic high (near VDD), and the gate of the switch 1038 is driven high. This turns on the transistor 1038, discharges the gates of the initialization transistors 1016, 1017, 1096, and 1097, and turns off the initialization transistors 1016, 1017, 1096, and 1097. In the hold mode, the logic high outputs of inverters 1082 and 1052 respectively discharge the gates of current sources 1084 and 1054 (through respective level shift capacitors 1085 and 1055), preventing any charge from being individually transferred to The control terminal 1035 and the initialization control terminal 1036. Furthermore, the output of the inverter 1052 is at a logic high level to maintain the corrected square law device 1095 in the off state.

在保持狀態期間，反相器1041的輸入位於邏輯高位準，且反相器1041的輸出位於邏輯低位準。該等位準透過位準移位電容器1042與1043開啟電晶體1044，並關閉電晶體1045。因此，跨位準移位電容器1042的電壓被回復至約V_CP -VDD(因為反相器1041輸入處的電壓為接近VDD)，同時電晶體1045汲極的電壓被維持於約 V_CP -VDD。因此，充電開關1046與1047為開啟。因此，跨位準移位電容器1085與1055的電壓被回復至約V_CP -VDD(因為反相器1082與1052輸出處的電壓為接近VDD)。During the hold state, the input of inverter 1041 is at a logic high level and the output of inverter 1041 is at a logic low level. The levels turn on the transistor 1044 through the level shifting capacitors 1042 and 1043 and turn off the transistor 1045. Therefore, the voltage across the level shift capacitor 1042 is restored to approximately V _CP -VDD (because the voltage at the input of the inverter 1041 is close to VDD) while the voltage of the drain of the transistor 1045 is maintained at approximately V _CP -VDD . Therefore, the charging switches 1046 and 1047 are turned on. Thus, the voltage across the level shift capacitors 1085 and 1055 is restored to about V _{CP -} VDD (because the voltage at the output of inverters 1082 and 1052 is close to VDD).

隨著保持訊號從邏輯高切換至低，電路1000轉變至取樣模式，使反相器1041的輸入位於邏輯低位準，同時反相器1041的輸出位於邏輯高。該等位準，透過位準移位電容器1042與1043關閉電晶體1044，並開啟電晶體1045。因此，跨位準移位電容器1043的電壓被回復至約V_CP -VDD(因為反相器1041輸出處的電壓為接近VDD)，同時電晶體1045汲極的電壓被維持於約V_CP ，且充電開關1046與1047被關閉。As the hold signal switches from logic high to low, circuit 1000 transitions to the sample mode, with the input of inverter 1041 at a logic low level while the output of inverter 1041 is at a logic high. The levels turn off the transistor 1044 through the level shifting capacitors 1042 and 1043 and turn on the transistor 1045. Therefore, the voltage across the level shift capacitor 1043 is restored to about V _CP -VDD (because the voltage at the output of the inverter 1041 is close to VDD) while the voltage of the drain of the transistor 1045 is maintained at about V _CP , and Charging switches 1046 and 1047 are turned off.

在電路1000從保持狀態轉變成取樣狀態時，在指令節點1030處的保持訊號可從邏輯高切換成邏輯低。此舉關閉重置裝置1098，關閉放電電晶體1028與1099，並且此舉觸發初始化控制電路1026於取樣狀態的初始部分中。此使時序電路1081產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯高至低轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝在反相器1082輸出處產生短邏輯低脈衝，短邏輯低脈衝關閉電晶體1038。在反相器1082輸出處的邏輯低脈衝亦透過位準移位電容器1085開啟電流源1084，電流源1084允許電流透過初始化控制節點1036流入初始化電晶體1016、1017、1096與1097的閘極。因此，預定電荷量 被傳遞至初始化控制終端1036，開啟初始化電晶體1016、1017、1096與1097。因此，主開關1010的閘極與連接成電容器的裝置1091與1092的閘極，被充電至追蹤呈現在節點1015處的輸入訊號的值。The hold signal at instruction node 1030 can be switched from logic high to logic low as circuit 1000 transitions from the hold state to the sample state. This turns off reset device 1098, turning off discharge transistors 1028 and 1099, and this triggers initialization control circuit 1026 in the initial portion of the sampling state. This causes the timing circuit 1081 to generate a short logic high pulse (eg, a logic high signal having a relatively short duration generated when a logic high to low transition at the trigger input is detected), and a short logic high pulse at the inverter 1082 A short logic low pulse is generated at the output and a short logic low pulse turns off the transistor 1038. The logic low pulse at the output of inverter 1082 also turns on current source 1084 through level shift capacitor 1085, which allows current to flow through initialization control node 1036 into the gates of initialization transistors 1016, 1017, 1096, and 1097. Therefore, the predetermined amount of charge It is passed to the initialization control terminal 1036 to turn on the initialization transistors 1016, 1017, 1096, and 1097. Thus, the gate of main switch 1010 and the gates of devices 1091 and 1092 connected to the capacitor are charged to track the value of the input signal presented at node 1015.

在預定時間週期之後，單擊1081的輸出返回邏輯低，因此反相器1082的輸出返回邏輯高。透過位準移位電容器1085，反相器1082的輸出關閉電流源1084並開啟電晶體1038。此舉將初始化電晶體1016、1017、1096與1097的閘極放電，並關閉電晶體1016、1017、1096與1097，但此舉在MOSFET 1010閘極處以及連接成電容器的電晶體1091與1092閘極處維持初始化電荷。傳遞至電晶體1016、1017、1096與1097閘極的電荷量，因此相依於由電晶體1084產生的電流(在約等於VDD的電壓被施加於電晶體1084的源極與閘極之間時)以及單擊1081的時間常數，以上各者可由電路設計者選定以對電晶體1016、1017、1096與1097確保所需的開啟狀態阻抗。After a predetermined period of time, the output of the click 1081 returns to a logic low, so the output of the inverter 1082 returns to a logic high. Through the level shift capacitor 1085, the output of the inverter 1082 turns off the current source 1084 and turns on the transistor 1038. This will initialize the gate discharge of transistors 1016, 1017, 1096, and 1097 and turn off transistors 1016, 1017, 1096, and 1097, but this is at the gate of MOSFET 1010 and the gates of transistors 1091 and 1092 that are connected into capacitors. The initial charge is maintained at the pole. The amount of charge transferred to the gates of transistors 1016, 1017, 1096, and 1097, thus dependent on the current generated by transistor 1084 (when a voltage approximately equal to VDD is applied between the source and gate of transistor 1084) And click on the time constant of 1081, which can be selected by the circuit designer to ensure the desired on-state impedance for transistors 1016, 1017, 1096, and 1097.

因此，在訊號獲取程序中的此時刻，MOSFET 1010的閘極包含初始化電荷，初始化電荷部分地或完整地偏移任何閘極對源極電壓差，將任何瞬時阻抗變化最小化(或實質上消除)，藉以增進所獲取訊號的精確度。Thus, at this point in the signal acquisition procedure, the gate of MOSFET 1010 contains an initial charge that partially or completely offsets any gate-to-source voltage difference, minimizing (or substantially eliminating) any transient impedance variations. ) to improve the accuracy of the signals obtained.

在初始化電路1026作業完成時，反相器1082的輸出返回邏輯高狀態，對時序電路1051產生上升邊緣觸發輸入，指示單擊電路1051產生短邏輯高脈衝(例如在偵測 到於觸發輸入處的邏輯低至高轉變時所產生之具有相當短持續期間的邏輯高訊號)，在反相器1052輸出處產生短邏輯低脈衝。此脈衝將平方律裝置1095的閘極帶到接近地，且此脈衝透過位準移位電容器1055相伴地開啟並聯連接的電流源電晶體1054與1094。因此，此允許電流經由路徑1035各別流入開關1010閘極，透過耦合電容器1093流入校正塑型平方律裝置1095，並流入連接成電容器的校正注入裝置1091與1092的閘極。經由路徑1035流動的電荷被加入已提供的初始化電荷，開啟開關1010並允許電容器1020獲取輸入訊號。透過連接成電容器的裝置1091與1092注入訊號路徑(訊號路徑建立於輸入終端1015與取樣電容器1020之間)的校正電荷，係由平方律裝置1095連同先前設定之跨耦合電容器1093的電壓來塑型(在此期間平方律裝置1095的閘極被維持為接近地)。When the initialization circuit 1026 is completed, the output of the inverter 1082 returns to a logic high state, and a rising edge trigger input is generated to the sequential circuit 1051, instructing the click circuit 1051 to generate a short logic high pulse (eg, in the detection). A short logic low pulse is generated at the output of inverter 1052 as the logic high signal generated during the logic low to high transition at the trigger input has a relatively short duration. This pulse brings the gate of the square-law device 1095 to near ground, and this pulse, through the level shift capacitor 1055, concomitantly turns on the parallel-connected current source transistors 1054 and 1094. Therefore, the allowable current flows into the gate of the switch 1010 via the path 1035, passes through the coupling capacitor 1093, flows into the correction square-law device 1095, and flows into the gates of the correction injection devices 1091 and 1092 connected to the capacitor. The charge flowing through path 1035 is added to the provided initialization charge, switch 1010 is turned on and capacitor 1020 is allowed to acquire the input signal. The corrected charge injected into the signal path (the signal path is established between the input terminal 1015 and the sampling capacitor 1020) through the devices 1091 and 1092 connected to the capacitor is shaped by the square law device 1095 along with the voltage of the previously set transconjugation capacitor 1093. (The gate of the square-law device 1095 is maintained close to ground during this period).

如上文所述，傳遞至電晶體1010閘極的電荷量係相依於由電晶體1054產生的電流(在約等於VDD的電壓被施加於電晶體1054的源極與閘極之間時)以及單擊1051的時間常數，以上各者可由電路設計者選定以對電晶體1010確保所需的開啟狀態阻抗。As described above, the amount of charge transferred to the gate of the transistor 1010 is dependent on the current generated by the transistor 1054 (when a voltage approximately equal to VDD is applied between the source and the gate of the transistor 1054) and The time constant of 1051 is hit, and each of the above can be selected by the circuit designer to ensure the desired on-state impedance of the transistor 1010.

類似的，由電路1090注入訊號路徑的電荷量，係相依於由電晶體1094產生的電流(在約等於VDD的電壓被施加於電晶體1094的源極與閘極之間時)，連接成電容器的裝置1091與1092的大小，以及單擊1051的時間常 數，以上各者可由電路設計者選定以確保所需校正程度。訊號相依電荷注入的消去程度，係進一步藉由選定耦合電容器1093大小與平方律裝置1095特性來調整。Similarly, the amount of charge injected into the signal path by circuit 1090 is dependent on the current generated by transistor 1094 (when a voltage approximately equal to VDD is applied between the source and gate of transistor 1094), connected into a capacitor The size of the devices 1091 and 1092, as well as the time of clicking 1051 The number, each of which can be selected by the circuit designer to ensure the degree of correction required. The degree of cancellation of the signal dependent charge injection is further adjusted by selecting the coupling capacitor 1093 size and the square law device 1095 characteristics.

再者，在一些具體實施例中，單擊1051(及/或單擊1081)的時間常數可由終端使用者使用已知技術來選擇(例如藉由耦合具有電阻器及/或電容器的外部網路)。在替代性具體實施例中，單擊1051(及/或單擊1081)的時間常數可使用已知的複製與比例控制電路技術，被決定為適應性地追蹤半導體製程參數及/或環境參數(諸如溫度、電力供應電壓等等)。再者，在一些具體實施例中可移除單擊1081。Moreover, in some embodiments, the time constant of clicking 1051 (and/or clicking on 1081) may be selected by the end user using known techniques (eg, by coupling an external network with resistors and/or capacitors). ). In an alternative embodiment, the time constant of clicking 1051 (and/or clicking on 1081) can be determined to adaptively track semiconductor process parameters and/or environmental parameters using known replication and proportional control circuit techniques ( Such as temperature, power supply voltage, etc.). Again, click 1081 can be removed in some embodiments.

第10圖中的電路1000圖示說明連同取樣系統實施(類似於第9圖之電路900)來使用的補償電路1090。在本發明領域中具有通常知識者將認知到，此補償方案可類似地連同其他取樣系統實施(例如第7圖中的電路700、第8圖中的電路800等等)來使用，以大量地減少或消除訊號相依電荷，該訊號相依電荷在電路從保持狀態轉變至取樣狀態時注入訊號路徑。Circuit 1000 in Figure 10 illustrates a compensation circuit 1090 for use with a sampling system implementation (similar to circuit 900 of Figure 9). It will be appreciated by those of ordinary skill in the art that this compensation scheme can be similarly used in conjunction with other sampling system implementations (e.g., circuit 700 in Figure 7, circuit 800 in Figure 8, etc.) to The signal dependent charge is reduced or eliminated, and the signal dependent charge is injected into the signal path as the circuit transitions from the hold state to the sample state.

在該等電路大大地增進取樣系統效能的同時，在由主取樣開關所經歷的體極偏壓改變中，存在小型但不能被忽略的訊號相依失真來源。作為實例，參照第6圖，主取樣開關(MOSFET 610)的體極係隱含地連接至地電位。在終端615處的輸入訊號變化的同時，MOSFET 610的源極對體極電位與汲極對體極電位亦變化。在上文所 說明的電荷驅動取樣系統大大地緩和臨限電壓的改變的同時，MOSFET 610特性對於輸入訊號的變異(例如，源極對體極與汲極對體極電容等等的變異)，持續轉譯成訊號相依的失真。While these circuits greatly enhance the performance of the sampling system, there is a small but unnegligible source of signal dependent distortion in the body bias changes experienced by the main sampling switch. As an example, referring to Fig. 6, the body of the main sampling switch (MOSFET 610) is implicitly connected to ground potential. While the input signal at terminal 615 changes, the source-to-body potential and the drain-to-body potential of MOSFET 610 also change. Above The illustrated charge-driven sampling system greatly mitigates the change in threshold voltage while the MOSFET 610 characteristics are continually translated into signals for variations in the input signal (eg, source-to-body and buck-to-body capacitance variations, etc.) Dependent distortion.

若可在主取樣開關體極與源極或汲極終端之間維持相對固定的電壓差，則該等訊號失真可被實質上消除。若在取樣與保持狀態兩者期間維持固定的體極偏壓電壓，而因此避免不良的電荷注入(以及特定而言，不良的輸入訊號相依電荷注入)，則可獲得進一步的優點。If a relatively fixed voltage difference can be maintained between the body of the main sampling switch and the source or drain terminal, the signal distortion can be substantially eliminated. Further advantages are obtained if a fixed body bias voltage is maintained during both the sample and hold states, thereby avoiding poor charge injection (and, in particular, poor input signal dependent charge injection).

可在主取樣開關的體極終端可被獨立地控制時考慮此種作法(例如，主取樣開關被建構入被隔離的井)。為了清晰起見，此討論使用n通道MOSFET裝置作為主取樣開關來作為實例，但在本發明領域中具有通常知識者將認知到該等考量可被直接延伸至所有的場效裝置範圍。This can be considered when the body terminal of the main sampling switch can be independently controlled (eg, the main sampling switch is built into the isolated well). For the sake of clarity, this discussion uses an n-channel MOSFET device as the primary sampling switch as an example, but those of ordinary skill in the art will recognize that such considerations can be directly extended to all field effect devices.

第11圖圖示說明此作法的一般化示意圖為電路1100A與1100B。電路1100A與1100B在許多方面類似於第4圖所說明的電路400，且電路1100A與1100B一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路1100A與1100B包含控制電路1125(第4圖中的控制電路425)、取樣開關1110(第4圖中的取樣開關410)、電容器1120(第4圖中的電容器420)等等。Figure 11 illustrates a generalized schematic of this approach for circuits 1100A and 1100B. Circuits 1100A and 1100B are similar in many respects to circuit 400 illustrated in FIG. 4, and circuits 1100A and 1100B generally include components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, circuits 1100A and 1100B include control circuit 1125 (control circuit 425 in FIG. 4), sampling switch 1110 (sampling switch 410 in FIG. 4), capacitor 1120 (capacitor 420 in FIG. 4), and the like.

取樣開關1110經圖示說明為具有明確地可用的體極終端1109的n通道MOSFET裝置。電路1100A與1100B 進一步包含體極偏壓電路1160，體極偏壓電路1160相對於開關1110的源極或汲極終端在開關1110的體極終端上維持實質上固定的偏壓電壓。此偏壓電壓必需被選擇以對整個所需的輸入訊號範圍，確保電晶體1110的源極與汲極接面保持為正確地被偏壓。偏壓電壓被維持在跨偏壓電容器1162上，偏壓電容器1162可代表相關聯於裝置1110的本徵體極電容，或在不足以應付特定的應用時，偏壓電容器1162可從電晶體1110體極電容與額外明確電容的並聯來建置。The sampling switch 1110 is illustrated as an n-channel MOSFET device with a body terminal 1109 that is explicitly available. Circuits 1100A and 1100B Further included is a body bias circuit 1160 that maintains a substantially fixed bias voltage at the body terminal of switch 1110 with respect to the source or drain terminal of switch 1110. This bias voltage must be selected to ensure that the source and drain junctions of transistor 1110 are properly biased for the entire desired input signal range. The bias voltage is maintained across the bias capacitor 1162, which may represent the intrinsic body capacitance associated with device 1110, or when insufficient to handle a particular application, bias capacitor 1162 may The transistor 1110 body capacitance is built in parallel with an additional explicit capacitance.

隨著時間，跨偏壓電容器1162的電壓必需被更新，且此係由更新操作於雙相位更新週期中的電容器1165與開關1163、1164、1166與1167來完成。在第一相位中，開關1163與1164被開啟，同時開關1166與1167被關閉，且施加電壓V_BIAS 於跨電容器1165上。在第二相位中，開關1166與1167被開啟，同時開關1163與1164被關閉，且電容器1165被與電容器1162並聯連接。控制開關對1163、1164與1166、1167的訊號，需維持非重疊的時序關係，而使開關對1166、1167僅在開關對1163、1164關閉之後開啟，且類似地，僅在開關對1166、1167關閉之後開啟開關對1163、1164。在足夠長的由循序更新週期所組成的啟動序列之後，跨偏壓電容器1162的電壓將約到達偏壓電壓V_BIAS ，而在達到該偏壓電壓V_BIAS 後該跨偏壓電容器1162將實質上維持固定。Over time, the voltage across the bias capacitor 1162 must be updated, and this is done by updating the capacitor 1165 and switches 1163, 1164, 1166, and 1167 operating in the dual phase update cycle. In the first phase, switches 1163 and 1164 are turned on while switches 1166 and 1167 are turned off and voltage V _{BIAS is} applied across capacitor 1165. In the second phase, switches 1166 and 1167 are turned on, while switches 1163 and 1164 are turned off, and capacitor 1165 is connected in parallel with capacitor 1162. The signals of the control switch pairs 1163, 1164 and 1166, 1167 need to maintain a non-overlapping timing relationship, so that the switch pairs 1166, 1167 are only turned on after the switch pairs 1163, 1164 are turned off, and similarly, only the switch pairs 1166, 1167 The switch pairs 1163, 1164 are turned on after being turned off. After a sufficiently long start sequence consisting of a sequential update cycle, the voltage across the bias capacitor 1162 will reach approximately the bias voltage V _BIAS , and after reaching the bias voltage V _BIAS the cross bias capacitor 1162 will It remains essentially fixed.

有益的是更新週期的第一與第二相位被與取樣系統的 取樣與保持狀態同步，以最小化可被開關1163與1164注入訊號路徑(輸入終端及/或取樣電容器)的電荷。開關對1163、1164的控制訊號需被適當地對齊，相對於取樣系統從取樣狀態至保持狀態的轉變。此時序關係係由源自控制電路1125控制開關對1163、1164與1166、1167的虛線來指示。例如，可使用已知的邏輯、時序與延遲電路，來從保持訊號直接導出該等控制訊號，如將於下文說明。在一種可能的實施中，第一相位可在保持狀態期間發生，而第二相位可在取樣狀態期間發生。It is beneficial that the first and second phases of the update cycle are associated with the sampling system The samples are synchronized with the hold state to minimize the charge that can be injected into the signal path (input terminal and/or sampling capacitor) by switches 1163 and 1164. The control signals of switch pairs 1163, 1164 need to be properly aligned relative to the sampling system transition from the sample state to the hold state. This timing relationship is indicated by the dashed lines from control circuit 1125 controlling switch pairs 1163, 1164 and 1166, 1167. For example, known logic, timing, and delay circuits can be used to derive the control signals directly from the hold signals, as will be explained below. In one possible implementation, the first phase may occur during the hold state and the second phase may occur during the sample state.

儘管非常類似，電路1100A與1100B仍具有特定的優點與缺點。在電路1100A中，較不關注由開關對1163、1164潛在地注入的電荷，因為此電荷流入相對低阻抗的輸入終端。此對開關1163、1164之控制訊號與施加至節點1135的取樣開關之控制訊號之間的時序關係，產生較不迫切的要求。如將於下文說明，該等控制訊號可為同時的。在同時，在電路1100A中體極終端1109經歷電壓變化，此電壓變化接近地跟隨施加至輸入終端1115的訊號。在保持狀態期間，此訊號可部分地洩漏入取樣電容器1120中，透過相關聯於取樣開關1110的擴散電容，產生不良的錯誤。Although very similar, circuits 1100A and 1100B still have particular advantages and disadvantages. In circuit 1100A, less attention is paid to the charge potentially injected by switch pairs 1163, 1164 because this charge flows into the relatively low impedance input terminal. The timing relationship between the control signals of the pair of switches 1163, 1164 and the control signals applied to the sampling switches of node 1135 creates less stringent requirements. As will be explained below, the control signals can be simultaneous. At the same time, the body terminal 1109 undergoes a voltage change in circuit 1100A that closely follows the signal applied to input terminal 1115. During the hold state, this signal can partially leak into the sampling capacitor 1120, passing through the diffusion capacitor associated with the sampling switch 1110, producing a bad error.

在電路1100B中，在保持狀態期間在體極終端1109上的電壓為實質上固定，而避免任何顯著之透過擴散電容的電荷重分配。在同時，由開關對1163、1164注入的電荷流入取樣電容器，且因此在保持狀態期間由開關對 1163、1164注入的電荷可毀壞所獲取的取樣。因此需允許在對開關對1163、1164的控制訊號轉變之時刻，至取樣系統進入保持狀態之時刻之間，有足夠的安定時間。In circuit 1100B, the voltage on the body terminal 1109 during the hold state is substantially fixed, avoiding any significant charge redistribution through the diffusion capacitance. At the same time, the charge injected by the switch pairs 1163, 1164 flows into the sampling capacitor, and thus by the switch pair during the hold state The charge injected in 1163, 1164 can destroy the sample taken. Therefore, it is necessary to allow sufficient settling time between the timing at which the control signals of the switch pairs 1163 and 1164 are switched, and the time when the sampling system enters the hold state.

在本發明領域中具有通常知識者將認知到，第11圖所說明的固定體極偏壓方案，可被有益地連同從第5圖至第10圖所圖示的此種新穎的取樣系統，以及其他已知的取樣配置來實施。Those of ordinary skill in the art will recognize that the fixed body pole biasing scheme illustrated in Figure 11 can be beneficially coupled to such novel sampling systems illustrated in Figures 5 through 10. And other known sampling configurations are implemented.

在諸如從第5圖至第10圖所圖示的實施中，在取樣系統轉變於取樣狀態與保持狀態間的期間內，主取樣開關的閘極終端經歷約為追蹤輸入訊號的電壓擺幅。此電壓轉變，在流過固有地呈現於主取樣開關閘極終端與訊號路徑之間的本徵電容時，可給予失真至取樣系統所獲取的訊號上。如先前所提及，此變異亦可轉譯成取樣抖動，該取樣抖動進一步讓取樣作業的結果失真。因此需在施加至主取樣開關閘極的電壓擺幅中，大量地減少或消除與輸入訊號相關的變異。In an implementation such as illustrated from Figures 5 through 10, during the transition of the sampling system between the sampling state and the holding state, the gate terminal of the main sampling switch experiences a voltage swing that is approximately tracking the input signal. This voltage transition can be imparted to the signal acquired by the sampling system as it flows through the intrinsic capacitance inherently present between the gate terminal of the main sampling switch and the signal path. As mentioned previously, this variation can also be translated into sample jitter, which further distort the results of the sampling operation. Therefore, the variation associated with the input signal is greatly reduced or eliminated in the voltage swing applied to the gate of the main sampling switch.

第7圖至第10圖所圖示的電路試圖透過使用初始化步驟來緩解此效應，在初始化步驟中主取樣開關的閘極被初始地偏壓於追蹤輸入訊號的位準。第11圖所說明的體極偏壓電路提供了增進配置的機會。在保持狀態期間，為了將輸入終端與取樣電容器解耦合(decouple)，主取樣開關的閘極可被放電至約為主取樣開關體極電位的電位(而非如第5圖至第10圖所圖示的固定地電位)。因此，藉由較佳地使用如電路1100A所圖示的體極偏壓方 案，使主取樣開關閘極上的電壓擺幅實質上獨立於輸入訊號。The circuit illustrated in Figures 7 through 10 attempts to mitigate this effect by using an initialization step in which the gate of the main sampling switch is initially biased to track the level of the input signal. The body bias circuit illustrated in Figure 11 provides an opportunity to enhance configuration. During the hold state, in order to decouple the input terminal from the sampling capacitor, the gate of the main sampling switch can be discharged to a potential that is approximately the potential of the main sampling switch body (rather than as shown in Figures 5 through 10). The fixed ground potential shown). Therefore, by preferably using the body biasing side as illustrated by circuit 1100A In this case, the voltage swing on the gate of the main sampling switch is substantially independent of the input signal.

現參照第12圖，第12圖圖示根據本發明原則所建置之可能的特定實施1200。電路1200一般地包含已被類似地編號以標註類似的功能性與一般對應性的部件與功能方塊。例如，電路1200包含輸入節點1215、指令節點1230、控制節點1235、取樣開關1210、取樣電容器1220、控制電路1225、電荷幫浦電路1270、電荷幫浦電壓軌1271以及體極偏壓電路1260等等。Referring now to Figure 12, Figure 12 illustrates a possible implementation 1200 that may be implemented in accordance with the principles of the present invention. Circuitry 1200 generally includes components and functional blocks that have been similarly numbered to indicate similar functionality and general correspondence. For example, the circuit 1200 includes an input node 1215, an instruction node 1230, a control node 1235, a sampling switch 1210, a sampling capacitor 1220, a control circuit 1225, a charge pump circuit 1270, a charge pump voltage rail 1271, and a body bias circuit 1260. Wait.

如圖示，控制電路1225可包含電流鏡電晶體1233與1253以及放電開關1228。額外裝置1232限制跨電流鏡裝置1233的電壓，且額外裝置1232可或不可被包含，取決於裝置1233的操作範圍。電荷產生電路1250可包含經控制的電流源，電流源包含MOSFET電晶體1254與電阻器1255以及時序電路1251。時序電路1251在時序電路1251的控制輸入處被高至低訊號轉變觸發。如先前所說明，藉由大量地減少或消除施加至取樣開關控制節點1235之電壓擺幅的輸入訊號相依性，來進一步減少訊號失真。此係由透過放電開關1228將控制終端1235放電至開關體極終端1209來達成。As shown, control circuit 1225 can include current mirror transistors 1233 and 1253 and discharge switch 1228. The additional device 1232 limits the voltage across the current mirror device 1233, and the additional device 1232 may or may not be included, depending on the operating range of the device 1233. The charge generation circuit 1250 can include a controlled current source including a MOSFET transistor 1254 and a resistor 1255 and a timing circuit 1251. The timing circuit 1251 is triggered by a high to low signal transition at the control input of the timing circuit 1251. As explained previously, signal distortion is further reduced by substantially reducing or eliminating input signal dependencies applied to the voltage swing of the sampling switch control node 1235. This is accomplished by discharging the control terminal 1235 through the discharge switch 1228 to the switch body terminal 1209.

電路1200可進一步包含放電控制電路2226，放電控制電路2226可包含電流鏡電晶體2243與2283以及放電開關2238。額外裝置2242限制跨電流鏡裝置2243的電壓，且額外裝置2242可或不可被包含，取決於裝置2243 的操作範圍。放電控制電荷產生器電路2280可包含經控制的電流源，電流源包含MOSFET電晶體2284與電阻器2285以及時序電路2281。時序電路2281在時序電路2281的控制輸入處由低至高訊號轉變來觸發。Circuitry 1200 can further include a discharge control circuit 2226 that can include current mirror transistors 2243 and 2283 and a discharge switch 2238. The additional device 2242 limits the voltage across the current mirror device 2243, and the additional device 2242 may or may not be included, depending on the device 2243 The scope of operation. The discharge control charge generator circuit 2280 can include a controlled current source comprising a MOSFET transistor 2284 and a resistor 2285 and a timing circuit 2281. The timing circuit 2281 is triggered by a low to high signal transition at the control input of the timing circuit 2281.

類似於第10圖所圖示之電路1100A的電路1200，亦可包含體極偏壓電路1260，該體極偏壓電路1260耦合在取樣開關體極終端1209與取樣系統輸入終端1215之間。電路1260可由電容1262、更新電容器1265、更新開關1263、1264、1266與1267以及邏輯反相器1261組成。The circuit 1200, similar to the circuit 1100A illustrated in FIG. 10, may also include a body bias circuit 1260 coupled between the sampling switch body terminal 1209 and the sampling system input terminal 1215. . Circuitry 1260 can be comprised of capacitor 1262, update capacitor 1265, update switches 1263, 1264, 1266 and 1267, and logic inverter 1261.

電荷幫浦電路1270可或不可被包含，取決於供應電壓V_CP 的有效性，供應電壓V_CP 自身可由特定的實施細節來決定(例如所需的輸入訊號範圍、取樣開關1210的電氣參數等等)。類似於先前所討論的電路，電荷幫浦電路1270之操作可或不可被與呈現在指令節點1230處的保持訊號同步(或甚至被此保持訊號直接控制)。A charge pump circuit 1270 may or may not be included, depending on the effectiveness of the supply voltage V _CP, the specific implementation details of the supply voltage V _CP itself may be determined (e.g., the desired input signal range, the electrical parameters of the sampling switch 1210 and the like ). Similar to the circuits discussed previously, the operation of charge pump circuit 1270 may or may not be synchronized with the hold signal presented at instruction node 1230 (or even directly controlled by this hold signal).

如上文所述，電路1200操作於至少兩個模式：取樣模式與保持模式，並且電路1200可操作如下文。可施加邏輯高訊號至指令節點1230的輸入。此訊號較佳地具有足夠的量值以直接開啟電晶體1267，且亦透過反相器1261開啟電晶體1266。因此，操作於更新週期的第一階段的體極偏壓電路1260，在電容器1265上建立約等於V_BIAS 的電壓，V_BIAS 經選定以對取樣開關1210確保在全輸入訊號範圍中的偏壓條件為正確。As described above, circuit 1200 operates in at least two modes: a sampling mode and a hold mode, and circuit 1200 is operable as follows. A logic high signal can be applied to the input of the instruction node 1230. This signal preferably has a magnitude sufficient to directly turn on the transistor 1267 and also turn on the transistor 1266 through the inverter 1261. Thus, the body bias circuit 1260, operating in the first phase of the update cycle, establishes a voltage on capacitor 1265 that is approximately equal to V _BIAS , and V _BIAS is selected to ensure bias in the full input signal range for sampling switch 1210. The condition is correct.

在進入保持狀態時，受施加至指令終端1230的低至高轉變影響，放電控制電路2226被觸發並且放電控制電路2226提供經界定的電荷量至放電開關1228的閘極，而開啟放電開關1228。此允許主取樣開關1210與更新開關對1263與1264的閘極被放電至主取樣開關體極終端1209的位準。因此，MOSFET 1210關閉，並且MOSFET 1210將節點1215處的輸入訊號與電容器1220斷開，隔離電容器1220，並將電路1200置於保持狀態中。同時，開關對1263與1264關閉，將偏壓電容1262與更新電容器1265隔離。需使開關對1263與1264在裝置1266與1267開啟之前關閉。此舉可由隱含地存在於實體實施中(且未明確地於第12圖中指示)的延遲來達成，並(若為必要)由在裝置1265與1266的控制路徑中引入已知的時序延遲裝置(例如RC電路、邏輯穿越閘等等)來達成。Upon entering the hold state, the discharge control circuit 2226 is triggered by the low to high transition applied to the command terminal 1230, and the discharge control circuit 2226 provides a defined amount of charge to the gate of the discharge switch 1228, and turns on the discharge switch 1228. This allows the gates of the main sampling switch 1210 and the refresh switch pairs 1263 and 1264 to be discharged to the level of the main sampling switch body terminal 1209. Thus, MOSFET 1210 is turned off, and MOSFET 1210 disconnects the input signal at node 1215 from capacitor 1220, isolating capacitor 1220, and places circuit 1200 in a hold state. At the same time, switch pairs 1263 and 1264 are turned off, isolating bias capacitor 1262 from refresh capacitor 1265. Switch pairs 1263 and 1264 need to be closed before devices 1266 and 1267 are turned on. This can be achieved by a delay implicitly present in the entity implementation (and not explicitly indicated in Figure 12), and (if necessary) introduced by known delays in the control paths of devices 1265 and 1266. Devices (such as RC circuits, logic crossing gates, etc.) are achieved.

在保持狀態開始時，在指令節點1230處的低至高轉變觸發，使時序電路2281產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯低至高轉變時所產生之具有相當短持續期間的邏輯高訊號)，短邏輯高脈衝開啟包含電晶體2284與電阻器2285的電流源，並且短邏輯高脈衝允許電流透過由裝置2283與2243形成的電流鏡流入放電電晶體1228的閘極。在預定時間週期之後，單擊2281的輸出返回邏輯低並關閉電流源2284。因此，由電流源裝置2284連同電阻器2285界定，以及由單擊電路2281 的時間常數界定的預定電荷量，被傳遞至裝置1228的閘極。該等元件的每一者可由電路設計者選定，以對電晶體1228確保有所需的開啟狀態阻抗，且因此確保主取樣開關1210與更新開關對1263、1264被適當快速關閉。At the beginning of the hold state, a low-to-high transition at the instruction node 1230 triggers the timing circuit 2281 to generate a short logic high pulse (e.g., a relatively short duration produced when a logic low to high transition at the trigger input is detected). The logic high signal), the short logic high pulse turns on the current source containing the transistor 2284 and the resistor 2285, and the short logic high pulse allows current to flow into the gate of the discharge transistor 1228 through the current mirror formed by the devices 2283 and 2243. After a predetermined period of time, click on the output of 2281 to return to logic low and turn off current source 2284. Thus, defined by current source device 2284 along with resistor 2285, and by click circuit 2281 The predetermined amount of charge defined by the time constant is passed to the gate of device 1228. Each of these elements can be selected by the circuit designer to ensure that the transistor 1228 has the desired on-state impedance and thus ensures that the main sampling switch 1210 and the update switch pair 1263, 1264 are properly turned off quickly.

裝置2238被選定而使得在約等於V_BIAS 的電壓被施加於裝置2238閘極與源極終端之間時，裝置2238允許由放電控制電荷產生器電路2280所提供的電荷開啟電晶體1228並適當地將控制節點1235放電。在同時，裝置2238需能夠在保持狀態結束之前，從裝置1228的閘極移除恰於先前被注入的電荷。Device 2238 is selected such that when a voltage approximately equal to V _BIAS is applied between the gate and source terminals of device 2238, device 2238 allows the charge provided by discharge control charge generator circuit 2280 to turn on transistor 1228 and appropriately The control node 1235 is discharged. At the same time, device 2238 needs to be able to remove the charge that was previously injected from the gate of device 1228 before the end of the hold state.

為了從保持狀態轉變成取樣狀態，在指令節點1230處的保持訊號可從邏輯高被切換至邏輯低。此直接關閉電晶體1267，並透過反相器1261關閉電晶體1266。此亦使時序電路1251產生短邏輯高脈衝(例如在偵測到於觸發輸入處的邏輯高至低轉變時所產生之具有相當短持續期間的邏輯高訊號)。此脈衝開啟包含電晶體1254與電阻器1255的電流源，並且此脈衝允許電流透過由電晶體1253與1233形成的電流鏡，經由路徑1235流入開關1210的閘極。此電荷開啟開關1210，允許電容器1220獲取輸入訊號。In order to transition from the hold state to the sample state, the hold signal at the command node 1230 can be switched from logic high to logic low. This directly turns off the transistor 1267 and turns off the transistor 1266 through the inverter 1261. This also causes the timing circuit 1251 to generate a short logic high pulse (e.g., a logic high signal having a relatively short duration generated when a logic high to low transition at the trigger input is detected). This pulse turns on a current source comprising transistor 1254 and resistor 1255, and this pulse allows current to flow through the current mirror formed by transistors 1253 and 1233, flowing into the gate of switch 1210 via path 1235. This charge turns on the switch 1210, allowing the capacitor 1220 to take an input signal.

經界定的電荷量亦流入更新開關對1263、1264的閘極，開啟更新開關對1263、1264並將更新電容器1265耦合至偏壓電容1262。The defined amount of charge also flows into the gates of the refresh switch pair 1263, 1264, turns on the update switch pair 1263, 1264, and couples the update capacitor 1265 to the bias capacitor 1262.

如上文所述，傳遞至電晶體1210、1263與1264閘極 的電荷量，係相依於由電晶體1254連同電阻器1255與單擊1251之時間常數所產生的電流，以上之每一者可由電路設計者選定，以對電晶體120與更新開關對1263、1264確保所需的開啟狀態阻抗。再者，在一些具體實施例中，單擊1251(及/或單擊2281)的時間常數，可由終端使用者使用已知的技術來選定(例如藉由耦合具有電阻器及/或電容器的外部網路)。在替代性具體實施例中，單擊1251(及/或單擊2281)的時間常數可被使用已知的複製與比例控制電路技術選定，以適應性地追蹤半導體製程參數及/或環境參數(諸如溫度、電力供應電壓等等)。Passed to the gates of transistors 1210, 1263 and 1264 as described above The amount of charge is dependent on the current generated by the transistor 1254 along with the resistor 1255 and the time constant of the click 1251, each of which can be selected by the circuit designer to pair the transistor 120 with the update switch pair 1263, 1264. Ensure the required on-state impedance. Moreover, in some embodiments, the time constant of clicking 1251 (and/or clicking 2281) may be selected by the end user using known techniques (eg, by coupling an external with a resistor and/or capacitor) network). In an alternative embodiment, the time constant of clicking 1251 (and/or clicking 2281) may be selected using known replication and proportional control circuit techniques to adaptively track semiconductor process parameters and/or environmental parameters ( Such as temperature, power supply voltage, etc.).

電路1200使用時序電路(1251與2281)與流過電流鏡(1253、1233與2283、2243)之以電阻性為基礎的電流源(1254、1255與2284、2285)，來產生用以控制取樣開關1210、更新開關對1263、1264與放電開關1228的預定電荷。在本發明領域中具有通常知識者將認知到，取決於特定的應用，可使用其他電荷產生方案以作為電路600與900所採用的方案(作為實例而不為限制)。Circuitry 1200 uses sequential circuits (1251 and 2281) and resistive-based current sources (1254, 1255 and 2284, 2285) that flow through current mirrors (1253, 1233 and 2283, 2243) to generate sampling switches. 1210. Update the predetermined charge of the switch pair 1263, 1264 and the discharge switch 1228. Those of ordinary skill in the art will recognize that other charge generation schemes can be used as the scheme employed by circuits 600 and 900 (as an example and not by way of limitation), depending on the particular application.

雖然已由連接至其他電路的各種電路揭示了本發明的較佳具體實施例，在本發明領域中具有通常知識者將瞭解此種連接並不需為直接的，且額外電路可交互連接於所圖示的所連接電路之間，而不脫離如圖示之本發明的精神。在本發明領域中具有通常知識者亦將瞭解，本發明可由除了所特定說明之具體實施例以外的具體實施例 來實現。所說明的具體實施例係用於圖示說明之目的而呈現，並非做為限制，而本發明係僅由下列申請專利範圍來限制。Although the preferred embodiment of the present invention has been disclosed by various circuits connected to other circuits, those of ordinary skill in the art will appreciate that such a connection need not be straightforward and that additional circuitry may be interconnected Between the connected circuits shown, without departing from the spirit of the invention as illustrated. It will also be apparent to those skilled in the art that the present invention may be embodied in a specific embodiment other than the specific embodiments described. to realise. The specific embodiments described are presented for purposes of illustration and not limitation.

100‧‧‧先前技術取樣保持電路100‧‧‧Previous technical sample-and-hold circuit

110‧‧‧開關110‧‧‧ switch

115‧‧‧輸入終端115‧‧‧Input terminal

120‧‧‧取樣電容器120‧‧‧Sampling capacitor

125‧‧‧控制電路125‧‧‧Control circuit

130‧‧‧指令終端130‧‧‧Command terminal

135‧‧‧控制終端135‧‧‧Control terminal

210‧‧‧開關210‧‧‧ switch

215‧‧‧輸入訊號215‧‧‧ Input signal

220‧‧‧取樣電容器220‧‧‧Sampling capacitor

225‧‧‧控制電路225‧‧‧Control circuit

230‧‧‧外部保持訊號230‧‧‧External hold signal

235‧‧‧控制終端235‧‧‧Control terminal

310‧‧‧開關310‧‧‧Switch

315‧‧‧輸入終端315‧‧‧ input terminal

320‧‧‧取樣電容器320‧‧‧Sampling capacitor

325‧‧‧控制電路325‧‧‧Control circuit

528‧‧‧開關528‧‧‧Switch

335‧‧‧閘極終端335‧‧ ‧ gate terminal

340‧‧‧體極終端340‧‧‧ body terminal

345‧‧‧緩衝器345‧‧‧buffer

400‧‧‧取樣電路400‧‧‧Sampling circuit

410‧‧‧取樣開關410‧‧‧Sampling switch

415‧‧‧輸入終端415‧‧‧ input terminal

420‧‧‧儲存部件420‧‧‧Storage parts

425‧‧‧控制電路425‧‧‧Control circuit

430‧‧‧指令節點430‧‧‧ instruction node

435‧‧‧控制終端435‧‧‧Control terminal

500‧‧‧取樣電路500‧‧‧Sampling circuit

510‧‧‧取樣開關510‧‧‧Sampling switch

511‧‧‧閘極對通道電容511‧‧‧ gate-to-channel capacitance

512‧‧‧寄生電容512‧‧‧Parasitic capacitance

515‧‧‧輸入終端515‧‧‧ input terminal

520‧‧‧儲存電容器520‧‧‧Storage capacitor

525‧‧‧控制電路525‧‧‧Control circuit

530‧‧‧指令節點530‧‧‧ instruction node

535‧‧‧控制節點535‧‧‧Control node

551‧‧‧時序電路551‧‧‧Sequence circuit

554‧‧‧經控制電流源554‧‧‧Controlled current source

570‧‧‧電荷幫浦電路570‧‧‧ Charge pump circuit

651‧‧‧時序電路651‧‧‧Sequence circuit

600‧‧‧取樣電路600‧‧‧Sampling circuit

610‧‧‧取樣開關610‧‧‧Sampling switch

611‧‧‧閘極對通道電容611‧‧‧ gate-to-channel capacitance

612‧‧‧寄生電容612‧‧‧Parasitic capacitance

615‧‧‧輸入終端615‧‧‧ input terminal

620‧‧‧電容器620‧‧‧ capacitor

625‧‧‧控制電路625‧‧‧Control circuit

628‧‧‧放電開關628‧‧‧Discharge switch

629‧‧‧額外裝置629‧‧‧Additional device

630‧‧‧指令節點630‧‧‧ instruction node

631‧‧‧電荷轉移開關631‧‧‧ Charge Transfer Switch

632‧‧‧額外裝置632‧‧‧Additional device

635‧‧‧控制節點635‧‧‧Control node

650‧‧‧電荷產生器650‧‧‧Charge generator

656‧‧‧連接成電容器的電晶體656‧‧‧Connected into a capacitor transistor

657‧‧‧開關657‧‧‧Switch

658‧‧‧開關658‧‧‧Switch

659‧‧‧連接成電容器的電晶體659‧‧‧Connected into a capacitor transistor

670‧‧‧電荷幫浦電路670‧‧‧ Charge pump circuit

671‧‧‧電壓軌671‧‧‧ voltage rail

700‧‧‧取樣電路700‧‧‧Sampling circuit

710‧‧‧取樣開關710‧‧‧Sampling switch

715‧‧‧輸入訊號節點715‧‧‧Input signal node

716‧‧‧初始化電晶體716‧‧‧Initializing the transistor

717‧‧‧初始化電晶體717‧‧‧ Initializing the transistor

720‧‧‧電容器720‧‧‧ capacitor

725‧‧‧控制電路725‧‧‧Control circuit

726‧‧‧初始化控制電路726‧‧‧Initialization control circuit

728‧‧‧放電開關728‧‧‧Discharge switch

729‧‧‧額外裝置729‧‧‧Additional devices

730‧‧‧指令節點730‧‧‧ instruction node

731‧‧‧電荷傳送開關731‧‧‧Charge transfer switch

732‧‧‧額外裝置732‧‧‧Additional device

741‧‧‧電荷傳送開關741‧‧‧Charge transfer switch

742‧‧‧放電開關742‧‧‧Discharge switch

750‧‧‧電荷產生器電路750‧‧‧charge generator circuit

751‧‧‧時序電路751‧‧‧Sequence circuit

752‧‧‧反相器752‧‧‧Inverter

756‧‧‧連接成電容器的電晶體756‧‧‧Connected into a capacitor transistor

757‧‧‧開關757‧‧‧Switch

758‧‧‧開關758‧‧‧ switch

759‧‧‧連接成電容器的電晶體759‧‧‧Transistors connected to capacitors

770‧‧‧電荷幫浦電路770‧‧‧ Charge pump circuit

771‧‧‧電壓軌771‧‧‧ voltage rail

780‧‧‧初始化電荷產生器電路780‧‧‧Initialization of the charge generator circuit

781‧‧‧單擊電路781‧‧‧Click circuit

782‧‧‧反相器782‧‧‧Inverter

786‧‧‧連接成電容器的電晶體786‧‧‧Connected into a capacitor transistor

787‧‧‧開關787‧‧‧ switch

788‧‧‧開關788‧‧‧ switch

789‧‧‧連接成電容器的電晶體789‧‧‧Connected into a capacitor transistor

800‧‧‧取樣電路800‧‧‧Sampling circuit

810‧‧‧取樣開關810‧‧‧Sampling switch

815‧‧‧輸入訊號節點815‧‧‧Input signal node

816‧‧‧閘極初始化電晶體816‧‧‧gate initializing transistor

817‧‧‧閘極初始化電晶體817‧‧‧ Gate Initialization Transistor

820‧‧‧電容器820‧‧‧ capacitor

826‧‧‧初始化控制電路826‧‧‧Initialization control circuit

828‧‧‧放電開關828‧‧‧Discharge switch

829‧‧‧額外裝置829‧‧‧Additional devices

830‧‧‧指令節點830‧‧‧ instruction node

832‧‧‧額外裝置832‧‧‧Additional devices

833‧‧‧電流鏡電晶體833‧‧‧current mirror transistor

835‧‧‧控制終端835‧‧‧Control terminal

836‧‧‧初始化控制終端836‧‧‧Initial control terminal

838‧‧‧開關838‧‧‧ switch

839‧‧‧額外裝置839‧‧‧Additional devices

842‧‧‧額外裝置842‧‧‧Additional devices

843‧‧‧電流鏡電晶體843‧‧‧current mirror transistor

850‧‧‧電荷產生器電路850‧‧‧Charge generator circuit

851‧‧‧時序電路851‧‧‧Sequence circuit

853‧‧‧電流鏡電晶體853‧‧‧current mirror transistor

854‧‧‧電流源854‧‧‧current source

855‧‧‧電阻器855‧‧‧Resistors

870‧‧‧電荷幫浦電路870‧‧‧ Charge pump circuit

825‧‧‧控制電路825‧‧‧Control circuit

880‧‧‧初始化脈衝產生電路880‧‧‧Initialization pulse generation circuit

881‧‧‧時序電路881‧‧‧Sequence circuit

882‧‧‧反相器882‧‧‧Inverter

883‧‧‧電流鏡電晶體883‧‧‧current mirror transistor

884‧‧‧電流源884‧‧‧current source

885‧‧‧電阻器885‧‧‧Resistors

900‧‧‧取樣電路900‧‧‧Sampling circuit

910‧‧‧取樣開關910‧‧‧Sampling switch

915‧‧‧輸入訊號節點915‧‧‧Input signal node

916‧‧‧閘極初始化電晶體916‧‧‧gate initializing transistor

917‧‧‧閘極初始化電晶體917‧‧‧gate initializing transistor

920‧‧‧取樣電容器920‧‧‧Sampling capacitor

925‧‧‧控制電路925‧‧‧Control circuit

928‧‧‧放電開關928‧‧‧Discharge switch

926‧‧‧初始化控制電路926‧‧‧Initialization control circuit

930‧‧‧指令節點930‧‧‧ instruction node

935‧‧‧控制路徑935‧‧‧Control path

936‧‧‧初始化控制終端936‧‧‧Initial control terminal

938‧‧‧放電開關938‧‧‧Discharge switch

940‧‧‧充電電路940‧‧‧Charging circuit

941‧‧‧反相器941‧‧‧Inverter

942‧‧‧位準移位電容器942‧‧‧bit displacement capacitor

943‧‧‧位準移位電容器943‧‧‧bit displacement capacitor

944‧‧‧電晶體944‧‧‧Optoelectronics

945‧‧‧電晶體945‧‧‧Optoelectronics

946‧‧‧充電開關946‧‧‧Charge switch

947‧‧‧充電開關947‧‧‧Charge switch

950‧‧‧電荷產生器電路950‧‧‧Charge generator circuit

951‧‧‧單擊電路951‧‧‧Click circuit

952‧‧‧反相器952‧‧‧Inverter

954‧‧‧電流源電晶體954‧‧‧current source transistor

955‧‧‧位準移位電容器955‧‧‧bit displacement capacitor

970‧‧‧電荷幫浦電路970‧‧‧ Charge pump circuit

1070‧‧‧電荷幫浦電路1070‧‧‧ Charge pump circuit

980‧‧‧初始化電荷產生電路980‧‧‧Initialization of charge generation circuit

981‧‧‧單擊電路981‧‧‧Click circuit

982‧‧‧反相器982‧‧‧Inverter

984‧‧‧電流源電晶體984‧‧‧current source transistor

985‧‧‧位準移位電容器985‧‧‧ position shift capacitor

1000‧‧‧取樣電路1000‧‧‧Sampling circuit

1010‧‧‧取樣開關1010‧‧‧Sampling switch

1015‧‧‧輸入訊號節點1015‧‧‧Input signal node

1016‧‧‧閘極初始化電晶體1016‧‧‧ Gate Initialization Transistor

1017‧‧‧閘極初始化電晶體1017‧‧‧ Gate Initialization Transistor

1020‧‧‧取樣電容器1020‧‧‧Sampling capacitor

1028‧‧‧放電電晶體1028‧‧‧Discharge transistor

1030‧‧‧指令節點1030‧‧‧ instruction node

1036‧‧‧初始化控制節點1036‧‧‧Initialization Control Node

1038‧‧‧電晶體1038‧‧‧Optoelectronics

1026‧‧‧初始化控制電路1026‧‧‧Initialization control circuit

1035‧‧‧控制路徑1035‧‧‧Control path

1025‧‧‧控制電路1025‧‧‧Control circuit

1040‧‧‧充電電路1040‧‧‧Charging circuit

1041‧‧‧反相器1041‧‧‧Inverter

1042‧‧‧位準移位電容器1042‧‧‧bit displacement capacitor

1043‧‧‧位準移位電容器1043‧‧‧bit displacement capacitor

1044‧‧‧電晶體1044‧‧‧Optoelectronics

1045‧‧‧電晶體1045‧‧‧Optoelectronics

1046‧‧‧充電開關1046‧‧‧Charge switch

1047‧‧‧充電開關1047‧‧‧Charge switch

1050‧‧‧電荷產生器電路1050‧‧‧Charge generator circuit

1051‧‧‧時序電路1051‧‧‧Sequence circuit

1052‧‧‧反相器1052‧‧‧Inverter

1054‧‧‧電流源電晶體1054‧‧‧current source transistor

1055‧‧‧位準移位電容器1055‧‧‧bit displacement capacitor

1080‧‧‧初始化電荷產生器電路1080‧‧‧Initialization of the charge generator circuit

1081‧‧‧單擊1081‧‧‧Click

1082‧‧‧反相器1082‧‧‧Inverter

1084‧‧‧電流源1084‧‧‧current source

1085‧‧‧位準移位電容器1085‧‧‧bit displacement capacitor

1090‧‧‧補償電路1090‧‧‧Compensation circuit

1091‧‧‧連接成電容器的裝置1091‧‧‧Devices connected as capacitors

1092‧‧‧連接成電容器的裝置1092‧‧‧Devices connected as capacitors

1093‧‧‧耦合電容器1093‧‧‧Coupling capacitor

1094‧‧‧電流源電晶體1094‧‧‧current source transistor

1095‧‧‧平方律裝置1095‧‧‧ square law device

1096‧‧‧初始化電晶體1096‧‧‧ Initializing the transistor

1097‧‧‧初始化電晶體1097‧‧‧ Initializing the transistor

1098‧‧‧重置裝置1098‧‧‧Reset device

1099‧‧‧放電電晶體1099‧‧‧discharge transistor

1100A‧‧‧取樣電路1100A‧‧‧Sampling circuit

1109‧‧‧體極終端1109‧‧‧ body terminal

1110‧‧‧取樣開關1110‧‧‧Sampling switch

1115‧‧‧輸入終端1115‧‧‧Input terminal

1120‧‧‧取樣電容器1120‧‧‧Sampling capacitor

1125‧‧‧控制電路1125‧‧‧Control circuit

1135‧‧‧控制訊號節點1135‧‧‧Control signal node

1160‧‧‧體極偏壓電路1160‧‧‧ body pole bias circuit

1162‧‧‧電容器1162‧‧‧ capacitor

1163‧‧‧開關1163‧‧‧Switch

1164‧‧‧開關1164‧‧‧Switch

1165‧‧‧電容器1165‧‧‧ capacitor

1166‧‧‧開關1166‧‧‧ switch

1167‧‧‧開關1167‧‧‧Switch

1100B‧‧‧取樣電路1100B‧‧‧Sampling circuit

1200‧‧‧取樣電路1200‧‧‧Sampling circuit

1209‧‧‧開關體極終端1209‧‧‧Switch body terminal

1210‧‧‧取樣開關1210‧‧‧Sampling switch

1215‧‧‧輸入節點1215‧‧‧Input node

1220‧‧‧取樣電容器1220‧‧‧Sampling capacitor

1225‧‧‧控制電路1225‧‧‧Control circuit

1228‧‧‧放電開關1228‧‧‧Discharge switch

1230‧‧‧指令節點1230‧‧‧ instruction node

1232‧‧‧額外裝置1232‧‧‧Additional device

1233‧‧‧電流鏡電晶體1233‧‧‧current mirror transistor

1235‧‧‧控制節點1235‧‧‧Control node

1250‧‧‧電荷產生電路1250‧‧‧Charge generation circuit

1251‧‧‧時序電路1251‧‧‧Sequence Circuit

1253‧‧‧電流鏡電晶體1253‧‧‧current mirror transistor

1254‧‧‧MOSFET電晶體1254‧‧‧MOSFET MOS

1255‧‧‧電阻器1255‧‧‧Resistors

1260‧‧‧體極偏壓電路1260‧‧‧ body pole bias circuit

1261‧‧‧反相器1261‧‧‧Inverter

1262‧‧‧偏壓電容1262‧‧‧ bias capacitor

1263‧‧‧開關1263‧‧‧Switch

1264‧‧‧開關1264‧‧‧Switch

1265‧‧‧更新電容器1265‧‧‧Update capacitor

1266‧‧‧電晶體1266‧‧‧Optoelectronics

1267‧‧‧電晶體1267‧‧‧Optoelectronics

1270‧‧‧電荷幫浦電路1270‧‧‧ Charge pump circuit

1271‧‧‧電壓軌1271‧‧‧ voltage rail

2226‧‧‧放電控制電路2226‧‧‧Discharge control circuit

2285‧‧‧電阻器2285‧‧‧Resistors

2238‧‧‧放電開關2238‧‧‧Discharge switch

2242‧‧‧額外裝置2242‧‧‧Additional devices

2243‧‧‧電流鏡電晶體2243‧‧‧current mirror transistor

2280‧‧‧放電控制電荷產生器電路2280‧‧‧Discharge Control Charge Generator Circuit

2281‧‧‧時序電路2281‧‧‧Sequence Circuit

2283‧‧‧電流鏡電晶體2283‧‧‧current mirror transistor

2284‧‧‧MOSFET電晶體2284‧‧‧MOSFET MOS

Q_P ‧‧‧預定電荷Q _P ‧‧‧Predetermined charge

VDD‧‧‧電力供應電壓VDD‧‧‧Power supply voltage

V_CP ‧‧‧供應電壓V _CP ‧‧‧ supply voltage

V_BIAS ‧‧‧偏壓電壓V _BIAS ‧‧‧ bias voltage

I_P ‧‧‧輸出電流I _P ‧‧‧Output current

T_P ‧‧‧持續時間T _P ‧‧‧ duration

本發明之上述與其他的目標與優點，將隨著連同附加圖式考量前述實施方式而顯然，在附加圖式中類似的元件符號代表所有圖式中類似的零件，且其中：第1圖為先前技術取樣保持電路的示意圖；第2圖為另一先前技術取樣保持電路的示意圖；第3圖為另一先前技術取樣保持電路的示意圖；第4圖為根據本發明原則所建置之取樣保持電路的一個具體實施例的概括示意圖；第5圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的示意圖；第6圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖；第7圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖；第8圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖；第9圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖； 第10圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖；第11圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的概括示意圖；且第12圖為根據本發明原則所建置之取樣保持電路的另一具體實施例的較詳細示意圖。The above and other objects and advantages of the present invention will be apparent from the description of the appended claims. A schematic diagram of a prior art sample and hold circuit; FIG. 2 is a schematic diagram of another prior art sample and hold circuit; FIG. 3 is a schematic diagram of another prior art sample and hold circuit; and FIG. 4 is a sample hold constructed in accordance with the principles of the present invention. A schematic diagram of a specific embodiment of a circuit; FIG. 5 is a schematic diagram of another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention; and FIG. 6 is a sample and hold circuit constructed in accordance with the principles of the present invention. A more detailed schematic diagram of another embodiment; FIG. 7 is a more detailed schematic diagram of another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention; and FIG. 8 is a sample hold constructed in accordance with the principles of the present invention. A more detailed schematic diagram of another embodiment of a circuit; FIG. 9 is another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention. A detailed schematic; Figure 10 is a more detailed schematic diagram of another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention; and Figure 11 is a schematic illustration of another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention. And Figure 12 is a more detailed schematic diagram of another embodiment of a sample and hold circuit constructed in accordance with the principles of the present invention.

400‧‧‧取樣電路400‧‧‧Sampling circuit

410‧‧‧取樣開關410‧‧‧Sampling switch

415‧‧‧輸入終端415‧‧‧ input terminal

420‧‧‧儲存部件420‧‧‧Storage parts

425‧‧‧控制電路425‧‧‧Control circuit

430‧‧‧指令節點430‧‧‧ instruction node

435‧‧‧控制終端435‧‧‧Control terminal

Claims (14)

一種減少一取樣電路中的訊號失真的方法，該方法包含以下步驟：耦合一半導體開關於一輸入訊號源與一輸出節點之間；耦合一可控制電荷源至該半導體開關的一控制節點；耦合一控制電路至該可控制電荷源，以選擇性地開啟與關閉該可控制電荷電路；及選擇性提供步驟，選擇性提供一電荷至該半導體開關的該控制節點，該電荷係實質上等於或大於在該半導體開關被開啟時，該半導體開關的該控制節點吸收的一能源量，而使該半導體開關的一阻抗被維持為實質上固定。 A method for reducing signal distortion in a sampling circuit, the method comprising the steps of: coupling a semiconductor switch between an input signal source and an output node; coupling a control charge source to a control node of the semiconductor switch; coupling a control circuit to the controllable charge source to selectively turn the controllable charge circuit on and off; and an optional providing step of selectively providing a charge to the control node of the semiconductor switch, the charge system being substantially equal to or And greater than an amount of energy absorbed by the control node of the semiconductor switch when the semiconductor switch is turned on, such that an impedance of the semiconductor switch is maintained substantially constant. 如請求項1所述之方法，其中該可控制電荷源與該控制電路係獨立於該輸入訊號。 The method of claim 1, wherein the controllable charge source and the control circuit are independent of the input signal. 如請求項1所述之方法，其中該選擇性提供步驟進一步包含以下步驟：配置該可控制電荷源為一值，該值係實質上等於或大於由一閘極對通道電容吸收的該能源量。 The method of claim 1, wherein the selectively providing step further comprises the step of configuring the controllable charge source to a value that is substantially equal to or greater than the amount of energy absorbed by a gate to channel capacitance. . 如請求項3所述之方法，其中該選擇性提供步驟進一步包含以下步驟：耦合該可控制電荷源至該半導體開關的該控制節點，以開啟該半導體開關。 The method of claim 3, wherein the selectively providing step further comprises the step of coupling the controllable charge source to the control node of the semiconductor switch to turn on the semiconductor switch. 如請求項4所述之方法，其中該選擇性提供步驟進一步包含以下步驟：維持施加至該控制節點的該電荷，以將該半導體開關維持為開啟。 The method of claim 4, wherein the selectively providing step further comprises the step of maintaining the charge applied to the control node to maintain the semiconductor switch on. 如請求項4所述之方法，其中施加至該控制節點以維持該半導體開關的該電荷，相對於該輸入訊號為實質上固定。 The method of claim 4 wherein the charge applied to the control node to maintain the semiconductor switch is substantially fixed relative to the input signal. 如請求項1所述之方法，其中該選擇性提供步驟進一步包含以下步驟：提供一電荷至該半導體開關的該控制節點，該電荷實質上等於或大於由該控制節點的一閘極對通道電容以及在對於該控制節點的一傳輸路徑中遭遇到的任何寄生電容所吸收的該能源量。 The method of claim 1, wherein the selectively providing step further comprises the step of providing a charge to the control node of the semiconductor switch, the charge being substantially equal to or greater than a gate-to-channel capacitance of the control node And the amount of energy absorbed by any parasitic capacitance encountered in a transmission path for the control node. 一種用於減少一取樣電路中的訊號失真的電路，該電路包含：一半導體開關，該半導體開關耦合於一輸入訊號源與一輸出節點之間；一可控制電荷源，該可控制電荷源耦合至該半導體開關的一控制節點； 一可控制電荷電路，該可控制電荷電路耦合於該輸入訊號源與該可控制電荷源之間；一控制電路，該控制電路耦合至該可控制電荷源並經配置以：選擇性地開啟與關閉該可控制電荷電路；及選擇性地提供一電荷至該半導體開關的該控制節點，該電荷係實質上等於或大於在該半導體開關被開啟時，該半導體開關的該控制節點吸收的一能源量，而使該半導體開關的一阻抗被維持為實質上固定。 A circuit for reducing signal distortion in a sampling circuit, the circuit comprising: a semiconductor switch coupled between an input signal source and an output node; a controllable charge source, the controllable charge source coupling To a control node of the semiconductor switch; a controllable charge circuit coupled between the input signal source and the controllable charge source; a control circuit coupled to the controllable charge source and configured to: selectively turn on Turning off the controllable charge circuit; and selectively providing a charge to the control node of the semiconductor switch, the charge system being substantially equal to or greater than an energy absorbed by the control node of the semiconductor switch when the semiconductor switch is turned on The amount is such that an impedance of the semiconductor switch is maintained substantially constant. 如請求項8所述之電路，其中該可控制電荷源與該控制電路經配置為獨立於該輸入訊號。 The circuit of claim 8, wherein the controllable charge source and the control circuit are configured to be independent of the input signal. 如請求項8所述之電路，其中該可控制電荷源具有一值，該值係實質上等於或大於由一閘極對通道電容吸收的該能源量。 The circuit of claim 8 wherein the controllable charge source has a value that is substantially equal to or greater than the amount of energy absorbed by a gate to channel capacitance. 如請求項10所述之電路，其中該可控制電荷源經配置為耦合至該半導體開關的該控制節點，以開啟該半導體開關。 The circuit of claim 10, wherein the controllable charge source is configured to be coupled to the control node of the semiconductor switch to turn on the semiconductor switch. 如請求項11所述之電路，其中該控制電路經配置以維持施加至該控制節點的該電荷，以將該半導體開關維持為開啟。 The circuit of claim 11, wherein the control circuit is configured to maintain the charge applied to the control node to maintain the semiconductor switch open. 如請求項11所述之電路，其中該控制電路經配置以施加一電荷至該控制節點，該電荷相對於該輸入訊號為實質上固定。 The circuit of claim 11, wherein the control circuit is configured to apply a charge to the control node, the charge being substantially fixed relative to the input signal. 如請求項8所述之電路，其中該控制電路經配置以提供一電荷至該半導體開關的該控制節點，該電荷實質上等於或大於由該控制節點的一閘極對通道電容以及在對於該控制節點的一傳輸路徑中遭遇到的任何寄生電容所吸收的該能源量。 The circuit of claim 8 wherein the control circuit is configured to provide a charge to the control node of the semiconductor switch, the charge being substantially equal to or greater than a gate-to-channel capacitance of the control node and The amount of energy absorbed by any parasitic capacitance encountered in a transmission path of the control node.