TWI509709B - Manufacturing method for semiconductor structures - Google Patents
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本發明有關於一種半導體結構之製作方法，尤指一種可同時完成不同尺寸的半導體結構之製作方法。The invention relates to a method for fabricating a semiconductor structure, in particular to a method for fabricating semiconductor structures of different sizes at the same time.
當元件發展至65奈米技術世代後，使用傳統平面式的金氧半導體(metal-oxide-semiconductor，MOS)電晶體製程係難以持續微縮，因此，習知技術係提出以立體或非平面(non-planar)多閘極電晶體元件如鰭式場效電晶體(Fin Field effect transistor，FinFET)元件取代平面電晶體元件之解決途徑。After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a Fin Field effect transistor (FinFET) component replaces a planar transistor component.
請參閱第1圖，第1圖係為一習知FinFET元件之立體示意圖。如第1圖所示，習知FinFET元件100係先利用蝕刻等方式圖案化一矽覆絕緣(silicon-on-insulator，SOI)基板102表面之單晶矽層，以於矽覆絕緣基板102中形成一鰭片狀的矽薄膜(圖未示)，並於矽薄膜上形成包覆部分矽薄膜的絕緣層104，而閘極106係包覆絕緣層104與矽薄膜上，最後再藉由離子佈植製程與回火製程等步驟於未被閘極106包覆之鰭片狀的矽薄膜中形成源極/汲極108。由於FinFET元件100的製程能與傳統的邏輯元件製程整合，因此具有相當的製程相容性。此外，當FinFET元件100設置於如第1圖所示之SOI基底102上時，傳統隔離技術如淺溝隔離(shallow trench isolation)等係可省卻。更重要的是，由於FinFET元件100的立體結構增加了閘極106與鰭片狀之矽基體的接觸面積，因此可增加閘極106對於通道區域的載子控制，從而降低小尺寸元件面臨的由源極引發的能帶降低(drain induced barrier lowering，DIBL)效應以及短通道效應(short channel effect)。此外，由於FinFET元件100中同樣長度的閘極106具有更大的通道寬度，因此可獲得加倍的汲極驅動電流。Please refer to FIG. 1 , which is a perspective view of a conventional FinFET device. As shown in FIG. 1 , the conventional FinFET device 100 firstly patterns a single crystal germanium layer on the surface of a silicon-on-insulator (SOI) substrate 102 by etching or the like to coat the insulating substrate 102. Forming a fin-shaped germanium film (not shown), and forming an insulating layer 104 covering a portion of the germanium film on the germanium film, and the gate 106 is coated on the insulating layer 104 and the germanium film, and finally by ion The steps of the implantation process and the tempering process form a source/drain 108 in the fin-shaped germanium film not covered by the gate 106. Since the process of the FinFET device 100 can be integrated with a conventional logic device process, it has considerable process compatibility. Further, when the FinFET element 100 is disposed on the SOI substrate 102 as shown in Fig. 1, conventional isolation techniques such as shallow trench isolation can be omitted. More importantly, since the three-dimensional structure of the FinFET element 100 increases the contact area of the gate 106 with the fin-shaped germanium substrate, the carrier control of the gate 106 for the channel region can be increased, thereby reducing the size of the small-sized component. The source induced induced drain induced barrier lowering (DIBL) effect and the short channel effect. Furthermore, since the gate 106 of the same length in the FinFET element 100 has a larger channel width, a doubled drain drive current can be obtained.
雖然FinFET元件100可獲得較高的汲極驅動電流，但FinFET元件100仍然面對許多待解決的問題。舉例來說，基底102上可能包含各種尺寸大小不同的半導體結構，而構成精細圖案(fine pattern)(如FinFET元件的鰭片結構)或大圖案(large pattern)，但在習知技術中該等不同尺寸的圖案必需以不同的製程完成。因此，目前仍需要可於基底上同時製作尺寸不同的半導體結構之製作方法，亦即仍需要可將精細圖案與大圖案整合的製作方法。While the FinFET component 100 can achieve higher drain drive currents, the FinFET component 100 still faces many problems to be solved. For example, the substrate 102 may include semiconductor structures of various sizes and different sizes to form a fine pattern (such as a fin structure of a FinFET element) or a large pattern, but in the prior art, such Different sized patterns must be completed in different processes. Therefore, there is still a need for a method of fabricating semiconductor structures of different sizes simultaneously on a substrate, that is, a method of fabricating a fine pattern and a large pattern is still required.
因此，本發明之一目的係在於提供一可整合具有不同尺寸的半導體結構的製作方法。Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor structure having different sizes.
根據本發明所提供之申請專利範圍，係提供一種半導體結構之製作方法，該製作方法首先提供一基底，該基底上定義有一第一區域與一第二區域。隨後，於該第一區域內形成複數個第一圖案，同時於該第二區域內形成至少一個第二圖案。而在形成該等第一圖案與該第二圖案之後，於該等第一圖案之側壁與該第二圖案之側壁分別形成複數個第一側壁子與至少一第二側壁子。接下來，於該第二區域內形成一圖案化保護層。之後移除該第一區域內之該等第一圖案，以於該第一區域內形成複數個第一遮罩圖案與於該第二區域內形成至少一第二遮罩圖案。在形成該等第一遮罩圖案與該第二遮罩圖案之後，係轉移該等第一遮罩圖案與該第二遮罩圖案至該基底，而於該第一區域內形成複數個第一半導體結構與於該第二區域內形成至少一個第二半導體結構。According to the scope of the invention provided by the present invention, a method of fabricating a semiconductor structure is provided, which first provides a substrate having a first region and a second region defined thereon. Subsequently, a plurality of first patterns are formed in the first region while at least one second pattern is formed in the second region. After forming the first pattern and the second pattern, a plurality of first sidewalls and at least one second sidewall are formed on sidewalls of the first pattern and sidewalls of the second pattern, respectively. Next, a patterned protective layer is formed in the second region. And removing the first patterns in the first region to form a plurality of first mask patterns in the first region and at least one second mask pattern in the second region. After forming the first mask pattern and the second mask pattern, transferring the first mask pattern and the second mask pattern to the substrate, and forming a plurality of firsts in the first region The semiconductor structure forms at least one second semiconductor structure in the second region.
根據本發明所提供的半導體結構之製作方法，係於預定形成大圖案的第二區域內形成圖案化保護層，用以保護寬度較大的第二遮罩圖案。因此在製作寬度較小的第一遮罩圖案時，第二遮罩圖案係受到圖案化保護層的保護而不致受到影響。待第一遮罩圖案製作完成之後，係將具有較小寬度的第一遮罩圖案與具有較大寬度的第二遮罩圖案同時轉移至該基底上，是以可同時完成具有較小尺寸的第一半導體結構與具有較大尺寸的第二半導體結構。換句話說，本發明所提供之半導體結構之製作方法可在不增加製程複雜度的前提下，成功地將不同尺寸的半導體結構整合製作。According to the method of fabricating a semiconductor structure provided by the present invention, a patterned protective layer is formed in a second region where a large pattern is to be formed to protect a second mask pattern having a larger width. Therefore, when the first mask pattern having a small width is formed, the second mask pattern is protected from being affected by the patterned protective layer. After the first mask pattern is completed, the first mask pattern having a smaller width and the second mask pattern having a larger width are simultaneously transferred onto the substrate, so that the smaller size can be simultaneously completed. The first semiconductor structure and the second semiconductor structure having a larger size. In other words, the fabrication method of the semiconductor structure provided by the present invention can successfully integrate semiconductor structures of different sizes without increasing the complexity of the process.
請參閱第2圖至第9圖，第2圖至第9圖係為本發明所提供之一半導體結構之製作方法之一第一較佳實施例之示意圖。如第2圖所示，本較佳實施例首先提供一基底200，基底200可包含一矽覆絕緣(SOI)基底或一塊矽(bulk silicon)基底。基底200上定義有一第一區域202與一第二區域204，用以形成不同的半導體元件。另外基底200至少包含一含矽層206，例如一單晶矽層，但不限於此。接下來，於基底202上，尤其是含矽層206上形成一遮罩層210。遮罩層210可包含一單一膜層，或如第2圖所示之一複合膜層，且由下而上至少包含一第一單層212與一第二單層214。另外遮罩層210或可如本較佳實施例所示，較佳更包含一第三單層216，且第一單層212係設置於第三單層216與第二單層214之間。第一單層212、第二單層214、與第三單層216之蝕刻率係不同於彼此。舉例來說，第一單層212可採用先進圖膜(advanced patterning film，APF)、第二單層214可包含氮化矽(silicon nitride)、而第三單層216則可包含氧化矽(silicon oxide)，但皆不限於此。Please refer to FIG. 2 to FIG. 9 . FIG. 2 to FIG. 9 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor structure according to the present invention. As shown in FIG. 2, the preferred embodiment first provides a substrate 200 which may comprise a blanket insulating (SOI) substrate or a bulk silicon substrate. A first region 202 and a second region 204 are defined on the substrate 200 to form different semiconductor components. In addition, the substrate 200 includes at least one germanium-containing layer 206, such as a single crystal germanium layer, but is not limited thereto. Next, a mask layer 210 is formed on the substrate 202, particularly the germanium-containing layer 206. The mask layer 210 may comprise a single film layer, or a composite film layer as shown in FIG. 2, and includes at least a first single layer 212 and a second single layer 214 from bottom to top. In addition, as shown in the preferred embodiment, the mask layer 210 may further include a third single layer 216, and the first single layer 212 is disposed between the third single layer 216 and the second single layer 214. The etching rates of the first single layer 212, the second single layer 214, and the third single layer 216 are different from each other. For example, the first single layer 212 may employ an advanced patterning film (APF), the second single layer 214 may include silicon nitride, and the third single layer 216 may include silicon oxide (silicon). Oxide), but not limited to this.
請繼續參閱第2圖。接下來於遮罩層210上形成一圖案化光阻(圖未示)，用以圖案化遮罩層210。在本較佳實施例中，圖案化步驟係僅圖案化遮罩層210的第一單層212與第二單層214，而不影響第三單層216。在圖案化遮罩層210之後，係於第一區域202中形成複數個第一圖案222，同時於第二區域204中形成至少一個第二圖案224，且第一圖案222與第二圖案224即可包含不同的寬度。Please continue to see Figure 2. A patterned photoresist (not shown) is then formed on the mask layer 210 to pattern the mask layer 210. In the preferred embodiment, the patterning step only patterns the first single layer 212 and the second single layer 214 of the mask layer 210 without affecting the third single layer 216. After the mask layer 210 is patterned, a plurality of first patterns 222 are formed in the first region 202, and at least one second pattern 224 is formed in the second region 204, and the first pattern 222 and the second pattern 224 are Can contain different widths.
請參閱第3圖。在形成第一圖案222與第二圖案224之後，係於基底200上，尤其是遮罩層210上形成另一遮罩層230，且遮罩層230係覆蓋第一圖案222與第二圖案224。遮罩層230可包含與第二單層214相同或不同的材料，舉例來說，當第二單層214包含氮化矽時，遮罩層230可包含氮化矽、氧化矽或其組合，且遮罩層230可為單一膜層或為一複合膜層。此外需注意的是，遮罩層230之厚度，係可等於所欲形成的半導體結構，例如多閘極電晶體之鰭片部分的預期寬度。舉例來說，當多閘極電晶體之鰭片部分之寬度為20奈米(nanometer，nm)時，遮罩層230之厚度較佳即約等於20nm。Please refer to Figure 3. After the first pattern 222 and the second pattern 224 are formed, another mask layer 230 is formed on the substrate 200, in particular, the mask layer 210, and the mask layer 230 covers the first pattern 222 and the second pattern 224. . The mask layer 230 can comprise the same or a different material than the second single layer 214. For example, when the second single layer 214 comprises tantalum nitride, the mask layer 230 can comprise tantalum nitride, tantalum oxide, or a combination thereof. The mask layer 230 can be a single film layer or a composite film layer. In addition, it should be noted that the thickness of the mask layer 230 may be equal to the desired width of the semiconductor structure to be formed, such as the fin portion of the multi-gate transistor. For example, when the width of the fin portion of the multi-gate transistor is 20 nanometers (nm), the thickness of the mask layer 230 is preferably about 20 nm.
請參閱第4圖。接下來進行一回蝕刻製程，以移除部分遮罩層230，而於第一圖案222之側壁與第二圖案224之側壁分別形成複數個第一側壁子232與至少一第二側壁子234。而在形成第一側壁子232與第二側壁子234之後，係於第二區域204內形成一圖案化保護層236。圖案化保護層236可包含光阻，但不限於此。此外需注意的是，第二區域204內的圖案化保護層236係覆蓋第二圖案224與第二側壁子234。Please refer to Figure 4. Next, an etching process is performed to remove a portion of the mask layer 230, and a plurality of first sidewalls 232 and at least a second sidewall 234 are formed on the sidewalls of the first pattern 222 and the sidewalls of the second pattern 224, respectively. After the first sidewall 232 and the second sidewall 234 are formed, a patterned protective layer 236 is formed in the second region 204. The patterned protective layer 236 may include photoresist, but is not limited thereto. In addition, it should be noted that the patterned protective layer 236 in the second region 204 covers the second pattern 224 and the second sidewall 234.
請參閱第5圖。在形成圖案化保護層236後，係移除第一區域202內的第一圖案222。而移除第一圖案222之步驟又可細分如下：首先，先移除第一圖案222的第二單層214。需注意的是，若遮罩層230包含與第二單層214相同之材料，則第一區域202內的部分第一側壁子232亦可能於此步驟中如第5圖所示被消耗；此外第二區域204內的圖案化保護層236亦可能如第5圖所示於此步驟中消耗。Please refer to Figure 5. After the patterned protective layer 236 is formed, the first pattern 222 within the first region 202 is removed. The step of removing the first pattern 222 can be further subdivided as follows: First, the second single layer 214 of the first pattern 222 is removed first. It should be noted that if the mask layer 230 includes the same material as the second single layer 214, a portion of the first sidewall sub-232 in the first region 202 may also be consumed as shown in FIG. 5 in this step; The patterned protective layer 236 in the second region 204 may also be consumed in this step as shown in FIG.
請參閱第6圖。在移除第二單層214之後，係立即移除第一單層212，即將第一圖案222全部移除，以於第一區域202中形成複數個第一遮罩圖案242。如第6圖所示，第一遮罩圖案242分別包含一第一側壁子232。值得注意的是，由於第一單層212與遮罩層230的材料並不相同，因此在移除第一單層212時，並不影響第一側壁子232的圖案輪廓。而在形成第一遮罩圖案242後，係移除剩餘的圖案化保護層236，而於第二區域204內形成至少一個第二遮罩圖案244。如第6圖所示，各第二遮罩圖案244係包含一第二圖案224(包含第一單層212與第二單層214)與形成於其側壁之第二側壁子234。由第6圖可知，第二遮罩圖案244與第一遮罩圖案242具有不同的寬度，且第二遮罩圖案244之寬度大於第一遮罩圖案242之寬度。舉例來說，第二遮罩圖案244之寬度與第一遮罩圖案242之寬度具有一比值，且該比值大於等於2。Please refer to Figure 6. After the second single layer 214 is removed, the first single layer 212 is removed immediately, that is, the first pattern 222 is completely removed to form a plurality of first mask patterns 242 in the first region 202. As shown in FIG. 6, the first mask patterns 242 each include a first sidewall 232. It should be noted that since the material of the first single layer 212 and the mask layer 230 are not the same, the pattern profile of the first sidewall sub-232 is not affected when the first single layer 212 is removed. After the first mask pattern 242 is formed, the remaining patterned protective layer 236 is removed, and at least one second mask pattern 244 is formed in the second region 204. As shown in FIG. 6, each of the second mask patterns 244 includes a second pattern 224 (including the first single layer 212 and the second single layer 214) and a second sidewall 234 formed on the sidewall thereof. As can be seen from FIG. 6 , the second mask pattern 244 has a different width from the first mask pattern 242 , and the width of the second mask pattern 244 is greater than the width of the first mask pattern 242 . For example, the width of the second mask pattern 244 has a ratio to the width of the first mask pattern 242, and the ratio is greater than or equal to 2.
請參閱第7圖。接下來進行一第一蝕刻製程，以將第一遮罩圖案242與第二遮罩圖案244轉移至第三單層216中。然而需注意的是，在無第三單層216設置的變化型中，第一蝕刻製程係可直接將第一遮罩圖案242與第二遮罩圖案244轉移至基底200，尤其是基底200上的含矽層206。Please refer to Figure 7. Next, a first etching process is performed to transfer the first mask pattern 242 and the second mask pattern 244 into the third single layer 216. It should be noted, however, that in a variation without the third monolayer 216 arrangement, the first etch process can directly transfer the first mask pattern 242 and the second mask pattern 244 to the substrate 200, particularly the substrate 200. The ruthenium containing layer 206.
請參閱第8圖與第9圖。接下來，移除第一側壁子232、第二圖案224、與第二側壁子234，隨後進行一第二蝕刻製程，以將第一遮罩圖案242與第二遮罩圖案244由第三單層216轉移至基底200，尤其是基底200上的含矽層206，而於基底200上形成複數個第一半導體結構252與至少一個第二半導體結構254。最後如第9圖所示，移除第一遮罩圖案242與第二遮罩圖案244。值得注意的是，第一半導體結構252之寬度與第二半導體結構254之寬度分別與第一遮罩圖案242之寬度與第二遮罩圖案244之寬度相同，因此第一半導體結構252之寬度係小於第二半導體結構254之寬度。如第9圖所示，第一區域202內形成包含第一半導體結構252的精細圖案；而第二區域204內係形成包含第二半導體結構254的大圖案。具有不同寬度的第一半導體結構252與第二半導體結構254具有不同的功用，舉例來說，具有較小寬度的第一半導體結構252可作為多閘極電晶體元件的鰭片部分；而具有大寬度的第二半導體結構254則可因應不同的產品要求作為其他元件的構成單元。Please refer to Figure 8 and Figure 9. Next, the first sidewall 232, the second pattern 224, and the second sidewall 234 are removed, and then a second etching process is performed to make the first mask pattern 242 and the second mask pattern 244 from the third single Layer 216 is transferred to substrate 200, particularly germanium containing layer 206 on substrate 200, and a plurality of first semiconductor structures 252 and at least one second semiconductor structure 254 are formed on substrate 200. Finally, as shown in FIG. 9, the first mask pattern 242 and the second mask pattern 244 are removed. It should be noted that the width of the first semiconductor structure 252 and the width of the second semiconductor structure 254 are respectively the same as the width of the first mask pattern 242 and the width of the second mask pattern 244, and thus the width of the first semiconductor structure 252 is Less than the width of the second semiconductor structure 254. As shown in FIG. 9, a fine pattern including the first semiconductor structure 252 is formed in the first region 202; and a large pattern including the second semiconductor structure 254 is formed in the second region 204. The first semiconductor structure 252 having different widths has a different function than the second semiconductor structure 254. For example, the first semiconductor structure 252 having a smaller width can serve as a fin portion of the multi-gate transistor element; The width of the second semiconductor structure 254 can be used as a constituent unit of other components in response to different product requirements.
根據本較佳實施例所提供的半導體結構之製作方法，係於預定形成大圖案的第二區域204內形成圖案化保護層236，用以保護寬度較大的第二遮罩圖案244。因此在製作寬度較小的第一遮罩圖案242時，第二遮罩圖案244係受到圖案化保護層236的保護而不致受到影響。而待第一遮罩圖案242與第二遮罩圖案244製作完之後，係將具有較小寬度的第一遮罩圖案242與具有較大寬度的第二遮罩圖案244同時轉移至基底200上，是以可同時完成具有較小尺寸的第一半導體結構252與具有較大尺寸的第二半導體結構254。換句話說，本發明所提供之半導體結構之製作方法係可在不增加製程複雜度的前提下，同時於基底200上同時完成具有不同尺寸的半導體結構252/254的製作。According to the method of fabricating the semiconductor structure provided by the preferred embodiment, a patterned protective layer 236 is formed in the second region 204 where the large pattern is to be formed to protect the second mask pattern 244 having a larger width. Therefore, when the first mask pattern 242 having a small width is formed, the second mask pattern 244 is protected by the patterned protective layer 236 without being affected. After the first mask pattern 242 and the second mask pattern 244 are formed, the first mask pattern 242 having a smaller width and the second mask pattern 244 having a larger width are simultaneously transferred to the substrate 200. The first semiconductor structure 252 having a smaller size and the second semiconductor structure 254 having a larger size can be simultaneously completed. In other words, the semiconductor structure provided by the present invention can simultaneously fabricate semiconductor structures 252/254 having different sizes on the substrate 200 without increasing the complexity of the process.
接下來請參閱第10圖，第10圖為本發明所提供之一半導體結構之製作方法之一第二較佳實施例之示意圖。值得注意的是，第二較佳實施例中與第一較佳實施例相同之元件係沿用相同的元件符號說明，且第二較佳實施例中與第一較佳實施例相同之步驟係於此省略而不贅述。第二較佳實施例與第一較佳實施例不同之處在於：在形成第一遮罩圖案242與第二遮罩圖案244之後，本較佳實施例係藉由一道蝕刻製程直接將第一遮罩圖案242與第二遮罩圖案244轉移至第三單層216與基底200，尤其是基底200上的含矽層206。當然，在不具第三單層216的變化型中，第一遮罩圖案242與第二遮罩圖案244係可直接轉移至含矽層206。Next, please refer to FIG. 10, which is a schematic diagram of a second preferred embodiment of a method for fabricating a semiconductor structure according to the present invention. It is to be noted that the same components of the second preferred embodiment as the first preferred embodiment are denoted by the same reference numerals, and the steps of the second preferred embodiment are the same as those of the first preferred embodiment. This is omitted and will not be described. The second preferred embodiment is different from the first preferred embodiment in that after forming the first mask pattern 242 and the second mask pattern 244, the preferred embodiment directly performs the first process by an etching process. The mask pattern 242 and the second mask pattern 244 are transferred to the third monolayer 216 and the substrate 200, particularly the germanium containing layer 206 on the substrate 200. Of course, in a variation without the third single layer 216, the first mask pattern 242 and the second mask pattern 244 can be directly transferred to the germanium containing layer 206.
最後，移除第一遮罩圖案242(包含第一側壁子232)、第二遮罩圖案(包含第二圖案224與第二側壁子234)與第三單層216，而如第9圖所示，於基底200上形成複數個第一半導體結構252與至少一個第二半導體結構254。如前所述，第一半導體結構252之寬度與第二半導體結構254之寬度分別與第一遮罩圖案242之寬度與第二遮罩圖案244之寬度相同，因此第一半導體結構252之寬度係小於第二半導體結構254之寬度，且具有不同寬度的第一半導體結構252與第二半導體結構254具有不同的功用。Finally, the first mask pattern 242 (including the first sidewall sub-232), the second mask pattern (including the second pattern 224 and the second sidewall sub-234), and the third single layer 216 are removed, as shown in FIG. A plurality of first semiconductor structures 252 and at least one second semiconductor structure 254 are formed on the substrate 200. As described above, the width of the first semiconductor structure 252 and the width of the second semiconductor structure 254 are respectively the same as the width of the first mask pattern 242 and the width of the second mask pattern 244, and thus the width of the first semiconductor structure 252 is The width of the second semiconductor structure 254 is smaller than that of the second semiconductor structure 254, and the first semiconductor structure 252 having a different width has a different function than the second semiconductor structure 254.
綜上所述，根據本發明所提供的半導體結構之製作方法，係於預定形成大圖案的第二區域內形成圖案化保護層，用以保護寬度較大的第二遮罩圖案。因此在製作寬度較小的第一遮罩圖案時，第二遮罩圖案係受到圖案化保護層的保護而不致受到影響。而待第一遮罩圖案製作完之後，係將具有較小寬度的第一遮罩圖案與具有較大寬度的第二遮罩圖案同時轉移至該基底上，是以可同時完成具有較小尺寸的第一半導體結構與具有較大尺寸的第二半導體結構。換句話說，本發明所提供之半導體結構之製作方法係可在不增加製程複雜度的前提下，成功地將不同尺寸的半導體結構整合製作。In summary, the method for fabricating a semiconductor structure according to the present invention forms a patterned protective layer in a second region where a large pattern is to be formed to protect a second mask pattern having a larger width. Therefore, when the first mask pattern having a small width is formed, the second mask pattern is protected from being affected by the patterned protective layer. After the first mask pattern is finished, the first mask pattern having a smaller width and the second mask pattern having a larger width are simultaneously transferred to the substrate, so that the smaller size can be simultaneously completed. The first semiconductor structure and the second semiconductor structure having a larger size. In other words, the fabrication method of the semiconductor structure provided by the present invention can successfully integrate semiconductor structures of different sizes without increasing the complexity of the process.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．鰭式場效電晶體元件100. . . Fin field effect transistor component
102．．．矽覆絕緣基板102. . . Overlying insulating substrate
104．．．高介電常數絕緣層104. . . High dielectric constant insulating layer
106．．．閘極106. . . Gate
108．．．源極/汲極108. . . Source/bungee
200．．．基底200. . . Base
202．．．第一區域202. . . First area
204．．．第二區域204. . . Second area
206．．．含矽層206. . . Layer containing
210．．．遮罩層210. . . Mask layer
212．．．第一單層212. . . First single layer
214．．．第二單層214. . . Second single layer
216．．．第三單層216. . . Third single layer
222．．．第一圖案222. . . First pattern
224．．．第二圖案224. . . Second pattern
230．．．遮罩層230. . . Mask layer
232．．．第一側壁子232. . . First side wall
234．．．第二側壁子234. . . Second side wall
236．．．圖案化保護層236. . . Patterned protective layer
242．．．第一遮罩圖案242. . . First mask pattern
244．．．第二遮罩圖案244. . . Second mask pattern
252．．．第一半導體結構252. . . First semiconductor structure
254．．．第二半導體結構254. . . Second semiconductor structure
第1圖係為一習知FinFET元件之立體示意圖。Figure 1 is a perspective view of a conventional FinFET device.
第2圖至第9圖係為本發明所提供之一半導體結構之製作方法之一第一較佳實施例之示意圖。2 to 9 are schematic views showing a first preferred embodiment of a method of fabricating a semiconductor structure provided by the present invention.
第10圖為本發明所提供之一半導體結構之製作方法之一第二較佳實施例之示意圖。FIG. 10 is a schematic view showing a second preferred embodiment of a method for fabricating a semiconductor structure according to the present invention.
200．．．基底200. . . Base
202．．．第一區域202. . . First area
204．．．第二區域204. . . Second area
206．．．含矽層206. . . Layer containing
210．．．遮罩層210. . . Mask layer
212．．．第一單層212. . . First single layer
214．．．第二單層214. . . Second single layer
216．．．第三單層216. . . Third single layer
222．．．第一圖案222. . . First pattern
224．．．第二圖案224. . . Second pattern
232．．．第一側壁子232. . . First side wall
234．．．第二側壁子234. . . Second side wall
236．．．圖案化保護層236. . . Patterned protective layer
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