TWI506689B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TWI506689B
TWI506689B TW101142147A TW101142147A TWI506689B TW I506689 B TWI506689 B TW I506689B TW 101142147 A TW101142147 A TW 101142147A TW 101142147 A TW101142147 A TW 101142147A TW I506689 B TWI506689 B TW I506689B
Authority
TW
Taiwan
Prior art keywords
wafer
carrier
heat sink
trenches
semiconductor device
Prior art date
Application number
TW101142147A
Other languages
English (en)
Other versions
TW201342453A (zh
Inventor
謝政傑
侯上勇
鄭心圃
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201342453A publication Critical patent/TW201342453A/zh
Application granted granted Critical
Publication of TWI506689B publication Critical patent/TWI506689B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • H01L21/4878Mechanical treatment, e.g. deforming
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427Cooling by change of state, e.g. use of heat pipes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/33104Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/33106Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area
    • H01L2224/33107Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area the layer connectors connecting two common bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

半導體裝置之製造方法
本發明係有關於半導體裝置之製造方法,且特別是有關於一種含散熱器之半導體裝置之製造方法。
在半導體製程中,積體電路係形成於半導體晶圓上,而這些晶圓經切割成晶片後封裝,以作使用。在目前趨勢中,晶圓厚度係逐漸變薄,而隨著使用較薄的晶圓,能夠容許立體積體電路(3DIC)製程。
薄化的晶圓會導致積體電路製程的困難度增加。例如,薄晶圓具有顯著的翹曲,而某些製程可能無法在翹曲的晶圓上進行。為解決上述問題,係以載材與經過處理或薄化的薄晶圓結合,由於載材具有足夠的厚度,可避免翹曲的問題。藉由黏著劑,薄化的晶圓可黏著在載材上並可保持平坦。
然而,當薄晶圓自載材上移除時,的翹曲問題即會再度產生。為解決上述問題,可將薄晶圓隨載材一併切割。由於晶片之尺寸相對較小,翹曲問題在切割後的晶片上不明顯。然而,如使用上述方法,載材會隨晶片一併被切割,因而無法再度使用。
本發明實施例係提供一種半導體裝置之製造方法,包括:透過一黏著劑附接一晶圓至一載材上;形成複數溝槽 於此載材中,以將此載材轉換成一散熱器;以及切割此散熱器、此載材及此黏著劑進入複數封裝體中。
本發明實施例亦提供一種半導體裝置之製造方法,包含:透過一黏著劑附接一半導體晶圓至一載材上;在進行此附接步驟之後,形成複數導電元件於此半導體晶圓上,其中這些導電元件與此半導體晶圓中的元件電性連接;在進行此形成這些導電元件之步驟後,形成複數溝槽於載材中,以將此載材轉換為一散熱器;以及切割此散熱器、此載材及此黏著劑進入複數封裝體中。
本發明實施例更提供一種半導體裝置之製造方法,包含:透過一黏著劑附接一晶圓至一載材上;在進行此附接步驟之後,薄化此晶圓;在進行此薄化步驟之後,形成複數溝槽於載材中,以將此載材轉換成一散熱器;以及切割此散熱器、此載材及此黏著劑進入複數封裝體中。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。值得注意的是,這些實施例提供許多可行之發明概念並可實施於各種特定情況。然而,在此所討論之這些特定實施例僅用於舉例說明,但非用於限定本發明之範圍。
在本發明實施例中,提供了包含由載材轉換而成之散 熱器(heat sink)之封裝體及其製造方法,並舉例說明其中間製程及其可能的實施例變化。在各圖式及所舉例之實施例中,相似元件標號可用以指定相似元件。
第1圖顯示為晶圓100之剖面圖。在某些實施例中,如第1及2A圖所示,晶圓100包含封裝元件20,且此封裝元件20係與封裝元件44相接合。在其他實施例中,如第2B圖所示,晶圓100為一之裝置晶圓,於其上未有晶片接合,主動元件23係直接形成於基材22之表面上。如第2B圖所示之晶圓100亦包含晶片(或晶粒)40其中。
重新參見第1圖,封裝元件20包含基材22。在某些實施例中,基材22為半導體基材,其可更包含結晶矽基材。或者,基材22可由其他半導體材料形成,例如鍺化矽、碳化矽或其類似物。在其他實施例中,基材22為介電基材。封裝元件20可為裝置晶圓,其包含如電晶體等主動元件23形成於半導體基材22之表面22A上。當封裝元件20為裝置晶圓時,其亦可包含如電阻器及/或電容器等被動元件(未顯示)。在某些實施例中,封裝元件20係為中介晶圓(interposer wafer),不包含主動元件於其中,但可包含或不包含被動元件形成於其中。通孔(through vias)24可自基材之22頂表面22A延伸至基材22中。通孔24有時亦可稱為貫通孔,或者,當基材22為矽基材時,通孔24有時亦可稱為矽穿孔。封裝元件20包含多個封裝元件40,且這些封裝元件40可為彼此相同的封裝元件。封裝元件40可為裝置晶片/晶粒(chips/dies)、中介晶片或其類似物。因此,在本說明書中,封裝元件40又可稱為晶片(chips)或晶粒 (dies)40。
內連線結構28係形成於基材22上,且用以電性連接積體電路(如有需要)及/或通孔24。內連線結構28可包含多層介電層30。金屬線32形成於介電層30中。通孔34形成於介電層中,並作內連接,例如連接位於其上及其下的金屬線32。金屬線32及通孔34有時亦可稱為重分佈線(RDL)32/34。在某些實施例中,介電層30包含氧化矽、氮化矽、碳化矽、氮氧化矽、前述之組合及/或前述之多層組合。或者,介電層30可包含一或多層的低介電常數介電層,其具有例如低於30,或更低於約2.5之介電常數值(k值)。
連接器38形成於封裝元件20之頂表面。在某些實施例中,連接器38包含金屬柱,且在金屬柱之頂面上可具有或不具有焊料蓋(solder caps)形成。在某些實施例中,連接器38可包含焊接區域。在其他實施例中,連接器38可為複合凸塊,包含銅柱、鎳層、焊料蓋、無電鍍鎳浸金(electroless nickel immersion gold,ENIG)、無電鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)、及/或其類似物。
封裝元件44可透過例如覆晶接合方式與封裝元件20接合。因此,封裝元件44中的電路與封裝元件20中的重分佈線32及通孔24係透過連接器38接合並電性偶接。封裝元件44可為裝置晶粒,包含邏輯電路、記憶電路或其類似物。因此,此後封裝元件44又可稱為晶粒44。或者,封裝元件44可包含接合於中介物、封裝基材及/或其類似 物之晶粒40。在每一晶粒40上皆可具有二或多個晶粒44接合於其上。在某些實施例中,晶粒44包含基材46,例如矽基材。在其他實施例中,基材46可由例如鍺化矽、碳化矽、III-V化合物半導體或其類似物形成。因此,基材46之表面46A即為矽、鍺化矽、碳化矽、III-V化合物半導體或其類似物之表面。
接著,施予聚合物50進入晶片44及封裝元件20之間。聚合物50可為底部填充材料(underfill),並因此可稱為底部填充材料50。底部填充材料50可包含環氧樹脂,或亦可為塑模材料(molding material)。
塑模材料52模塑(molded)於晶片44及封裝元件20上,例如使用壓縮模塑方法。塑模材料52可例如為聚合物。在某些實施例中,塑模材料52包含塑模化合物,例如環氧樹脂或其類似物。塑模材料可由進行固化步驟予以固化,固化步驟可例如為熱固化、UV固化或其類似方法。在上述實施例中,晶粒44係埋藏於塑模材料中20。在固化塑模材料52之後,可進行例如研磨之平坦化製程,以移除塑模材料之過剩部分,例如塑模材料52之凸出於裝置晶粒44頂表面46的部分。因此,基材46之頂表面46A係暴露於外,且與塑模材料52之頂表面52A同一水平。
參見第2A及2B圖,導熱載材54可透過黏著劑55附接於晶圓100上。在第2圖所示之實施例中,黏著層55可與晶粒44及塑模材料52接觸。在第2B圖所示之實施例中,黏著層55可與基材22接觸。在某些實施例中,導熱載材54為矽晶圓,其可包含結晶矽。在其他實施例中,導 熱載材54可包含玻璃、陶瓷或其類似物。導熱載材54之導熱性可大於約100 Watts/m*K或大於約150 Watts/m*K。黏著層55可包含導熱黏著劑,其可為晶片貼膜(die attach film,DAF)、熱環氧膠材、黏著性熱界面材料(adhesive thermal interface material,TIM)或其類似物。
第3A圖顯示第2A圖所示之封裝元件20之背端結構之形成。此背端結構之形成步驟可包含:對半導體基材22之背端進行研磨,以薄化半導體基材22,直至暴露出通孔24;形成一或多層介電層56於半導體基材22之背端;形成連接器58於封裝元件20之背端上,並與通孔24電性連接。在某些實施例中,連接器58可為焊球。在其他實施例中,連接器58可包含金屬墊、金屬凸塊、銲蓋(solder cap)或其類似物。重分佈線可形成於封裝元件20之背端及於介電層56中,其中元件62即為重分佈線。連接器58可用以接合其他額外的電子元件(未顯示),例如半導體基材、封裝基材、印刷電路板(PCB)或其類似物。
第3B圖顯示為第2B圖之晶圓100之前端內連線結構28。主動元件23可形成於基材22之前端。內連線結構可包含形成於介電層130中的金屬線132。通孔134形成於位在其上及其上之金屬線132之間,並將其內連接。介電層130可包含一或多層的低介電常數介電層,其具有例如低於3.0,或更低於約2.5之介電常數值。電子連接器138形成於晶圓100之前端。
接著,如第4A及4B圖所示,形成多個溝槽64於導熱載材54中,以將導熱載材54轉換為散熱器(heat sink), 其亦可稱為散熱器54。溝槽64可透過蝕刻形成。或者,溝槽64可由切割刀切割導熱載材54形成。所形成之散熱器54包含多個鰭66於溝槽64之間。這些鰭66亦可形成陣列。第7A及7B圖顯示溝槽64之上視圖。由散熱器54之上視角度觀之,溝槽64可包含複數個彼此相互平行之第一溝槽64A。溝槽64可包含(或不包含)複數個彼此相互平行之第二溝槽64B,其中這些第二溝槽64B可垂直於第一溝槽64A。如第4A及4B圖所示,溝槽64自表面54A延伸至導熱載材54之中間。在某些實施例中,溝槽64之深度D1(亦為鰭66的鰭高度)可介於約200 μm及約800 μm之間。深度D1之實際數值係可決定於基材22厚度。至此,即完成晶片堆疊晶圓(chip-on-wafer)封裝體。
接著,沿切割線68進行切割製程,以將第4A及4B圖中之封裝體切割成封裝體70。封裝體70可如第5A及5B圖所示。在第5A圖中,封裝體70包含一部分的散熱器54、一部分的晶粒40及一或多個晶粒44。可發現的是,在封裝體70中,散熱器54之邊緣54B係與塑模材料52之對應邊緣對齊。在第5B圖中,封裝體70包含裝置晶粒40,其中散熱器54之邊緣係與晶粒40之對應邊緣40A對齊。此外,以上視角度觀之時,散熱器54與其對應的晶粒40具有相同的形狀及尺寸。
第6圖顯示依照本發明一實施例之封裝體,此封裝體可為第5A或5B圖所示之封裝體70。散熱器54可與積體散熱器(integrated heat spreader,IHS)72接合,例如透過氧化物-氧化物接合方式接合。在某些實施例中,積體散熱器 72為一金屬蓋,其包含平坦部分72A及側邊部分72B,其中側邊部分72B在如第6圖之上視角度中係為一環狀。或者,積體散熱器72可為平坦的積體散熱器。溝槽64被積體散熱器72自頂部密封。因此,密封的溝槽64形成多個微通道,冷卻媒介可藉由這些微通道傳導。在某些實施例中,在散熱器54及積體散熱器72接合之後,可於積體散熱器72中形成連接至溝槽64的多個孔洞74。管線76可安裝於積體散熱器72上。此外,這些孔洞74亦可在接合積體散熱器72與散熱器54之前就已預形成。晶粒40在操作時,會產生廢熱,而這些廢熱會傳導至散熱器54。冷卻媒介,例如水、油、冷空氣或其他類似物,可透過管線76傳導至溝槽64,並因此可將廢散出。圖中箭頭80所指方向即為冷卻媒介之流動方向。
第7A及7B圖顯示為依照本發明實施例之第6圖之結構之上視圖。參見第7A圖,某些溝槽64(標示為64A)係彼此平行,且其長度方向(lengthwise direction)係由輸入管線76A指向輸出管線76B。某些溝槽64(標示為64B)係可形成於垂直於溝槽64A之長度方向的方向上。溝槽64B與溝槽64A相互連接。在某些實施例中,溝槽64B之間的間距較溝槽64A大。
在第7B圖中,溝槽64B與溝槽64A具有實質上相同的間距,因而溝槽64A及64B可形成棋盤(grid)結構。在這些實施例中,輸入和輸出管線76可放置於散熱器54之兩端或相反側。在這些實施例中,溝槽64A及64B可用作為揮發通道。冷卻媒介78流入至輸入管線76中,並可藉 由溝槽64中藉由晶片40產生的廢熱揮發成蒸氣,由輸出管線76B散出而帶走廢熱。
第8圖顯示依照本發明其他實施例之封裝體70。在此實施例中,散熱器54與散熱器82透過導熱黏著劑894相接合。散熱器82可由例如金屬或金屬合金形成。導熱黏著劑84可由晶片貼膜(die attach film,DAF)、熱環氧膠材、黏著性熱界面材料(adhesive thermal interface material,TIM)或其類似物形成。目前已知的是,透過黏著劑接合晶圓/晶粒及散熱器時,可能會在黏著劑中產生氣泡。氣泡為熱的絕緣體,因而較佳需避免氣泡產生。然而,某些實施例中,溝槽64可能會吸入部分的氣泡86。例如,參見第8圖,某些氣泡86係被擠壓至溝槽64中,因此由上視圖可看出氣泡86減少。因此,可減少氣泡86對導熱性的影響。因此,在難以避免氣泡86生成的清況下,即使黏著劑84的導熱性低於散熱器54,散熱器82及晶粒40之間的導熱性可藉由形成溝槽而增加。
在某上述實施例中,散熱器可由晶圓級製程製造,而非晶片級,並因可減少製造成本。既然散熱器隨著晶粒一起切割,即沒有散熱器及晶粒對準問題。此外,即使如第1至6B圖所示之晶圓為薄晶圓,既然晶圓100未自對應的載材上移除,晶圓100在製造時亦無翹曲的問題。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾。此外,本發明之範圍不限定於現有或未來所發展的特 定程序、機器、製造、物質之組合、功能、方法或步驟,其實質上進行與依照本發明所述之實施例相同的功能或達成相同的結果。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外,每個申請專利範圍建構成一獨立的實施例,且各種申請專利範圍及實施例之組合皆介於本發明之範圍內。
20‧‧‧封裝元件
22‧‧‧基材
22A‧‧‧基材表面
23‧‧‧主動元件
24‧‧‧通孔
28‧‧‧內連線結構
32‧‧‧金屬線
34‧‧‧通孔
38‧‧‧連接器
40‧‧‧晶粒
40A‧‧‧晶粒邊緣
44‧‧‧晶粒
46‧‧‧基材
46A‧‧‧基材表面
50‧‧‧聚合物
52‧‧‧塑模材料
52A‧‧‧塑模材料頂表面
52B‧‧‧塑模材料邊緣
54‧‧‧導熱載材
54A‧‧‧表面
54B‧‧‧散熱器邊緣
55‧‧‧黏著劑
56‧‧‧介電層
58‧‧‧連接器
62‧‧‧重分佈線
64‧‧‧溝槽
64A‧‧‧溝槽
64B‧‧‧溝槽
66‧‧‧鰭
68‧‧‧切割線
70‧‧‧封裝體
72‧‧‧積體散熱器
72A‧‧‧平坦部分
72B‧‧‧側邊部分
74‧‧‧孔洞
76‧‧‧管線
78‧‧‧冷卻媒介
80‧‧‧流動方向
82‧‧‧散熱器
84‧‧‧導熱黏著劑
86‧‧‧氣泡
100‧‧‧晶圓
130‧‧‧介電層
132‧‧‧金屬線
134‧‧‧通孔
138‧‧‧電子連接器
D1‧‧‧深度
第1、2A~5A及2B~5B圖顯示為依照本發明示範實施例之封裝體於各種中間製程階段之剖面圖。
第6、7A、7B及8圖顯示為依照這本發明某些實施例之封裝體之使用。
40‧‧‧晶粒
54‧‧‧導熱載材
55‧‧‧黏著劑
64‧‧‧溝槽
70‧‧‧封裝體
72‧‧‧積體散熱器
72A‧‧‧平坦部分
72B‧‧‧側邊部分
74‧‧‧孔洞
76‧‧‧管線
78‧‧‧冷卻媒介
80‧‧‧流動方向

Claims (10)

  1. 一種半導體裝置之製造方法,包括:透過一黏著劑附接一晶圓至一載材上;形成複數溝槽於該載材中,以將該載材轉換成一散熱器;以及切割該散熱器、該晶圓及該黏著劑成為複數封裝體。
  2. 如申請專利範圍第1項所述之半導體裝置之製造方法,更包含將該載材與一散熱器接合,其中該散熱器密封該些溝槽。
  3. 如申請專利範圍第2項所述之半導體裝置之製造方法,更包含:形成該些孔洞於該散熱器中,其中該些孔洞與該些溝槽相連接;及透過該些孔洞連接複數管線至該些溝槽。
  4. 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該晶圓包含一額外的晶圓於其中,其中該額外的晶圓包含一第一基材及複數通孔自該第一基材之一頂表面延伸,其中該半導體裝置之製造方法更包含接合複數晶粒於該額外的晶圓上,其中每一晶粒包含一第二基材,且其中該載材係與該些晶粒之該些第二基材之頂表面相接合。
  5. 一種半導體裝置之製造方法,包含:透過一黏著劑附接一半導體晶圓至一載材上;在進行該附接步驟之後,形成複數導電元件於該半導體晶圓上,其中該些導電元件與該半導體晶圓中的元件電性連接; 在進行該形成該些導電元件之步驟後,形成複數溝槽於載材中,以將該載材轉換為一散熱器;以及切割該散熱器、該半導體晶圓及該黏著劑成為複數封裝體。
  6. 如申請專利範圍第5項所述之半導體裝置之製造方法,其中該進行該切割步驟時,該些溝槽為未填充的溝槽。
  7. 如申請專利範圍第5項所述之半導體裝置之製造方法,其中該半導體晶圓包含矽晶圓,且其中該矽晶圓實質上沒有積體電路裝置設於其中。
  8. 如申請專利範圍第5項所述之半導體裝置之製造方法,其中該形成該些溝槽之步驟包含形成複數相互平行的第一溝槽及複數相互平行的第二溝槽,其中該些第二溝槽垂直於該些第一溝槽且與該些第二溝槽相互連接。
  9. 一種半導體裝置之製造方法,包含:透過一黏著劑附接一晶圓至一載材上;在進行該附接步驟之後,薄化該晶圓;在進行該薄化步驟之後,形成複數溝槽於載材中,以將該載材轉換成一散熱器;以及切割該散熱器、該晶圓及該黏著劑成為複數封裝體。
  10. 如申請專利範圍第9項所述之半導體裝置之製造方法,其中該晶圓包含複數通孔於該晶圓之一基材中,且其中該薄化步驟包含薄化該基材以暴露出該些通孔,且其中該半導體裝置之製造方法更包含形成複數導電元件連接至該些通孔。
TW101142147A 2012-04-11 2012-11-13 半導體裝置之製造方法 TWI506689B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/444,662 US9034695B2 (en) 2012-04-11 2012-04-11 Integrated thermal solutions for packaging integrated circuits

Publications (2)

Publication Number Publication Date
TW201342453A TW201342453A (zh) 2013-10-16
TWI506689B true TWI506689B (zh) 2015-11-01

Family

ID=49232120

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101142147A TWI506689B (zh) 2012-04-11 2012-11-13 半導體裝置之製造方法

Country Status (3)

Country Link
US (1) US9034695B2 (zh)
DE (1) DE102012110982B4 (zh)
TW (1) TWI506689B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123780B2 (en) 2012-12-19 2015-09-01 Invensas Corporation Method and structures for heat dissipating interposers
US9167723B1 (en) * 2013-04-02 2015-10-20 Gerald Ho Kim Silicon-based heat-dissipation device for heat-generating devices
KR20150018099A (ko) * 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 적층 반도체 장치
US10510707B2 (en) * 2013-11-11 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive molding compound structure for heat dissipation in semiconductor packages
KR101695708B1 (ko) * 2014-01-09 2017-01-13 한국전자통신연구원 반도체 소자 및 그 제조방법
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9406650B2 (en) 2014-01-31 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US9704841B2 (en) * 2014-03-26 2017-07-11 United Microelectronics Corp. Method of packaging stacked dies on wafer using flip-chip bonding
US10269767B2 (en) * 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US9666539B1 (en) * 2015-12-03 2017-05-30 International Business Machines Corporation Packaging for high speed chip to chip communication
JP6536397B2 (ja) * 2015-12-25 2019-07-03 富士通株式会社 電子装置、電子装置の製造方法及び電子機器
WO2017146739A1 (en) * 2016-02-26 2017-08-31 Intel Corporation Pressure and load measurement for silicon die thermal solution attachment
US9941186B2 (en) 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
CN108695266A (zh) * 2017-04-12 2018-10-23 力成科技股份有限公司 封装结构及其制作方法
US10553548B2 (en) * 2017-06-28 2020-02-04 Intel Corporation Methods of forming multi-chip package structures
US10957656B2 (en) 2017-09-27 2021-03-23 Intel Corporation Integrated circuit packages with patterned protective material
EP3547360A1 (de) * 2018-03-29 2019-10-02 Siemens Aktiengesellschaft Halbleiterbaugruppe und verfahren zur herstellung der halbleiterbaugruppe
US10658263B2 (en) * 2018-05-31 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10818588B2 (en) * 2019-01-31 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, package structure and method of fabricating the same
US11011448B2 (en) * 2019-08-01 2021-05-18 Intel Corporation IC package including multi-chip unit with bonded integrated heat spreader
TWI723802B (zh) * 2020-03-12 2021-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
CN113394118B (zh) * 2020-03-13 2022-03-18 长鑫存储技术有限公司 封装结构及其形成方法
US11282825B2 (en) * 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
CN112614785B (zh) * 2020-12-17 2023-07-28 上海先方半导体有限公司 集成微流道的三维封装结构及封装方法
TWI796694B (zh) * 2021-05-21 2023-03-21 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136640A1 (en) * 2002-01-07 2005-06-23 Chuan Hu Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
TWI313505B (en) * 2004-09-30 2009-08-11 Intel Corporatio Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
TWI322821B (zh) * 2008-10-24 2010-04-01 Sumitomo Bakelite Co

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5500540A (en) * 1994-04-15 1996-03-19 Photonics Research Incorporated Wafer scale optoelectronic package
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5990552A (en) * 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
JPH11289023A (ja) * 1998-04-02 1999-10-19 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6242778B1 (en) 1998-09-22 2001-06-05 International Business Machines Corporation Cooling method for silicon on insulator devices
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP3339572B2 (ja) * 1999-10-04 2002-10-28 日本電気株式会社 半導体装置及びその製造方法
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
US20060022330A1 (en) 2004-02-23 2006-02-02 Jonathon Mallari Porous silicon heat sinks and heat exchangers and related methods
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060154393A1 (en) * 2005-01-11 2006-07-13 Doan Trung T Systems and methods for removing operating heat from a light emitting diode
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7382620B2 (en) 2005-10-13 2008-06-03 International Business Machines Corporation Method and apparatus for optimizing heat transfer with electronic components
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US20070108595A1 (en) 2005-11-16 2007-05-17 Ati Technologies Inc. Semiconductor device with integrated heat spreader
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7369410B2 (en) 2006-05-03 2008-05-06 International Business Machines Corporation Apparatuses for dissipating heat from semiconductor devices
DE102006054311B4 (de) * 2006-11-17 2012-05-24 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleitervorrichtung und mit diesem herstellbare Halbleitervorrichtung
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8624360B2 (en) 2008-11-13 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling channels in 3DIC stacks
US8269341B2 (en) 2008-11-21 2012-09-18 Infineon Technologies Ag Cooling structures and methods
US8314483B2 (en) 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
US7964951B2 (en) 2009-03-16 2011-06-21 Ati Technologies Ulc Multi-die semiconductor package with heat spreader

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050136640A1 (en) * 2002-01-07 2005-06-23 Chuan Hu Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
TWI313505B (en) * 2004-09-30 2009-08-11 Intel Corporatio Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
TWI320227B (en) * 2004-09-30 2010-02-01 Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
TWI322821B (zh) * 2008-10-24 2010-04-01 Sumitomo Bakelite Co

Also Published As

Publication number Publication date
DE102012110982B4 (de) 2016-06-02
TW201342453A (zh) 2013-10-16
US20130273694A1 (en) 2013-10-17
DE102012110982A1 (de) 2013-10-17
US9034695B2 (en) 2015-05-19

Similar Documents

Publication Publication Date Title
TWI506689B (zh) 半導體裝置之製造方法
US11916023B2 (en) Thermal interface material having different thicknesses in packages
TWI669785B (zh) 半導體封裝體及其形成方法
US8816495B2 (en) Structures and formation methods of packages with heat sinks
US11011448B2 (en) IC package including multi-chip unit with bonded integrated heat spreader
KR101884971B1 (ko) 더미 다이들을 갖는 팬-아웃 적층 시스템 인 패키지(sip) 및 그 제조 방법
TWI613740B (zh) 具有較高密度之積體電路封裝結構以及方法
US9984998B2 (en) Devices employing thermal and mechanical enhanced layers and methods of forming same
US9536862B2 (en) Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
TWI546915B (zh) 多重中介層基板電路組件以及其製造方法
TWI538145B (zh) 半導體裝置及其製造方法
US8526186B2 (en) Electronic assembly including die on substrate with heat spreader having an open window on the die
TWI567916B (zh) 封裝與方法
CN104733329B (zh) 半导体封装结构和工艺
CN109427702A (zh) 散热器件和方法
TWI508255B (zh) 散熱型覆晶封裝構造
TW201714274A (zh) 三維晶片堆疊的方法與結構
KR20190045374A (ko) 고효율 열 경로 및 몰딩된 언더필을 구비한 적층형 반도체 다이 조립체
TW201546954A (zh) 半導體裝置的結構及其製造方法
TWI760125B (zh) 半導體元件與半導體封裝件及其製造方法
JP6213554B2 (ja) 半導体装置
TWI587464B (zh) 封裝結構及其製造方法
TW201618246A (zh) 半導體封裝件及其製法
US20150091154A1 (en) Substrateless packages with scribe disposed on heat spreader
JP2007142105A (ja) 半導体装置および半導体装置の製造方法