TWI502706B - Robust joint structure for flip-chip bonding - Google Patents
Robust joint structure for flip-chip bonding Download PDFInfo
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- TWI502706B TWI502706B TW099135905A TW99135905A TWI502706B TW I502706 B TWI502706 B TW I502706B TW 099135905 A TW099135905 A TW 099135905A TW 99135905 A TW99135905 A TW 99135905A TW I502706 B TWI502706 B TW I502706B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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Description
本發明係有關於積體電路，且特別是有關於一種覆晶接合結構。The present invention relates to integrated circuits, and more particularly to a flip chip bonded structure.
在半導體晶片/晶圓的製程中，積體電路裝置(例如電晶體)形成於半導體晶片/晶圓中的半導體基材上。隨後，內連線結構形成於積體電路裝置上。金屬及焊料凸塊形成於半導體晶片/晶圓上，以使積體電路裝置能形成通路。In a semiconductor wafer/wafer process, an integrated circuit device (eg, a transistor) is formed on a semiconductor substrate in a semiconductor wafer/wafer. Subsequently, the interconnect structure is formed on the integrated circuit device. Metal and solder bumps are formed on the semiconductor wafer/wafer to enable the integrated circuit device to form a via.
在半導體晶片的封裝中，通常使用覆晶封裝來接合半導體晶片。半導體晶片中的金屬凸塊及封裝基材中的連接墊係使用焊料來作接合。傳統的共晶焊料凸塊使用含有鉛及錫的材料來接合金屬凸塊。例如，常用的含鉛共晶焊料含有約63%的錫及37%的鉛，此種成分使焊料能具有合適的熔點及低電阻。此外，此種共晶焊料具有良好的破裂抵抗能力。In the packaging of semiconductor wafers, a flip chip package is typically used to bond the semiconductor wafer. The metal bumps in the semiconductor wafer and the connection pads in the package substrate are bonded using solder. Conventional eutectic solder bumps use materials containing lead and tin to bond metal bumps. For example, commonly used lead-containing eutectic solders contain about 63% tin and 37% lead, which allows the solder to have a suitable melting point and low electrical resistance. In addition, such eutectic solders have good fracture resistance.
鉛為具有毒性的材料，因而無鉛材料是較佳的選擇。因此，已發展出以無鉛焊料來取代含鉛焊料的方法。然而，習知的無鉛焊料，例如SnAg、SnAgCu及其介金屬化合物，皆過脆而易碎，因而會遭遇破裂的問題。因此，由無鉛焊料所形成的焊點(solder joint)通常可靠度不足且無法通過例如熱循環之可靠度測試。Lead is a toxic material, so lead-free materials are the better choice. Therefore, a method of replacing lead-containing solder with lead-free solder has been developed. However, conventional lead-free solders, such as SnAg, SnAgCu, and their intermetallic compounds, are too brittle and brittle, and thus suffer from cracking problems. Therefore, solder joints formed of lead-free solders are generally insufficiently reliable and cannot pass reliability tests such as thermal cycling.
焊料破裂通常是由應力所導致。封裝組件中，不同材料間熱膨脹係數(CTE)的差異是造成應力的主要原因之一。例如，矽基材通常具有約3 ppm/℃之熱膨脹係數，低介電常數材料通常具有約20 ppm/℃之熱膨脹係數，而封裝基材通常具有約17 ppm/℃之熱膨脹係數。熱膨脹係數的顯著差異，導致在熱交換時形成應力並施予至結構中。在金屬凸塊中使用銅使得此問題更加惡化，既然銅是剛性材料，可施予高應力至鄰接於銅凸塊之焊料上，並因此使焊料易於破裂。例如，迴焊的製程容許度(process window)(意指可承受重複進行多少次迴焊，不會有破裂產生)對於積體電路的量產可能過窄。並且，所得到的接合結構對於抗電遷移能力不佳。Solder cracking is usually caused by stress. In package components, the difference in coefficient of thermal expansion (CTE) between different materials is one of the main causes of stress. For example, tantalum substrates typically have a coefficient of thermal expansion of about 3 ppm/°C, low dielectric constant materials typically have a coefficient of thermal expansion of about 20 ppm/°C, and package substrates typically have a coefficient of thermal expansion of about 17 ppm/°C. Significant differences in thermal expansion coefficients result in stress formation during heat exchange and application to the structure. The use of copper in the metal bumps exacerbates this problem. Since copper is a rigid material, high stress can be applied to the solder adjacent to the copper bumps, and thus the solder is susceptible to cracking. For example, the process window of reflow (meaning how many reflows can be repeated, without cracking) may be too narrow for mass production of integrated circuits. Moreover, the resulting joint structure is not good for electromigration resistance.
本發明係提供一種積體電路結構，包括：一第一工作件，包括：一銅凸塊，位於此第一工作件之主要表面上，且在一平行於第一工作件之主要表面之第一平面中具有一第一尺寸：及一含鎳阻障層，位於此銅凸塊上並與其鄰接；一第二工作件，接合至此第一工作件上且包括：一連接墊，位於此第二工作件之主要表面上；一阻銲層，位於此第二工作件之主要表面，且具有一第二尺寸之阻焊開口，暴露一部份之此連接墊，其中此第二尺寸係以平行於此第二工作件之主要表面之一第二表面所量測，且其中此第一尺寸對此第二尺寸之比例大於約1；以及一焊接區，電性連接此銅凸塊及此連接墊，其中此連接墊及此銅凸塊之間的垂直距離大於約30 μm。The present invention provides an integrated circuit structure, comprising: a first working member, comprising: a copper bump on a main surface of the first working member, and a portion parallel to a main surface of the first working member a plane having a first dimension: and a nickel-containing barrier layer on and adjacent to the copper bump; a second workpiece coupled to the first workpiece and including: a connection pad a main surface of the second working member; a solder resist layer on the main surface of the second working member and having a second size solder resist opening exposing a portion of the connecting pad, wherein the second size is Parallel to a second surface of one of the major surfaces of the second workpiece, and wherein the ratio of the first dimension to the second dimension is greater than about 1; and a soldering region electrically connecting the copper bump and the The connection pad, wherein the vertical distance between the connection pad and the copper bump is greater than about 30 μm.
本發明亦提供一種體體電路結構，包括：一半導體晶片，包括：一半導體基材；一銅凸塊，設置於此半導體基材之主要表面上，且具有一平行於此半導體基材之主要表面之第一水平尺寸；及一含鎳阻障層，位於此銅凸塊上；一封裝基材，包括：一連接墊，位於此封裝基材之主要表面；及一阻焊層，位於此連接墊上並透過此阻焊層中的阻焊開口暴露此連接墊之一中央部分，其中此阻焊開口具有一平行於此第一水平尺寸之第二水平尺寸，且其中此第一水平尺寸對此第二水平尺寸之比例於大於約1；以及一焊料區，透過此阻焊開口電性連接此含鎳阻障層及此連接墊，其中此含鎳阻障層及此連接墊相加的總厚度大於約30 μm。The present invention also provides a body circuit structure comprising: a semiconductor wafer comprising: a semiconductor substrate; a copper bump disposed on a major surface of the semiconductor substrate and having a main parallel to the semiconductor substrate a first horizontal dimension of the surface; and a nickel-containing barrier layer on the copper bump; a package substrate comprising: a connection pad on a main surface of the package substrate; and a solder resist layer located thereon Forming a central portion of the connection pad through the solder resist opening in the solder resist layer, wherein the solder resist opening has a second horizontal dimension parallel to the first horizontal dimension, and wherein the first horizontal dimension pair The second horizontal dimension is greater than about 1; and a solder region is electrically connected to the nickel-containing barrier layer and the connection pad through the solder resist opening, wherein the nickel-containing barrier layer and the connection pad are added The total thickness is greater than about 30 μm.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;
本發明接下來將詳加討論各種的實施例的製造及討論。然而，值得注意的是，本發明所提供之這些實施例僅提供本發明之發明概念，且其可以寬廣的形式應用於各種特定情況下。在此所討論之實施例僅用於舉例說明，並非以各種形式限制本發明。The invention will be discussed in detail below for the fabrication and discussion of various embodiments. However, it is to be noted that the embodiments provided by the present invention provide only the inventive concept of the present invention, and that it can be applied to a wide variety of specific situations. The embodiments discussed herein are for illustrative purposes only and are not intended to limit the invention in any form.
依照本發明實施例，在此提供了一種新穎的積體電路結構，並將討論此實施例之各種變化。在本說明書中的各種圖示及實施例中，相似符號代表相似元件。In accordance with an embodiment of the present invention, a novel integrated circuit structure is provided herein and various variations of this embodiment will be discussed. In the various figures and embodiments of the specification, like symbols represent like elements.
參見第1A圖，首先提供工作件2，其可為包含基材10之半導體晶片。在本說明書中，工作件2亦可稱為晶片2，或可為封裝基材、轉接基材(interposer substrate)或其類似物。在一實施例中，基材10為半導體基材，例如矽基材，或者，其可包含其他半導體材料，例如第III族、第IV族及/或第V族之元素。半導體裝置14，例如電晶體，可形成基材10表面。內連線結構12，其包含金屬線及通孔(未顯示)形成於其中，可形成於基材10上並與半導體裝置14連接。金屬線及通孔可由銅及銅合金形成，且可使用習知的鑲嵌製程形成。內連線結構12可包含習知的層間介電層(ILDs)及金屬間介電層(IMDs)。Referring to FIG. 1A, a workpiece 2, which may be a semiconductor wafer comprising a substrate 10, is first provided. In the present specification, the workpiece 2 may also be referred to as a wafer 2, or may be a package substrate, an interposer substrate, or the like. In one embodiment, substrate 10 is a semiconductor substrate, such as a germanium substrate, or it may comprise other semiconductor materials, such as elements of Group III, Group IV, and/or Group V. A semiconductor device 14, such as a transistor, can form the surface of the substrate 10. The interconnect structure 12, which includes metal lines and vias (not shown) formed therein, may be formed on the substrate 10 and connected to the semiconductor device 14. The metal lines and vias may be formed of copper and a copper alloy, and may be formed using a conventional damascene process. The interconnect structure 12 can comprise conventional interlayer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs).
金屬墊28形成於內連線結構12上。金屬墊28可包含鋁、銅、銀、金、鎳、鎢、前述之合金及/或前述之多層結構。金屬墊28可與半導體裝置14電性連接，例如，透過底下的內連線結構12。保護層30可形成用以覆蓋金屬墊28的邊緣部分。在一實施例中，保護層30係由聚亞醯胺或其他習知介電材料形成，例如氧化矽、氮化矽或前述之多層結構。A metal pad 28 is formed on the interconnect structure 12. Metal pad 28 may comprise aluminum, copper, silver, gold, nickel, tungsten, alloys of the foregoing, and/or multilayer structures as described above. The metal pad 28 can be electrically connected to the semiconductor device 14, for example, through the underlying interconnect structure 12. The protective layer 30 may be formed to cover an edge portion of the metal pad 28. In one embodiment, the protective layer 30 is formed of a polymethyleneamine or other conventional dielectric material, such as hafnium oxide, tantalum nitride, or a multilayer structure as described above.
凸塊下金屬(under bump metallurgy，UBM)32形成於金屬墊28上並與其電性連接。凸塊下金屬32可包含銅層及鈦層(未顯示)。銅凸塊34形成於凸塊下金屬32上。在一實施例中，銅凸塊34由電鍍形成。在形成凸塊下金屬之電鍍製程中，包含形成罩幕於凸塊下金屬層上；圖案化罩幕以形成開口；在開口中電鍍銅凸塊34；及移除罩幕使凸塊下金屬層具有未被覆蓋的部分。銅凸塊34可由實質上純的銅形成，其超過約95%是銅原子，或甚至超過99%。銅凸塊34的厚度T可大於約30 μm，或甚至大於約45 μm。厚度T亦可小於約60 μm。銅凸塊34可具有水平尺寸(長度或寬度)L1，其可介於約80 μm至約110 μm之間。尺寸L1可在平行於工作件2之頂面或底面的平面中量測得到。本領域所屬通常知識者可知的是，在本說明書中所述的尺寸僅用於舉例，且可在不同的製造技術中隨之變化。An under bump metallurgy (UBM) 32 is formed on and electrically connected to the metal pad 28. The under bump metal 32 may comprise a copper layer and a titanium layer (not shown). A copper bump 34 is formed on the under bump metal 32. In an embodiment, the copper bumps 34 are formed by electroplating. In the electroplating process for forming a metal under bump, comprising forming a mask on the underlying metal layer; patterning the mask to form an opening; plating a copper bump 34 in the opening; and removing the mask to make the metal under the bump The layer has uncovered portions. Copper bumps 34 may be formed of substantially pure copper, more than about 95% of which are copper atoms, or even more than 99%. The thickness T of the copper bumps 34 can be greater than about 30 μm, or even greater than about 45 μm. The thickness T can also be less than about 60 μm. The copper bumps 34 can have a horizontal dimension (length or width) L1 that can be between about 80 μm and about 110 μm. The dimension L1 can be measured in a plane parallel to the top or bottom surface of the workpiece 2. It will be apparent to those skilled in the art that the dimensions described in this specification are by way of example only and may vary in different manufacturing techniques.
阻障層36係形成於銅凸塊34上，例如，由電鍍形成。阻障層36可由鎳或鎳合金形成，因而在此後亦可稱為(含)鎳阻障層36，雖然其亦可由其他金屬形成。焊料層38可形成於鎳阻障層36上。焊料層38可相對較薄，例如其厚度可小於約35 μm。此外，電鍍形成焊料層38時，所使用之罩幕可使用與電鍍銅凸塊34及鎳阻障層36時所使用的罩幕相同。因此，可限制焊料層38的邊緣及鎳阻障層36僅位於銅凸塊34所佔區域之垂直向上的區域內。在一實施例中，鎳阻障層36之厚度大於約0.1 μm。焊料層38之厚度可小於約35 μm，或介於約1 μm至約35 μm之間。The barrier layer 36 is formed on the copper bumps 34, for example, by electroplating. The barrier layer 36 may be formed of nickel or a nickel alloy and may hereinafter be referred to as a nickel barrier layer 36, although it may be formed of other metals. A solder layer 38 may be formed on the nickel barrier layer 36. Solder layer 38 can be relatively thin, for example, having a thickness of less than about 35 μm. Further, when the solder layer 38 is formed by electroplating, the mask used may be the same as that used when the copper bump 34 and the nickel barrier layer 36 are plated. Therefore, the edge of the solder layer 38 and the nickel barrier layer 36 can be limited to be located only in the vertically upward region of the area occupied by the copper bumps 34. In one embodiment, the nickel barrier layer 36 has a thickness greater than about 0.1 μm. The thickness of the solder layer 38 can be less than about 35 μm, or between about 1 μm to about 35 μm.
在另一實施例中，如第1B圖所示，沒有形成焊料層38，但形成含金層40於銅凸塊34上。電鍍銅凸塊34、鎳阻障層36及/或含金層40所使用之罩幕可使用與電鍍銅凸塊34時所使用之罩幕(未顯示)相同。因此，形成之鎳阻障層36及/或含金層40係為限制在銅凸塊34所佔區域垂直向上的區域內，但未形成在銅凸塊34的側壁上。在又一實施例中，係在移除用以電鍍銅凸塊34之罩幕後，電鍍形成鎳阻障層36及/或含金層40。因此，鎳阻障層36及/或含金層40亦形成於銅凸塊34之側壁上。含金層40之厚度可小於約1 μm。In another embodiment, as shown in FIG. 1B, the solder layer 38 is not formed, but the gold-containing layer 40 is formed on the copper bumps 34. The mask used for the electroplated copper bumps 34, the nickel barrier layer 36, and/or the gold-containing layer 40 can be the same as the mask (not shown) used in electroplating the copper bumps 34. Therefore, the formed nickel barrier layer 36 and/or the gold-containing layer 40 is limited to a region vertically perpendicular to the region occupied by the copper bumps 34, but is not formed on the sidewalls of the copper bumps 34. In yet another embodiment, the nickel barrier layer 36 and/or the gold-containing layer 40 are electroplated after the mask used to plate the copper bumps 34 is removed. Therefore, the nickel barrier layer 36 and/or the gold-containing layer 40 are also formed on the sidewalls of the copper bumps 34. The gold-containing layer 40 can have a thickness of less than about 1 μm.
第2圖顯示工作件100。在一實施例中，工作件100為封裝基材(因而此後稱為封裝基材100)，雖然其亦可為半導體晶片、轉接基材或其類似物。封裝基材100包含連接墊110，其透過金屬內連線112與連接墊114電性連接。連接墊114及連接墊110位於封裝基材100之兩側。金屬內連線112可形成於介電基材116中。Figure 2 shows the work piece 100. In one embodiment, the workpiece 100 is a package substrate (and thus referred to hereinafter as package substrate 100), although it may also be a semiconductor wafer, a transfer substrate, or the like. The package substrate 100 includes a connection pad 110 electrically connected to the connection pad 114 through the metal interconnection 112. The connection pads 114 and the connection pads 110 are located on both sides of the package substrate 100. Metal interconnects 112 may be formed in dielectric substrate 116.
連接墊110包含金屬墊122，其可由銅(例如純或實質上為純的銅)、鋁、銀及/或前述之合金形成。阻障層124可視需要由例如電鍍或無電電鍍方式形成於金屬墊122上。阻障層124可由鎳或鎳合金形成，或亦可添加其他金屬。阻銲層128形成於金屬墊122上，且具有阻焊開口(solder resist opening，SRO)123，透過此阻焊開口123暴露出連接墊110。在一實施例中，阻焊開口123具有一尺寸L2，其可小於約100 μm，例如可介於約60至約100 μm之間。The connection pad 110 includes a metal pad 122 that may be formed of copper (eg, pure or substantially pure copper), aluminum, silver, and/or alloys of the foregoing. The barrier layer 124 can be formed on the metal pad 122 by, for example, electroplating or electroless plating, as desired. The barrier layer 124 may be formed of nickel or a nickel alloy, or other metals may be added. The solder resist layer 128 is formed on the metal pad 122 and has a solder resist opening (SRO) 123 through which the connection pad 110 is exposed. In one embodiment, the solder mask opening 123 has a dimension L2 that can be less than about 100 μιη, such as between about 60 and about 100 μιη.
焊料層130設置於連接墊110上。在一實施例中，焊料層130係由無鉛材料形成，例如包含SnAg、SnAgCu等。或者，焊料層130亦可由其他例如含鉛及錫之共晶焊料形成。The solder layer 130 is disposed on the connection pad 110. In an embodiment, the solder layer 130 is formed of a lead-free material, for example, including SnAg, SnAgCu, or the like. Alternatively, the solder layer 130 may be formed of other eutectic solders such as lead and tin.
如第3圖所示，無論第1A或1B圖所示之工作件2皆可透過覆晶接合與工作件100接合。進行例如回焊或熱壓接合之高溫製程，以熔融焊料層130及焊料層38。因此，焊料層130得以將工作件2及工作件100相互接合，並使銅凸塊34及連接墊110電性連接。藉由熔融焊料層130及焊料層38所形成之回焊區域，在此後稱為焊接區(solder joint region)。As shown in Fig. 3, the workpiece 2 shown in Fig. 1A or 1B can be joined to the workpiece 100 through a flip chip joint. A high temperature process such as reflow or thermocompression bonding is performed to melt the solder layer 130 and the solder layer 38. Therefore, the solder layer 130 can bond the workpiece 2 and the workpiece 100 to each other, and electrically connect the copper bumps 34 and the connection pads 110. The reflow region formed by the molten solder layer 130 and the solder layer 38 is hereinafter referred to as a solder joint region.
所得結構如第3圖所示，尺寸L1對尺寸L2的比例(L1/L2)為約大於1。此比例亦可大於約1.15。銅凸塊34及連接墊110之間的距離D可大於約30 μm或甚至大於約40 μm。在某些實施例中，銅凸塊34的表面為非平坦的，距離D係非在銅凸塊34的中央處量測，而是在銅凸塊34之角隅(corner)處量測(如虛線及箭頭所示)。因此，距離D可與焊接區131及鎳阻障層36(或更加上含金層40，如其存在)之總厚度之相等。距離D及比例L1/L2的重要性將於以下段落中討論。The resultant structure is as shown in Fig. 3, and the ratio (L1/L2) of the dimension L1 to the dimension L2 is about more than 1. This ratio can also be greater than about 1.15. The distance D between the copper bumps 34 and the connection pads 110 can be greater than about 30 μm or even greater than about 40 μm. In some embodiments, the surface of the copper bumps 34 is non-flat, and the distance D is not measured at the center of the copper bumps 34, but is measured at the corners of the copper bumps 34 ( As indicated by the dotted line and the arrow). Thus, the distance D can be equal to the total thickness of the land 131 and the nickel barrier layer 36 (or more preferably the gold-containing layer 40, if present). The importance of distance D and ratio L1/L2 will be discussed in the following paragraphs.
第4圖顯示本發明之另一實施例，其中銅凸塊34及鎳阻障層36(或含金層40，未顯示於第4圖中，請參見第1B圖)形成於封裝基材100之一側上，且在封裝基材100與半導體晶片2相接合之前，焊料層130(請參見第2圖)為預先設置在半導體晶片2之一側上。4 shows another embodiment of the present invention in which a copper bump 34 and a nickel barrier layer 36 (or a gold-containing layer 40, not shown in FIG. 4, see FIG. 1B) are formed on the package substrate 100. On one side, and before the package substrate 100 is bonded to the semiconductor wafer 2, the solder layer 130 (see FIG. 2) is previously disposed on one side of the semiconductor wafer 2.
第5圖顯示本發明之一些實驗數據，其顯示距離D及比例L1/L2(參見第3圖)之重要性。由這些實驗數據可發現到不可預期的結果。X軸為比例L1/L2。Y軸為距離D。量測每個樣品晶圓在焊接區131(參見第3圖)破裂的最大長度。可發現的是，破裂的最大長度為比例L1/L2與距離D的函數，且意外的是，當比例L1/L2與距離D增大至某種程度後，可實質上消除焊接區131中的破裂。可觀察到，當比例L1/L2增加及/或距離D增加時，在焊接區的破裂長度可變得較小。實驗顯示當比例L1/L2大於約1.15且距離D大於約40 μm時，在晶圓中的破裂最大長度將降低至可接受的程度，例如小於約15 μm，且有時甚至不會破裂。另一方面，當比例L1/L2小於約1.15及/或距離D小於約40 μm時，破裂最大長度即顯著增長，有時甚至達約83 μm或更長。可能的解釋為，銅凸塊34的角隅造成高應力，且連接墊110(在連接墊110及焊接區131之間的區段)角隅的應力亦很高。藉由將高應力區遙遠地隔離，將實質上消除倍增效應(multiplication effect)，因而使應力降低至某種程度，例如至產生破裂之臨界點以下。比例L1/L2的增加更可使應力分散。Figure 5 shows some experimental data of the present invention showing the importance of distance D and ratio L1/L2 (see Figure 3). Unexpected results can be found from these experimental data. The X axis is the ratio L1/L2. The Y axis is the distance D. The maximum length of rupture of each sample wafer in the lands 131 (see Figure 3) was measured. It can be found that the maximum length of the rupture is a function of the ratio L1/L2 and the distance D, and unexpectedly, when the ratio L1/L2 and the distance D are increased to some extent, the lands 113 can be substantially eliminated. rupture. It can be observed that as the ratio L1/L2 increases and/or the distance D increases, the length of the break in the weld zone can become smaller. Experiments have shown that when the ratio L1/L2 is greater than about 1.15 and the distance D is greater than about 40 μm, the maximum length of cracking in the wafer will be reduced to an acceptable level, such as less than about 15 μm, and sometimes not even broken. On the other hand, when the ratio L1/L2 is less than about 1.15 and/or the distance D is less than about 40 μm, the maximum length of cracking is significantly increased, sometimes even up to about 83 μm or longer. A possible explanation is that the corners of the copper bumps 34 cause high stress, and the stress of the corner pads of the connection pads 110 (the sections between the connection pads 110 and the pads 131) is also high. By isolating the high stress regions remotely, the multiplication effect is substantially eliminated, thereby reducing the stress to some extent, for example, below the critical point at which the crack occurs. The increase in the ratio L1/L2 allows the stress to be dispersed.
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外，熟知本領域技藝人士將可依照本發明所揭示之現有或未來所發展之特定程序、機器、製造、物質之組合、功能、方法或步驟達成相同的功能或相同的結果。因此本發明之保護範圍包含這些程序、機器、製造、物質之組合、功能、方法或步驟。While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. In addition, those skilled in the art will be able to achieve the same function or the same results in the specific procedures, machines, manufactures, combinations, functions, methods, or steps of the present invention. The scope of the invention, therefore, encompasses such procedures, machines, manufactures, combinations, functions, methods or steps.
2‧‧‧工作件2‧‧‧Workpieces
10‧‧‧基材10‧‧‧Substrate
12‧‧‧內連線結構12‧‧‧Interconnection structure
14‧‧‧半導體裝置14‧‧‧Semiconductor device
28‧‧‧金屬墊28‧‧‧Metal pad
30‧‧‧保護層30‧‧‧Protective layer
32‧‧‧凸塊下金屬32‧‧‧Under bump metal
34‧‧‧銅凸塊34‧‧‧ copper bumps
36‧‧‧鎳阻障層36‧‧‧ Nickel barrier layer
38‧‧‧焊料層38‧‧‧ solder layer
40‧‧‧含金層40‧‧‧ gold layer
100‧‧‧工作件100‧‧‧Workpieces
110‧‧‧連接墊110‧‧‧Connecting mat
112‧‧‧金屬內連線112‧‧‧Metal interconnection
114‧‧‧連接墊114‧‧‧Connecting mat
116‧‧‧介電基材116‧‧‧Dielectric substrate
122‧‧‧金屬墊122‧‧‧Metal pad
123‧‧‧阻焊開口123‧‧‧ solder mask opening
124‧‧‧阻障層124‧‧‧Barrier layer
128‧‧‧阻銲層128‧‧‧ solder mask
130‧‧‧焊料層130‧‧‧ solder layer
131‧‧‧焊接區131‧‧‧welding area
第1A及1B圖顯示含銅凸塊之半導體晶片之剖面圖；第2圖顯示含有連接墊及設於其上之銲球之封裝基材；第3圖顯示將第1A/1B圖所示之結構接合至第2圖所示之結構；第4圖顯示依照本發明另一實施例之封裝體；以及第5圖顯示本發明實施例之實驗結果。1A and 1B are cross-sectional views showing a semiconductor wafer containing copper bumps; FIG. 2 is a view showing a package substrate including a connection pad and a solder ball provided thereon; and FIG. 3 is a view showing the first A/1B. The structure is bonded to the structure shown in Fig. 2; Fig. 4 shows a package according to another embodiment of the present invention; and Fig. 5 shows the experimental results of the embodiment of the present invention.
2．．．工作件2. . . Work piece
10．．．基材10. . . Substrate
12．．．內連線結構12. . . Inline structure
14．．．半導體裝置14. . . Semiconductor device
28．．．金屬墊28. . . Metal pad
30．．．保護層30. . . The protective layer
32．．．凸塊下金屬32. . . Bump metal
34．．．銅凸塊34. . . Copper bump
36．．．鎳阻障層36. . . Nickel barrier layer
100．．．工作件100. . . Work piece
110．．．連接墊110. . . Connection pad
114．．．連接墊114. . . Connection pad
116．．．介電基材116. . . Dielectric substrate
122．．．金屬墊122. . . Metal pad
128．．．阻銲層128. . . Solder mask
131．．．焊接區131. . . Weld zone
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US25619909P | 2009-10-29 | 2009-10-29 | |
| US12/842,304 US8847387B2 (en) | 2009-10-29 | 2010-07-23 | Robust joint structure for flip-chip bonding |
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| TW201115704A TW201115704A (en) | 2011-05-01 |
| TWI502706B true TWI502706B (en) | 2015-10-01 |
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| TWI511246B (en) * | 2011-07-05 | 2015-12-01 | Chipbond Technology Corp | Bumping process and structure thereof |
| CN103745939B (en) * | 2013-12-05 | 2017-02-15 | 通富微电子股份有限公司 | Packaging structure forming method |
| CN107871674A (en) * | 2017-09-26 | 2018-04-03 | 宁波芯健半导体有限公司 | A kind of method for packing of 50 μm of copper posts |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI267206B (en) * | 2005-03-17 | 2006-11-21 | Taiwan Semiconductor Mfg | Package assembly |
| US20090091024A1 (en) * | 2007-06-11 | 2009-04-09 | Texas Instruments Incorporated | Stable Gold Bump Solder Connections |
| US20090146303A1 (en) * | 2007-09-28 | 2009-06-11 | Tessera, Inc. | Flip Chip Interconnection with double post |
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| US6550666B2 (en) * | 2001-08-21 | 2003-04-22 | Advanpack Solutions Pte Ltd | Method for forming a flip chip on leadframe semiconductor package |
| CN1169413C (en) * | 2001-12-05 | 2004-09-29 | 全懋精密科技股份有限公司 | Soldering tin electroplating method to organic circuit board |
| AU2003218085A1 (en) * | 2002-03-12 | 2003-09-29 | Fairchild Semiconductor Corporation | Wafer-level coated copper stud bumps |
| CN2845167Y (en) * | 2005-06-14 | 2006-12-06 | 威盛电子股份有限公司 | Reversed sheet packing structure |
| JP4431606B2 (en) * | 2007-10-05 | 2010-03-17 | シャープ株式会社 | Semiconductor device, semiconductor device mounting method, and semiconductor device mounting structure |
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|---|---|---|---|---|
| TWI267206B (en) * | 2005-03-17 | 2006-11-21 | Taiwan Semiconductor Mfg | Package assembly |
| US20090091024A1 (en) * | 2007-06-11 | 2009-04-09 | Texas Instruments Incorporated | Stable Gold Bump Solder Connections |
| US20090146303A1 (en) * | 2007-09-28 | 2009-06-11 | Tessera, Inc. | Flip Chip Interconnection with double post |
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| CN102064136A (en) | 2011-05-18 |
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