TWI501551B - Frequency divider circuit - Google Patents
Frequency divider circuit Download PDFInfo
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- TWI501551B TWI501551B TW102116900A TW102116900A TWI501551B TW I501551 B TWI501551 B TW I501551B TW 102116900 A TW102116900 A TW 102116900A TW 102116900 A TW102116900 A TW 102116900A TW I501551 B TWI501551 B TW I501551B
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本發明是有關於一種相位切換電路及應用相位切換電路之相位切換除頻器電路，特別是有關於一種可提高解析度之相位切換除頻器電路及其相位切換電路。The invention relates to a phase switching circuit and a phase switching frequency divider circuit using the phase switching circuit, in particular to a phase switching frequency divider circuit and a phase switching circuit thereof with improved resolution.
第1圖繪示習知技術之一種除以三電路之電路圖。第1圖繪示的除以三電路包含四正反器DFF、二反或閘NOR及二或閘OR，且除以三電路之輸入端需要差動輸入信號CLK_I以及差動輸入信號CLK_Q，但其僅能產生輸出訊號OUT_T及OUT_Q，故如須產生四個不同相位的輸出信號，必須需要兩組的除以三電路才能完成。此除以三電路存在有振幅大小不相等以及頻寬的限制之問題。FIG. 1 is a circuit diagram of a conventional circuit divided by three circuits. The divide by three circuit includes four flip-flops DFF, two-reverse or gate NOR, and two or gate OR, and the input of the three circuits requires a differential input signal CLK_I and a differential input signal CLK_Q, but It can only generate the output signals OUT_T and OUT_Q, so if four different phase output signals are to be generated, it is necessary to divide the two groups by three circuits. This division by the three circuits has problems in that the amplitudes are not equal and the bandwidth is limited.
第2A圖及第2B圖係繪示習知技術之一種多相位訊號產生裝置之電路圖及訊號圖。多相位訊號產生裝置包含六正反器DFF及四延遲器BUF，其藉由接收同時到達的時脈信號CLK，並依據同時到達的時脈信號CLK來對除頻信號DIV4進行延遲，進而產生四個不同相位的輸出信號I+、輸出信號Q+、輸出信號I-及輸出信號Q-。與上述習知技術相比，此多相位訊號產生裝置僅需要利用單端輸入的 時脈信號CLK，便可以達到產生至少四個相位的多相位輸出信號，而不需要差動輸入信號。2A and 2B are circuit diagrams and signal diagrams of a multi-phase signal generating apparatus of the prior art. The multi-phase signal generating device comprises a six-reactor DFF and a four-depressor BUF, which receives the simultaneously arriving clock signal CLK and delays the frequency-divided signal DIV4 according to the simultaneously-arrived clock signal CLK, thereby generating four Output signals I+, output signals Q+, output signals I-, and output signals Q- of different phases. Compared with the above prior art, the multi-phase signal generating device only needs to utilize single-ended input. With the clock signal CLK, a multi-phase output signal that produces at least four phases can be achieved without the need for a differential input signal.
以上之習知技術皆用以產生多相位，而第3圖則繪示習知技術之一種高解析度頻率合成器(High resolution frequency synthesis)之電路圖，此高解析度頻率合成器包含除頻器N1及除頻器N2，其中除頻器N1之除率為N1，除頻器N2之除率為N2，輸入訊號Fref_1經除頻器N1改變成輸入除頻器N2的參考頻率Fref_2(Fout_1)，藉此可提升除頻器N2的輸出訊號Fout_2的解析度。The above conventional techniques are used to generate multi-phase, and the third figure shows a circuit diagram of a high resolution frequency synthesizer of the prior art. The high-resolution frequency synthesizer includes a frequency divider. N1 and the frequency divider N2, wherein the division ratio of the frequency divider N1 is N1, the division ratio of the frequency divider N2 is N2, and the input signal Fref_1 is changed to the reference frequency Fref_2 (Fout_1) of the input frequency divider N2 via the frequency divider N1. Thereby, the resolution of the output signal Fout_2 of the frequency divider N2 can be improved.
然而，上述的習知各種除頻器電路，其電路的工作頻率會受到限制，雖可產生多相位輸出進而提升工作頻率範圍，但是電路設計卻十分複雜。However, in the above-mentioned various frequency divider circuits, the operating frequency of the circuit is limited, and although the multi-phase output can be generated to increase the operating frequency range, the circuit design is very complicated.
本發明之一態樣之一實施方式是在提供一種相位切換電路，其係配合於一除頻器電路，相位切換電路包含一控制電路以及一切換電路。控制電路包含一累加器(accumlator)及一解多工器(demultiplexer)，累加器耦接除頻器電路，累加器接收除頻器電路之一輸出訊號，且累加器輸出一控制訊號，控制訊號為二進位制。解多工器耦接累加器，解多工器將累加器輸出之控制訊號轉為十進位制。切換電路耦接除頻器電路及解多工器，切換電路包含至少二注入鎖定電晶體(injection MOS)及至少二切換電晶體(switch MOS)。各切換電晶體對應耦接各注入鎖定電晶體，且各切換電晶體接收十進位制之控制訊號並進行切換，藉 此使對應之各注入鎖定電晶體之頻率同步除頻器電路所需之頻率，用以使輸出訊號之頻率除以二。One embodiment of an aspect of the present invention provides a phase switching circuit that is coupled to a frequency divider circuit that includes a control circuit and a switching circuit. The control circuit includes an accumulator and a demultiplexer. The accumulator is coupled to the frequency divider circuit, the accumulator receives an output signal of the frequency divider circuit, and the accumulator outputs a control signal, and the control signal It is a binary system. The demultiplexer is coupled to the accumulator, and the demultiplexer converts the control signal output by the accumulator into a decimal system. The switching circuit is coupled to the frequency divider circuit and the demultiplexer, and the switching circuit comprises at least two injection locking transistors (injection MOS) and at least two switching transistors (switch MOS). Each switching transistor is coupled to each injection locking transistor, and each switching transistor receives a decimal control signal and switches This causes the corresponding frequency of each of the frequency-synchronized frequency divider circuits injected into the lock transistor to be used to divide the frequency of the output signal by two.
本發明之一態樣之另一實施方式是在提供一種相位切換除頻器電路，包含一四級環型振盪器(ring oscillator)、四注入式切換電路以及一控制電路，四級環型振盪器包含四雙端反相器，各雙端反相器之輸出端耦接至下一級之雙端反相器之輸入端，第四級之雙端反相器之輸出端回授至第一級之雙端反相器之輸入端，且第四級之雙端反相器之輸出端為四級環型振盪器之輸出端。四注入式切換電路對應各反相器，各注入式切換電路包含四注入鎖定電晶體及八切換電晶體，各二切換電晶體分別對應耦接各注入鎖定電晶體及各雙端反相器之輸出端。控制電路耦接注入式切換電路，控制電路包含一累加器及一解多工器，累加器耦接四級環型振盪器，且累加器輸出一控制訊號，控制訊號為二進位制。解多工器耦接累加器及對應之切換電晶體，解多工器將累加器輸出之控制訊號轉為十進位制，用以控制各切換電晶體。Another embodiment of an aspect of the present invention provides a phase switching frequency divider circuit including a four-stage ring oscillator, a four-injection switching circuit, and a control circuit, four-stage ring type oscillation. The device comprises four double-ended inverters, the output ends of the double-ended inverters are coupled to the input ends of the double-ended inverters of the next stage, and the output terminals of the fourth-stage double-ended inverters are fed back to the first The input of the double-ended inverter of the stage, and the output of the fourth-stage double-ended inverter is the output of the four-stage ring oscillator. The four injection switching circuits correspond to the inverters, and each of the injection switching circuits includes four injection locking transistors and eight switching transistors, and each of the two switching transistors is respectively coupled to each of the injection locking transistors and the double-ended inverters. Output. The control circuit is coupled to the injection switching circuit. The control circuit includes an accumulator and a demultiplexer. The accumulator is coupled to the four-stage ring oscillator, and the accumulator outputs a control signal, and the control signal is a binary system. The demultiplexer is coupled to the accumulator and the corresponding switching transistor, and the demultiplexer converts the control signal outputted by the accumulator into a decimal system for controlling each switching transistor.
依據本發明一實施例，上述各雙端反相器包含一第一電晶體、一第二電晶體、一第三電晶體及一第四電晶體，第一電晶體之閘極為雙端反相器之正極輸入，第一電晶體之汲極為雙端反相器之負極輸出。第二電晶體之閘極為雙端反相器之負極輸入，第二電晶體之汲極為雙端反相器之正極輸出。第三電晶體之汲極耦接第一電晶體之汲極，第三電晶體之閘極耦接第二電晶體之汲極。第四電晶 體之汲極耦接第二電晶體之汲極，第四電晶體之閘極耦接第一電晶體之汲極。According to an embodiment of the invention, each of the double-ended inverters comprises a first transistor, a second transistor, a third transistor and a fourth transistor, and the gate of the first transistor is extremely double-ended The positive input of the device, the first transistor is the negative output of the double-ended inverter. The gate of the second transistor is the negative input of the double-ended inverter, and the second transistor is the positive output of the double-ended inverter. The drain of the third transistor is coupled to the drain of the first transistor, and the gate of the third transistor is coupled to the drain of the second transistor. Fourth crystal The drain of the body is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.
依據本發明另一實施例，上述累加器包含一第一互斥或閘、一第一及閘、一第二互斥或閘、一第二及閘、一或閘、一第一D型正反器、一第二D型正反器、一第三及閘及一第三D型正反器，第一互斥或閘之輸入端接收一輸入訊號及一接地訊號。第一及閘輸入端接收輸入訊號及接地訊號。第二互斥或閘輸入端耦接第一互斥或閘之輸出端，第二互斥或閘輸出一相加訊號。第二及閘輸入端耦接第一互斥或閘之輸出端。或閘耦接第一及閘之輸出端及第二及閘之輸出端，或閘之輸出端輸出一進位訊號。第一D型正反器之輸入端耦接第二互斥或閘之輸出端，第一D型正反器之時脈端耦接四級環型振盪器之輸出端。第二D型正反器之輸入端耦接或閘之輸出端，第二D型正反器之時脈端耦接四級環型振盪器之輸出端。第三及閘之輸入端耦接第一D型正反器之輸出端及第二D型正反器之輸出端，第三及閘之輸出端耦接第一D型正反器之重置端及第二D型正反器之重置端。第三D型正反器之輸入端耦接第二互斥或閘之輸出端，第三D型正反器之時脈端耦接四級環型振盪器之輸出端，第三D型正反器之重置端耦接第三及閘之輸出端，第三D型正反器之輸出端耦接第二互斥或閘之輸入端及第二及閘之輸入端。According to another embodiment of the present invention, the accumulator includes a first mutex or gate, a first gate, a second mutex or gate, a second gate, a gate, and a first D-type. The inverter, a second D-type flip-flop, a third-gate and a third D-type flip-flop, the input of the first mutex or gate receives an input signal and a ground signal. The first and the gate inputs receive the input signal and the ground signal. The second mutex or gate input is coupled to the output of the first mutex or gate, and the second mutex or gate outputs an addition signal. The second AND gate input is coupled to the output of the first mutex or gate. Or the gate is coupled to the output end of the first gate and the output end of the second gate, or the output end of the gate outputs a carry signal. The input end of the first D-type flip-flop is coupled to the output end of the second mutex or the gate, and the clock end of the first D-type flip-flop is coupled to the output end of the fourth-stage ring oscillator. The input end of the second D-type flip-flop is coupled to the output end of the gate, and the clock end of the second D-type flip-flop is coupled to the output end of the fourth-stage ring oscillator. The input end of the third gate is coupled to the output end of the first D-type flip-flop and the output end of the second D-type flip-flop, and the output end of the third gate is coupled to the reset of the first D-type flip-flop The reset end of the terminal and the second D-type flip-flop. The input end of the third D-type flip-flop is coupled to the output end of the second mutex or the gate, and the clock end of the third D-type flip-flop is coupled to the output end of the four-stage ring oscillator, and the third D-type is positive The reset end of the counter is coupled to the output end of the third and the gate, and the output end of the third D-type flip-flop is coupled to the input end of the second mutex or gate and the input end of the second gate.
依據本發明又一實施例，上述解多工器包含一第一單端反相器、一第二單端反相器、一第四及閘、一第 五及閘、一第六及閘以及一第七及閘，第一單端反相器之輸入端耦接或閘之輸出端，用以接收進位訊號。第二單端反相器之輸入端耦接第二互斥或閘之輸出端，用以接收相加訊號。第四及閘之輸入端耦接第一單端反相器之輸出端及第二單端反相器之輸出端。第五及閘之輸入端耦接第一單端反相器之輸出端及第二互斥或閘之輸出端。第六及閘之輸入端耦接第二單端反相器之輸出端及或閘之輸出端。第七及閘輸入端耦接第二互斥或閘之輸出端及或閘之輸出端。According to still another embodiment of the present invention, the demultiplexer includes a first single-ended inverter, a second single-ended inverter, a fourth gate, and a first The fifth and the gates, the sixth and the gates, and the seventh and the gates, the input end of the first single-ended inverter is coupled to the output of the gate for receiving the carry signal. The input end of the second single-ended inverter is coupled to the output of the second mutex or gate for receiving the addition signal. The input end of the fourth sum gate is coupled to the output end of the first single-ended inverter and the output end of the second single-ended inverter. The input end of the fifth sum gate is coupled to the output end of the first single-ended inverter and the output end of the second mutex or gate. The input end of the sixth and the gate is coupled to the output end of the second single-ended inverter and the output end of the gate. The seventh and gate inputs are coupled to the output of the second mutex or gate and the output of the gate.
本發明之一態樣之再一實施方式是在提供一種相位切換除頻器電路，包含一主從除頻器、一切換電路以及一控制電路。主從除頻器包含一主正反器及一從正反器，從正反器之輸入端耦接主正反器之輸出端，從正反器之輸出端回授至主正反器之輸入端。切換電路耦接主正反器及從正反器，各切換電路包含四注入鎖定電晶體及四切換電晶體，其中各切換電晶體分別對應耦接各注入鎖定電晶體。控制電路耦接切換電路，控制電路包含一累加器及一解多工器，累加器耦接主正反器及從正反器，且累加器輸出一控制訊號，控制訊號為二進位制。解多工器耦接累加器及對應之切換電晶體，解多工器將累加器輸出之控制訊號轉為十進位制，用以控制四切換電晶體。Yet another embodiment of an aspect of the present invention provides a phase switching frequency divider circuit including a master slave frequency divider, a switching circuit, and a control circuit. The master-slave frequency divider comprises a main flip-flop and a slave flip-flop, and the input end of the flip-flop is coupled to the output of the main flip-flop, and is fed back from the output of the flip-flop to the main flip-flop. Input. The switching circuit is coupled to the main flip-flop and the slave flip-flop. Each switching circuit comprises a four-injection locking transistor and a four-switching transistor, wherein each switching transistor is respectively coupled to each of the injection locking transistors. The control circuit is coupled to the switching circuit. The control circuit includes an accumulator and a demultiplexer. The accumulator is coupled to the main flip-flop and the slave flip-flop, and the accumulator outputs a control signal, and the control signal is a binary system. The demultiplexer is coupled to the accumulator and the corresponding switching transistor, and the demultiplexer converts the control signal outputted by the accumulator into a decimal system for controlling the four switching transistors.
本發明之一態樣之又一實施方式是在提供一種相位切換除頻器電路，包含一電流式邏輯除頻器、四切換電路以及一控制電路，電流式邏輯除頻器包含一第一輸 入閂(latch)、一第一延遲閂、一第二輸入閂以及一第二延遲閂。第一延遲閂耦接第一輸入閂。第二輸入閂耦接第一輸入閂及第一延遲閂。第二延遲閂耦接第二輸入閂及第一輸入閂。四切換電路中，各切換電路分別對應耦接第一輸入閂、第一延遲閂、第二輸入閂及第二延遲閂，且各切換電路包含四注入鎖定電晶體及四切換電晶體。其中各切換電晶體分別對應耦接各注入鎖定電晶體。控制電路耦接切換電路，控制電路包含一累加器及一解多工器，累加器耦接電流式邏輯除頻器，且累加器輸出一控制訊號，控制訊號為二進位制。解多工器耦接累加器及對應之切換電晶體，解多工器將累加器輸出之控制訊號轉為十進位制，用以控制四切換電晶體。Yet another embodiment of the present invention provides a phase switching frequency divider circuit including a current logic divider, a four switching circuit, and a control circuit. The current logic divider includes a first input. A latch, a first delay latch, a second input latch, and a second delay latch. The first delay latch is coupled to the first input latch. The second input latch is coupled to the first input latch and the first delay latch. The second delay latch is coupled to the second input latch and the first input latch. In the four switching circuits, each switching circuit is respectively coupled to the first input latch, the first delay latch, the second input latch and the second delay latch, and each switching circuit comprises four injection locking transistors and four switching transistors. Each of the switching transistors is respectively coupled to each of the injection locking transistors. The control circuit is coupled to the switching circuit. The control circuit includes an accumulator and a demultiplexer. The accumulator is coupled to the current logic demultiplexer, and the accumulator outputs a control signal, and the control signal is a binary system. The demultiplexer is coupled to the accumulator and the corresponding switching transistor, and the demultiplexer converts the control signal outputted by the accumulator into a decimal system for controlling the four switching transistors.
由此可得知本發明之相位切換電路及應用相位切換電路之相位切換除頻器電路，藉由相位切換電路之控制電路決定切換電路之切換順序，藉此可提高相位切換除頻器電路之解析度。Therefore, the phase switching circuit of the present invention and the phase switching frequency divider circuit using the phase switching circuit can be known, and the switching circuit of the phase switching circuit determines the switching sequence of the switching circuit, thereby improving the phase switching frequency divider circuit. Resolution.
100‧‧‧相位切換除頻器電路100‧‧‧ phase switching frequency divider circuit
200‧‧‧四級環型振盪器200‧‧‧four-stage ring oscillator
210‧‧‧雙端反相器210‧‧‧Double-end inverter
211‧‧‧第一電晶體211‧‧‧First transistor
212‧‧‧第二電晶體212‧‧‧Second transistor
213‧‧‧第三電晶體213‧‧‧ Third transistor
214‧‧‧第四電晶體214‧‧‧4th transistor
300‧‧‧注入式切換電路300‧‧‧Injection switching circuit
310‧‧‧注入鎖定電晶體310‧‧‧Injected locking transistor
320‧‧‧切換電晶體320‧‧‧Switching transistor
400‧‧‧控制電路400‧‧‧Control circuit
410‧‧‧累加器410‧‧‧ accumulator
411‧‧‧第一互斥或閘411‧‧‧First mutual exclusion or gate
412‧‧‧第一及閘412‧‧‧First Gate
413‧‧‧第二互斥或閘413‧‧‧Second exclusive or gate
414‧‧‧第二及閘414‧‧‧Second Gate
415‧‧‧或閘415‧‧‧ or gate
416‧‧‧第一D型正反器416‧‧‧First D-type flip-flop
417‧‧‧第二D型正反器417‧‧‧Second D-type flip-flop
418‧‧‧第三及閘418‧‧‧ Third Gate
419‧‧‧第三D型正反器419‧‧‧ Third D-type flip-flop
420‧‧‧解多工器420‧‧ ‧ multiplexer
421‧‧‧第一單端反相器421‧‧‧First single-ended inverter
422‧‧‧第二單端反相器422‧‧‧Second single-ended inverter
423‧‧‧第四及閘423‧‧‧fourth gate
424‧‧‧第五及閘424‧‧‧ Fifth Gate
425‧‧‧第六及閘425‧‧‧ sixth gate
426‧‧‧第七及閘426‧‧‧ seventh gate
500‧‧‧相位切換除頻器電路500‧‧‧ phase switching frequency divider circuit
600‧‧‧主從除頻器600‧‧‧Master-slave frequency divider
610‧‧‧主正反器610‧‧‧Main flip-flop
620‧‧‧從正反器620‧‧‧From the flip-flop
700‧‧‧切換電路700‧‧‧Switching circuit
710‧‧‧注入鎖定電晶體710‧‧‧Injected locking transistor
720‧‧‧切換電晶體720‧‧‧Switching transistor
800‧‧‧相位切換除頻器電路800‧‧‧ phase switching frequency divider circuit
900‧‧‧電流式邏輯除頻器900‧‧‧current logic divider
910‧‧‧第一輸入閂910‧‧‧first input latch
920‧‧‧第一延遲閂920‧‧‧First delay latch
930‧‧‧第二輸入閂930‧‧‧Second input latch
940‧‧‧第二延遲閂940‧‧‧Second delay latch
fdiv‧‧‧振盪訊號Fdiv‧‧‧ oscillation signal
A1U‧‧‧串接端A1U‧‧‧Spliced end
A1D‧‧‧串接端A1D‧‧‧Spliced end
A2U‧‧‧串接端A2U‧‧‧Spliced end
A2D‧‧‧串接端A2D‧‧‧Spliced end
B1U‧‧‧串接端B1U‧‧‧Spliced end
B1D‧‧‧串接端B1D‧‧‧Spliced end
B2U‧‧‧串接端B2U‧‧‧Spliced end
B2D‧‧‧串接端B2D‧‧‧Spliced end
F4Q‧‧‧串接端F4Q‧‧‧Spliced end
F4Q’‧‧‧串接端F4Q’‧‧‧Spliced end
F4I‧‧‧串接端F4I‧‧‧Spliced end
F4I’‧‧‧串接端F4I’‧‧‧Spliced end
S0~S3‧‧‧開關S0~S3‧‧‧ switch
MC‧‧‧模數控制MC‧‧‧Modular Control
Vdivp‧‧‧輸出端Vdivp‧‧‧ output
Vdivn‧‧‧輸出端Vdivn‧‧‧ output
Vi+‧‧‧正極輸入Vi+‧‧‧ positive input
Vi‧‧‧-負極輸入Vi‧‧‧- negative input
Vo+‧‧‧正極輸出Vo+‧‧‧ positive output
Vo-‧‧‧負極輸出Vo-‧‧‧negative output
MC‧‧‧輸入訊號MC‧‧‧ input signal
C‧‧‧進位訊號C‧‧‧ carry signal
S‧‧‧相加訊號S‧‧‧ Adding signals
P90‧‧‧相位差P90‧‧‧ phase difference
P0‧‧‧相位差P0‧‧‧ phase difference
P270‧‧‧相位差P270‧‧‧ phase difference
P180‧‧‧相位差P180‧‧‧ phase difference
NOR‧‧‧反或閘NOR‧‧‧ anti-gate
CLK_I‧‧‧差動輸入信號CLK_I‧‧‧Differential input signal
DFF‧‧‧正反器DFF‧‧‧ forward and reverse
OUT_T‧‧‧輸出訊號OUT_T‧‧‧ output signal
OR‧‧‧或閘OR‧‧‧ or gate
BUF‧‧‧延遲器BUF‧‧‧ retarder
CLK_Q‧‧‧差動輸入信號CLK_Q‧‧‧Differential input signal
I+‧‧‧輸出訊號I+‧‧‧ output signal
OUT_Q‧‧‧輸出訊號OUT_Q‧‧‧ output signal
Q+‧‧‧輸出訊號Q+‧‧‧ output signal
CLK‧‧‧時脈信號CLK‧‧‧ clock signal
DIV4‧‧‧除頻信號DIV4‧‧‧frequency signal
I-‧‧‧輸出訊號I-‧‧‧ output signal
N2‧‧‧除頻器N2‧‧‧Densator
Q-‧‧‧輸出訊號Q-‧‧‧ output signal
Fref_2‧‧‧輸入訊號Fref_2‧‧‧ input signal
N1‧‧‧除頻器N1‧‧‧Deterlator
Fout_2‧‧‧輸出訊號Fout_2‧‧‧ output signal
Fref_1‧‧‧輸入訊號Fref_1‧‧‧ input signal
Fout_1‧‧‧輸出訊號Fout_1‧‧‧ output signal
第1圖係繪示依照習知技術的一種除以三電路之電路圖。Figure 1 is a circuit diagram showing a divide by three circuit in accordance with the prior art.
第2A圖係繪示依照習知技術的一種多相位信號產生裝置之電路圖。Fig. 2A is a circuit diagram showing a multi-phase signal generating apparatus according to the prior art.
第2B圖係繪示依照第2A圖之訊號圖。Figure 2B is a diagram showing the signal according to Figure 2A.
第3圖係繪示依照習知技術的一種高解析度頻率合成器之電路圖。Figure 3 is a circuit diagram of a high resolution frequency synthesizer in accordance with conventional techniques.
第4A圖係繪示依照本發明之一實施方式的一種相位切換除頻器電路之方塊圖。4A is a block diagram of a phase switching frequency divider circuit in accordance with an embodiment of the present invention.
第4B圖係繪示依照本發明之一實施方式的一種相位切換除頻器電路之示意圖。4B is a schematic diagram of a phase switching frequency divider circuit in accordance with an embodiment of the present invention.
第5A圖係繪示依照本發明之一實施方式的四級環型振盪器之電路圖。Figure 5A is a circuit diagram showing a four-stage ring oscillator in accordance with an embodiment of the present invention.
第5B圖係繪示依照本發明之一實施方式的雙端反相器之電路圖。Figure 5B is a circuit diagram of a double-ended inverter in accordance with an embodiment of the present invention.
第6圖係繪示依照本發明之一實施方式的切換電路之電路圖。Figure 6 is a circuit diagram showing a switching circuit in accordance with an embodiment of the present invention.
第7圖係繪示依照本發明之一實施方式的累加器之電路圖。Figure 7 is a circuit diagram of an accumulator in accordance with an embodiment of the present invention.
第8圖係繪示依照本發明之一實施方式的解多工器之電路圖。Figure 8 is a circuit diagram of a demultiplexer in accordance with an embodiment of the present invention.
第9圖係繪示依照本發明之另一實施方式的一種相位切換除頻器電路之方塊圖。Figure 9 is a block diagram showing a phase switching frequency divider circuit in accordance with another embodiment of the present invention.
第10圖係繪示依照第9圖之主從除頻器之電路圖。Figure 10 is a circuit diagram showing the master-slave frequency divider in accordance with Figure 9.
第11圖係繪示依照第9圖之切換電路之電路圖。Figure 11 is a circuit diagram showing the switching circuit in accordance with Figure 9.
第12圖係繪示依照本發明之再一實施方式的一種相位切換除頻器電路之方塊圖。Figure 12 is a block diagram showing a phase switching frequency divider circuit in accordance with still another embodiment of the present invention.
第13圖係繪示第12圖的電流式邏輯除頻器及其切換電路之電路圖。Figure 13 is a circuit diagram showing the current type logic frequency divider of Fig. 12 and its switching circuit.
請參照第4A圖及第4B圖，其係繪示依照本發明之一實施方式的一種相位切換除頻器電路之方塊圖及示 意圖。相位切換除頻器電路100包含一四級環型振盪器200、四注入式切換電路300以及一控制電路400，其中控制電路400包含一累加器410及一解多工器420。Please refer to FIG. 4A and FIG. 4B , which are block diagrams and diagrams of a phase switching frequency divider circuit according to an embodiment of the invention. intention. The phase switching frequency divider circuit 100 includes a four-stage ring oscillator 200, a four-injection switching circuit 300, and a control circuit 400. The control circuit 400 includes an accumulator 410 and a demultiplexer 420.
請一併參照第5A圖，其係繪示上述相位切換除頻器電路100之四級環型振盪器200之電路圖。四級環型振盪器200係由四雙端反相器210分別耦接而成，第一級之雙端反相器210之輸出端耦接至第二級之雙端反相器210之輸入端形成一串接端A1U及一串接端A1D，第二級之雙端反相器210之輸出端耦接至第三級之雙端反相器210之輸入端形成一串接端B1U及一串接端B1D，第三級之雙端反相器210之輸出端耦接至第四級之雙端反相器210之輸入端形成一串接端A2U及一串接端A2D，且第四級之雙端反相器210之輸出端回授至第一級之雙端反相器210之輸入端形成一串接端B2U及一串接端B2D，其中第四級之雙端反相器210之輸出端為四級環型振盪器200之一輸出端Vdivp及一輸出端Vdivn。Referring to FIG. 5A, a circuit diagram of the fourth-stage ring oscillator 200 of the phase switching frequency divider circuit 100 is shown. The four-stage ring oscillator 200 is coupled by four double-ended inverters 210, and the output of the first-stage double-ended inverter 210 is coupled to the input of the second-stage dual-ended inverter 210. Forming a series of terminals A1U and a series of terminals A1D, the output of the second-stage dual-ended inverter 210 of the second stage is coupled to the input end of the third-stage dual-ended inverter 210 to form a series of terminals B1U and a series of terminals B1D, the output end of the third-stage dual-ended inverter 210 is coupled to the input end of the fourth-stage double-ended inverter 210 to form a series of terminals A2U and a series of terminals A2D, and The output of the four-stage double-ended inverter 210 is fed back to the input end of the first-stage double-ended inverter 210 to form a series of terminals B2U and a series of terminals B2D, wherein the fourth stage is double-ended The output of the device 210 is an output terminal Vdivp of the four-stage ring oscillator 200 and an output terminal Vdivn.
請一併參照第5B圖，其係繪示上述四級環型振盪器200之雙端反相器210之電路圖。各雙端反相器210包含一第一電晶體211、一第二電晶體212、一第三電晶體213及一第四電晶體214，第一電晶體211之閘極為反相器210之正極輸入Vi+，第一電晶體211之汲極為雙端反相器210之負極輸出Vo-。第二電晶體212之閘極為雙端反相器210之負極輸入Vi-，第二電晶體212之汲極為雙端反相器210之正極輸出Vo+。第三電晶體213之汲極耦接第一電晶 體211之汲極，第三電晶體213之閘極耦接第二電晶體212之汲極。第四電晶體214之汲極耦接第二電晶體212之汲極，第四電晶體214之閘極耦接第一電晶體211之汲極。Referring to FIG. 5B together, a circuit diagram of the double-ended inverter 210 of the fourth-stage ring oscillator 200 is shown. Each of the double-ended inverters 210 includes a first transistor 211, a second transistor 212, a third transistor 213, and a fourth transistor 214. The gate of the first transistor 211 is substantially the anode of the inverter 210. Input Vi+, the first transistor 211 is the anode output Vo- of the double-ended inverter 210. The gate of the second transistor 212 is substantially the negative input Vi- of the double-ended inverter 210, and the second transistor 212 is substantially the positive output Vo+ of the double-ended inverter 210. The drain of the third transistor 213 is coupled to the first transistor The drain of the body 211, the gate of the third transistor 213 is coupled to the drain of the second transistor 212. The drain of the fourth transistor 214 is coupled to the drain of the second transistor 212, and the gate of the fourth transistor 214 is coupled to the drain of the first transistor 211.
請一併參照第6圖，其係繪示上述注入式切換電路300之電路圖。四注入式切換電路300分別對應各級之雙端反相器210，各注入式切換電路300包含四注入鎖定電晶體310及八切換電晶體320，其中二切換電晶體320對應耦接各注入鎖定電晶體310及各級之雙端反相器210之輸出端。以第一級之雙端反相器210為例，兩兩切換電晶體320為一組各串接一注入鎖定電晶體310連接至第一級之雙端反相器210之串接端A1U及串接端A1D，分別構成開關S0、開關S1、開關S2及開關S3，而開關S0、開關S1、開關S2及開關S3分別對應到各注入鎖定電晶體310延遲之相位差P0、相位差P90、相位差P180及相位差P270。其中P0代表0度，P90代表90度，P180代表180度，P270代表270度。Referring to FIG. 6, a circuit diagram of the above-described injection switching circuit 300 is shown. The four injection switching circuits 300 respectively correspond to the double-ended inverters 210 of the respective stages, and each of the injection switching circuits 300 includes four injection locking transistors 310 and eight switching transistors 320, wherein the two switching transistors 320 are coupled to each injection locking. The transistor 310 and the output of the double-ended inverter 210 of each stage. Taking the double-ended inverter 210 of the first stage as an example, the two switching transistors 320 are connected to the series connection terminal A1U of the double-ended inverter 210 of the first stage by a series of injection-locking transistors 310. The serial connection terminal A1D constitutes a switch S0, a switch S1, a switch S2, and a switch S3, respectively, and the switch S0, the switch S1, the switch S2, and the switch S3 respectively correspond to a phase difference P0 and a phase difference P90 of each injection locking transistor 310. Phase difference P180 and phase difference P270. P0 represents 0 degrees, P90 represents 90 degrees, P180 represents 180 degrees, and P270 represents 270 degrees.
請一併參照第7圖，其係繪示上述控制電路400之累加器410之電路圖。累加器410包含一第一互斥或閘411、一第一及閘412、一第二互斥或閘413、一第二及閘414、一或閘415、一第一D型正反器416、一第二D型正反器417、一第三及閘418及一第三D型正反器419。第一互斥或閘411之輸入端接收一輸入訊號MC及一接地訊號。第一及閘412輸入端接收輸入訊號MC及接地訊號。第二互斥或閘413輸入端耦接第一互斥或閘411之輸出 端，第二互斥或閘413輸出一相加訊號S。第二及閘414輸入端耦接第一互斥或閘411之輸出端。或閘415耦接第一及閘412之輸出端及第二及閘414之輸出端，或閘415之輸出端輸出一進位訊號C。第一D型正反器416之輸入端耦接第二互斥或閘413之輸出端，第一D型正反器416之時脈端耦接四級環型振盪器200之輸出端，用以接收一振盪訊號fdiv。第二D型正反器417之輸入端耦接或閘415之輸出端，第二D型正反器417之時脈端耦接四級環型振盪器200之輸出端。第三及閘418之輸入端耦接第一D型正反器416之輸出端及第二D型正反器417之輸出端，第三及閘418之輸出端耦接第一D型正反器416之重置端及第二D型正反器417之重置端。第三D型正反器419之輸入端耦接第二互斥或閘413之輸出端用以接收相加訊號S，第三D型正反器419之時脈端耦接四級環型振盪器200之輸出端，第三D型正反器419之重置端耦接第三及閘418之輸出端，第三D型正反器419之輸出端耦接第二互斥或閘413之輸入端及第二及閘414之輸入端。Referring to FIG. 7, a circuit diagram of the accumulator 410 of the control circuit 400 is shown. The accumulator 410 includes a first mutex or gate 411, a first sum gate 412, a second mutex or gate 413, a second sum gate 414, a gate 415, and a first D-type flip-flop 416. A second D-type flip-flop 417, a third AND gate 418, and a third D-type flip-flop 419. The input of the first mutex or gate 411 receives an input signal MC and a ground signal. The input of the first and gate 412 receives the input signal MC and the ground signal. The second mutex or gate 413 input is coupled to the output of the first mutex or gate 411 The second mutex or gate 413 outputs an addition signal S. The input of the second AND gate 414 is coupled to the output of the first mutex or gate 411. The gate 415 is coupled to the output of the first AND gate 412 and the output of the second AND gate 414, or the output of the gate 415 outputs a carry signal C. The input end of the first D-type flip-flop 416 is coupled to the output end of the second mutex or gate 413, and the clock-end end of the first D-type flip-flop 416 is coupled to the output end of the fourth-stage ring oscillator 200. To receive an oscillation signal fdiv. The input end of the second D-type flip-flop 417 is coupled to the output end of the gate 415, and the clock end of the second D-type flip-flop 417 is coupled to the output end of the fourth-stage ring oscillator 200. The input end of the third AND gate 418 is coupled to the output end of the first D-type flip-flop 416 and the output end of the second D-type flip-flop 417, and the output end of the third AND gate 418 is coupled to the first D-type positive and negative The reset end of the 416 and the reset end of the second D-type flip-flop 417. The input end of the third D-type flip-flop 419 is coupled to the output of the second mutex or gate 413 for receiving the addition signal S, and the clock terminal of the third D-type flip-flop 419 is coupled to the fourth-order ring oscillator. The output end of the third D-type flip-flop 419 is coupled to the output end of the third AND gate 418, and the output end of the third D-type flip-flop 419 is coupled to the second mutually exclusive or gate 413 The input terminal and the input terminal of the second AND gate 414.
請一併參照第8圖，其係繪示上述控制電路400之解多工器420之電路圖。解多工器420包含一第一單端反相器421、一第二單端反相器422、一第四及閘423、一第五及閘424、一第六及閘425以及一第七及閘426，第一單端反相器421之輸入端耦接或閘415之輸出端用以接收進位訊號C。第二單端反相器422之輸入端耦接第二互斥或閘413之輸出端用以接收相加訊號S。第四及閘423 之輸入端耦接第一單端反相器421之輸出端及第二單端反相器422之輸出端。第五及閘424之輸入端耦接第一單端反相器421之輸出端及第二互斥或閘413之輸出端。第六及閘425輸入端耦接第二單端反相器422之輸出端及或閘415之輸出端。第七及閘426輸入端耦接第二互斥或閘413之輸出端及或閘415之輸出端。Referring to FIG. 8 together, a circuit diagram of the multiplexer 420 of the control circuit 400 is shown. The multiplexer 420 includes a first single-ended inverter 421, a second single-ended inverter 422, a fourth and a gate 423, a fifth and a gate 424, a sixth and a gate 425, and a seventh. And the gate 426, the input end of the first single-ended inverter 421 is coupled to the output of the gate 415 for receiving the carry signal C. The input end of the second single-ended inverter 422 is coupled to the output of the second mutex or gate 413 for receiving the addition signal S. Fourth and gate 423 The input end is coupled to the output end of the first single-ended inverter 421 and the output end of the second single-ended inverter 422. The input end of the fifth sum gate 424 is coupled to the output end of the first single-ended inverter 421 and the output end of the second mutex or gate 413. The input of the sixth and gate 425 is coupled to the output of the second single-ended inverter 422 and the output of the gate 415. The input of the seventh sum gate 426 is coupled to the output of the second mutex or gate 413 and the output of the gate 415.
由上述可知本實施方式之相位切換除頻器電路100由一四級環型振盪器200、四切換電路300以及一控制電路400構成。其利用控制電路400、切換電路300配合四級環型振盪器200為一注入鎖定式之相位切換除頻器電路100，針對四級環型振盪器200之振盪頻率使其接近在欲除頻的中心頻率，並且藉由切換電路300中之注入鎖定電晶體320注入時脈信號與四級環型振盪器200輸出訊號的諧波(harmonics)混合，藉以產生與四級環型振盪器200振盪頻率相近頻率的信號，此信號會拉扯並鎖定四級環型振盪器200的輸出訊號，最後以注入鎖定式之相位切換除頻器100結合控制電路400之相位選擇使輸出訊號之解析度變成四倍，藉此提高相位切換除頻器100之解析度。As described above, the phase switching frequency divider circuit 100 of the present embodiment is constituted by a four-stage ring type oscillator 200, four switching circuits 300, and a control circuit 400. The control circuit 400 and the switching circuit 300 cooperate with the four-stage ring oscillator 200 as an injection-locked phase switching frequency divider circuit 100 for the oscillation frequency of the four-stage ring oscillator 200 to be close to the frequency division. The center frequency, and the clock signal injected by the injection locking transistor 320 in the switching circuit 300 is mixed with the harmonics of the output signal of the fourth-order ring oscillator 200, thereby generating an oscillation frequency with the fourth-order ring oscillator 200. a signal of similar frequency, which pulls and locks the output signal of the fourth-stage ring oscillator 200, and finally the phase selection of the injection-locked phase switching frequency divider 100 in combination with the control circuit 400 makes the resolution of the output signal four times. Thereby, the resolution of the phase switching frequency divider 100 is improved.
以下針對本實施方式之相位切換除頻器電路100之作動方式進行詳細說明。設計四級環型振盪器200為訊號源頻率(ω)的四分之一(ω/4)，其最高振盪頻率為(2N τ)-1 ，其中N為雙端反相器210的階數，τ為雙端反相器210的延遲時間，並且此四級環型振盪器200可提供2N組相位，以此實施方式來說，雙端反相器210有四級，故 N=4提供了八個相位，分別如下：第一級(0度及180度)、第二級(45度及225度)、第三級(90度及270度)及第四級(135度及315度)。The mode of operation of the phase switching frequency divider circuit 100 of the present embodiment will be described in detail below. The four-stage ring oscillator 200 is designed to be one quarter (ω/4) of the signal source frequency (ω), and its highest oscillation frequency is (2N τ) -1 , where N is the order of the double-ended inverter 210 , τ is the delay time of the double-ended inverter 210, and the four-stage ring oscillator 200 can provide 2N sets of phases. In this embodiment, the double-ended inverter 210 has four stages, so N=4 provides Eight phases are as follows: first level (0 degrees and 180 degrees), second level (45 degrees and 225 degrees), third level (90 degrees and 270 degrees), and fourth level (135 degrees and 315 degrees) ).
然後在串接端A1U、串接端A1D、串接端A2U、串接端A2D、串接端B1U、串接端B1D、串接端B2U及串接端B2D各接上注入鎖定電晶體310來達到除頻的效果，其乃根據超諧波注入鎖定(superharmonic injection locking)的現象，主要原理是依靠訊號源頻率的四分之一頻段的諧波來拉四級環型振盪器200的頻率使其一致，所以各注入鎖定電晶體310之主要功用就是扮演電流的混合器(mixer)，使其產生所需的頻率，即四級環型振盪器200的頻率與四分之一諧波同步，藉此達到頻率除四的效用。接著在注入鎖定電晶體310兩端接上切換電晶體320，並在串接端A1U、串接端A1D、串接端A2U、串接端A2D、串接端B1U、串接端B1D、串接端B2U及串接端B2D各做四組開關S0~S3來作相位切換使用(如第6圖所示)，並於圖式上標註開關S0~S3對應之相位差，在此要注意相位切換的順序，其將決定頻率是多除0.25或是少除0.25，舉例來說相位從0度切換至90度則少了四分之一周期，則頻率除率為3.75。最後相位切換的控制是由累加器410加上解多工器420所構成，本實施方式中由模數控制之輸入訊號MC決定頻率要除4或4.25，當模數控制之輸入訊號MC=1時，第一互斥或閘411接收模數控制之輸入訊號MC後，使累加器410產生相加訊號S及進位訊號C，相加訊號S及進 位訊號C開始從00、01、10及11不斷循環，再由解多工器420將相加訊號S及進位訊號C轉換為十進制後，控制開關S0~S3依序開關使其相位不斷切換來達到一直延遲四分之一週期，藉此達到接收振盪訊號fdiv除4.25的作用。Then, the serial connection terminal A1U, the serial connection terminal A1D, the serial connection terminal A2U, the serial connection terminal A2D, the serial connection terminal B1U, the serial connection terminal B1D, the serial connection terminal B2U, and the serial connection terminal B2D are respectively connected with the injection locking transistor 310. The effect of frequency division is achieved, which is based on the phenomenon of superharmonic injection locking. The main principle is to draw the frequency of the four-stage ring oscillator 200 by the harmonic of the quarter frequency band of the signal source frequency. The same, so the main function of each injection locking transistor 310 is to act as a current mixer to generate the desired frequency, that is, the frequency of the four-stage ring oscillator 200 is synchronized with the quarter harmonic. Thereby achieving the effect of dividing the frequency by four. Then, the switching transistor 320 is connected to both ends of the injection locking transistor 310, and is connected at the serial terminal A1U, the serial terminal A1D, the serial terminal A2U, the serial terminal A2D, the serial terminal B1U, the serial terminal B1D, and the serial connection. The end B2U and the serial end B2D do four sets of switches S0~S3 for phase switching (as shown in Fig. 6), and indicate the phase difference corresponding to the switches S0~S3 on the drawing, and pay attention to the phase switching here. The order will determine whether the frequency is more than 0.25 or less than 0.25. For example, if the phase is switched from 0 degrees to 90 degrees, then a quarter cycle is lost, and the frequency division rate is 3.75. The control of the final phase switching is composed of the accumulator 410 plus the demultiplexer 420. In the present embodiment, the input signal MC controlled by the modulus determines the frequency to be divided by 4 or 4.25, and the input signal MC=1 when the modulus control is performed. When the first mutex or gate 411 receives the input signal MC of the analog-to-digital control, the accumulator 410 generates the sum signal S and the carry signal C, and adds the signal S and The bit signal C starts to circulate continuously from 00, 01, 10 and 11, and after the multiplexer 420 converts the addition signal S and the carry signal C into decimal, the control switches S0~S3 are sequentially switched to make the phase continuously switch. A quarter period of delay is reached, thereby achieving the effect of receiving the oscillation signal fdiv by 4.25.
請參照第9圖至第11圖，其係繪示依據本發明另一實施方式之一種相位切換除頻器電路之電路圖、主從除頻器之電路圖及切換電路之電路圖，相位切換除頻器電路500包含一主從除頻器600、一切換電路700以及一控制電路400。主從除頻器600包含一主正反器610及一從正反器620，其中從正反器620之輸入端耦接主正反器610之輸出端形成一串接端F4Q及一串接端F4Q’，從正反器620之輸出端回授至主正反器610之輸入端形成一串接端F4I及一串接端F4I’。切換電路700耦接主正反器610及從正反器620，各切換電路700包含四注入鎖定電晶體710及四切換電晶體720，其中各切換電晶體720分別對應耦接各注入鎖定電晶體710。控制電路400耦接切換電路700，控制電路400同上個實施方式包含一累加器410及一解多工器420(請參照第4B圖)，而累加器410耦接主正反器610及從正反器620，且累加器410輸出一控制訊號，控制訊號為二進位制。解多工器420耦接累加器410及對應之切換電晶體720，解多工器420將累加器410輸出之控制訊號轉為十進位制，用以切換四切換電晶體720。Please refer to FIG. 9 to FIG. 11 , which are circuit diagrams of a phase switching frequency divider circuit, a circuit diagram of a master-slave frequency divider, and a circuit diagram of a switching circuit, and a phase switching frequency divider according to another embodiment of the present invention. Circuit 500 includes a master-slave frequency divider 600, a switching circuit 700, and a control circuit 400. The master-slave frequency divider 600 includes a main flip-flop 610 and a slave flip-flop 620. The input end of the flip-flop 620 is coupled to the output end of the main flip-flop 610 to form a series of terminals F4Q and a series connection. The terminal F4Q' is fed back from the output end of the flip-flop 620 to the input end of the main flip-flop 610 to form a series terminal F4I and a series terminal F4I'. The switching circuit 700 is coupled to the main flip-flop 610 and the slave flip-flop 620. Each of the switching circuits 700 includes a four-injection locking transistor 710 and a four-switching transistor 720. The switching transistors 720 are respectively coupled to the respective injection-locking transistors. 710. The control circuit 400 is coupled to the switching circuit 700. The control circuit 400 includes an accumulator 410 and a demultiplexer 420 (refer to FIG. 4B), and the accumulator 410 is coupled to the main flip-flop 610 and the slave The counter 620, and the accumulator 410 outputs a control signal, and the control signal is a binary system. The demultiplexer 420 is coupled to the accumulator 410 and the corresponding switching transistor 720. The demultiplexer 420 converts the control signal output from the accumulator 410 into a decimal system for switching the four switching transistors 720.
上述之相位切換除頻器電路500，同上個實施方式將主從除頻器600之串接端F4I、串接端F4I’、串接端 F4Q及串接端F4Q’連接至切換電路700之注入鎖定電晶體710，並藉由切換電晶體720形成之開關S0~S3進行相位切換，而相位切換的順序由控制電路400決定，將主從除頻器600之串接端F4I、串接端F4I’、串接端F4Q及串接端F4Q’所輸出之訊號頻率除四，提供相位切換除頻器電路500更高之解析度，相位切換及控制的動作已於上述說明，在此不詳加贅述。The phase switching frequency divider circuit 500 described above, in the same embodiment as the serial connection terminal F4I of the master-slave frequency divider 600, the serial connection terminal F4I', and the serial connection terminal The F4Q and the serial connection terminal F4Q' are connected to the injection locking transistor 710 of the switching circuit 700, and are phase-switched by switching the switches S0 to S3 formed by the transistor 720, and the order of the phase switching is determined by the control circuit 400, and the master-slave The signal frequency output by the serial connection terminal F4I, the serial connection terminal F4I', the serial connection terminal F4Q and the serial connection terminal F4Q' of the frequency divider 600 is divided by four, and the phase switching frequency divider circuit 500 is provided with higher resolution and phase switching. And the action of the control has been described above, and will not be described in detail herein.
請參照第12圖及第13圖，其係繪示依據本發明另一實施方式是在提供一種相位切換除頻器電路之電路圖及電流式邏輯除頻器與切換電路之電路圖。相位切換除頻器電路800包含一電流式邏輯除頻器900、四切換電路700以及一控制電路400，電流式邏輯除頻器900包含一第一輸入閂910、一第一延遲閂920、一第二輸入閂930以及一第二延遲閂940。第一延遲閂920耦接第一輸入閂910。第二輸入閂930耦接第一輸入閂910及第一延遲閂920。第二延遲閂940耦接第二輸入閂930及第一輸入閂910。四切換電路700與上個實施方式相同，各切換電路700分別對應耦接第一輸入閂910、第一延遲閂920、第二輸入閂930及第二延遲閂940，且各切換電路700包含四注入鎖定電晶體710及四切換電晶體720。其中各切換電晶體720分別對應耦接各注入鎖定電晶體710。控制電路400耦接切換電路700，控制電路400同前實施方式包含一累加器410及一解多工器420(請參照第4B圖)，累加器410耦接電流式邏輯除頻器900，且累加器410輸出一控制訊號，控制訊號為二 進位制。解多工器420耦接累加器410及對應之切換電晶體720，解多工器420將累加器410輸出之控制訊號轉為十進位制，用以切換四切換電晶體720。12 and FIG. 13 are circuit diagrams showing a circuit diagram of a phase switching frequency divider circuit and a current type logic frequency divider and switching circuit according to another embodiment of the present invention. The phase switching frequency divider circuit 800 includes a current logic frequency divider 900, a four switching circuit 700, and a control circuit 400. The current logic frequency divider 900 includes a first input latch 910, a first delay latch 920, and a A second input latch 930 and a second delay latch 940. The first delay latch 920 is coupled to the first input latch 910. The second input latch 930 is coupled to the first input latch 910 and the first delay latch 920. The second delay latch 940 is coupled to the second input latch 930 and the first input latch 910. The four switching circuits 700 are the same as the previous embodiment, and each switching circuit 700 is coupled to the first input latch 910, the first delay latch 920, the second input latch 930, and the second delay latch 940, respectively, and each switching circuit 700 includes four The locking transistor 710 and the four switching transistor 720 are injected. Each of the switching transistors 720 is coupled to each of the injection locking transistors 710. The control circuit 400 is coupled to the switching circuit 700. The control circuit 400 includes an accumulator 410 and a demultiplexer 420 (see FIG. 4B). The accumulator 410 is coupled to the current logic descaler 900, and The accumulator 410 outputs a control signal, and the control signal is two Carry system. The demultiplexer 420 is coupled to the accumulator 410 and the corresponding switching transistor 720. The demultiplexer 420 converts the control signal output from the accumulator 410 into a decimal system for switching the four switching transistors 720.
其中第一輸入閂910及第一延遲閂920形成一交叉耦合d型閂(cross coupled d-latch)，而第二輸入閂930及第二延遲閂940形成另一交叉耦合d型閂。上述之相位切換除頻器電路800，同上述兩個實施方式藉由切換電路700之注入鎖定電晶體710及切換電晶體720形成之開關S0~S3進行相位切換，而相位切換的順序由控制電路400決定，將電流式邏輯除頻器900所輸出之訊號頻率除四，提供相位切換除頻器電路800更高之解析度，相位切換及控制的動作已於上述說明，在此不詳加贅述。Wherein the first input latch 910 and the first delay latch 920 form a cross-coupled d-latch, and the second input latch 930 and the second delay latch 940 form another cross-coupled d-type latch. The phase switching frequency divider circuit 800 described above is phase-switched by the switches S0 to S3 formed by the injection locking transistor 710 and the switching transistor 720 of the switching circuit 700 in the above two embodiments, and the phase switching sequence is controlled by the control circuit. 400 determines that the signal frequency output by the current-type logic frequency divider 900 is divided by four to provide a higher resolution of the phase-switching frequency divider circuit 800. The phase switching and control operations are described above, and are not described in detail herein.
藉由上述實施方式可知，本實施方式之相位切換電路及應用相位切換電路之相位切換除頻器電路，藉由切換電晶體及注入鎖定電晶體形成相位切換電路，並由累加器及解多工器決定相位切換順序，藉此可提高除頻器電路之解析度。According to the above embodiment, the phase switching circuit of the present embodiment and the phase switching frequency divider circuit using the phase switching circuit form a phase switching circuit by switching the transistor and injecting the locking transistor, and the accumulator and the multiplexer are demultiplexed. The phase change sequence is determined by the device, thereby improving the resolution of the frequency divider circuit.
此外，本實施方式之相位切換除頻器電路對比先前技術之除頻器電路，其訊號藉由差動輸入的方式之相雜訊(phase noise)較單端輸入為優。再者，相位切換除頻器電路的架構面積較小且除頻的工作範圍廣，提供多相位輸出及低功耗之優點。In addition, the phase switching frequency divider circuit of the present embodiment compares the prior art frequency divider circuit, and the phase noise of the signal by the differential input method is superior to the single-ended input. Furthermore, the phase switching frequency divider circuit has a small architectural area and a wide operating range of frequency division, and provides the advantages of multi-phase output and low power consumption.
100‧‧‧相位切換除頻器電路100‧‧‧ phase switching frequency divider circuit
200‧‧‧四級環型振盪器200‧‧‧four-stage ring oscillator
300‧‧‧注入式切換電路300‧‧‧Injection switching circuit
400‧‧‧控制電路400‧‧‧Control circuit
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7327783B2 (en) * | 2000-08-09 | 2008-02-05 | Skybitz, Inc. | Frequency translator using a cordic phase rotator |
| TW200847640A (en) * | 2007-05-29 | 2008-12-01 | Univ Nat Taiwan | Frequency shift keying modulator having sigma-delta modulated phase rotator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7327783B2 (en) * | 2000-08-09 | 2008-02-05 | Skybitz, Inc. | Frequency translator using a cordic phase rotator |
| TW200847640A (en) * | 2007-05-29 | 2008-12-01 | Univ Nat Taiwan | Frequency shift keying modulator having sigma-delta modulated phase rotator |
| US7667551B2 (en) * | 2007-05-29 | 2010-02-23 | National Taiwan University | Frequency shift keying modulator having sigma-delta modulated phase rotator |
Non-Patent Citations (1)
| Title |
|---|
| 年6月18日公開文件Ching-Yuan Yang "A Low-Voltage, 9-GHz, 0.13-µm CMOS Frequency Synthesizer With a Fractional Phase-Rotating and Frequency-Doubling Topology" VLSI Circuits, 2009 Symposium on 2009年1月1日公開文件Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong "A Δ-Σ PLL-based spread-spectrum clock generator with a ditherless fractional topology" IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS * |
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